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MOTOROLA CMOS LOGIC DATA
1
MC14506UB
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The MC14506UB is an expandable AND–OR–INVERT gate with inhibit
and 3–state output. The expand option allows cascading with any other gate,
which may be carried as far as desired as long as the propagation delay
added with each gate is considered. For example, the second AOI gate in
this device may be used to expand the first gate, giving an expanded 4–wide,
2–input AOI gate. This device is useful in data control and digital multiplexing
applications.
• 3–State Output
• Separate Inhibit Line
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage – 0.5 to + 18.0 V
Vin, V
out
Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, I
out
Input or Output Current (DC or Transient),
per Pin
± 10 mA
P
D
Power Dissipation, per Package† 500 mW
T
stg
Storage Temperature – 65 to + 150
_
C
T
L
Lead Temperature (8–Second Soldering) 260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
LOGIC DIAGRAM
AA1
BA2
CA3
DA4
EA5
INH 6
DIS 14
EB13
DB12
CB11
BB10
AB9
3–STATE
OUTPUT DISABLE
15 Z
A
7 Z
B
VDD = PIN 16
VSS = PIN 8
Z = (AB + CD + E
+ I)
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXUBCP Plastic
MC14XXXUBCL Ceramic
MC14XXXUBD SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of
any voltage higher than maximum rated voltages to this high–impedance circuit. For proper
operation, Vin and V
out
should be constrained
to the range VSS v (Vin or V
out
) v VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V
SS
or VDD). Unused outputs must be left open.
TRUTH TABLE
A B C D E Inhibit Disable Z
0 0 0 0 1 0 0 1
0 X 0 X 1 0 0 1
0 X X 0 1 0 0 1
X 0 0 X 1 0 0 1
X 0 X 0 1 0 0 1
1 1 X X X X 0 0
X X 1 1 X X 0 0
X X X X 0 X 0 0
X X X X X 1 0 0
X X X X X X 1 High
Impedance
X = Don’t Care
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MOTOROLA CMOS LOGIC DATAMC14506UB
2
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
Min Max Min Typ # Max Min Max
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.0
2.0
2.5
—
—
—
2.25
4.50
6.75
1.0
2.0
2.5
—
—
—
1.0
2.0
2.5
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
4.0
8.0
12.5
—
—
—
4.0
8.0
12.5
2.75
5.50
8.25
—
—
—
4.0
8.0
12.5
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
I
OH
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current I
in
15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance
(Vin = 0)
C
in
— — — — 5.0 7.5 — — pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
—
—
—
1.0
2.0
4.0
—
—
—
0.002
0.004
0.006
1.0
2.0
4.0
—
—
—
30
60
120
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
IT = (0.6 µA/kHz) f + I
DD
IT = (1.1 µA/kHz) f + I
DD
IT = (1.7 µA/kHz) f + I
DD
µAdc
Three–State Leakage Current I
TL
15 — ± 0.1 — ± 0.0001 ± 0.1 — ± 3.0 µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
D
B
E
B
DISABLE
Z
A
V
DD
A
B
B
B
C
B
D
A
C
A
B
A
A
A
V
SS
Z
B
INH
E
A
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MOTOROLA CMOS LOGIC DATA
3
MC14506UB
SWITCHING CHARACTERISTICS* (C
L
= 50 pF, TA = 25_C)
Characteristic
Symbol V
DD
Min Typ # Max Unit
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) CL + 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) CL + 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) CL + 9.5 ns
t
TLH
, t
THL
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Data Propagation Delay Time
t
PLH
= (1.7 ns/pF) CL + 210 ns
t
PLH
= (0.66 ns/pF) CL + 77 ns
t
PLH
= (0.5 ns/pF) CL + 50 ns
t
PLH
5.0
10
15
—
—
—
295
110
75
580
225
180
ns
t
PHL
= (1.7 ns/pF) CL + 185 ns
t
PHL
= (0.66 ns/pF) CL + 62 ns
t
PHL
= (0.5 ns/pF) CL + 40 ns
t
PHL
5.0
10
15
—
—
—
270
95
65
480
175
140
ns
Expand Propagation Delay Time
t
PLH
= (1.7 ns/pF) CL + 95 ns
t
PLH
= (0.66 ns/pF) CL + 42 ns
t
PLH
= (0.5 ns/pF) CL + 25 ns
t
PLH
5.0
10
15
—
—
—
180
75
50
430
160
125
ns
t
PHL
= (1.7 ns/pF) CL + 115 ns
t
PHL
= (0.66 ns/pF) CL + 47 ns
t
PHL
= (0.5 ns/pF) CL + 30 ns
t
PHL
5.0
10
15
—
—
—
200
80
55
330
110
90
ns
Inhibit Propagation Delay Time
t
PLH
= (1.7 ns/pF) CL + 135 ns
t
PLH
= (0.66 ns/pF) CL + 67 ns
t
PLH
= (0.5 ns/pF) CL + 40 ns
t
PLH
5.0
10
15
—
—
—
220
100
65
500
225
160
ns
t
PHL
= (1.7 ns/pF) CL + 145 ns
t
PHL
= (0.66 ns/pF) CL + 62 ns
t
PHL
= (0.5 ns/pF) CL + 35 ns
t
PHL
5.0
10
15
—
—
—
230
95
60
400
175
150
ns
3–State Propagation Delay Time
“1” to High Impedance
t
PHZ
5.0
10
15
—
—
—
60
45
35
150
110
90
ns
“0” to High Impedance t
PLZ
5.0
10
15
—
—
—
90
55
40
225
140
100
ns
High Impedance to “1” t
PZH
5.0
10
15
—
—
—
110
50
40
300
125
100
ns
High Impedance to “0” t
PZL
5.0
10
15
—
—
—
170
70
50
425
175
125
ns
*The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” Is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Typical Voltage Transfer Characteristics
(a) Expand Inputs (b) Data Inputs
161412108.06.04.02.00
16
14
12
10
8.0
6.0
4.0
2.0
0
Vin, INPUT VOLTAGE (Vdc)
V
out
, OUTPUT VOLTAGE (Vdc)
a
b
c
c
a
b
a
b
c
VDD = 15 Vdc
10 Vdc
5.0 Vdc
a
b
c
TA = + 125°C
TA = + 25
°
C
TA = – 55
°
C
UNUSED INPUTS
CONNECTED TO
V
SS
161412108.06.04.02.00
16
14
12
10
8.0
6.0
4.0
2.0
0
Vin, INPUT VOLTAGE (Vdc)
V
out
, OUTPUT VOLTAGE (Vdc)
a
b
c
TA = + 125°C
TA = + 25
°
C
TA = – 55
°
C
A AND B CONNECTED TO V
in
ENABLE INPUT CONNECTED TO
VDD. OTHER INPUTS CONNECTED
TO VSS.
VDD = 15 Vdc
10 Vdc
5.0 Vdc
b
c
a
b
a
c
b
c
a