Motorola MC14501BD, MC14501BCL, MC14501BCP Datasheet
MOTOROLA CMOS LOGIC DATA
1
MC14501UB
Dual 4–Input “NAND” Gate
2–Input “NOR/OR” Gate
8–Input “AND/NAND” Gate
The MC14501UB is constructed with MOS P–channel and N–channel
enhancement mode d evices in a s ingle m onolithic structure. These
complementary MOS logic gates find p rimary use where low p ower
dissipation and/or high noise immunity is desired. Additional characteristics
can be found on the Family Data Sheet.
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Swing Independent of Fanout
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage
– 0.5 to + 18.0
V
Vin, V
out
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
Iin,
Iout
Input or Output Current (DC or Transient),
per Pin
± 10
mA
P
D
Power Dissipation, per Package†
500
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature (8–Second Soldering)
260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
CIRCUIT SCHEMATIC
(5) 4
(9) 3
(7) 2
(6) 1
13 (10)
VDD16
VSS8
V
DD
11
12
14
15
V
SS
V
SS
Numbers in parenthesis are for second 4–input gate.
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
LOGIC DIAGRAM
(POSITIVE LOGIC)
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC
1
2
3
4
11
12
5
6
7
9
13
14 AND
15 NAND
10
VDD = PIN 16
VSS = PIN 8
Use Dotted Connection Externally to
Obtain 8–Input AND/NAND
NOTE: Pin 14 must not be used as an input
NOTE: to the inverter.
MOTOROLA CMOS LOGIC DATAMC14501UB
2
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 55_C
25_C
125_C
Characteristic
Symbol
V
DD
Vdc
Min
Max
Min
Typ #
Max
Min
ÎÎÎ
ÎÎÎ
ÎÎÎ
Max
Unit
Output Voltage
“0” Level
Vin = VDD or 0
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
Vdc
Input Voltage
“0” Level
(VO = 3.6 or 1.4 Vdc)
(VO = 7.2 or 2.8 Vdc)
(VO = 11.5 or 3.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
3.75
—
—
—
2.25
4.50
6.75
1.5
3.0
3.75
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
1.4
2.9
3.6
Vdc
(VO = 1.4 or 3.6 Vdc)
“1” Level
(VO = 2.8 or 7.2 Vdc)
(VO = 3.5 or 11.5 Vdc)
V
IH
5.0
10
15
3.6
7.1
11.4
—
—
—
3.5
7.0
11.25
2.75
5.50
8.25
—
—
—
3.5
7.0
11
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc) NAND*
(VOH = 13.5 Vdc)
I
OH
5.0
5.0
10
15
– 1.2
– 0.25
– 0.62
– 1.8
—
—
—
—
– 1.0
– 0.2
– 0.5
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
—
—
—
—
– 0.7
– 0.14
– 0.35
– 1.1
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
—
mAdc
(VOH = 2.5 Vdc) NOR
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc
(VOH = 13.5 Vdc)
5.0
5.0
10
15
– 2.1
– 0.42
– 1.06
– 3.1
—
—
—
—
– 1.75
– 0.35
– 0.88
– 2.63
– 3.0
– 0.63
– 1.58
– 6.12
—
—
—
—
– 1.22
– 0.24
– 0.62
– 1.84
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
—
mAdc
(VOH = 2.5 Vdc) NOR–
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc) Inverter
(VOH = 13.5 Vdc)
5.0
5.0
10
15
– 3.6
– 0.72
– 1.8
– 5.4
—
—
—
—
– 3.0
– 0.6
– 1.5
– 4.5
– 5.1
– 1.08
– 2.7
– 10.5
—
—
—
—
– 2.1
– 0.42
– 1.05
– 3.15
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
—
mAdc
OH
= 13.5 Vdc)
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc) NAND*
(VOL = 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
mAdc
OL
= 1.5 Vdc)
(VOL = 0.4 Vdc) NOR
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
5.0
10
15
0.92
2.34
6.12
—
—
—
0.77
1.95
5.1
1.32
3.37
13.2
—
—
—
0.54
1.36
3.57
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
mAdc
OL
= 1.5 Vdc)
(VOL = 0.4 Vdc) NOR–
(VOL = 0.5 Vdc) Inverter
(VOL = 1.5 Vdc)
5.0
10
15
1.54
3.90
10.2
—
—
—
1.28
3.25
8.5
2.2
5.63
22
—
—
—
0.90
2.27
5.95
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
mAdc
Input Current
I
in
15
—
± 0.1
—
±0.00001
± 0.1
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
± 1.0
µAdc
Input Capacitance
(Vin = 0)
C
in
—
—
—
—
5.0
7.5
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
—
—
—
0.25
0.5
1.0
—
—
—
0.0005
0.0010
0.0015
0.25
0.5
1.0
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
7.5
15
30
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
IT = (1.2 µA/kHz) f + I
DD
IT = (2.4 µA/kHz) f + I
DD
IT = (3.6 µA/kHz) f + I
DD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.
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