Motorola MC141537T1, MCC141537 Datasheet
MCM64PE32•MCM64PE64
1
MOTOROLA FAST SRAM
Advance Information
256K/512K Pipelined BurstRAM
Secondary Cache Module
for Pentium
The MCM64PE32 (256K) and MCM64PE64 (512K) are designed to provide
a burstable, high performance, L2 cache for the Pentium microprocessor in
conjunction with Intel’s Triton II chip set. The MCM64PE32 is configured as 32K
x 64 bits and the MCM64PE64 is configured as 64K x 64 bits. Both are packaged
in a 160 pin card edge memory module. The MCM64PE32 module uses
Motorola’s 3.3 V 32K x 32 BurstRAMs and one Motorola 5 V 32K x 8 FSRAM for
the tag RAM. The MCM64PE64 module uses Motorola’s 3.3 V 64K x 32
BurstRAMs and one Motorola 5 V 32K x 8 FSRAM for the tag RAM.
Bursts can be initiated with either address status processor (ADSP
) or cache
address status (CADS
). Subsequent burst addresses are generated internal to
the BurstRAM by the cache burst advance (CADV
) input pin.
Write cycles are internally self timed and are initiated by the rising edge of the
clock (CLK0) input. Eight write enables are provided for byte write control.
PD0 – PD3 map into the Triton II chip set for auto–configuration of the cache
control.
• Pentium–Style Burst Counter on Chip
• Pipelined Data Out
• 160 Pin Card Edge Module
• Address Pipeline Supported by ADSP
Disabled with Ex
• All Cache Data and Tag I/Os are TTL Compatible
• Three State Outputs
• Byte Write Capability
• Fast Module Clock Rate: 66 MHz
• Fast SRAM Access Times:15 ns for Tag RAM
8 ns for Data RAMs
• One–Cycle Deselect Data RAMs
• Decoupling Capacitors for Each Fast Static RAM
• High Quality Multi–Layer FR4 PWB with Separate Power and Ground
Planes
• 8 Bits Tag RAM
• Dual Power Supplies: 3.3 V + 10%, – 5%
5 V ± 10%
• Burndy Connector, Part Number: CELP2X80SC3Z48
• Intel COAST 3.0 Option III Compliant
• Burst Order Select (BOSEL) Option
BurstRAM is a trademark of Motorola.
Mfax is a trademark of Motorola.
Pentium is a trademark of Intel Corp.
This document contains information on a new product. Motorola reserves the right to change or discontinue this product without notice.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM64PE32/D
MCM64PE32
MCM64PE64
160–LEAD CARD EDGE
CASE TBD
TOP VIEW
80
43
42
1
12/9/96
Motorola, Inc. 1996
MCM64PE32•MCM64PE64
2
MOTOROLA FAST SRAM
MCM64PE32 BLOCK DIAGRAM
BWE
CADV
ADSP
CADS
CLK0
CG
SE1
32K x 32
ADV
K
G
SW
SE2
LBO
ADSP
ADSC
DQ0 – DQ31
ZZ
V
DD
CCS
V
DD
SA0 – SA14
TIO0 – TIO7
TWE
15
13
A3 – A17
GWE
SGW
CWE0 – CWE3
SBa – SBd
SE3
ECS2
ECS1
4.7 k
Ω
DQ0 – DQ31
SE1
32K x 32
ADV
K
G
SW
SE2
LBO
ADSP
ADSC
DQ0 – DQ31
ZZ
SA0 – SA14
15
SGW
SBa – SBd
SE3
DQ32 – DQ63
CWE4 – CWE7
A0 – A12
DQ0 – DQ7
A13
W
A14
G
32K x 8
E
BOSEL
A5 – A17
MCM64PE32•MCM64PE64
3
MOTOROLA FAST SRAM
MCM64PE64 BLOCK DIAGRAM
BWE
CADV
ADSP
CADS
CLK0
CG
SE1
64K x 32
ADV
K
G
SW
SE2
LBO
ADSP
ADSC
DQ0 – DQ31
ZZ
V
DD
CCS
SA0 – SA15
TIO0 – TIO7
TWE
16
14
A3 – A18
GWE
SGW
CWE0 – CWE3
SBa – SBd
SE3
4.7 k
Ω
DQ0 – DQ31
SE1
64K x 32
ADV
K
G
SW
SE2
LBO
ADSP
ADSC
DQ0 – DQ31
ZZ
SA0 – SA15
15
SGW
SBa – SBd
SE3
DQ32 – DQ63
CWE4 – CWE7
A0 – A13
DQ0 – DQ7
W
A14
G
32K x 32
E
16
V
DD
BOSEL
A5 – A18
PIN ASSIGNMENT
160–LEAD CARD EDGE MODULE
TOP VIEW
CWE3
NC
NC
V
SS
RSVD
A4
A6
A8
A10
VCC5
A17
V
SS
A9
A14
A15
RSVD
PD0
PD2
BOSEL
V
SS
CLK0
V
SS
DQ63
VCC5
DQ61
DQ59
DQ57
81
82
83
84
85
86
87
88
89
90
8
9
10
CWE4
CWE6
CWE0
CWE2
VDD3
CCS
GWE
BWE
V
SS
A3
A7
A5
A11
A16
VDD3
A18
V
SS
A12
A13
ADSP
ECS1
ECS2
PD1
PD3
V
SS
NC
V
SS
DQ62
VDD3
DQ60
DQ58
DQ56
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
V
SS
DQ55
DQ53
DQ51
DQ49
V
SS
DQ47
DQ45
DQ43
VCC5
DQ41
DQ39
DQ37
V
SS
DQ35
DQ33
DQ31
VCC5
DQ29
DQ27
DQ25
V
SS
DQ23
DQ21
DQ19
VCC5
DQ17
DQ15
DQ13
V
SS
DQ11
DQ9
DQ7
VCC5
DQ5
DQ3
DQ1
V
SS
V
SS
DQ54
DQ52
DQ50
DQ48
V
SS
DQ46
DQ44
DQ42
VDD3
DQ40
DQ38
DQ36
V
SS
DQ34
DQ32
DQ30
V
DD
DQ28
DQ26
DQ24
V
SS
DQ22
DQ20
DQ18
VDD3
DQ16
DQ14
DQ12
V
SS
DQ10
DQ8
DQ6
VDD3
DQ4
DQ2
DQ0
V
SS
V
SS
TIO0
TIO2
TIO6
TIO4
NC
VDD3
TWE
CADS
V
SS
1
2
3
4
5
6
7
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
V
SS
TIO1
TIO7
TIO5
TIO3
NC
VCC5
NC
CADV
V
SS
CG
CWE5
CWE7
CWE1
VCC5
91
92
93
94
95
MCM64PE32•MCM64PE64
4
MOTOROLA FAST SRAM
PRESENCE DETECT TABLE
Cache Size and
Functionality
PD0 PD1 PD2 PD3
256K Pipe Burst NC NC V
SS
NC
512K Pipe Burst NC NC NC V
SS
MCM64PE32•MCM64PE64
5
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
160–Lead Card Edge Pin Locations Symbol
Type Description
20, 21, 22, 23, 24, 26, 28, 29,
101, 102, 103, 104, 106, 108, 109, 110
A3 – A18 Input Address Inputs: These inputs are registered into data RAMs and must
meet setup and hold times. The tag RAM addresses are not registered.
30 ADSP Input Address Status Processor: Initiates READ, WRITE, or chip deselect
cycle (Exception — chip deselect does not occur when ADSP
is
asserted and CCS
is high.
114 BOSEL Input Burst Order Select: NC for interleaved burst counter. Tie to ground for
linear burst counter.
18 BWE Input Byte Write Enable: To be used in future modules.
9 CADS Input Cache Address Status: Initiates READ, WRITE, or chip deselect cycle.
89 CADV Input Cache Burst Advance: Increments address count in accordance with
interleaved count style.
16 CCS Input Chip Select: Active low chip enable for data RAMs.
91 CG Input Cache Output Enable: Active low asynchronous input.
Low — enables output buffers (DQ pins)
High — DQx pins are high impedance.
116 CLK0 Input Clock: This signal registers the address, data in, and all control signals
except CG
.
11, 12, 13, 14, 92, 93, 94, 96 CWE0 –
CWE7
Input Cache Data Byte Write Enable: Active low write signal for data RAMs.
38, 40, 41, 42, 44, 45, 46, 47, 49, 50, 51,
53, 54, 55, 57, 58, 59, 61, 62, 63, 65, 66,
67, 69, 70, 71, 73, 74, 75, 77, 78, 79,
118, 120, 121, 122, 124, 125, 126, 127,
129, 130, 131, 133, 134, 135, 137, 138,
139, 141, 142, 143, 145, 146, 147, 149,
150, 151, 153, 154, 155, 157, 158, 159
DQ0 –
DQ63
I/O Synchronous Data I/O:
Drives data out of data RAMs during READ cycles.
Stores data to data RAMs during WRITE cycles.
31, 32 ECS1,
ECS2
Input Expansion Chip Select.
17 GWE Input Global Write Enable: To be used in future modules.
33, 34, 112, 113 PD0 –
PD3
— Presence Detect: See Presence Detect Table.
100, 111 RSVD — No Connection: Reserved for future use.
2, 3, 4, 5, 82, 83, 84, 85 TIO0 –
TIO7
I/O Tag RAM I/O:
Drives data out during tag compare cycles.
Stores data to tag RAM during tag WRITE cycles.
8 TWE Input Tag W rite Enable: Active low write signal for tag RAMs.
87, 95, 105, 119, 132, 140, 148, 156 VCC5 Supply Power Supply: 5.0 V ± 5%.
7, 15, 25, 39, 52, 60, 68, 76 VDD3 Supply Power Supply: 3.3 V + 10%, – 5%.
1, 10, 19, 27, 35, 37, 43, 48, 56, 64, 72,
80, 81, 90, 99, 107, 115, 117, 123, 128,
136, 144, 152, 160
V
SS
Supply Ground.
6, 36, 86, 88, 97, 98 NC — No Connection: There is no connection to the module.
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