Motorola MC141535T, MCC141535Z Datasheet

MCM64PD32•MCM64PD64

1

MOTOROLA FAST SRAM

Advance Information

256K/512K Pipelined BurstRAM
Secondary Cache Module
for Pentium

The MCM64PD32 (256K) and MCM64PD64 (512K) are designed to provide
a burstable, high performance, L2 cache for the Pentium microprocessor in
conjunction with Intel’s Triton II chip set. The MCM64PD32 is configured as 32K
x 64 bits and the MCM64PD64 is configured as 64K x 64 bits. Both are packaged
in a 160 pin card edge memory module. Each module uses Motorola’s 3.3 V 32K
x 32 BurstRAMs and two Motorola 3.3 V 32K x 8 FSRAM for the tag RAM.

Bursts can be initiated with either address status processor (ADSP

) or cache

address status (CADS

). Subsequent burst addresses are generated internal to

the BurstRAM by the cache burst advance (CADV

) input pin.

Write cycles are internally self timed and are initiated by the rising edge of the
clock (CLK0) input. Eight write enables are provided for byte write control.

PD0 – PD3 map into the Triton II chip set for auto–configuration of the cache
control.

• Pentium–Style Burst Counter on Chip

• Pipelined Data Out

• 160 Pin Card Edge Module

• Address Pipeline Supported by ADSP

Disabled with Ex

• All Cache Data and Tag I/Os are TTL Compatible

• Three State Outputs

• Byte Write Capability

• Fast Module Clock Rate: 66 MHz

• Fast SRAM Access Times:15 ns for Tag RAM

8 ns for Data RAMs

• One–cycle Deselect Data RAMs

• Decoupling Capacitors for Each Fast Static RAM

• High Quality Multi–Layer FR4 PWB with Separate Power and Ground

Planes

• Single 3.3 V +10%, – 5% Power Supply

• Burndy Connector, Part Number: CELP2X80SC3Z48

• Intel COAST 3.0 Option III Compliant

• Burst Order Select (BOSEL) Option

BurstRAM is a trademark of Motorola.
Pentium is a trademark of Intel Corp.

This document contains information on a new product. Motorola reserves the right to change or discontinue this product without notice.

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MCM64PD32/D

MCM64PD32
MCM64PD64

160–LEAD CARD EDGE

CASE TBD, TOP VIEW

80

43

42

1

6/14/96

 Motorola, Inc. 1996

MCM64PD32•MCM64PD64
2

MOTOROLA FAST SRAM

MCM64PD32 BLOCK DIAGRAM

BWE

CADV

ADSP
CADS

CLK0

CG

SE1

32K x 32

ADV

K
G

SW

SE2

LBO

ADSP
ADSC

DQ0 – DQ31

ZZ

V

DD

CCS

V

DD

SA0 – SA14

TIO0 – TIO7

TWE

15

13

A3 – A17

GWE

SGW

CWE0 – CWE3

SBa – SBd

SE3

ECS2
ECS1

DQ0 – DQ31

SE1

32K x 32

ADV

K
G

SW

SE2

LBO

ADSP
ADSC

DQ0 – DQ31

ZZ

SA0 – SA14

15

SGW
SBa – SBd

SE3

DQ32 – DQ63

CWE4 – CWE7

A0 – A12

DQ0 – DQ7

A13

W

A14
G

32K x 8

E

TIO8
TIO9

TIO10

VDD3

8.2 k

Ω

8.2 k

Ω

BOSEL

8.2 k

Ω

4.7 k

Ω

MCM64PD32•MCM64PD64

3

MOTOROLA FAST SRAM

MCM64PD64 BLOCK DIAGRAM

BWE

CADV

ADSP
CADS

CLK0

CG

SE1

32K x 32

ADV

K
G

SW

SE2

LBO

ADSP
ADSC

DQ0 – DQ31

ZZ

V

DD

V

DD

SA0 – SA14

TIO0 – TIO7

TWE

13

A3 – A17

GWE

SGW

CWE0 –

CWE3

SBa – SBd

SE3

DQ0 –
DQ31

SE1

32K x 32

ADV

K
G

SW

SE2

LBO

ADSP
ADSC

DQ0 – DQ31

ZZ

SA0 – SA14

15

SGW
SBa – SBd

SE3

DQ32 –
DQ63

CWE4 –

CWE7

A0 – A12

DQ0 – DQ7

A13

W

A14
G

32K x 8

E

TIO8
TIO9
TIO10

VDD3

8.2 k

Ω

4.7 k

Ω

BOSEL

8.2 k

Ω

A18

SE1

32K x 32

ADV

K
G

SW

SE2

LBO

ADSP
ADSC

DQ0 – DQ31

ZZ

SA0 – SA14

15

SGW
SBa – SBd

SE3

SE1

32K x 32

ADV

K
G

SW

SE2

LBO

ADSP
ADSC

DQ0 – DQ31

ZZ

SA0 – SA14

SGW
SBa – SBd

SE3

V

DD

8.2 k

Ω

CCS

CLK1

MCM64PD32•MCM64PD64
4

MOTOROLA FAST SRAM

PIN ASSIGNMENT 160–LEAD CARD EDGE MODULE (DIMM)

Pin Name Pin Name Pin Name Pin Name Pin Name

1 V

SS

33 PD1 65 DQ22 97 NC 129 DQ47
2 TIO0 34 PD3 66 DQ20 98 NC 130 DQ45
3 TIO2 35 V

SS

67 DQ18 99 V

SS

131 DQ43
4 TIO6 36 CLK1 68 VDD3 100 RSVD 132 VDD5
5 TIO4 37 V

SS

69 DQ16 101 A4 133 DQ41
6 TIO8 38 DQ62 70 DQ14 102 A6 134 DQ39
7 VDD3 39 VDD3 71 DQ12 103 A8 135 DQ37
8 TWE 40 DQ60 72 V

SS

104 A10 136 V

SS

9 CADS 41 DQ58 73 DQ10 105 VDD5 137 DQ35

10 V

SS

42 DQ56 74 DQ8 106 A17 138 DQ33

11 CWE4 43 V

SS

75 DQ6 107 V

SS

139 DQ31
12 CWE6 44 DQ54 76 VDD3 108 A9 140 VDD5
13 CWE0 45 DQ52 77 DQ4 109 A14 141 DQ29
14 CWE2 46 DQ50 78 DQ2 110 A15 142 DQ27
15 VDD3 47 DQ48 79 DQ0 111 RSVD 143 DQ25
16 CCS 48 V

SS

80 V

SS

112 PD0 144 V

SS

17 GWE 49 DQ46 81 V

SS

113 PD2 145 DQ23
18 BWE 50 DQ44 82 TIO1 114 BOSEL 146 DQ21
19 V

SS

51 DQ42 83 TIO7 115 V

SS

147 DQ19
20 A3 52 VDD3 84 TIO5 116 CLK0 148 VDD5
21 A7 53 DQ40 85 TIO3 117 V

SS

149 DQ17
22 A5 54 DQ38 86 TIO9 118 DQ63 150 DQ15
23 A11 55 DQ36 87 VDD5 119 VDD5 151 DQ13
24 A16 56 V

SS

88 TIO10 120 DQ61 152 V

SS

25 VDD3 57 DQ34 89 CADV 121 DQ59 153 DQ11
26 A18 58 DQ32 90 V

SS

122 DQ57 154 DQ9

27 V

SS

59 DQ30 91 CG 123 V

SS

155 DQ7
28 A12 60 VDD3 92 CWE5 124 DQ55 156 VDD5
29 A13 61 DQ28 93 CWE7 125 DQ53 157 DQ5
30 ADSP 62 DQ26 94 CWE1 126 DQ51 158 DQ3
31 ECS1 63 DQ24 95 VDD5 127 DQ49 159 DQ1
32 ECS2 64 V

SS

96 CWE3 128 V

SS

160 V

SS

TOP VIEW – CASE TBD

1

42

43

80

81

122

123

160

PRESENCE DETECT TABLE

Cache Size and

Functionality

PD0 PD1 PD2 PD3

256K Pipe Burst NC NC V

SS

NC

512K Pipe Burst V

SS

V

SS

NC V

SS

MCM64PD32•MCM64PD64

5

MOTOROLA FAST SRAM

PIN DESCRIPTIONS

160–Lead Card Edge Pin Locations Symbol

Type Description

20, 21, 22, 23, 24, 26, 28, 29,

101, 102, 103, 104, 106, 108, 109, 110

A3 – A18 Input Address Inputs: These inputs are registered into data RAMs and must

meet setup and hold times. The tag RAM addresses are not registered.

30 ADSP Input Address Status Processor: Initiates READ, WRITE, or chip deselect

cycle (Exception–chip deselect dGs not occur when ADSP

is asserted

and CCS

is high.

114 BOSEL Input Burst Order Select: NC for interleaved burst counter. T ie to ground for

linear burst counter.

18 BWE Input Byte Write Enable: To be used in future modules.

9 CADS Input Cache Address Status: Initiates READ, WRITE, or chip deselect cycle.

89 CADV Input Cache Burst Advance: Increments address count in accordance with

interleaved count style.
16 CCS Input Chip Select: Active low chip enable for data RAMs.
91 CG Input Cache Output Enable: Active low asynchronous input.

Low – enables output buffers (DQ pins)

High – DQx pins are high impedance.

36, 116 CLK0,

CLK1

Input Clock: This signal registers the address, data in, and all control signals

except CG

.

11, 12, 13, 14, 92, 93, 94, 96 CWE0 –

CWE7

Input Cache Data Byte Write Enable: Active low write signal for data RAMs.

38, 40, 41, 42, 44, 45, 46, 47, 49, 50, 51,
53, 54, 55, 57, 58, 59, 61, 62, 63, 65, 66,

67, 69, 70, 71, 73, 74, 75, 77, 78, 79,
118, 120, 121, 122, 124, 125, 126, 127,
129, 130, 131, 133, 134, 135, 137, 138,
139, 141, 142, 143, 145, 146, 147, 149,

150, 151, 153, 154, 155, 157, 158, 159

DQ0 –

DQ63

I/O Synchronous Data I/O:

Drives data out of data RAMs during READ cycles.
Stores data to data RAMs during WRITE cycles.

31, 32 ECS1,

ECS2

Input Expansion Chip Select

17 GWE Input Global Write Enable: To be used in future modules.

33, 34, 112, 113 PD0 –

PD3

— Presence Detect: See Presence Detect Table

2, 3, 4, 5, 6, 82, 83, 84, 85, 86, 88 TIO0 –

TIO10

I/O Tag RAM I/O:

Drives data out during tag compare cycles.
Stores data to tag RAM during tag WRITE cycles.

8 TWE Input Tag Write Enable: Active low write signal for tag RAMs.

7, 15, 25, 39, 52, 60, 68, 76 VDD3 Supply Power Supply: 3.3 V + 10%, – 5%.

87, 95, 105, 119, 132, 140, 148, 156 VDD5 Supply Power Supply: 5.0 V ± 5%.

1, 10, 19, 27, 35, 37, 43, 48, 56, 64, 72,
80, 81, 90, 99, 107, 115, 117, 123, 128,

136, 144, 152, 160

V

SS

Supply Ground.

100, 111 RSVD — No Connection: Reserved for future use.

97, 98 NC — No Connection: There is no connection to the module.