MOTOROLA MC14077BD, MC14077BDR2, MC14077BF, MC14077BFEL, MC14077BCP Datasheet

...

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 3

1 Publication Order Number:

MC14070B/D

MC14070B, MC14077B

CMOS SSI

Quad Exclusive “OR” and “NOR” Gates

The MC14070B quad exclusive OR gate and the MC14077B quad exclusive NOR gate are constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. These complementary MOS logic gates find primary use where low power dissipation and/or high noise immunity is desired.

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• All Outputs Buffered

• Capable of Driving Two Low–Power TTL Loads or One Low–Power

Schottky TTL Load Over the Rated Temperature Range

• Double Diode Protection on All Inputs

• MC14070B — Replacement for CD4030B and CD4070B Types

• MC14077B — Replacement for CD4077B Type

MAXIMUM RATINGS (Voltages Referenced to V

) (Note 2.)

Symbol Parameter Value Unit

DC Supply Voltage Range –0.5 to +18.0 V

Vin, V

out

Input or Output Voltage Range

(DC or Transient)

–0.5 to VDD + 0.5 V

Iin, I

out

Input or Output Current

(DC or Transient) per Pin

±10 mA

Power Dissipation,

per Package (Note 3.)

500 mW

Ambient Temperature Range –55 to +125 °C

stg

Storage Temperature Range –65 to +150 °C

Lead Temperature

(8–Second Soldering)

260 °C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, V

and V

out

should be constrained

to the range V

v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V

or VDD). Unused outputs must be left open.

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XX = Specific Device Code A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week

Device Package Shipping

ORDERING INFORMATION

MC140XXBCP PDIP–14 2000/Box MC140XXBD SOIC–14

2750/Box MC140XXBDR2 SOIC–14 2500/Tape & Reel MC140XXBF SOEIAJ–14 See Note 1.

MARKING

DIAGRAMS

PDIP–14

P SUFFIX

CASE 646

MC140XXBCP

AWLYYWW

SOIC–14

D SUFFIX

CASE 751A

140XXB

AWLYWW

SOEIAJ–14

F SUFFIX

CASE 965

MC140XXB

AWLYWW

MC140XXBFEL SOEIAJ–14 See Note 1.

1. For ordering information on the EIAJ version of

the SOIC packages, please contact your local ON Semiconductor representative.

MC14070B, MC14077B

http://onsemi.com

PIN ASSIGNMENT

105

OUT

IN 1

IN 2

IN 1

IN 2

OUT

IN 2

IN 1

IN 2

IN 1

Figure 1. Power Dissipation Test Circuit and Waveform

20 ns 20 ns

90%

50%

10%

1/f

50% DUTY CYCLE

*Inverted output on MC14077B only.

Figure 2. Switching Time Test Circuit and Waveforms

20 ns

90%

OUTPUT

20 ns

THL

TLH

50%

10%

90%

50%

10%

PLH

PHL

INPUT

*Inverted output on MC14077B only.

PULSE

GENERATOR

#Connect unused input to V

for MC14070B, to VSS for MC14077B.

MC14070B

QUAD Exclusive OR

Gate

MC14077B

QUAD Exclusive NOR

Gate

= PIN 14

= PIN 7

(BOTH DEVICES)

MC14070B, MC14077B

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ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

)

– 55_C

25_C

125_C

Characteristic

Symbol

Vdc

Min

Max

Min

Typ

(4.)

Max

Min

Max

Unit

ООООООООО

Output Voltage “0” Level

= VDD or 0

ÎÎ

5.0 10 15

ÎÎ

— — —

0.05

— — —

ÎÎ

0 0 0

0.05

— — —

0.05

Vdc

ООООООООО

“1” Level

= 0 or V

ÎÎ

5.0 10 15

ÎÎ

4.95

9.95

14.95

— — —

4.95

9.95

14.95

ÎÎ

5.0 10 15

— — —

4.95

9.95

14.95

— — —

Vdc

ООООООООО

Input Voltage “0” Level

= 4.5 or 0.5 Vdc)

= 9.0 or 1.0 Vdc)

= 13.5 or 1.5 Vdc)

ÎÎ

5.0 10 15

ÎÎ

— — —

1.5

3.0

4.0

— — —

ÎÎ

2.25

4.50

6.75

1.5

3.0

4.0

— — —

1.5

3.0

4.0

Vdc

ООООООООО

“1” Level

= 0.5 or 4.5 Vdc)

= 1.0 or 9.0 Vdc)

= 1.5 or 13.5 Vdc)

ÎÎ

5.0 10 15

ÎÎ

3.5

7.0 11

— — —

3.5

7.0 11

ÎÎ

2.75

5.50

8.25

— — —

3.5

7.0 11

— — —

Vdc

ООООООООО

Output Drive Current

= 2.5 Vdc) Source

= 4.6 Vdc)

= 9.5 Vdc)

= 13.5 Vdc)

ÎÎ

5.0

5.0 10 15

ÎÎ

– 3.0

– 0.64

– 1.6 – 4.2

— — — —

– 2.4

– 0.51

– 1.3 – 3.4

ÎÎ

– 4.2 – 0.88 – 2.25

– 8.8

— — — —

– 1.7

– 0.36

– 0.9 – 2.4

— — — —

mAdc

ООООООООО

(VOL = 0.4 Vdc) Sink (V

= 0.5 Vdc)

= 1.5 Vdc)

ÎÎ

5.0 10 15

ÎÎ

0.64

1.6

4.2

— — —

0.51

1.3

3.4

ÎÎ

0.88

2.25

8.8

— — —

0.36

0.9

2.4

— — —

mAdc

Input Current

—

± 0.1

—

±0.00001

± 0.1

—

± 1.0

µAdc

ООООООООО

Input Capacitance

= 0)

ÎÎ

—

ÎÎ

—

ÎÎ

5.0

7.5

—

ООООООООО

Quiescent Current

(Per Package)

ÎÎ

5.0 10 15

ÎÎ

— — —

0.25

0.5

1.0

— — —

ÎÎ

0.0005

0.0010

0.0015

0.25

0.5

1.0

— — —

7.5 15 30

µAdc

ООООООООО

Total Supply Current

(5.) (6.)

(Dynamic plus Quiescent, Per Package) (C

= 50 pF on all outputs, all

buffers switching)

ÎÎ

5.0 10 15

ООООООООООООООО

IT = (0.3 µA/kHz) f + I

IT = (0.6 µA/kHz) f + I

IT = (0.9 µA/kHz) f + I

µAdc

ООООООООО

Output Rise and Fall Times

(5.)

(CL = 50 pF)

TLH

, t

THL

= (1.35 ns/pF) CL + 33 ns

TLH

, t

THL

= (0.60 ns/pF) CL + 20 ns

TLH

, t

THL

= (0.40 ns/pF) CL + 20 ns

ÎÎ

TLH

THL

5.0 10 15

ÎÎ

— — —

ÎÎ

100

50 40

200 100

— — —

ООООООООО

Propagation Delay Times

(5.)

(CL = 50 pF)

PLH

, t

PHL

= (0.90 ns/pF) CL + 130ns

PLH

, t

PHL

= (0.36 ns/pF) CL + 57 ns

PLH

, t

PHL

= (0.26 ns/pF) CL + 37 ns

ÎÎ

PLH

PHL

5.0 10 15

ÎÎ

— — —

ÎÎ

175

75 55

350 150 110

— — —

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF: I

T(CL

) = IT(50 pF) + (CL – 50) Vfk

where: I

is in µH (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

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