MOTOROLA MC14015BFEL, MC14015BFL1, MC14015BFL2, MC14015BFR1, MC14015BCP Datasheet

...

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 3

1 Publication Order Number:

MC14015B/D

MC14015B

Dual 4-Bit Static Shift Register

The MC14015B dual 4–bit static shift register is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. It consists of two identical, independent 4–state serial–input/parallel–output registers. Each register has independent Clock and Reset inputs with a single serial Data input. The register states are type D master–slave flip–flops. Data is shifted from one stage to the next during the positive–going clock transition. Each register can be cleared when a high level is applied on the Reset line. These complementary MOS shift registers find primary use in buffer storage and serial–to–parallel conversion where low power dissipation and/or noise immunity is desired.

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Logic Edge–Clocked Flip–Flop Design —

Logic state is retained indefinitely with clock level either high or low; information is transferred to the output only on the positive going edge of the clock pulse.

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range.

MAXIMUM RATINGS (Voltages Referenced to V

) (Note 2.)

Symbol Parameter Value Unit

DC Supply Voltage Range –0.5 to +18.0 V

Vin, V

out

Input or Output Voltage Range

(DC or Transient)

–0.5 to VDD + 0.5 V

Iin, I

out

Input or Output Current

(DC or Transient) per Pin

±10 mA

Power Dissipation,

per Package (Note 3.)

500 mW

Ambient Temperature Range –55 to +125 °C

stg

Storage Temperature Range –65 to +150 °C

Lead Temperature

(8–Second Soldering)

260 °C

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, V

and V

out

should be constrained

to the range V

v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V

or VDD). Unused outputs must be left open.

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A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week

Device Package Shipping

ORDERING INFORMATION

MC14015BCP PDIP–16 2000/Box MC14015BD SOIC–16 48/Rail MC14015BDR2 SOIC–16 2500/Tape & Reel

1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.

MARKING

DIAGRAMS

PDIP–16

P SUFFIX

CASE 648

MC14015BCP

AWLYYWW

SOIC–16

D SUFFIX

CASE 751B

14015B

AWLYWW

SOEIAJ–16

F SUFFIX

CASE 966

MC14015B

AWLYWW

TSSOP–16 DT SUFFIX

CASE 948F

015B

ALYW

MC14015BDT TSSOP–16 2000/Tape & Reel MC14015BF SOEIAJ–16 See Note 1. MC14015BFEL SOEIAJ–16 See Note 1.

MC14015B

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TRUTH TABLE

C D R Q0 Q

0 0 0 Q

n–1

1 0 1 Q

n–1

X 0 No Change No Change

X X 1 0 0

X = Don’t Care Q

= Q0, Q1, Q2, or Q3, as applicable.

n–1

= Output of prior stage.

BLOCK DIAGRAM

5 4 3 10

13 12 11 2

Q0 Q1 Q2 Q3

= PIN 16

= PIN 8

PIN ASSIGNMENT

125

MC14015B

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ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

)

– 55_C

25_C

125_C

Characteristic

Symbol

Vdc

Min

Max

Min

Typ

(4.)

Max

Min

Max

Unit

ОООООООО

Output Voltage “0” Level

= VDD or 0

ÎÎ

5.0 10 15

— — —

0.05

ÎÎ

— — —

0 0 0

ÎÎ

0.05

— — —

0.05

Vdc

ОООООООО

Vin = 0 or V

“1” Level

ÎÎ

5.0 10 15

4.95

9.95

14.95

— — —

ÎÎ

4.95

9.95

14.95

5.0 10 15

ÎÎ

— — —

4.95

9.95

14.95

— — —

Vdc

ОООООООО

Input Voltage “0” Level

= 4.5 or .05 Vdc)

= 9.0 or 1.0 Vdc)

= 13.5 or 1.5 Vdc)

ÎÎ

5.0 10 15

— — —

1.5

3.0

4.0

ÎÎ

— — —

2.25

4.50

6.75

ÎÎ

1.5

3.0

4.0

— — —

1.5

3.0

4.0

Vdc

ОООООООО

(VO = 0.5 or 4.5 Vdc) “1” Level (V

= 1.0 or 9.0 Vdc)

= 1.5 or 13.5 Vdc)

ÎÎ

5.0 10 15

3.5

7.0 11

— — —

ÎÎ

3.5

7.0 11

2.75

5.50

8.25

ÎÎ

— — —

3.5

7.0 11

— — —

Vdc

ОООООООО

Output Drive Current

= 2.5 Vdc) Source

= 4.6 Vdc)

= 9.5 Vdc)

= 13.5 Vdc)

ÎÎ

5.0

5.0 10 15

– 3.0

– 0.64

– 1.6 – 4.2

— — — —

ÎÎ

– 2.4

– 0.51

– 1.3 – 3.4

– 4.2 – 0.88 – 2.25

– 8.8

ÎÎ

— — — —

– 1.7

– 0.36

– 0.9 – 2.4

— — — —

mAdc

ОООООООО

(VOL = 0.4 Vdc) Sink (V

= 0.5 Vdc)

= 1.5 Vdc)

ÎÎ

5.0 10 15

0.64

1.6

4.2

— — —

ÎÎ

0.51

1.3

3.4

0.88

2.25

8.8

ÎÎ

— — —

0.36

0.9

2.4

— — —

mAdc

Input Current

—

± 0.1

—

±0.00001

± 0.1

—

± 1.0

µAdc

Input Capacitance

= 0)

—

5.0

7.5

—

ОООООООО

Quiescent Current

(Per Package)

ÎÎ

5.0 10 15

— — —

5.0 10 20

ÎÎ

— — —

0.005

0.010

0.015

ÎÎ

5.0 10 20

— — —

150 300 600

µAdc

ОООООООО

Total Supply Current

(5.) (6.)

(Dynamic plus Quiescent, Per Package) (C

= 50 pF on all outputs, all

buffers switching)

ÎÎ

5.0 10 15

ООООООООООООООО

IT = (1.2 µA/kHz)f + I

IT = (2.4 µA/kHz)f + I

IT = (3.6 µA/kHz)f + I

µAdc

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF: I

T(CL

) = IT(50 pF) + (CL – 50) Vfk

where: I

is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

MC14015B

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SWITCHING CHARACTERISTICS

(7.)

= 50 pF, T

= 25_C)

Characteristic

Symbol

Min

Typ

(8.)

Max

Unit

ООООООООООООО

Output Rise and Fall Time

TLH

, t

THL

= (1.5 ns/pF) CL + 25 ns

TLH

, t

THL

= (0.75 ns/pF) CL + 12.5 ns

TLH

, t

THL

= (0.55 ns/pF) CL + 9.5 ns

ÎÎÎ

TLH

THL

ÎÎ

5.0 10 15

ÎÎ

— — —

ÎÎ

100

50 40

ÎÎ

200 100

ООООООООООООО

Propagation Delay Time

Clock, Data to Q

PLH

, t

PHL

= (1.7 ns/pF) CL + 225 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 92 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 65 ns

Reset to Q

PLH

, t

PHL

= (1.7 ns/pF) CL + 375 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 147 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 95 ns

ÎÎÎ

PLH

PHL

ÎÎ

5.0 10 15

ÎÎ

— — —

ÎÎ

310 125

460 180 120

ÎÎ

750 250 170

ООООООООООООО

Clock Pulse Width

ÎÎÎ

ÎÎ

5.0 10 15

ÎÎ

400 175 135

ÎÎ

185

85 55

ÎÎ

— — —

ООООООООООООО

Clock Pulse Frequency

ÎÎÎ

ÎÎ

5.0 10 15

ÎÎ

— — —

ÎÎ

2.0

6.0

7.5

ÎÎ

1.5

3.0

3.75

MHz

ООООООООООООО

Clock Pulse Rise and Fall Times

ÎÎÎ

TLH

, t

THL

ÎÎ

5.0 10 15

ÎÎ

— — —

ÎÎ

— — —

ÎÎ

5 4

µs

ООООООООООООО

Reset Pulse Width

ÎÎÎ

ÎÎ

5.0 10 15

ÎÎ

400 160 120

ÎÎ

200

80 60

ÎÎ

— — —

ООООООООООООО

Setup Time

ÎÎÎ

ÎÎ

5.0 10 15

ÎÎ

350 100

ÎÎ

100

50 40

ÎÎ

— — —

7. The formulas given are for typical characteristics only at 25_C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Figure 1. Power Dissipation Test Circuit and Waveform

PULSE

GENERATOR

CLOCK

DATA

50%

PULSE

GENERATOR

500 µF

0.01 µF CERAMIC

Q0 Q1 Q2 Q3

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