MOTOROLA MC14012BF, MC14012BCP, MC14012BD, MC14012BDR2, MC14012BFEL Datasheet

MC14012B

B-Suffix Series CMOS Gates

The B Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high noise immunity is desired.

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• All Outputs Buffered

• Capable of Driving T wo Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated T emperature Range.

• Double Diode Protection on All Inputs

• Pin–for–Pin Replacements for Corresponding CD4000 Series B

Suffix Devices

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PDIP–14

P SUFFIX

CASE 646

MARKING

DIAGRAMS

MC14012BCP

AWLYYWW

MAXIMUM RATINGS (Voltages Referenced to V

Symbol

Vin, V

Iin, I

stg

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, V to the range V

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V

DC Supply Voltage Range –0.5 to +18.0 V Input or Output Voltage Range

out

Input or Output Current

out

Power Dissipation,

Ambient Temperature Range –55 to +125 °C

Storage Temperature Range –65 to +150 °C Lead Temperature

or VDD). Unused outputs must be left open.

Parameter Value Unit

(DC or Transient)

(DC or Transient) per Pin

per Package (Note 3.)

(8–Second Soldering)

v (Vin or V

) v VDD.

out

) (Note 2.)

–0.5 to VDD + 0.5 V

±10 mA

500 mW

260 °C

and V

should be constrained

out

SOIC–14

D SUFFIX

CASE 751A

SOEIAJ–14

F SUFFIX

CASE 965

A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week

14012B

AWLYWW

MC14012B

AWLYWW

ORDERING INFORMATION

Device Package Shipping

MC14012BCP PDIP–14 2000/Box MC14012BD SOIC–14 MC14012BDR2 SOIC–14 2500/Tape & Reel MC14012BF SOEIAJ–14 See Note 1.

55/Rail

 Semiconductor Components Industries, LLC, 2000

April, 2000 – Rev. 3

MC14012BFEL SOEIAJ–14 See Note 1.

1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.

1 Publication Order Number:

MC14012B/D

MC14012B

Dual 4–Input NAND Gate

OUT

IN 1

IN 2

IN 3

IN 4

NC = NO CONNECTION

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

Characteristic

Output Voltage “0” Level

ОООООООО

= VDD or 0

ОООООООО

= 0 or V

ОООООООО

Input Voltage “0” Level

= 4.5 or 0.5 Vdc)

ОООООООО

= 9.0 or 1.0 Vdc)

ОООООООО

= 13.5 or 1.5 Vdc)

= 0.5 or 4.5 Vdc)

ОООООООО

= 1.0 or 9.0 Vdc)

ОООООООО

= 1.5 or 13.5 Vdc)

Output Drive Current

= 2.5 Vdc) Source

ОООООООО

= 4.6 Vdc)

ОООООООО

= 9.5 Vdc)

= 13.5 Vdc)

ОООООООО

(VOL = 0.4 Vdc) Sink (V

= 0.5 Vdc)

= 1.5 Vdc)

ОООООООО

Input Current Input Capacitance

= 0)

ОООООООО

Quiescent Current

(Per Package)

ОООООООО

Total Supply Current

(Dynamic plus Quiescent,

ОООООООО

Per Gate, C

= 50 pF)

“1” Level

(5.) (6.)

OUT

IN 4

IN 3 IN 2

105

IN 1

Symbol

ÎÎ

B B B B B

)

V Vdc

5.0

10 15

5.0 10

5.0

10 15

5.0 10 15

15 —

5.0 10 15

5.0 10

– 55_C

Min

—

— —

4.95

9.95

14.95

—

3.5

7.0

– 3.0

– 0.64

– 1.6 – 4.2

0.64

1.6

4.2

— —

— — —

Max

0.05

1.5

3.0

4.0

± 0.1

0.25

0.5

1.0

Min

ÎÎ

— — —

— — — —

—

4.95

9.95

ÎÎ

14.95

ÎÎ

– 2.4

ÎÎ

– 0.51

ÎÎ

– 1.3 – 3.4

ÎÎ

0.51 — —

ÎÎ

—

ÎÎ

IT = (0.3 µA/kHz) f + IDD/N

ООООООООООООООО

I I

2 3

4 5

10 11

= PIN 14

= PIN 7

25_C

(4.)

Typ

— — —

0 0

ÎÎ

5.0 10

— — —

3.5

7.0 11

2.25

4.50

6.75

2.75

5.50

8.25

– 4.2

– 0.88

– 2.25

– 8.8

ÎÎ

0.88

1.3

3.4 — —

— — —

= (0.6 µA/kHz) f + IDD/N

= (0.9 µA/kHz) f + IDD/N

2.25

8.8

±0.00001

5.0

0.0005

0.0010

0.0015

ÎÎ

± 0.1

ÎÎ

NC = 6, 8

Max

0.05

0.05 —

— —

1.5

3.0

4.0

— — —

— — — —

— — —

7.5

0.25

0.5

1.0

Min

—

— —

4.95

9.95

14.95

—

3.5

7.0

– 1.7

– 0.36

– 0.9 – 2.4

0.36

0.9

2.4

— —

— — —

125_C

Max

0.05

± 1.0

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25_C.

6. To calculate total supply current at loads other than 50 pF: ) = IT(50 pF) + (CL – 50) Vfk

T(CL

where: I

is in µA (per package), CL in pF , V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per

package.

— — —

1.5

3.0

4.0

— — —

— — — —

— — —

—

7.5 15 30

Unit

Vdc

mAdc

µAdc

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MC14012B

B–SERIES GATE SWITCHING TIMES

SWITCHING CHARACTERISTICS

ООООООООООООО

Characteristic

(7.)

= 50 pF, T

Output Rise Time

= (1.35 ns/pF) CL + 33 ns

TLH

ООООООООООООО

= (0.60 ns/pF) CL + 20 ns

TLH

ООООООООООООО

= (0.40 ns/PF) CL + 20 ns

TLH

Output Fall Time

= (1.35 ns/pF) CL + 33 ns

ООООООООООООО

THL

= (0.60 ns/pF) CL + 20 ns

THL

ООООООООООООО

= (0.40 ns/pF) CL + 20 ns

THL

Propagation Delay Time

ООООООООООООО

, t

PLH

ООООООООООООО

PLH

= (0.90 ns/pF) CL + 115 ns

PHL

, t

= (0.36 ns/pF) CL + 47 ns

PHL

, t

= (0.26 ns/pF) CL + 37 ns

PHL

= 25_C)

ÎÎÎ

Symbol

TLH

ÎÎÎ

THL

ÎÎÎ

, t

PLH

ÎÎÎ

PHL

ÎÎ

Vdc

5.0

ÎÎ

5.0 10

ÎÎ

5.0 10

ÎÎ

Min

—

ÎÎ

—

ÎÎ

—

ÎÎ

— —

ÎÎ

—

ÎÎ

— —

ÎÎ

—

ÎÎ

(8.)

Typ

100

ÎÎ

100

ÎÎ

160

ÎÎ

Max

200

ÎÎ

100

ÎÎ

200 100

ÎÎ

300 130

ÎÎ

100

7. The formulas given are for the typical characteristics only at 25_C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

PULSE

GENERATOR

INPUT

OUTPUT

VSS7

*All unused inputs of AND, NAND gates must be connected to VDD.

All unused inputs of OR, NOR gates must be connected to V

INVERTING

NON–INVERTING

20 ns 20 ns

INPUT

PHL

OUTPUT

THL

OUTPUT

PLH

TLH

50%

10%

90%

50%

10%

50%

10%

90%

PLH

TLH

PHL

THL

Unit

V 0 V

V V

Figure 1. Switching Time Test Circuit and Waveforms

CIRCUIT SCHEMATIC

MC14012B

One of Two Gates Shown

2, 9

3, 10

4, 11

5, 12

SAME AS

ABOVE

*Inverter omitted

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