MOTOROLA MC10124FNR2 Datasheet
SEMICONDUCTOR TECHNICAL DATA
3–82
REV 5
Motorola, Inc. 1996
3/93
The MC10124 is a quad translator for interfacing data and control signals
between a saturated logic section and the MECL section of digital systems. The
MC10124 has TTL compatible inputs, and MECL complementary open–emitter
outputs that allow use as an inverting/ non–inverting translator or as a
differential line driver . When the common strobe input is at the low logic level, it
forces all true outputs to a MECL low logic state and all inverting outputs to a
MECL high logic state.
Power supply requirements are ground, +5.0 Volts, and –5.2 Volts.
Propagation delay of the MC10124 is typically 3.5 ns. The dc levels are
standard or Schottky TTL in, MECL 10,000 out.
An advantage of this device is that TTL level information can be transmitted
differentially , via balanced twisted pair lines, to the MECL equipment, where the
signal can be received by the MC10115 or MC10116 differential line receivers.
The MC10124 is useful in computers, instrumentation, peripheral controllers,
test equipment, and digital communications systems.
PD= 380 mW typ/pkg (No Load)
tpd= 3.5 ns typ (+ 1.5 Vdc in to 50% out)
tr, tf= 2.5 ns typ (20%–80%)
LOGIC DIAGRAM
Gnd = PIN 16
VCC (+5.0Vdc) = PIN 9
VEE (–5.2Vdc) = PIN 8
11
13
14
10
12
15
7
3
1
6
5
4
2
DIP
PIN ASSIGNMENT
B
OUT
A
OUT
B
OUT
A
OUT
A
IN
COMMON
STROBE
B
IN
V
EE
GND
C
OUT
D
OUT
D
OUT
C
OUT
D
IN
C
IN
V
CC
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
T ables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
MC10124
3–83 MOTOROLAMECL Data
DL122 — Rev 6
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
–30°C +25°C +85°C
Characteristic Symbol
Under
Test
Min Max Min Typ Max Min Max
Unit
Negative Power Supply Drain
Current
I
E
8 72 66 72 mAdc
Positive Power Supply Drain
I
CCH
9 16 16 18 mAdc
pp y
Current
I
CCL
9 25 25 25 mAdc
Reverse Current I
R
6
7
200
50
200
50
20050µAdc
Forward Current I
F
6
7
–12.8
–3.2
–12.8
–3.2
–12.8
–3.2
mAdc
Input Breakdown Voltage BV
in
6
7
5.5
5.5
5.5
5.5
5.5
5.5
Vdc
Clamp Input Voltage V
I
6
7
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
Vdc
High Output Voltage V
OH
1
3
–1.060
–1.060
–0.890
–0.890
–0.960
–0.960
–0.810
–0.810
–0.890
–0.890
–0.700
–0.700
Vdc
Low Output Voltage V
OL
1
3
–1.890
–1.890
–1.675
–1.675
–1.850
–1.850
–1.650
–1.650
–1.825
–1.825
–1.615
–1.615
Vdc
High Threshold Voltage V
OHA
1
3
–1.080
–1.080
–0.980
–0.980
–0.910
–0.910
Vdc
Low Threshold Voltage V
OLA
1
3
–1.655
–1.655
–1.630
–1.630
–1.595
–1.595
Vdc
Switching Times (50Ω Load) ns
Propagation Delay
(+3.5Vdc to 50%)
1
t
6+1+
t
6–1–
t
7+1+
t
7–1–
t
7+3–
t
7–3+
1
1
1
1
3
3
1.5
1.0
1.5
1.0
1.5
1.0
6.8
6.0
6.8
6.0
6.8
6.0
1.0
1.0
1.0
1.0
1.0
1.0
3.5
3.5
3.5
3.5
3.5
3.5
6.0
6.0
6.0
6.0
6.0
6.0
1.0
1.5
1.0
1.5
1.0
1.5
6.0
6.8
6.0
6.8
6.0
6.8
Rise Time (20 to 80%) t
1+
1 1.0 4.2 1.1 2.5 3.9 1.1 4.3
Fall Time (20 to 80%) t
1–
1 1.0 4.2 1.1 2.5 3.9 1.1 4.3
1. See switching time test circuit. Propagation delay for this circuit is specified from +1.5Vdc in to the 50% point on the output waveform. The
+3.5Vdc is shown here because all logic and supply levels are shifted 2 volts positive.
MC10124
MOTOROLA MECL Data
DL122 — Rev 6
3–84
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature V
IH
V
ILmax
V
IHA’
V
ILA’
V
F
–30°C +4.0 +0.40 +2.00 +1.10 +0.40
+25°C +4.0 +0.40 +1.80 +1.10 +0.40
+85°C +4.0 +0.40 +1.80 +0.90 +0.40
Pin
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
Characteristic Symbol
Und
er
Test
V
IH
V
ILmax
V
IHA’
V
ILA’
V
F
Gnd
Negative Power Supply Drain
Current
I
E
8 16
Positive Power Supply Drain
I
CCH
9 5,6,7,10,1 1 16
pp y
Current
I
CCL
9
5,6,7,10,11,16
Reverse Current I
R
6
7
5,7,10,1 1
6
16
16
Forward Current I
F
6
7
5,7,10,1 1
6
6
7
16
16
Input Breakdown Voltage BV
in
6
7
5,7,10,1 1,16
6,16
Clamp Input Voltage V
I
6
7
16
16
High Output Voltage V
OH
1
3
6,7
6,7
16
16
Low Output Voltage V
OL
1
3
6,7
6,7 16
16
High Threshold Voltage V
OHA
1
3
6
6
7
7
16
16
Low Threshold Voltage V
OLA
1
3
6
6
7
7 16
16
Switching Times (50Ω Load) +6.0 V Pulse In Pulse Out +2.0 V
Propagation Delay
(+3.5Vdc to 50%)
1
t
6+1+
t
6–1–
t
7+1+
t
7–1–
t
7+3–
t
7–3+
1
1
1
1
3
3
7
7
6
6
6
6
6
6
7
7
7
7
1
1
1
1
3
3
16
16
16
16
16
16
Rise Time (20 to 80%) t
1+
1 6 7 1 16
Fall Time (20 to 80%) t
1–
1 6 7 1 16
1. See switching time test circuit. Propagation delay for this circuit is specified from +1.5Vdc in to the 50% point on the output waveform. The
+3.5Vdc is shown here because all logic and supply levels are shifted 2 volts positive.
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