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MC100EP139
Product Preview
÷
2/4,÷4/5/6 Clock
Generation Chip
The MC100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by
either a differential or single–ended ECL or, if positive power supplies
are used, L VPECL input signals. In addition, by using the VBB output,
a sinusoidal source can be AC coupled into the device. If a
single–ended input is to be used, the VBB output should be connected
to the CLK
The common enable (EN) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. The internal enable
flip–flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of
the clock input.
Upon startup, the internal flip–flops will attain a random state;
therefore, for systems which utilize multiple EP139s, the master reset
(MR) input must be asserted to ensure synchronization. For systems
which only use one EP139, the MR pin need not be exercised as the
internal divider design ensures synchronization between the ÷2/4 and
the ÷4/5/6 outputs of a single device. All VCC and VEE pins must be
externally connected to power supply to guarantee proper operation.
• 50ps Output–to–Output Skew
• PECL mode: 3.0V to 5.5V V
• ECL mode: 0V V
• Synchronous Enable/Disable
• Master Reset for Synchronization of Multiple Chips
• Q Output will default LOW with inputs open or at V
• ESD Protection: >2KV HBM, >100V MM
• V
• New Differential Input Common Mode Range
• Moisture Sensitivity Level 2
For Additional Information, See Application Note AND8003/D
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 758 devices
input and bypassed to ground via a 0.01µF capacitor.
with VEE = 0V
CC
with VEE = –3.0V to –5.5V
CC
Output
BB
EE
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TSSOP–20
DT SUFFIX
CASE 948E
MARKING DIAGRAM
KEP
139
ALYW
A = Assembly Location
L = Wafer Lot
Y = Y ear
W = Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device Package Shipping
MC100EP139DT TSSOP 75 Units/Rail
MC100EP139DTR2 TSSOP 2500 Tape/Reel
MC100EP139DW SOIC 38 Units/Rail
MC100EP139DWR2 SOIC 2500 Tape/Reel
A = Assembly Location
WL = Wafer Lot
YY = Year
WW= Work Week
SO–20
DW SUFFIX
CASE 751D
MC100EP139
AWLYWW
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 1
1 Publication Order Number:
MC100EP139/D
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MC100EP139
V
Q0
CC
V
CC
Q0
1920
21
EN
DIVSELb0
Figure 1. 20–Lead SOIC (Top View)
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
FUNCTION TABLES
CLK EN FUNCTION
Z
ZZ
X
Z = Low–to–High Transition
ZZ = High–to–Low Transition
DIVSELa Q0:1 OUTPUTS
0
1
DIVSELb0 Q2:3 OUTPUTS
0
1
0
1
L
H
X
Divide by 2
Divide by 4
DIVSELb1
MR
L
Divide
L
Hold Q0:3
H
Reset Q0:3
0
0
1
1
Divide by 4
Divide by 6
Divide by 5
Divide by 5
Q1 Q1 Q2 Q2 Q3 Q3 V
1718 16 15 14 13 12
43
56789
CLK
CLK MR V
V
BB
CC
DIVSELb1
PIN DESCRIPTION
PIN
CLK, CLK
EN ECL Sync Enable
MR
V
BB
Q0, Q1, Q0, Q1
Q2, Q3, Q2, Q3 ECL Diff ÷4/5/6 Outputs
DIVSELa
DIVSELb0 ECL Freq. Select Input B4/5/6
DIVSELb1 ECL Freq. Select Input B4/5/6
V
CC
V
EE
ECL Diff Clock Inputs
ECL Master Reset
ECL Reference Output
ECL Diff ÷2/4 Outputs
ECL Freq. Select Input B2/4
ECL Positive Supply
ECL Negative, 0 Supply
EE
11
10
DIVSELa
FUNCTION
DIVSELa
CLK
CLK
EN
MR
DIVSELb0
DIVSELb1
Figure 2. Logic Diagram
÷2/4
÷4/5/6
R
Q0
R
Q0
Q1
Q1
Q2
Q2
Q3
Q3
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CLK
Q (÷2)
Q (÷4)
Q (÷5)
Q (÷6)
CLK
RESET
Q (÷n)
MC100EP139
Figure 3. Timing Diagram
t
RR
Figure 4. Timing Diagram
MAXIMUM RATINGS*
Symbol Parameter Value Unit
V
EE
V
CC
V
I
V
I
I
out
I
BB
T
A
T
stg
θJA (DT Suffix) Thermal Resistance (Junction–to–Ambient) Still Air
θJC (DT Suffix) Thermal Resistance (Junction–to–Case) 23 to 41 ± 5% °C/W
θJA (DW Suffix) Thermal Resistance (Junction–to–Ambient) Still Air
θJC (DW Suffix) Thermal Resistance (Junction–to–Case) 33 to 35 ± 5% °C/W
T
sol
* Maximum Ratings are those values beyond which damage to the device may occur.
{
Use for inputs of same package only.
Power Supply (VCC = 0V) –6.0 to 0 VDC
Power Supply (VEE = 0V) 6.0 to 0 VDC
Input Voltage (VCC = 0V, VI not more negative than VEE) –6.0 to 0 VDC
Input Voltage (VEE = 0V, VI not more positive than VCC) 6.0 to 0 VDC
Output Current Continuous
VBB Sink/Source Current
Operating Temperature Range –40 to +85 °C
Storage Temperature –65 to +150 °C
Solder Temperature (<2 to 3 Seconds: 245°C desired) 265 °C
{
Surge
500lfpm
500lfpm
50
100
± 0.5 mA
140
100
90
60
mA
°C/W
°C/W
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