Motorola MC10E154FN, MC10E154FNR2, MC100E154FNR2, MC100E154FN Datasheet
D
2a
D1aD
1b
LOGIC DIAGRAM
SEL
LEN1
LEN2
V
EE
MR
D
0a
D
0b
26
27
28
2
3
4
25 24 23 22 21 20 19
18
17
16
15
14
13
12
115 6 7 8 9 10
D4bD4aD3bD3aV
CCO
Q
4
Q
4
Q
3
Q
3
V
CC
Q
2
Q
2
Q
1
Q
1
D2bV
CCOQ0
Q
0
D
0a
D
0b
D
1a
D
1b
D
2a
D
2b
D
3a
D
3b
D
4a
D
4b
SEL
LEN1
LEN2
MR
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
Q
4
Q
4
SEL
D
Q
EN
R
Q
D
Q
EN
R
Q
D
Q
EN
R
Q
D
Q
EN
R
Q
D
Q
EN
R
Q
MUX
SEL
MUX
SEL
MUX
SEL
MUX
SEL
MUX
1
Pinout: 28-Lead PLCC (Top View)
* All VCC and V
CCO
pins are tied together on the die.
SEMICONDUCTOR TECHNICAL DATA
2–1
REV 2
Motorola, Inc. 1996
12/93
The MC10E/100E154 contains five 2:1 multiplexers followed by
transparent latches with differential outputs. When both Latch Enables
(LEN1, LEN2) are LOW, the latch is transparent, and output data is
controlled by the multiplexer select control, SEL. A logic HIGH on either
LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR)
overrides all other controls to set the Q outputs LOW.
• 850ps Max. LEN to Output
• 825ps Max. D to Output
• Differential Outputs
• Asynchronous Master Reset
• Dual Latch-Enables
• Extended 100E V
EE
Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
PIN NAMES
Pin Function
D0a– D
4a
Input Data a
D0b– D
4b
Input Data b
SEL Data Select Input
LEN1, LEN2 Latch Enables
MR Master Reset
Q0– Q
4
True Outputs
Q
0
– Q
4
Inverted Outputs
TRUTH TABLE
SEL Data
H
L
a
b
5-BIT 2:1
MUX-LATCH
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
MC10E154 MC100E154
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 4
2–2
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V
CCO
= GND)
0°C 25°C 85°C
Symbol Characteristic min typ max min typ max min typ max Unit Condition
I
IH
Input HIGH Current 150 150 150 µA
I
EE
Power Supply Current mA
10E 76 91 76 91 76 91
100E 76 91 76 91 87 105
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V
CCO
= GND)
0°C 25°C 85°C
Symbol Characteristic min typ max min typ max min typ max Unit Condition
t
PLH
Propagation Delay to Output ps
t
PHL
D 325 500 700 325 500 700 325 500 700
SEL 475 650 925 475 650 925 475 650 925
LEN 350 500 750 350 500 750 350 500 750
MR 450 600 800 450 600 800 450 600 800
t
s
Setup Time ps
D 300 100 300 100 300 100
SEL 500 250 500 250 500 250
t
h
Hold Time ps
D 300 –100 300 –100 300 –100
SEL 200 – 250 200 – 250 200 – 250
t
RR
Reset Recovery Time 800 600 800 600 800 600 ps
t
PW
Minimum Pulse Width ps
MR 400 400 400
t
SKEW
Within-Device Skew 50 50 50 ps 1
t
r
Rise/Fall Times ps
t
f
20 - 80% 300 475 800 300 475 800 300 475 800
1. Within-device skew is defined as identical transitions on similar paths through a device.
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