Motorola IC-T81E User Manual

SERVICE
MANUAL

MULTIBAND FM TRANSCEIVER

INTRODUCTION

DANGER

ORDERING PARTS

REPAIR NOTES

This service manual describes the latest service information
for the

IC-T81A/E

at the time of publication.

NEVER connect the transceiver to an AC outlet or to a DC
power supply that uses more than 16 V. Such a connection
could cause a fire hazard and/or electric.

DO NOT expose the transceiver to rain, snow or any liquids.
DO NOT reverse the polarities of the power supply when

connecting the transceiver.
DO NOT apply an RF signal of more than 20 dBm (100mW)

to the antenna connector. This could damage the trans­ceiver's front end.

Be sure to include the following four points when ordering
replacement parts:

1. 10-digit order numbers

2. Component part number and name

3. Equipment model name and unit name

4. Quantity required
<SAMPLE ORDER>

1130009370 S.IC TB31242FN IC-T81A/E RF UNIT 1 pieces
8810008990 Screw PH BT M2x10 ZK IC-T81A/E Chassis 10 pieces

Addresses are provided on the inside back cover for your
convenience.

1. Make sure a problem is internal before disassembling the transceiver.

2. DO NOT open the transceiver until the transceiver is disconnected from its power source.

3. DO NOT force any of the variable components. Turn them slowly and smoothly.

4. DO NOT short any circuits or electronic parts. An insulated turning tool MUST be used for all adjustments.

5. DO NOT keep power ON for a long time when the transceiver is defective.

6. DO NOT transmit power into a signal generator or a sweep generator.

7. ALWAYS connect a 40 dB to 50 dB attenuator between the transceiver and a deviation meter or spectrum analyzer when
using such test equipment.

8. READ the instructions of test equipment thoroughly before connecting equipment to the transceiver.

To upgrade quality, all electrical or mechanical parts and
internal circuits are subject to change without notice or
obligation.

MODEL

IC-T81A

IC-T81E

VERSION

U.S.A.
Australia
S.E.Asia

Europe

U.K.
Italy

SYMBOL

USA-1

AUS
SEA
EUR

UK
ITA

TABLE OF CONTENTS

SECTION 1 SPECIFICATIONS

SECTION 2 INSIDE VIEWS

SECTION 3 DISASSEMBLY INSTRUCTIONS

SECTION 4 CIRCUIT DESCRIPTION

4-1 RECEIVER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1

4-2 TRANSMITTER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3

4-3 PLLCIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5

4-4 POWER SUPPLY CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5

4-5 PORT ALLOCATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6

SECTION 5 ADJUSTMENT PROCEDURES

5-1 PREPARATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1

5-2 PLLADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2

5-3 RECEIVER ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4

5-4 TRANSMITTER ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8

SECTION 6 PARTS LIST

SECTION 7 MECHANICAL PARTS AND DISASSEMBLY

SECTION 8 SEMI-CONDUCTOR INFORMATION

SECTION 9 BOARD LAYOUTS

9-1 LOGIC UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1

9-2 RF UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3

9-3 VCO BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5

SECTION 10 BLOCK DIAGRAM

SECTION 11 VOLTAGE DIAGRAM

11-1 LOGIC UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1

11-2 RF UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-2

M GENERAL

• Frequency range :

*1Specifications guaranteed 144 – 148 MHz, *2Specifications guaranteed 430 – 440 MHz
*3Specifications guaranteed 440 – 450 MHz, *4Not guaranteed

• Mode : FM and AM (RX only), WFM (Rx only)

• No. of memory channels : 124 (incl. 10 pairs of scan edges and 4 call channels)

• Frequency stability : ±3 ppm max.

(–10˚C to +60˚C; 14˚F to 140˚F)

• Tuning steps : 5*, 10, 12.5, 15*, 20, 25, 30, 50 and 100 kHz

*Not available for 1200 MHz band

• Usable tempareture range : –10˚C to +60˚C; 14˚F to 140˚F

• Usable battery pack/case : BP-198, BP-199, BP-200 and BP-197

• Power supply requirement : 4.5 – 16 V DC or specified battery pack

• Polarity : Negative ground

• Frequency resplution : 5 kHz and 12.5 kHz (10 kHz and 12.5 kHz for 1200 MHz band)

• Current drain (at 13.5 V DC) : (typical value)

• Anntena connector : SMA (50 Ω)

• Dimensions

(projections not included)

: 58(W) × 106(H) × 28.5(D) mm;

25⁄16(W) × 43⁄16(H) × 11⁄8(D) in

• Weight (with BP-197/Ant.) : 290 g; 10.2 oz

M TRANSMITTER

• Output power (at 13.5 V DC) : High 5.0 W typical (1.0 W at 1200 MHz band)
Low 1.0 W typical (0.1 W at 1200 MHz band)

• Modulation system :

Variable reactance modulation

• Max. freq. deviation : ±5 kHz

• Spurious Emissions : Less than –60 dB (50 MHz, 144 MHz and 440 MHz)
Less than –40 dB (other)
Less than –50 dB (Europe version at 1200 MHz)

• External MIC connector : 3-conductor 2.5(d) mm (

1

⁄8”); 2 kΩ

SECTION 1 SPECIFICATIONS

1 - 1

Version

U.S.A.

Australia
S.E.Asia

Europe, U.K.

Italy

50 MHz

50 – 53.995
50 – 53.995

50 – 53.995

50 – 52
50 – 52

145 MHz

TX: 144 – 148

RX: 118 – 173.995

*

1

144 – 148

TX: 136 – 173.995

*

1

RX: 118 – 173.995*

1

144 – 146

TX: 136 – 173.995

*

1

RX: 118 – 173.995*

1

440 MHz

TX: 430 – 450

*

3

RX: 400 – 469.995*

3

430 – 440

400 – 469.995

*

2

430 – 440

400 – 469.995

*

2

1200 MHz

1240 – 1300
1240 – 1300

1240 – 1300
1240 – 1300

1240 – 1300

91.5 MHz (RX only)

76 – 107.995

*

4

88 – 107.995*

4

76 – 107.995

*

4

88 – 107.995*

4

88 – 107.995

*

4

TX

RX

High power

Low power

Rated output

Standby

Power saved

50/144 MHz

1.4 A

0.6 A

440 MHz

1.3 A

0.5 A

1200 MHz

0.8 A

0.4 A

220 mA
80 mA (at 9.6 V)
40 mA (at 9.6 V)

1 - 2

M RECEIVER

• Receiver system : Double-conversion superheterodyne

• Intermediate frequency : 1st 69.45 MHz (13.35 MHz: WFM)
2nd 450 kHz

• Sensitivity* : (except spurious points; typical values)

* FM and WFM are measured at 12 dB SINAD, AM is measured at 10 dB S/N.

• Squelch sensitivity : 50, 144, 440 MHz Less than 0.18 µV (Threshold)
1200 MHz Less than 0.25 µV (Threshold)
AM (50 MHz only) Less than 0.56 µV (Threshold)
WFM Less than 5.6 µV (Threshold)

• Selectivity (except WFM) : More than 15 kHz/–6 dB
Less than 30 kHz/–60 dB

• Spurious and image rejection ratio : 50, 144 MHz More than 60 dB
440 MHz More than 50 dB
1200 MHz More than 38 dB
(except half IF, 2nd image, 50 MHz band IF and WFM)

• Audio output power : 250 mW typical at 10 % distortion with an 8 Ω load

All stated specifications are subject to change without notice or obligation.

Band

50 MHz
144 MHz
440 MHz

1200 MHz

91.5 MHz

FM

0.18 µV

0.18 µV

0.18 µV

0.25 µV
–

AM

0.56 µV
–
–
–
–

WFM

–
–
–
–

2.0 µV

2 - 2

SECTION 2 INSIDE VIEWS

•

LOGIC UNIT

•

RF UNIT

IF IC
(IC701: TA31136FN)

Crystal filter
(X1: CR-639 5.039MH)

AF power amplifier
(IC201: TA7368F)

AF volume
(IC202: M5222FP)

AF mute switch
(Q361: 2SJ364)

CPU
(IC1: M38267M8LGP)

BOTTOM VIEW

VCO circuit

1st mixer
(IC601: µPC2757T)

WFM RF
amplifier circuit

APC sensor drive amplifier
Q911: UN9215

(

Q913: XP6401

)

PLL IC
(IC801: µPD3140G)

Drive amplifier
(Q921: MRF9745)

Power amplifier
(Q922: 2SK3075)

TOP VIEW

BOTTOM VIEW

APC control
circuit

3 - 1

SECTION 3 DISASSEMBLY INSTRUCTIONS

A

B

Chassis panel

C

E

E

D

Sealing rubber

J1

LOGIC unit

D

Chassis panel

F

F

LOGIC unit

F

Shield plate

•

REMOVING THE CHASSIS PANEL

1 Remove 1 knob A, and unscrew 1 nut B.
2 Unscrew 2 screws C.
3 Remove the chassis panel in the direction of the arrow.

•

REMOVING THE LOGIC UNIT

1 Remove the sealing rubber.
2 Unsolder 1 point, D, to separate a SENSOR control.
3 Unscrew 3 screws, E.
4 Unplug J1 to separate LOGIC unit and RF unit.
5 Remove the LOGIC unit in the direction of the arrow.

•

REMOVING THE RF UNIT

1 Unsolder 1 point, G, to separate [ANT] plug.
2 Unscrew 8 screws, H, to separate the RF unit.
3 Remove the RF unit in the direction of the thick arrow.

•

REMOVING THE SHIELD PLATE

1 Unsolder 10 points, F, to separate the shield plate and

LOGIC unit.

H

H

G

[ANT] plug

RF unit

4 - 1

SECTION 4 CIRCUIT DESCRIPTION

4-1 RECEIVER CIRCUITS

4-1-1 DUPLEXER CIRCUIT (RF UNIT)

The transceiver has a duplexer (low-pass and high-pass fil­ters) on the frist stage from the antenna connector to sepa­rate the signals into below UHF and SHF signals. The high­pass filter (L51–L55, C41–C46 and C48–C50) is for SHF
(1200 MHz) signal and the low-pass filter (C9, C10,
C12–C14 and L7–L9) is for below UHF (50 MHz, 144 MHz,
440 MHz and WFM) signals. The filtered SHF signal is
applied to the low-pass fileter (C51–C54, L56 and L57).

The RF signals below UHF pass through the duplexer circuit
and are separated into VHF (50 MHz, 144 MHz and WFM
band) and UHF (440 MHz band) signals. The high-pass fil­ter (C4–C8, L5, L6) is for UHF (440 MHz band) signal and
the low-pass filter (C15–C20, L10–L12) is for VHF (50 MHz,
144 MHz and WFM band) signals.

The VHF signals are applied to the another duplexer circuit
for separation into 50 MHz and above WFM band signals.
The high-pass filter (C21–C24, C84 and L13–L15) is for 144
MHz and WFM band signals and the low-pass filter
(C27–C33 and L16–L18) is for 50 MHz band signal.

The separated signals are applied to each RF circuits.

4-1-2 ANTENNA SWITCHING CIRCUITS (RF UNIT)

The antenna switching circuit functions as a low-pass filter
while receiving. However, its impeadance becomes very
high while transmitting by applying a current to D101 and
D102 (50 MHz), D302 and D303 (144MHz and WFM), D402
and D403 (440 MHz), D51 and D52 (1200 MHz).

Thus, transmit signals are blocked from entering the receiv­er circuits. The antenna switching circuit employs a 1/4λ
type diode switching system. The passed signals are then
applied to each RF amplifier circuit.

4-1-3 50 MHz BAND RF CIRCUIT (RF UNIT)

The RF circuit amplifies signals within the range of frequen­cy coverage and filters out-of-band signals.

The signals from the antenna switching circuit (D101 and
D102) are amplified at the RF amplifier (Q101). The ampli­fied signals pass through the tunable bandpass filter
(L108–L110, C115, C117, C120, D106, D107) to suppress
out-of-band signals, and are then applied to the 1st mixer
circuit (IC601, pin 1).

4-1-4 144 MHz AND WFM BANDS RF CIRCUITS

(RF UNIT)

The signal from the antenna switching circuit (D302, D303)
are applied to the each band-pass fileters and RF amplifier.

• RF signals 144 MHz band

The 144 MHz band signals are applied to the RF amplifier
(Q301) via the tunable bandpass filter (L303, L304, C306,
D306). The amplified signals pass through the tunable band­pass filter (C318–C321, D309, D310, L305, L306), and are
then applied to the 1st mixer circuit (IC601, pin 1).

• RF CIRCUIT

1st mixer

HPFLPF

ANT
SW

RF

BPF

RF

BPF

ANT

SHF band
(1200 MHz)

LPF

ANT
SW

RF

BPF

RF

UHF band
(440 MHz)

HPF

HPF

ANT
SW

BPF

RF

BPF

VHF band
(144 MHz)

LPF

BPF

RF

BPF

WFM band
(RX only)

ANT

SW

RF

BPF

VHF band
(50 MHz)

LPF

IC601

1st LO

BPF

XTAL

BPF

CERAMIC

D601
Mode
SW

D602
Mode
SW

FM mode

FI601

69.45 NHz

WFM mode

FI602

13.35 NHz

LEVEL
CONV.

D51, D52Q51FI51IC51FI52

D402, D403Q401FI401IC501

D302, D303D306Q301D309, D310

D202Q201 D203

Q101

D106,
D107

D101,
D102

to IF amp.
(Q701)

Q9

"TUNE" signal from IC5, pin 11 (LOGIC unit)

4 - 2

• RF signals WFM band

The WFM band signals are applied to the RF amplifier
(Q201) via the tunable band-pass filter (D202). The ampli­fied signals pass through the tunable bandpass filter (D203),
and are then applied to the 1st mixer circuit (IC601, pin 1).

Varactor diodes (D106, D107, D202, D203, D306, D309,
D310) are employed by the tunable bandpass filter to tune
the center frequency of the bandpass filter. These diodes
are controlled by the PLL lock voltage and obtain good
image response rejection.

4-1-5 440 MHz BAND RF CIRCUIT (RF UNIT)

The signals from the antenna switching circuit (D402 and
D403) are amplified at the RF amplifier (Q401). The ampli­fied signals pass through the bandpass filter (FI401), and
are then applied to the 1st mixer circuit (IC601, pin 1) after
being amplified at another RF amplifier (IC501).

4-1-6 1200 MHz BAND RF CIRCUIT (RF UNIT)

The signals from the antenna switching circuit (D51 and
D52) are amplified at the RF amplifier (Q51). The amplified
signals pass through the bandpass filter (FI51), and are then
applied to the RF amplifier (IC51). The amplified signal is
applied to the 1st mixer circuit (IC601, pin 1) via the band­pass filter (FI52).

4-1-7 1ST MIXER CIRCUIT (RF UNIT)

The 1st mixer circuit converts the received RF signals into a
fixed frequency of the 1st IF signal with a 1st LO output fre­quency. By changing the PLL frequency, only the desired
frequency will pass through at the next stage of the 1st
mixer. 1st mixer circuit produces the different 1st IF signal
for WFM and other band signals.

• 50, 144, 440 and 1200 MHz band

The applied RF signals are mixed with 1st LO signals at the
1st mixer (IC601) to produce a 69.45 MHz 1st IF signal. The
1st IF signal is output from the 1st mixer (IC601, pin 6), and
then passed through the crystal bandpass filter (FI601) to
suppress unwanted harmonic components. The filtered 1st
IF signal is applied to the IF amplifier (IC701). The amplified
signal is applied to the 2nd mixer circuit (LOGIC unit; IC701,
pin 16).

• WFM band

The RF signals are mixed with 1st LO signals at the 1st
mixer (IC601) to produce a 13.35 MHz 1st IF signal. The 1st
IF signal is output from the 1st mixer (IC601, pin 6), and then
passed through the 1st IF filter (FI602) to suppress unwant­ed harmonic components. The filtered signal is applied to
the 2nd mixer circuit (LOGIC unit; IC701, pin 16).

The 1st LO signals are gererated at the VCO circuit which
consists of Q301, Q302, D301, Q311, Q312, D302, D311 for
50 MHz, 144 MHz and WFM, Q321, Q322, D321, D322 for
440 MHz, Q350, D351, D352 for 1200 MHz on the VCO unit.

• The 1st LO signal for 50, 144, 440, WFM band

The 1st LO signals which are generated on the VCO unit are
applied to the buffer-amplifier (Q313 and D312 for 50 MHz,
144 MHz and WFM, Q323 for 440 MHz). The buffer-ampli­fied signals are applied to the LO-amplifier (Q822 for 50
MHz, 144 MHz and WFM, Q823 for 440 MHz), and are then
applied to the 1st mixer circuit via the TX/RX switch (D802
and D803 for 50 MHz, 144 MHz and WFM, D804 and D805
for 440 MHz) on the RF unit.

• The 1st LO signal for 1200 MHz band

The 1st LO signals which are generated on the VCO unit are
applied to the buffer-amplifier (Q351). The buffer-amplified
signals are applied to the doubler circuit (Q353), and pass­es through the high-pass and low-pass filter. The filtered sig­nals are applied to the 1st mixer circuit (Q601) on the LOGIC
unit after being amplified at the LO-amplifier (Q824).

• 2nd IF AND DEMODULATOR CIRCUITS (LOGIC unit)

Mixer

16

Limiter
amp.

2nd IF filter
450 kHz

RSSI

IC701 TA31136FN

13

2nd IF (19.65 MHz)
from Q701 (RF unit)

"SD" signal to the CPU
pin 3

11

10

9

87 5 3

2

Active
filter

FI701

Noise

detector

FM

detector

Noise
comp.

"NOISE" signal to the CPU
pin 12

12

R729

C712

C720

C733

C734

C736

R731

R58

R730

WFM

AF signal to AF filter
(LOGIC unit; IC241)

2nd

Q702

"2nd LO" signal from
IC801, pin 13 (RF unit)

C733

R735

R706

R727

C701

4 - 3

4-1-8 2ND IF AND DEMODULATOR CIRCUITS

(RF AND LOGIC UNITS)

The 2nd mixer circuit converts the 1st IF signal to the 2nd IF
signal. Adouble conversion superheterodyne system (which
converts receive signals twice) improves the image rejection
ratio and obtain stable receiver gain.

The FM IF IC (LOGIC unit; IC701) contains 2nd local oscil­lator, 2nd mixer, limiter amplifier, quadrature detector and S­meter detector circuits.

The filtered 1st IF signal from the 1st IF filter (RF unit; FI601
or FI602) is mixed with the 2nd LO signal at the 2nd mixer
(LOGIC unit; IC701) to produce the 450 kHz 2nd IF signal.
The 2nd IF signal passes through or bypasses (WFM mode
signal) 2nd IF filter (FI701) where unwanted heterodyne sig­nals are suppressed via the mode switch (LOGIC unit;
D701, D702). The filtered signals are applied to the limiter
amplifier section (LOGIC unit; IC701, pin 5), and then
applied to the quadrature detector section to demodulate the
2nd IF signal into AF signals.

The demodulated AF signals are output from pin 9 of the IF
IC (LOGIC unit; IC701) and are applied to the AF circuit.

4-1-9 AF AMPLIFIER CIRCUIT (LOGIC UNIT)

The AF amplifier circuit which is included a low-pass and
high-pass filter, AF mute switch, AF volume controller and
AF amplifier amplifies the demodulated AF signals to drive a
speaker.

The demodulated AF signals (DETO signal) from the FM IF
IC (IC701) are passed through the AF filter (low-pass and
high-pass filters). The filtered signals are applied to the AF
mute switch (Q361) which is controlled by “RM/MM” signals
from the CPU (IC1, pin 31), and are then applied to the elec­tric volume control circuit (IC202, IC203). The level con­trolled AF signals are output from volume IC (IC202, pin 7)
and are then applied to the AF amplifier (IC201, pin 4). The
AF signals are then applied to the internal speaker (SP1) via
the [EXT SP] jack (LOGIC unit; J3) when no plug is con­nected to the jack.

The AF filter circuit (IC241) removes AF signals below 300
Hz (CTCSS signals) for clear AF output and these are
applied to the CPU (IC1, pin4) for CTCSS squelch detection
via the “CTCIN” line.

4-1-10 SQUELCH CIRCUIT (LOGIC UNIT)

• NOISE SQUELCH

The noise squelch circuit cuts out AF signals when no RF
signals are received. By detecting noise components in the
AF signals, the squelch circuit switches the AF mute switch.

A portion of the AF signals from the FM IF IC (IC701, pin 9)
are applied to the active filter section (IC701, pin 7, 8). The
active filter section amplifies and filters noise components.
The filtered signals are applied to the noise detector section
and output from IC701 (pin 13) as “NOISE” signal.

The “NOISE” signal from IC701 (pin 13) is applied to the
CPU (IC1, pin 12). The CPU analyzes the noise condition
and outputs the “RM/MM” signal to AF mute switch (Q361).

Even when the squelch is closed, the AF mute switch
(Q361) opens at the moment of emitting beep tones.

• TONE SQUELCH

The tone squelch circuit detects AF signals and opens the
squelch only when receiving a signal containing a matching
subaudible tone (CTCSS). When tone squelch is in use, and
a signal with a mismatched or no subaudible tone is
received, the tone squelch circuit mutes the AF signals even
when noise squelch is open.

A portion of the AF signals from the FM IF IC (IC701, pin9)
passes through the AF filter (IC241) to remove AF (voice)
signals and is applied to the CTCSS decoder inside the CPU
(IC1, pin 4) via the “CTCIN” line to control the AF mute
switch.

4-2 TRANSMITTER CIRCUITS

4-2-1 MICROPHON AMPLIFIER CIRCUIIT

(LOGIC UNIT)

The microphone amplifier circuit amplifies the audio signals
from the microphone, within +6 dB/octave pre-emphasis
characteristics (300 Hz–3 kHz), to a level needed for the
modulation circuit.

The AF signals from the internal microphone (MC1) or exter­nal [MIC] jack (J4) are applied to the microphone (limiter)
amplifier (IC301, pin 3) which has +6 dB/octave pre-empha­sis characteristics, and are then passed through the low­pass filter (IC301, pin 6 and 7). The filetered signals are
applied to the modulation circuit for each band in the RF unit
via the band switch (Q304: for 144 MHz band, Q305: for
UHF band, Q306: for 50 MHz band, Q309: for 120MHz
band) as the “MOD” signal.

4-2-2 MODULATION CIRCUIT (VCO AND RF UNIT)

The modulation circuit modulates the VCO oscillating signal
(RF signal) using the microphone AF signals.

(1) 50 MHz band

The signals from the limiter amplifier (RF unit; IC301)
changes the reactance of a diode (RF unit; D341) to modu­late the oscillated signal at the 50-VCO circuit (RF unit;
Q341, D341, L341–343). The modulated signals are ampli­fied at the buffer-amplifier (Q342) and the LO amplifier
(Q821). The amplified signals are applied to the drive/power
amplifier circuits for VHF band.

(2) 144 MHz band

The signals from the limiter amplifier (RF unit; IC301)
changes the reactance of a diode (VCO unit; D302) to mod­ulate the oscillated signal at the 144-VCO circuit (VCO unit;
Q311, Q312, D302, D311–D313). The modulated signals
are amplified at the buffer-amplifier (Q312, Q313) and the
LO amplifier (Q822). The amplified signals are applied to the
drive/power amplifier circuits for VHF band.

4 - 4

(3) 440 MHz band

The signals from the limiter amplifier (RF unit; IC301)
changes the reactance of a diode (VCO unit; D321) to mod­ulate the oscillated signal at the 440-VCO circuit (VCO unit;
Q321, Q322, D321, D322, L322). The modulated signals are
amplified at the buffer-amplifier (Q323) and the LO amplifier
(Q823). The amplified signals are applied to the drive/power
amplifier circuits for UHF band.

(4) 1200 MHz band

The signals from the limiter amplifier (RF unit: IC301)
changes the reactance of a diode (VCO unit; D352) to mod­ulate the oscillated signal at the 1200-VCO circuit (VCO unit;
Q350, D351, D352, L330). The modulated signals are ampli­fied at the buffer-ampifier (Q351). The amplified signals are
applied to the doubler circuit (Q353), and then passed
through the high-pass (C376–C380, L334, L335) and the
low-pass (C381–C386, L336, L337) filters. The filtered sig­nals are amplified at the buffer-amplifier (Q354) and the LO
amplifier (Q824). The amplified signals are applied to the
drive/power amplifier circuits for SHF band.

4-2-3 DRIVE/POWER AMPLIFIER CIRCUITS

(RF UNIT)

The amplifier circuit amplifies the VCO oscillating signal to
the output power level.

(1) 50 MHz PA

The signal from the LO amplifiers (Q821) is amplified at the
buffer-amplifier (Q133) and the YGR amplifier (Q134). The
amplified signal is applied to the driver amplifiers (Q921),
and is then amplified at the power amplifier (Q922) to obtain

5.0 W of RF power.
The amplified signal is passed through the antenna switch-

ing circuit (D101 and D102) and low-pass filters, and is then
applied to the antenna connector.

(2) 144 MHz PA

The signal from the LO amplifiers (Q822) is passed through
the Tx/Rx switch (D802 and D803), and is amplified at the
buffer-amplifier (Q133) and the YGR amplifier (Q134). The
amplified signal is applied to the driver amplifiers (Q921),
and is then amplified at the power amplifier (Q922) to obtain

5.0 W of RF power.

The amplified signal is passed through the antenna switch­ing circuit (D101 and D102), low-pass filters and high-pass
filters. The signal is applied to the antenna connector.

(3) 440 MHz PA

The signal from the LO amplifiers (Q823) is passed through
the Tx/Rx switch (D804 and D805), and is amplified at the
buffer amplifier (Q135) and the YGR amplifier (Q136). The
amplified signal is applied to the driver amplifier (Q921), and
is then amplified at the power amplifier (Q922) to obtain 5.0
W of RF power.

The amplified signal is passed through the antenna switch­ing circuit (D402 and D403), low-pass filters and high-pass
filters. The low-pass filtered signal is applied to the antenna
connector.

(4) 1200 MHz PA

The signal from the LO amplifiers (Q824) is passed through
the Tx/Rx switch (D806 and D807), and is amplified at the
buffer-amplifiers (Q131 and Q132) and the YGR amplifier
(Q138). The amplified signal is applied to the driver ampli­fiers (Q921) to obtain 1.0 W of RF power.

The amplified signal is passed through the antenna switch­ing circuit (D51 and D52), low-pass filter and high-pass fil­ters. The high-pass filtered signal is applied to the antenna
connector.

Collector voltages for the drive amplifier (Q921) and control
voltage for the power amplifier (Q922) and YGR amplifier
(Q138) are controlled by the APC circuit to protect the power
module from a mismatched condition as well as to stabilize
the output power.

4-2-4 APC CIRCUITS (RF UNIT)

The APC circuit protects the power amplifier from a mis­matched output load and stabilizes the output power. The
APC circuit is designed to use VHF, UHF and SHF bands
commonly.

• APC CONTROL CIRCUIT

Q912

Q913

TXC

VCC

R911

APC SENSOR CIRCUIT

D/A CONVERTER

IC5 (LOGIC unit)

+3C

IC901
+

–

Differential
amplifier

1

2
3

6

PSET

VGGC

1200 MHz
RF transmit
signal

Drive
amp.

Power
amp.

YGR
amp.

Q138

Q921

Q922

to the antenna

YGR
amp.

YGR
amp.

Q135

Q134

430 MHz
RF transmit
signal

50, 144 MHz
RF transmit
signal

4 - 5

The APC sensor (R911) detects driving current from the
drive voltage at the YGR (Q138), drive (Q921) and power
(Q922) amplifiers. The detected current is converted into DC
voltage at Q913, then applied to the APC control circuit
(IC901, pin 2). The applied voltage is compared with a
“PSET” voltage from the CPU via the D/A converter (LOGIC
unit; IC5), and the APC control circuit outputs “VGGC” volt­age from pin 1 to control the YGR, drive and power ampli­fiers.

When the driving current is increased, input voltage of the
differential amplifier (IC901, pin 2) will be increased. In such
cases, the differential amplifier output voltage (IC901, pin 1)
is decreased to reduce the driving current.

4-3 PLL CIRCUITS

4-3-1 50 MHz BAND PLL CIRCUIT (RF UNIT)

The osillated signal at the 6MVCO (Q341, D341) is amplified
at the buffer amplifiers (Q342, Q343). The amplified signal is
applied to the PLL IC (IC801, pin 2) via the buffer-amplifier
(Q813).

The signal which is applied to the PLL IC (IC801) is divided
by N-data from the CPU and phase-detected with the divid­ed reference frequency (5 kHz) then output from pin 8. The
output signal is converted into DC voltage at the active filter
(Q804, Q805) and is fed back to the 6MVCO as the lock volt­age.

4-3-2 144 MHz BAND PLL CIRCUIT

(VCO BOARD AND RF UNIT)

The osillated signal at the 144-VCO circuit (VCO unit; Q31 1,
Q312, D302 and D311) is amplified at the buffer amplifiers
(VCO unit; Q313).The amplified signal is applied to the PLL
IC (IC801, pin 19) via a buffer-amplifier (Q807).

The applied signal is divided by serial data from the CPU (N­data) and phase-detected with the divided reference fre­quency (5 kHz) at the phase detector section in the PLL IC.
The phase-detected signal is output from IC801 (pin 13) and
converted DC voltage at the active filter (Q811, Q812). The
converted DC voltage is fed back to the VCO board as the
“VLV” signal of the lock voltage.

While operating in the 144 MHz band, the lock voltage is
applied to the CPU (LOGIC unit; IC1) via the tune control cir­cuit (Q803) to track the center frequency of the tunable
bandpass filters (D306, D309, D310) as the “TUNE” signal.

4-3-3 440 MHz BAND PLL CIRCUIT

(VCO BOARD AND RF UNIT)

The osillated signal at the 440-VCO circuit (VCO unit; Q321,
Q322, D321 and Q322) is amplified at the buffer-amplifiers
(VCO unit; Q323).The amplified signal is applied to the PLL
IC (IC801, pin 19) via a buffer-amplifier (Q807).

The applied signal is divided by serial data from the CPU (N­data) and phase-detected with the divided reference fre­quency (5 kHz) at the phase detector section in the PLL IC.
The phase-detected signal is output from IC801 (pin 13) and
converted DC voltage at the active filter (Q811, Q812). The
converted DC voltage is fed back to the VCO board as the
“VLV” signal of the lock voltage.

4-3-4 1200MHz BAND PLL CIRCUIT

(VCO BOARD AND RF UNIT)

The osillated signal at the 1200-VCO circuit (VCO unit;
Q350, D351 and D352) is amplified at the buffer-amplifiers
(VCO unit; Q351 and Q353). The signal passes through the
buffer amplifier (Q354), the high-pass (C376–C380, L334
and L335) and the low-pass filter (C381–C385, L336 and
L337). The filtered signal is applied to the PLLIC (IC802, pin

1) via the buffer amplifier (Q816).
The applied signal is divided by serial data from the CPU (N-

data) and phase-detected with the divided reference fre­quency (5 kHz) at the phase detector section in the PLL IC.
The phase-detected signal is output from IC801 (pin 13) and
converted DC voltage at the active filter (Q811, Q812). The
converted DC voltage is fed back to the VCO board as the
“VLV” signal of the lock voltage.

LINE

HV

VCC

+3CPU

+3C

+3

R+3

T4

DESCRIPTION

The voltage from the external power supply or
attached battery pack.

The same voltage as the “HV” line (external
power supply or battery pack) passed through a
diode (RF unit; D1).

Common 3V converted from the “VCC” line by
+3C CPU regulator IC (LOGIC unit; IC141). The
output voltage is supplied to the +3C regulator
circuits, etc.

Common 3V converted from the “VCC” line by
the +3C regulator circuit (LOGIC unit; Q142 and
Q145) using the +3CPU regulator (LOGIC unit;
IC141.)

Common 3V converted from the “VCC” line by
the +3 regulator circuit (LOGIC unit; IC5, Q1, Q2
and Q3) using the +3C regulator (LOGIC unit;
Q142 and Q145).

3V for receiver circuit converted from the “VCC”
line by the “R+3” regulator circuit (RF unit; Q7
and Q8).

4V for transmitter circuit converted from the
“VCC” line by the T4 regulator circuit (RF unit;
Q901–Q903 and D901). The T4 regulator circuit
is controlled by the CPU (LOGIC unit; IC1, pin

21) via the “TXC” line.

4-4 POWER SUPPLY CIRCUITS

VOLTAGE LINE

4 - 6

• PLL circuit

Shift register

Prescaler

Phase
detector

Loop

filter

Programmable
counter

Programmable
divider

X1

13.8 MHz

Q311,
Q312,

D302,
D311

144 MHz VCO

50MHz RX VCO

Buff.

D802,
D803

Q807

Q313,
D312

3
4
5

PSTB

IC801 (PLL IC)

CLK
DATA

to transmitter circuit

to 1st mixer circuit
(IC601, pin 1)

16

13

19

Q301,
Q302,
D301

Q811,
Q812

VCO BOARD

8

Loop

filter

Q804,
Q805

50 MHz TX VCO

Buff.

Q342

Buff.

Q313

2

to transmitter circuit

Q321,
Q322,
D321,
D322

430 MHz VCO

Q341, D341

TX/RX

SW

Buff.

Q822

Amp.

Buff.

Q323

D804,
D805

to transmitter circuit

TX/RX

SW

Q823

Amp.

TUNE
CTRL

Q803

"LOCKV" signal
to the IC1, pin 5

IC802 (PLL IC)

3
4
5

CLK
DATA
STB

1

5

16

1200MHz VCO

Q350,
D351,
D352

Buff.

Q351,
Q354

D804,
D805

TX/RX

SW

Q823

Amp.

to transmitter circuit

Buff.

Q816

Pin Port

Description

number name

4

5

6

7

11

12

13

14

Q1

Q2

Q3

Q4

Q8

Q7

Q6

Q5

Outputs VHVCO3 regulator control
signal.

Outputs VLVCO3 regulator control
signal.

Outputs 6MVCO3 regulator control
signal.

Outputs VCO shift signal for SHF,
UHF, 144 MHz and 50 MHz.

Outputs 12VCO3 regulator control sig­nal.

Outputs UHVCO3 regulator control
signal.

Outputs UHF TX and RX regulator
control signal.

Outputs 1200 MHz TX and RX regula­tor control signal.

Pin Port

Description

number name

4

6

7

11

12

13

Outputs 300 MHz band RX regulator
control signal.

Outputs AM mode regulator control
signal.

Outputs WFM band RX switching con­trol signal.

Outputs WFM band RX regulator con­trol signal.

Outputs 50 MHz band TX and RX reg­ulator control signal.

Outputs VHF band TX and RX regula­tor control signal.

Q1

Q3

Q4

Q8

Q5

Q6

4-5-2 I/O EXPANDER IC (RF UNIT; IC3)

4-5 PORT ALLOCATIONS

4-5-1 I/O EXPANDER IC (RF UNIT; IC2)

Pin Port

Description

number name

Pin Port

Description

number name

1

2

3
4

5

6

7

8

9

10

11

12

13

14

15

16

17

18
19

VIN

REMOTE

SD

CTCIN

LOCKV

THERMC

SBATT

CONT

CTCOUT

BEEP

BPCPI

NOISE

PDA2/UL

PDA1/UL

DAST

IOST

PLST2

PLST1

CLONEOUT

Input port for the over-voltage detec­tion from connected battery pack or
external power supply.

Input port for remote control signals
from an optional HM-75A microphone
via the [MIC] jack.

Input port for the S-meter voltage.
Input port for CTCSS decoded sig-

nals.
Input port for the PLL lock voltage.
Input port for the tranceiver’s internal

temparature.
Input port for the VCC voltage (con-

nected battery voltage).
Outputs control signal for the LCD

contrast.

High : The LCD contrast is deep.

Outputs CTCSS signals while trans­mitting.

Output port for:

• Beep audio signals while receiving.

• DTMF signals or 1750 Hz Europe
tone signal while transmitting.

[EUR], [ITA], [UK]

Input port for the bias control voltage
to judge kinds of battery types.

High : Supply the bias control volt-

age.

Input port for the noise signal (pulse­type) from the IF IC (RF unit; IC 701,
pin 13).

Outputs data signals to the PLL IC2
(RF unit; IC802, pin 4).
Input port for the PLL unlock signal
from the PLL IC2 (RF unit; IC802, pin

4).

Outputs data signals to the PLL IC1
(RF unit; IC801, pin 5).
Input port for the PLL unlock signal
from the PLL IC1 (RF unit; IC801, pin

5).

Outputs strobe signals to the D/A IC
(LOGIC unit; IC5, pin2).

Outputs strobe signals to the I/O IC
(RF unit; IC2, pin 1 and IC3, pin 1).

Outputs strobe signals to the PLL IC2
(RF unit, IC802, pin5).

Outputs strobe signals to the PLL IC1
(RF unit, IC801, pin 3).

Output port for the cloning signal.

20

21

22

23

24

25

26

27

28

29

30

31

32

33
39

41

42

43–46
47, 48
49–54

55, 56

Input port for the cloning signal.
Outputs T4 regulator control signal.

High : While transmitting.

Outputs R3 regulator control signal.

High : While receiving.

Input port for the reset signal from
Q151 (LOGIC unit).

Outputs control signal for charger cir­cuit (RF unit; Q5).

High : While battery is charging.

Outputs control signal for the AF
amplifier requlator circuit.

High : Activates the AF amplifier cir-

cuit.

Outputs +3C regulator control signal
(LOGIC unit; Q142 and Q145).

Outputs control signal for the Europe
tone and DTMF.

Low : Activates the Europe tone.
High : Activates DTMF.

Outputs BUSY LED control singal.

Low : The BUSY LED is ON.

Outputs LCD backlight control signal.

High : Lights ON.

Outputs control signal for the regulator
secton of MIC amplifier (LOGIC unit;
IC301).

Low : Activates the MIC amplifier

circuit.

Outputs AF mute and MIC mute con­trol signals.

High : Mute is ON.
Input port for the [POWER] switch.
Input port for the RESET signal from

IC142, pin 1 (LOGIC unit).
Input port for the [PTT] switch.
Outputs clock signal to the PLL IC1

(IC801), PLL IC2 (IC802), D/AIC (IC5)
, I/O IC (IC2, IC3) on the RF unit and
EEPROM IC (LOGIC unit; IC2).

Data bus line for the EEPROM
(LOGIC unit; IC2).

Input ports for key matrix.
Input ports for Initial matrix.
Outputs port for key matrix.
Input port for the up/down signal from

the main dial (LOGIC unit; S1).

CLONEIN

TXC

R3C

CPUHV

CHGC

AFON

PCON

TCON

BLED

LIGHT

MICC

RM/MM

POWER

RESET

PTT

CK

ESIO

KR3–KR0

I1, I2

KS5–KS0

DICK,

DIUK

4 - 7

4-5-3 CPU (LOGIC UNIT; IC1)

5 - 1

AD-92SMA
Optional SMA–BNC adaptor

1/8" (3.5 mm)
3-conductor plug

68 kΩ

-

+

to [SP] jack

Audio generator

AC millivoltmeter

Power supply

13.5 V / 3 A

to [MIC] jack

FM Deviation
meter

Attenuator
40 dB or 50 dB

RF power meter
10 W/50 Ω

Frequency
counter

Standard signal
generator

CAUTION:

to the antenna connector

DO NOT transmit while
an SSG is connected to
the antenna connector.

JIG

5-1 PREPARATION

‘‘

REQUIRED TEST EQUIPMENT

‘‘

ENTERING THE ADJUSTMENT MODE

q Connect a 68 kΩ terminator to the [SP] jack.
w Push and hold the [SQL] key, and then turn power ON.

Note: The frequency of wide range appears at the display using this operation.

■ CONNECTION

EQUIPMENT

DC power supply

RF power meter
(terminated type)

Frequency counter

FM deviation meter

GRADE AND RANGE

Output voltage : 13.5 V DC
Current capacity : 3 Aor more

Measuring range : 1–10 W
Frequency range : 28–1500 MHz
Impedance : 50 Ω
SWR : Less than 1.2 : 1

Frequency range : 0.1–1500 MHz
Frequency accuracy: ±1 ppm or better
Sensitivity : 100 mV or better

Frequency range : 30–1500 MHz
Measuring range : 0 to ±10 kHz

EQUIPMENT

DC voltmeter
Audio generator

Standard signal
generator (SSG)

Oscilloscope

AC millivoltmeter
Attenuator

GRADE AND RANGE

Input impedance : 50 kΩ/V DC or better
Frequency range : 300–3000 Hz

Measuring range : 1–500 mV
Frequency range : 28–1300 MHz

Output level : 0.1 µV–32 mV

(–127 to –17 dBm)

Frequency range : DC–20 MHz
Measuring range : 0.01–20 V

Measuring range : 10 mV–10 V
Power attenuation : 40 or 50 dB

SECTION 5 ADJUSTMENT PROCEDURES

5 - 2

5-2 PLL ADJUSTMENT

The following adjustment must be performed at “ADJUSTMENT MODE”.

PLL LOCK
VOLTAGE

REFERENCE
FREQUENCY

DETECTER
OUTPUT
VOLTAGE

ADJUSTMENT

ADJUSTMENT ADJUSTMENT CONDITION

MEASUREMENT

VALUE

POINT

UNIT LOCATION UNIT ADJUST

1

2

3

4

5
6

7
8

1

1

• Displayed frequency :

51.000 MHz

• Receiving

• Transmitting

• Displayed frequency :

88.000 MHz

• Receiving

• Displayed frequency :

145.000 MHz

• Receiving

• Transmitting

• Displayed frequency :

440.000 MHz

• Receiving

• Transmitting

• Displayed frequency :

1270.000 MHz

• Receiving

• Transmitting

• Displayed frequency :

1270.000 MHz

• Transmitting

• Displayed frequency :

445.000 MHz [USA-1] only

435.000 MHz [ohter]

• Connect an SSG to the antenna
connector and set as:

Level : 1 mV

*

(–47dBm)

Modulation : OFF

• Receiving

RF

Top

Pannel

LOGIC

Connect the DC
voltmeter or an
oscilloscope to VLV.

Connect the DC
voltmeter or an
oscilloscope to
6MLV.

Connect the DC
voltmeter or an
oscilloscope to VLV.

Connect the DC
voltmeter or an
oscilloscope to ULV.

Connect the DC
voltmeter or an
oscilloscope to
12LV.

Loosely couple the
frequency counter
to the antenna con­nector.

Connect a digital­voltmeter to the
check point Q.

0.8 V – 1.8 V

1.8 V – 2.8 V

1.4 V – 2.4 V

1.5 V – 2.5 V

1.5 V – 2.5 V

2.0 V – 2.5 V

2.0 V – 2.5 V

1.9 V – 2.9 V

1270.0000 MHz

1.0 V

Top

panel

LOGIC

Verify

Push and

hold the

[SQL] key,

then turn

the [DIAL]

L702

*This output level of the standard signal generator (SSG) is indicated as SSG’s open circuit.