Motorola Freescale Semiconductor DSP56000, Freescale Semiconductor DSP56001 User Manual

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This appendix contains detailed information about each instruction in the DSP56000/ DSP56001 instruction set. An instruction guide is presented first to help understand the individual instruction descriptions. This guide is followed by sections on notation and addressing modes. Since parallel moves are allowed with many of the instructions, they are discussed before the instructions. The instructions are then discussed in alphabetical order.

A.1 INSTRUCTION GUIDE

The following information is included in each instruction description with the goal of mak-

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ing each description self-contained:

1. Name and Mnemonic: The mnemonic is highlighted in bold type for easy reference.

APPENDIX A

INSTRUCTION SET DETAILS

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2. Assembler Syntax and Operation: For each instruction syntax, the corresponding operation is symbolically described. If there are several operations indicated on a single line in the operation field, those operations do not necessarily occur in the order shown but are generally assumed to occur in parallel. If a parallel data move is allowed, it will be indicated in parenthesis in both the assembler syntax and operation fields. If a letter in the mnemonic is optional, it will be shown in parenthesis in the assembler syntax field.

3. Description: A complete text description of the instruction is given together with any special cases and/or condition code anomalies of which the user should be aware when using that instruction.

4. Example: An example of the use of the instruction is given. The example is shown in DSP56000/DSP56001 assembler source code format. Most arithmetic and logical instruction examples include one or two parallel data moves to illustrate the many types of parallel moves that are possible. The example includes a complete explanation, which discusses the contents of the registers referenced by the instruction (but not those referenced by the parallel moves) both before and after the execution of the instruction. Most examples are designed to be easily understood without the use of a calculator.

5. Condition Codes: The status register is depicted with the condition code bits which can be affected by the instruction highlighted in bold type. Not all bits in the status register are used. Those which are reserved are indicated with a double asterisk and are read as zeros.

6. Instruction Format: The instruction fields, the instruction opcode, and the instruction extension word are specified for each instruction syntax. When the extension

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word is optional, it is so indicated. The values which can be assumed by each of the variables in the various instruction fields are shown under the instruction field’s heading. Note that the symbols used in decoding the various opcode fields of an instruction are completely arbitrary . Furthermore, the opcode symbols used in one instruction are completely independent of the opcode symbols used in a different instruction.

7. Timing: The number of oscillator clock cycles required for each instruction syntax is given. This information provides the user a basis for comparison of the execution times of the various instructions in oscillator clock cycles. Refer to Table A-1 and A.7 INSTRUCTION TIMING for a complete explanation of instruction timing, including the meaning of the symbols ‘‘aio’’, ‘‘ap’’, ‘‘ax’’, ‘‘ay’’, ‘‘axy’’, ‘‘ea’’, ‘‘jx’’, ‘‘mv’’, ‘‘mvb’’, ‘‘mvc’’, ‘‘mvm’’, ‘‘mvp’’, ‘‘rx’’, ‘‘wio’’, ‘‘wp’’, ‘‘wx’’, and ‘‘wy’’.

8. Memory: The number of program memory words required for each instruction syntax is given. This information provides the user a basis for comparison of the number of program memory locations required for each of the various instructions in 24-

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bit program memory words. Refer to Table A-1 and A.7 INSTRUCTION TIMING for a complete explanation of instruction memory requirements, including the meaning of the symbols ‘‘ea’’ and ‘‘mv’’.

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A.2 NOTATION

Each instruction description contains symbols used to abbreviate certain operands and operations. Table A-1 lists the symbols used and their respective meanings. Depending on the context, registers refer to either the register itself or the contents of the register.

A.3 ADDRESSING MODES

The addressing modes are grouped into three categories: register direct, address register indirect, and special. These addressing modes are summarized in Table A-2. All address calculations are performed in the address ALU to minimize execution time and loop overhead. Addressing modes, which specify whether the operands are in registers, in memory, or in the instruction itself (such as immediate data), provide the specific address of the operands.

The register direct addressing mode can be subclassified according to the specific register addressed. The data registers include X1, X0, Y1, Y0, X, Y, A2, A1, A0, B2, B1, B0, A, and B. The control registers include SR, OMR, SP, SSH, SSL, LA, LC, CCR, and MR.

Address register indirect modes use an address register Rn (R0–R7) to point to locations in X, Y, and P memory. The contents of the Rn address register (Rn) is the effective address (ea) of the specified operand, except in the ‘‘indexed by offset’’ mode where the effective address (ea) is (Rn+Nn). Address register indirect modes use an address modifier register Mn to specify the type of arithmetic to be used to update the address register Rn. If an addressing mode specifies an address offset register Nn, the given address offset register is used to update the corresponding address register Rn. The Rn address register may only use the corresponding address offset register Nn and the corresponding address modifier register Mn. For example, the address register R0 may only use the

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Table A-1 Instruction Description Notation

Data ALU Registers Operands

Xn Input Register X1 or X0 (24 Bits) Yn Input Register Y1 or Y0 (24 Bits) An Accumulator Registers A2, A1, A0 (A2 — 8 Bits, A1 and A0 — 24 Bits) Bn Accumulator Registers B2, B1, B0 (B2 — 8 Bits, B1 and B0 — 24 Bits) X Input Register X = X1: X0 (48 Bits) Y Input Register Y = Y1: Y0 (48 Bits) A Accumulator A = A2: A1: A0 (56 Bits)*

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B Accumulator B = B2: B1: B0 (56 BIts)* AB Accumulators A and B = A1: B1 (48 Bits)* BA Accumulators B and A = B1: A1 (48 Bits)* A10 Accumulator A = A1: A0 (48 Bits) B10 Accumulator B= B1:B0 (48 bits) * NOTE: In data move operations , shifting and limiting are perf ormed when this register is speciﬁed

as a source operand. When speciﬁed as a destination operand, sign extension and possib ly zeroing are performed.

Address ALU Registers Operands

Rn Address Registers R0 - R7 (16 Bits) Nn Address Offset Registers N0 - N7 (16 Bits) Mn Address Modiﬁer Registers M0 - M7 (16 Bits)

N0 address offset register and the M0 address modifier register during actual address computation and address register update operations. This unique implementation is extremely powerful and allows the user to easily address a wide variety of DSP-oriented data structures. All address register indirect modes use at least one set of address registers (Rn, Nn, and Mn), and the XY memory reference uses two sets of address registers, one for the X memory space and one for the Y memory space.

The special addressing modes include immediate and absolute addressing modes as well as implied references to the program counter (PC), the system stack (SSH or SSL), and program (P) memory.

Addressing modes may also be categorized by the ways in which they may be used.

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Table A-1 Instruction Description Notation (Continued)

Program Controller Registers Operands

PC Progr am Counter Register (16 Bits) MR Mode Register (8 Bits) CCR Condition Code Register (8 Bits) SR Status Register = MR:CCR (16 Bits) OMR Operating Mode Register (8 Bits) LA Hardware Loop Address Register (16 Bits) LC Hardware Loop Counter Register (16 Bits) SP System Stack P ointer Register (6 Bits)

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SSH Upper Portion of the Current Top of the Stack (16 Bits)

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SSL Lower P ortion of the Current Top of the Stack (16 Bits) SS System Stack RAM = SSH: SSL (15 Locations b y 32 Bits)

Address Operands

ea Effective Address eax Effective Address for X Bus eay Effective Address for Y Bus xxxx Absolute Address (16 Bits) xxx Short Jump Address (12 Bits) aa Absolute Short Address (6 Bits, Zero Extended) pp I/O Short Address (6 Bits, Ones Extended) <. . .> Speciﬁies the Contents of the Speciﬁed Address X: X Memory Reference Y: Y Memory Reference L: Long Memory Reference = X:Y P: Program Memory Reference

Table A-3 shows the various categories to which each addressing mode belongs. The following classifications will be used in the instruction descriptions.

Table A-3. DSP56000/DSP56001 Addressing Mode Encoding These addressing mode categories may be combined so that additional, more restrictive

classifications may be defined. For example, the instruction descriptions may use a

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Table A-1 Instruction Description Notation (Continued)

Miscellaneous Operands

S, Sn Source Operand Register D , Dn Destination Operand Register D [n] Bit n of D Destination Operand Register #n Immediate Short Data (5 Bits) #xx Immediate Short Data (8 Bits) #xxx Immediate Short Data (12 Bits) #xxxxxx Immediate Data (24 Bits)

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Unary Operators

- Negation Operator — Logical NOT Operator PUSH Push Speciﬁed Value onto the System Stack (SS) Operator PULL Pull Speciﬁed Value from the System Stack (SS) Operator READ Read the Top of the System Stack (SS) Operator PURGE Delete the Top Value on the System Stac k (SS) Oper ator | | Absolute Value Operator

Binary Operators

+ Addition Operator

- Subtraction Operator * Multiplication Oper ator ÷, / Division Operator + Logical Inclusive OR Operator

• Logical AND Operator ⊕ Logical Exclusive OR Operator ➨ “Is T ransferred To” Operator : Concatenation Operator

memory alterable classification, which refers to addressing modes that are both mem-

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Table A-1 Instruction Description Notation (Continued)

Addressing Mode Operators

<< I/O Short Addressing Mode Force Operator < Short Addressing Mode Force Operator > Long Addressing Mode Force Operator # Immediate Addressing Mode Operator #> Immediate Long Addressing Mode Force Oper ator #< Immediate Short Addressing Mode Force Operator

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Mode Register (MR) Symbols

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LF Loop Flag Bit Indicating When a DO Loop is in Progress T Trace Mode Bit Indicating if the Tracing Function has been Enabled S1, S0 Scaling Mode Bits Indicating the Current Scaling Mode I1, I0 Interrupt Mask Bits Indicating the Current Interrupt Priority Level

Condition Code Register (CCR) Symbols

Standard Definitions (Table A - 3 Describes Exceptions)

L Limit Bit Indicating Arithmetic Ov erﬂo w and/or Data Shifting/Limiting E Extension Bit Indicating if the Integer Portion of A or B is in Use U Unnormalized Bit Indicating if the A or B Result is Unnormalized N Negativ e Bit Indicating if Bit 55 of the A or B Result is Set Z Zero Bit Indicating if the A or B Result Equals Zero V Overﬂow Bit Indicating if Arithmetic Overﬂo w has Occurred in A or B C Carry Bit Indicating if a Carry or Borrow Occurred in A or B Result

ory addressing modes and alterable addressing modes. Thus, memory alterable addressing modes use address register indirect and absolute addressing modes.

The address register indirect addressing modes require that the offset register number be the same as the address register number. However, future family members may allow the offset register number to be different from the address register number. The assembler syntax ‘‘Nn’’ supports the future feature. The assembler syntax ‘‘N’’ may be used

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Table A-1 Instruction Description Notation (Continued)

Instruction Timing Symbols

aio Time Required to Access an I/O Operand ap Time Required to Access a P Memory Operand ax Time Required to Access an X Memory Operand ay Time Required to Access a Y Memory Operand axy Time Required to Access XY Memory Operands ea Time or Number of W ords Required for an Effective Address jx Time Required to Execute Part of a Jump-Type Instruction mv Time or Number of W ords Required f or a Mo ve-Type Operation

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mvb Time Required to Execute P art of a Bit Manipulation Instruction

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mvc Time Required to Execute Part of a MOVEC Instruction mvm Time Required to Execute P art of a MO VEM Instruction mvp Time Required to Execute P art of a MO VEP Instruction rx Time Required to Execute P art of an TR TI or RTS Instruction wio Number of W ait States Used in Accessing External I/O wp Number of Wait States Used in Accessing External P Memory wx Number of W ait States Used in Accessing External X Memory wy Number of W ait States Used in Accessing External Y Memory

Other Symbols

( ) Optional Letter, Operand, or Operation

(. . . . .) An y Arithmetic or Logical Instruction Which Allo ws Parallel Moves

EXT Extension Register Portion of an Accumulator (A2 or B2) LS Least Signiﬁcant LSP Least Signiﬁcant Portion of an Accumulator (A0 or B0) MS Most Signiﬁcant MSP Most Signiﬁcant Portion of a n Accumulator (A1 or B1) r Rounding constant S/L Shifting and/or Limiting on a Data ALU Register Sign Ext Sign Externsion of a Data ALU Register Zero Zeroing of a Data ALU Register

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Table A-2 DSP 56000/56001 Addressing Modes

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Addressing Mode

Data or Control Register No X X X Address Register Rn No X Address Modiﬁer Register

Mn Address Offset Register Nn No X

No Update Yes XXXXX Postincrement b y 1 Yes XXXXX Postdecrement b y 1 Yes XXXXX Postincrement b y Offset Nn Yes XXXXX Postdecrement b y Offset Nn Yes XXXX Indexed b y Offset Nn Yes XXXX Predecrement by 1 Yes XXXX

Immediate Data No X Absolute Address No XXXX Immediate Short Data No X Short Jump Address No X Absolute Short Address No XXXX I/O Short Address No X X Implicit No X X X

Uses Mn

Modiﬁer

No X

Address Register Indirect

SCDAPXYLXY

Special

Operand Reference

NOTE:S = System Stack Reference X = X Memory Reference

C = Program Controller Register Reference Y = Y Memory Reference D = Data ALU Register Reference L = L Memory Reference A = Address ALU Register Reference XY = XY Memory Reference P = Program Memory Reference

instead of ‘‘Nn’’ in the address register indirect memory addressing modes. If ‘‘N’’ is specified, the offset register number is the same as the address register number.

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Table A-3 DSP56000/56001 Addressing Mode Encoding

Addressing Mode

Data or Control Register — — X (SeeTable A-1) Address Register — — X Rn Address Offset Register — — X Nn Address Modiﬁer Register — — X Mn

No Update 100 Rn X X X (Rn)

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Postincrement b y 1 011 Rn XXXX (Rn) + Postdecrement b y 1 010 Rn XXXX (Rn) Postincrement b y Offset Nn 001 Rn XXXX (Rn) + Nn Postdecrement b y Offset Nn 000 Rn X X X (RN) - Nn Indexed b y Offset Nn 101 Rn X X (Rn + Nn) Predecrement by 1 111 Rn X X - (Rn)

Immediate Data 110 100 X #xxxxxx Absolute Address 110 000 X X xxxx Immediate Short Data — — #xx Short Jump Address — — X xxx Absolute Short Address — — X aa I/O Short Address — — X pp

Mode

MMM

Address Register Indirect

Reg

RRR

Special

Addressing Categories

UPMA

Assembler

Syntax

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Implicit — — X

Update Mode (U) The update addressing mode is used to modify address registers without any

associated data move.

Parallel Mode (P) The parallel addressing mode is used in instructions where two effective

addresses are required.

Memory Mode (M) The memory addressing mode is used to refer to operands in memory using an

effective addressing ﬁeld.

Alterable Mode (A) The alterable addressing mode is used to refer to alter able or writable registers or

memory .

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A.3.1 Addressing Mode Modifiers

The addressing mode selected in the instruction word is further specified by the contents of the address modifier register Mn. The addressing mode update modifiers (M0–M7) are shown in Table A-4. There are no restrictions on the use of modifier types with any address register indirect addressing mode.

Table A-4 Addressing Mode Modifier Summary

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16-Bit Modiﬁer Reg. (M0 - M7)

MMMMMMMMMMMMMMMM*

0000000000000000 Reverse Carry (Bit Reversed) 0000000000000001 Modulo 2 0000000000000010 Modulo 3

•••

••• 0111111111111110 Modulo 32767 0111111111111111 Modulo 32768 1000000000000000 Undeﬁned

••• 1111111111111110 Undeﬁned 1111111111111111 Linear (Modulo 65536)

*MMMMMMMMMMMMMMMM = 16-Bit Modiﬁer Reg. Contents

A.4 CONDITION CODE COMPUTATION

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

** T ** S1 S0 I1 I0 ** LEUNZVC

MR CCR

Address Calculation Arithmetic

The condition code register (CCR) portion of the status register (SR) consists of seven defined bits:

L — Limit Bit Z — Zero Bit E — Extension Bit V — Overflow Bit U — Unnormalized Bit C — Carry Bit N — Negative Bit

The E, U, N, Z, V, and C bits are true condition code bits that reflect the condition of the result of a data ALU operation . These condition code bits are not latched and are not affected by address ALU calculations or by data transfers over the X, Y, or global data buses. The L bit is a latching overflow bit which indicates that an overflow has occurred in the data ALU or that data limiting has occurred when moving the contents of the Aand/or[lz B accumulators.

The standard definition of the condition code bits is as follows. Exceptions to these standard definitions are given in Table A-5.

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L (Limit Bit) Set if the overflow bit V is set or if the data shifter/limiters perform a limiting operation. Not affected otherwise. This bit is latched and must be reset by the user.

⊕

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E (Extension Bit) Cleared if all the bits of the signed integer portion of the A or B result are the same =m i.e., the bit patterns are either 00 . . . 00 or 11 . . . 11. Set otherwise. The signed integer portion is defined

by the scaling mode as shown in the following table:

S1 S0 Scaling Mode Signed Integer Portion

0 0 No Scaling Bits 55, 54, . . . . 48, 47

0 1 Scale Down Bits 55, 54, . . . . 49, 48

1 0 Scale Up Bits 55, 54, . . . . 47, 46

Note that the signed integer portion of an accumulator IS NOT necessarily the same as the extension register portion of that accumulator. The signed integer portion of an accumulator consists of the MS 8, 9, or 10 bits of that accumulator, depending on the scaling mode being used. The extension register portion of an accumulator (A2 or B2) is always the MS 8 bits of that accumulator. The E bit refers to the signed integer portion of an accumulator and NOT the extension register portion of that accumulator. For example, if the current scaling mode is set for no scaling (i.e., S1=S0=0), the signed integer portion of the A or B accumulator consists of bits 47 through 55 . If the A accumulator contained the signed 56-bit value $00:800000:000000 as a result of a data ALU oper-

ation , the E bit would be set (E=1) since the 9 MS bits of that accumulator were not all the same (i.e., neither 00 . . 00 nor 11 . . 11). This means that data limiting will occur if that 56-bit value is specified as a source operand in a move-type operation. This limiting

operation will result in either a positive or negative, 24-bit or 48-bit saturation constant being stored in the specified destination. The only situation in which the signed integer portion of an accumulator and the extension register portion of an accumulator are the same is in the ‘‘Scale Down’’ scaling mode (i.e., S1=0 and S0=1).

U (Unnormalized Bit) Set if the two MS bits of the MSP portion of the A or B result are the same. Cleared otherwise. The MSP portion is defined by the scaling mode. The U bit is computed as follows:

S1 S0 Scaling Mode U Bit Computation

0 0 No Scaling U=(Bit 47 ⊕ Bit 46) 0 1 Scale Down U=(Bit 48 ⊕ Bit 47 1 0 Scale Up U=(Bit 46

N (Negative Bit) Set if the MS bit 55 of the A or B result is set. Cleared otherwise.

Z (Zero Bit) Set if the A or B result equals zero. Cleared otherwise.

V (Overflow Bit) Set if an arithmetic overflow occurs in the 56-bit A or B result. This indicates that the result cannot be represented in the 56-bit accumulator; thus, the accumulator has overflowed. Cleared other-

C (Carry Bit) Set if a carry is generated out of the MS bit of the A or B result of an addition or if a borrow is generated out of the MS bit of the A or B result of a subtraction. The carry or borrow is generated out

Table A-5 details how each instruction affects the condition codes. The convention for the notation that is used is shown at the bottom of Table A-5.

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of bit 55 of the A or B result. Cleared otherwise.

Bit 45

) )

A.5 PARALLEL MOVE DESCRIPTIONS

Many of the instructions in the DSP56000/DSP56001 instruction set allow optional parallel data bus movement. A.6 INSTRUCTION DESCRIPTIONS indicates the parallel move option in the instruction syntax with the statement ‘‘(parallel move)’’. The MOVE instruction is equivalent to a NOP with parallel moves. Therefore, a detailed description of each parallel move is given with the MOVE instruction details in A.6 INSTRUCTION DESCRIPTIONS.

A.6 INSTRUCTION DESCRIPTIONS

The following section describes each instruction in the DSP56000/DSP56001 instruction set in complete detail. The format of each instruction description is given in A.1 INSTRUCTION GUIDE. Instructions which allow parallel moves include the notation ‘‘(parallel move)’’ in both the Assembler Syntax and the Operation fields. The example given with each instruction discusses the contents of all the registers and memory locations referenced by the opcode-operand portion of that instruction but not those referenced by the parallel move portion of that instruction. Refer to A.5 PARALLEL MOVE DESCRIPTIONS for a complete discussion of parallel moves, including examples which discuss the contents of all the registers and memory locations referenced by the parallel move portion of an instruction.

Whenever an instruction uses an accumulator as both a destination operand for a data ALU operation and as a source for a parallel move operation, the parallel move operation will use the value in the accumulator prior to execution of any data ALU operation.

Whenever a bit in the condition code register is defined according to the standard definition given in A.4 CONDITION CODE COMPUTATION, a brief definition will be given in normal text in the Condition Code section of that instruction description. Whenever a bit in the condition code register is defined according to a cerning its use.

special definition for some particular instruction, the complete special definition of that bit will be given in the Condition Code section of that instruction in bold text to alert the user to any special conditions con-

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Table A-5 Condition Code Computations

Mnemonic L E U N Z V C Notes Mnemonic L E U N Z V C Notes

ABS ******—MAC******— ADC ******* MACR ******— ADD ******* MOVE * —————— ADDL *****?* 1 MOVEC ??????? 13 ADDR ******* MOVEM ??????? 13 AND * ——??0— 8, 9 MOVEP ??????? 13 ANDI ??????? 2 MPY ******— ASL *****? ? 1, 3 MPYR ******— ASR *****0 ? 4 NEG ******— BCHG ? —————? 5, 14 NOP ——————— BCLR ? —————? 5, 14 NORM *****?— 1 BSET ? —————? 5, 14 NOT * — — ? ? 0 — 8, 9 BTST ? —————? 5, 14 OR * — — ? ? 0 — 8, 9 CLR *****0— ORI ??????? 6 CMP ******* REP * —————— CMPM ******* RESET ——————— DIV * ————? ? 1, 7 RND ******— DO * —————— ROL * — — ? ? 0 ? 8, 9, 10 ENDDO ——————— ROR * — — ? ? 0 ? 8, 9, 11 EOR * ——??0— 8, 9 RTI ??????? 12 Jcc ——————— RTS * —————— JCLR ——————— SBC ******* JMP ——————— STOP ——————— JScc ——————— SUB ******* JSCLR ——————— SUBL *****?* 1 JSET ——————— SUBR ******* JSR ——————— SWI ——————— JSSET ——————— Tcc ——————— LSL * ——??0?8, 9, 10TFR *—————— LSR * ——??0?8, 9, 11TST *****0— LUA ——————— WAIT ——————— where: * Set according to the standard deﬁnition of the operation

NOTES:

— Not affected by the operation ? Set according to a special deﬁnition and can be a 0 or 1 0 The V bit is cleared

1 V Set if an arithmetic overﬂow occurs in the 56-bit result. Also set if the MS bit of the destination oper and is changed as a result of

the left shift. Cleared otherwise. 2 ? Cleared if the corresponding bit in the immediate data is cleared when the operand is the CCR. Not affected otherwise. 3 C Set if bit 55 of the source operand is set. Cleared otherwise. 4 C Set if bit 0 of the source operand is set. Cleared otherwise. 5 C Set if bit #n of the source operand is set. Cleared otherwise. 6 ? Set if the corresponding bit in the immediate data is set when the operand is the CCR. Not affected otherwise. 7 C Set if bit 55 of the result is cleared. Cleared otherwise. 8 N Set if bit 47 of the result is set. Cleared otherwise. 9 Z Set if bits 47 - 24 of the result are zero. Cleared otherwise. 10 C Set if bit 47 of the source operand is set. Cleared otherwise . 11 C Set if bit 24 of the source operand is set. Cleared otherwise . 12 ? Set according to the value pulled from the stack. 13 ? If the status register (SR) is speciﬁed as a destination operand, set according to the corresponding bit of the source operand. If

SR is not speciﬁed as a destination operand, the L bit is set if data limiting occurred. All ? bits are not aff ected otherwise . 14 ? Set if limiting occurs, not affected otherwise.

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The definition and thus the computation of both the E (extension) and U (unnormalized) bits of the condition code register (CCR) varies according to the scaling mode being used. Refer to A.4 CONDITION CODE COMPUTATION for complete details.

The signed integer portion of an accumulator is NOT necessarily the same as either the A2 or B2 extension register portion of that accumulator. The signed integer portion of an accumulator is defined according to the scaling mode being used and can consist of the MS 8, 9, or 10 bits of an accumulator. Refer to A.4 CONDITION CODE COMPUTATION for complete details.

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ABS Absolute Value ABS

Operation: Assembler Syntax:

| D | ➞ D (parallel move) ABS D (parallel move)

Description: Take the absolute value of the destination operand D and store the result in the destination accumulator.

Example:

ABS A #$123456,X0 A,Y0 ;take abs. value, set up X0, save value

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Before Execution After Execution

A A

$FF:FFFFFF:FFFFF2 $00:000000:00000E

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Explanation of Example: Prior to execution, the 56-bit A accumulator contains the value $FF:FFFFFF:FFFFF2. Since this is a negative number, the execution of the ABS instruction takes the twos complement of that value and returns $00:000000:00000E.

Note: For the case in which the D operand equals $80:000000:000000 (-256.0), the ABS instruction will cause an overflow to occur since the result cannot be correctly expressed using the standard 56-bit, fixed-point, twos-complement data representation. Data limiting does not occur (i.e., A is not set to the limiting value of $7F:FFFFFF:FFFFFF).

Condition Codes

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

S1 S0 I1 I0

MR CCR

LEUNZVC

L — Set if limiting (parallel move) or overflow has occurred in result E — Set if the signed integer portion of A or B result is in use U — Set if A or B result is unnormalized N — Set if bit 55 of A or B result is set Z— Set if A or B result equals zero V — Set if overflow has occurred in A or B result

Note: The definition of the E and U bits varies according to the scaling mode being used. Refer to A.4 CONDITION CODE COMPUTATION for complete details.

A - 14 DSP56000/DSP56001 USER’S MANUAL MOTOROLA

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ABS Absolute Value ABS

Instruction Format:

ABS D

Opcode:

23 8 7 4 3 0

DATA BUS MOVE FIELD

OPTIONAL EFFECTIVE ADDRESS EXTENSION

0010

d110

nc...

cale Semiconductor,

Frees

Instruction Fields:

D d

A 0 B 1

Timing: 2+mv oscillator clock cycles

Memory: 1+mv program words

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ADC Add Long with Carry ADC

Operation: Assembler Syntax:

S+C+D ➞ D (parallel move) ADC S,D (parallel move)

Description: Add the source operand S and the carry bit C of the condition code register to the destination operand D and store the result in the destination accumulator. Long words (48 bits) may be added to the (56-bit) destination accumulator.

Note: The carry bit is set correctly for multiple precision arithmetic using long-word operands if the extension register of the destination accumulator (A2 or B2) is the sign extension of bit 47 of the destination accumulator (A or B).

nc...

cale Semiconductor,

Frees

Example:

: MOVE L:<$0,X ;get a 48-bit LS long-word operand in X MOVE L:<$1,A ;get other LS long word in A (sign ext.) MOVE L:<$2,Y ;get a 48-bit MS long-word operand in Y ADD X,A L:<$3,B ;add LS words; get other MS word in B ADC Y,B A10,L:<$4 ;add MS words with carry, save LS sum MOVE B10,L:<$5 ;save MS sum

Before Execution After Execution

A A

X X

B B

Y Y

$FF:800000:000000 $FF:000000:000000

$800000:000000 $800000:000000

$00:000000:000001 $00:000000:000003

$000000:000001 $000000:000001

Explanation of Example: This example illustrates long-word double-precision (96-bit) addition using the ADC instruction. Prior to execution of the ADD and ADC instructions, the double-precision 96-bit value $000000:000001:800000:000000 is loaded into the Y and X registers (Y:X), respectively. The other double-precision 96-bit value $000000:000001:800000:000000 is loaded into the B and A accumulators (B:A), respectively. Since the 48-bit value loaded into the A accumulator is automatically sign extended to 56 bits and the other 48-bit long-word operand is internally sign extended to 56 bits during instruction execution, the carry bit will be set correctly after the execution of the ADD X,A instruction. The ADC Y,B instruction then produces the correct MS 56-bit result. The actual 96-bit result is stored in memory using the A10 and B10 operands (instead of A and B) because shifting and limiting is not desired.

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ADC Add Long with Carry ADC

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

nc...

V — Set if overflow has occurred in A or B result C — Set if a carry (or borrow) occurs from bit 55 of A or B result.

S1 S0 I1 I0

MR CCR

LEUNZVC

cale Semiconductor,

Frees

Note: The definition of the E and U bits varies according to the scaling mode being used. Refer to A.4 CONDITION CODE COMPUTATION for complete details.

Instruction Format:

ADC S,D

Opcode:

23 8 7 4 3 0

DATA BUS MOVE FIELD

OPTIONAL EFFECTIVE ADDRESS EXTENSION

001J

d001

Instruction Fields:

S,D J d

X,A 0 0 X,B 0 1 Y,A 1 0 Y,B 1 1

Timing: 2+mv oscillator clock cycles Memory: 1+mv program words

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ADD Add ADD

Operation: Assembler Syntax:

S+D➞D (parallel move ADD S,D (parallel move)

Description: Add the source operand S to the destination operand D and store the result in the destination accumulator. Words (24 bits), long words (48 bits), and accumulators (56 bits) may be added to the destination accumulator.

Note: The carry bit is set correctly using word or long-word source operands if the extension register of the destination accumulator (A2 or B2) is the sign extension of bit 47

nc...

of the destination accumulator (A or B). Thus, the carry bit is always set correctly using accumulator source operands, but can be set incorrectly if A1, B1, A10, or B10 are used as source operands and A2 and B2 are not replicas of bit 47.

cale Semiconductor,

Frees

Example:

ADD X0,A A,X1 A,Y:(R1)+l ;24-bit add, set up X1, save prev. result

Before Execution After Execution

X0 X0

A A

$00:000100:000000 $00:0000FF:000000

$FFFFFF

Explanation of Example: Prior to execution, the 24-bit X0 register contains the value $FFFFFF and the 56-bit A accumulator contains the value $00:000100:000000. The ADD instruction automatically appends the 24-bit value in the X0 register with 24 LS zeros, sign extends the resulting 48-bit long word to 56 bits, and adds the result to the 56-bit A accumulator. Thus, 24-bit operands are added to the MSP portion of A or B (A1 or B1) because all arithmetic instructions assume a fractional, twos complement data representation. Note that 24-bit operands can be added to the LSP portion of A or B (A0 or B0) by loading the 24-bit operand into X0 or Y0, forming a 48-bit word by loading X1 or Y1 with the sign extension of X0 or Y0 and executing an ADD X,A or ADD Y,A instruction.

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

A - 18 DSP56000/DSP56001 USER’S MANUAL MOTOROLA

S1 S0 I1 I0

MR CCR

LEUNZVC

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ADD Add ADD

L — Set if limiting (parallel move) or overflow has occurred in result E — Set if the signed integer portion of A or B result is in use U — Set if A or B result is unnormalized N — Set if bit 55 of A or B result is set Z — Set if A or B result equals zero V — Set if overflow has occurred in A or B result C — Set if a carry (or borrow) occurs from bit 55 of A or B result.

Note: The definition of the E and U bits varies according to the scaling mode being

nc...

used. Refer to A.4 CONDITION CODE COMPUTATION for complete details.

Instruction Format:

ADD S,D

cale Semiconductor,

Frees

Opcode:

23 8 7 4 3 0

DATA BUS MOVE FIELD

OPTIONAL EFFECTIVE ADDRESS EXTENSION

Instruction Fields:

S,D J J J d S,D J J J d S,D J J J d

B,A 0 0 1 0 X0,A 1 0 0 0 Y1,A 1 1 1 0 A,B 0 0 1 1 X0,B 1 0 0 1 Y1,B 1 1 1 1 X,A 0 1 0 0 Y0,A 1 0 1 0 X,B 0 1 0 1 Y0,B 1 0 1 1 Y,A 0 1 1 0 X1,A 1 1 0 0 Y,B 0 1 1 1 X1,B 1 1 0 1

Timing: 2+mv oscillator clock cycles Memory: 1+mv program words

0JJJ

d000

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ADDL Shift Left and Add Accumulators ADDL

Operation: Assembler Syntax:

S+2

∗D➞D (parallel move) ADDL S,D (parallel move)

Description: Add the source operand S to two times the destination operand D and store the result in the destination accumulator. The destination operand D is arithmetically shifted one bit to the left, and a zero is shifted into the LS bit of D prior to the addition operation. The carry bit is set correctly if the source operand does not overflow as a result of the left shift operation. The overflow bit may be set as a result of either the shifting or addition operation (or both). This instruction is useful for efficient divide and deci-

nc...

mation in time (DIT) FFT algorithms.

Example:

ADDL A,B #$0,R0 ;A+2

∗B➞B, set up addr. reg. R0

cale Semiconductor,

Frees

Before Execution After Execution

$00:000000:000123

$00:005000:000000 $00:00A000:000123

$00:000000:000123

Explanation of Example: Prior to execution, the 56-bit accumulator contains the value $00:000000:000123, and the 56-bit B accumulator contains the value $00:005000:000000. The ADDL A,B instruction adds two times the value in the B accumulator to the value in the A accumulator and stores the 56-bit result in the B accumulator.

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

S1 S0 I1 I0

MR CCR

LEUNZVC

operand is changed as a result of the instruction’s left shift

C — Set if a carry (or borrow) occurs from bit 55 of A or B result.

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ADDL Shift Left and Add Accumulators ADDL

Note: The definition of the E and U bits varies according to the scaling mode being

used. Refer to A.4 CONDITION CODE COMPUTATION for complete details.

Instruction Format:

ADDL S,D

Opcode:

23 8 7 4 3 0

DATA BUS MOVE FIELD

nc...

OPTIONAL EFFECTIVE ADDRESS EXTENSION

0001

d010

cale Semiconductor,

Frees

Instruction Fields:

S,D d

B,A 0 A,B 1

Timing: 2+mv oscillator clock cycles Memory: 1+mv program words

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ADDR Shift Right and Add Accumulators ADDR

Operation: Assembler Syntax:

S+D / 2➞D (parallel move) ADDR S,D (parallel move)

Description: Add the source operand S to one-half the destination operand D and store the result in the destination accumulator. The destination operand D is arithmetically shifted one bit to the right while the MS bit of D is held constant prior to the addition operation. In contrast to the ADDL instruction, the carry bit is always set correctly, and the overflow bit can only be set by the addition operation and not by an overflow due to the initial shifting operation. This instruction is useful for efficient divide and decimation in

nc...

time (DIT) FFT algorithms.

Example:

ADDR B,A X0,X:(R1)+N1 Y0,Y:(R4)– ;B+A / 2➞A, save X0 and Y0

cale Semiconductor,

Frees

Before Execution After Execution

A A

B B

$80:000000:2468AC

$00:013570:000000 $00:013570:000000

$C0:013570:123456

Explanation of Example: Prior to execution, the 56-bit A accumulator contains the value $80:000000:2468AC, and the 56-bit B accumulator contains the value $00:013570:000000. The ADDR B,A instruction adds one-half the value in the A accumulator to the value in the B accumulator and stores the 56-bit result in the A accumulator.

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

S1 S0 I1 I0

MR CCR

LEUNZVC

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ADDR Shift Right and Add Accumulators ADDR

Note: The definition of the E and U bits varies according to the scaling mode being

used. Refer to A.4 CONDITION CODE COMPUTATION for complete details.

Instruction Format:

ADDR S,D

Opcode:

23 8 7 4 3 0

DATA BUS MOVE FIELD

nc...

OPTIONAL EFFECTIVE ADDRESS EXTENSION

0000

d010

cale Semiconductor,

Frees

Instruction Fields:

S,D d

B,A 0 A,B 1

Timing: 2+mv oscillator clock cycles Memory: 1+mv program words

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AND Logical AND AND

Operation: Assembler Syntax:

• D[47:24]➞D[47:24] (parallel move) AND S,D (parallel move)

where

Description: Logically AND the source operand S with bits 47–24 of the destination operand D and store the result in bits 47–24 of the destination accumulator. This instruction is a 24-bit operation. The remaining bits of the destination operand D are not affected.

•denotes the logical AND operator

nc...

cale Semiconductor,

Frees

Example:

AND X0,A (R5)–N5 ;AND X0 with A1, update R5 using N5

Before Execution After Execution

X0 X0

A A

$00:123456:789ABC $00:120000:789ABC

$FF0000

Explanation of Example: Prior to execution, the 24-bit X0 register contains the value $FF0000, and the 56-bit A accumulator contains the value $00:123456:789ABC. The AND X0,A instruction logically ANDs the 24-bit value in the X0 register with bits 47–24 of the A accumulator (A1) and stores the result in the A accumulator with bits 55–48 and 23–0 unchanged.

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

S1 S0 I1 I0

MR CCR

LEUNZVC

L — Set if data limiting has occurred during parallel move N — Set if bit 47 of A or B result is set Z— Set if bits 47–24 of A or B result are zero V — Always cleared

Instruction Format:

AND S,D

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AND Logical AND AND

Opcode:

23 8 7 4 3 0

DATA BUS MOVE FIELD

OPTIONAL EFFECTIVE ADDRESS EXTENSION

Instruction Fields:

S J J D d

nc...

X,0 0 0 A 0 (only A1 is changed) X,1 1 0 B 1 (only B1 is changed) Y,0 0 1 Y,1 1 1

01JJ

d110

cale Semiconductor,

Frees

Timing: 2+mv oscillator clock cycles Memory: 1+mv program words

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ANDI AND Immediate with Control Register ANDI

Operation: Assembler Syntax:

#xx

• D➞D AND(I) #xx,D

where

Description: Logically AND the 8-bit immediate operand (#xx) with the contents of the destination control register D and store the result in the destination control register. The condition codes are affected only when the condition code register (CCR) is specified as the destination operand.

• denotes the logical AND operator

nc...

cale Semiconductor,

Frees

Restrictions:The ANDI #xx,MR instruction cannot be used immediately before an ENDDO or RTI instruction and cannot be one of the last three instructions in a DO loop (at LA-2, LA-1, or LA).

The ANDI #xx,CCR instruction cannot be used immediately before an RTI instruction.

Example:

AND #$FE,CCR ;clear carry bit C in cond. code register

Before Execution After Execution

CCR

$31 $30

CCR

Explanation of Example: Prior to execution, the 8-bit condition code register (CCR) contains the value $31. The AND #$FE,CCR instruction logically ANDs the immediate 8bit value $FE with the contents of the condition code register and stores the result in the condition code register.

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

S1 S0 I1 I0

MR CCR

LEUNZVC

For CCR Operand:

L — Cleared if bit 6 of the immediate operand is cleared E — Cleared if bit 5 of the immediate operand is cleared U — Cleared if bit 4 of the immediate operand is cleared N — Cleared if bit 3 of the immediate operand is cleared Z— Cleared if bit 2 of the immediate operand is cleared

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ANDI AND Immediate with Control Register ANDI

V — Cleared if bit 1 of the immediate operand is cleared C — Cleared if bit 0 of the immediate operand is cleared

For MR and OMR Operands: The condition codes are not affected using these operands.

Instruction Format:

AND(I) #xx,D

Opcode:

nc...

23 16 15 8 7 0

00000000iiiiiiii101110EE

cale Semiconductor,

Frees

Instruction Fields:

#xx=8-bit Immediate Short Data — i i i i i i i i

DE E

MR 0 0 CCR 0 1 OMR 1 0

Timing: 2 oscillator clock cycles Memory: 1 program word

MOTOROLA DSP56000/DSP56001 USER’S MANUAL A - 27

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ASL Arithmetic Shift Accumulator Left ASL

55 47 23 0

Operation:

0 (parallel move)

Assembler Syntax: ASL D (parallel move)

Description: Arithmetically shift the destination operand D one bit to the left and store

the result in the destination accumulator. The MS bit of D prior to instruction execution is shifted into the carry bit C and a zero is shifted into the LS bit of the destination accumu-

nc...

lator D. If a zero shift count is specified, the carry bit is cleared. The difference between ASL and LSL is that ASL operates on the entire 56 bits of the accumulator and therefore sets the V bit if the number overflowed.

Example:

ASL A (R3)– ;multiply A by 2, update R3

Before Execution After Execution

SR SR

$A5:012345:012345

$0300 $0373

$4A:02468A:02468A

Explanation of Example: Prior to execution, the 56-bit A accumulator contains the

cale Semiconductor,

value $A5:012345:012345. The execution of the ASL A instruction shifts the 56-bit value in the A accumulator one bit to the left and stores the result back in the A accumulator.

Condition Codes:

Frees

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

S1 S0 I1 I0

MR CCR

LEUNZVC

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ASL Arithmetic Shift Accumulator Left ASL

Note: The definition of the E and U bits varies according to the scaling mode being

used. Refer to A.4 CONDITION CODE COMPUTATION for complete details.

Instruction Format:

ASL D

Opcode:

23 8 7 4 3 0

DATA BUS MOVE FIELD

nc...

OPTIONAL EFFECTIVE ADDRESS EXTENSION

0011

d010

cale Semiconductor,

Frees

Instruction Fields:

A0 B1

Timing: 2+mv oscillator clock cycles Memory: 1+mv program words

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ASR Arithmetic Shift Accumulator Right ASR

55 47 23 0

Operation:

Assembler Syntax: ASR D (parallel move)

Description: Arithmetically shift the destination operand D one bit to the right and store

the result in the destination accumulator. The LS bit of D prior to instruction execution is shifted into the carry bit C, and the MS bit of D is held constant.

C (parallel move)

nc...

cale Semiconductor,

Frees

Example:

ASR B X:–(R3),R3 ;divide B by 2, update R3, load R3

Before Execution After Execution

B B

SR SR

$A8:A86420:A86421

$0300 $0329

$D4:543210:543210

Explanation of Example: Prior to execution, the 56-bit B accumulator contains the value $A8:A86420:A86421. The execution of the ASR B instruction shifts the 56-bit value in the B accumulator one bit to the right and stores the result back in the B accumulator.

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

S1 S0 I1 I0

MR CCR

LEUNZVC

Note: The definition of the E and U bits varies according to the scaling mode being used.

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ASR Arithmetic Shift Accumulator Right ASR

Refer to A.4 CONDITION CODE COMPUTATION for complete details.

Instruction Format:

ASR D

Opcode:

23 8 7 4 3 0

DATA BUS MOVE FIELD

OPTIONAL EFFECTIVE ADDRESS EXTENSION

nc...

0010

d010

cale Semiconductor,

Frees

Instruction Fields:

A0 B1

Timing: 2+mv oscillator clock cycles Memory: 1+mv program words

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BCHG Bit Test and Change BCHG

Operation: Assembler Syntax:

D[n] ➞ C; BCHG #n,X:ea D[n] ➞ D[n]

D[n] ➞ C; BCHG #n,X:aa

] ➞ D[n]

D[n D[n] ➞ C; BCHG #n,X:pp

] ➞ D[n]

D[n

nc...

cale Semiconductor,

Frees

D[n] ➞ C; BCHG #n,Y:ea

] ➞ D[n]

D[n D[n] ➞ C; BCHG #n,Y:aa

] ➞ D[n]

D[n D[n] ➞ C; BCHG #n,Y:pp

] ➞ D[n]

D[n D[n] ➞ C; BCHG #n,D

] ➞ D[n]

D[n

Description: Test the n result in the destination location. The state of the n condition code register. After the test, the n

bit of the destination operand D, complement it, and store the

bit is stored in the carry bit C of the

bit of the destination location is complemented. The bit to be tested is selected by an immediate bit number from 0–23. This instruction performs a read-modify-write operation on the destination location using two destination accesses before releasing the bus. This instruction provides a test-andchange capability which is useful for synchronizing multiple processors using a shared memory. This instruction can use all memory alterable addressing modes.

Example:

BCHG #$7,X:<<$FFE2 ;test and change bit 7 in I/O Port B DDR

Before Execution After Execution

X:$FFE2

SR SR

A - 32 DSP56000/DSP56001 USER’S MANUAL MOTOROLA

$000000

$0300

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X;$FFE2

$000080

$0300

Page 33

nc...

cale Semiconductor,

Frees

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BCHG Bit Test and Change BCHG

Explanation of Example: Prior to execution, the 24-bit X location X:$FFE2 (I/O port B

data direction register) contains the value $000000. The execution of the BCHG #$7,X:<<$FFE2 instruction tests the state of the 7th bit in X:$FFE2, sets the carry bit C accordingly, and then complements the 7th bit in X:$FFE2.

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

CCR Condition Codes:

For destination operand SR:

C — Changed if bit 0 is specified. Not affected otherwise. V — Changed if bit 1 is specified. Not affected otherwise. Z — Changed if bit 2 is specified. Not affected otherwise. N — Changed if bit 3 is specified. Not affected otherwise. U — Changed if bit 4 is specified. Not affected otherwise. E — Changed if bit 5 is specified. Not affected otherwise.

L — Changed if bit 6 is specified. Not affected otherwise.

For other destination operands:

C — Set if bit tested is set. Cleared otherwise. V — Not affected Z — Not affected N — Not affected U — Not affected E —Not affected L —Not affected

S1 S0 I1 I0

MR CCR

LEUNZVC

MR Status Bits:

For destination operand SR:

I0 — Changed if bit 8 is specified. Not affected otherwise. I1 — Changed if bit 9 is specified. Not affected otherwise. S0 — Changed if bit 10 is specified. Not affected otherwise. S1 — Changed if bit 11 is specified. Not affected otherwise. T — Changed if bit 13 is specified. Not affected otherwise. LF — Changed if bit 15 is specified. Not affected otherwise.

MOTOROLA DSP56000/DSP56001 USER’S MANUAL A - 33

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BCHG Bit Test and Change BCHG

For other destination operands:

I0 — Not affected I1 — Not affected S0 — Not affected S1 — Not affected T — Not affected LF — Not affected

Instruction Format:

nc...

BCHG #n,X:ea BCHG #n,Y:ea

cale Semiconductor,

Frees

Opcode:

23 16 15 8 7 0

0000101101MMMRRR0S0bbbbb

OPTIONAL EFFECTIVE ADDRESS EXTENSION

Instruction Fields:

#n=bit number=bbbbb, ea=6-bit Effective Address=MMMRRR

Effective

Addressing Mode M M M R R R Memory SpaceS Bit Number bbbbb

(Rn)-Nn 0 0 0 r r r X Memory 0 00000 (Rn)+Nn 0 0 1 r r r Y Memory 1 (Rn)- 0 1 0 r r r (Rn)+ 0 1 1 r r r • (Rn) 1 0 0 r r r 10111 (Rn+Nn) 1 0 1 r r r

-(Rn) 1 1 1 r r r Absolute address 1 1 0 0 0 0

•

where “rrr” refers to an address register R0-R7

Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words

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BCHG Bit Test and Change BCHG

Instruction Format:

BCHG #n,X:aa BCHG #n,Y:aa

Opcode:

23 16 15 8 7 0

0000101100aaaaaa0S0bbbbb

Instruction Fields:

#n=bit number=bbbbb,

nc...

aa=6-bit Absolute Short Address=aaaaaa

Absolute Short Address aaaaaa Memory SpaceS Bit Number bbbbb

cale Semiconductor,

Frees

000000 X Memory 0 00000

• Y Memory 1 •

• 10111

111111

Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words

Instruction Format:

BCHG #n,X:pp BCHG #n,Y:pp

Opcode:

23 16 15 8 7 0 0000101110pppppp0S0bbbbb

Instruction Fields:

#n=bit number=bbbbb, ea=6-bit I/O Short Address=pppppp

I/O Short Address pppppp Memory SpaceS Bit Number bbbbb

000000 X Memory 0 00000

• Y Memory 1 •

• 10111

111111

Timing: 4+mvb oscillator clock cycles

MOTOROLA DSP56000/DSP56001 USER’S MANUAL A - 35

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BCHG Bit Test and Change BCHG

Memory: 1+ea program words Instruction Format:

BCHG #n,D

Opcode:

23 16 15 8 7 0

0000101111DDDDDD010bbbbb

Instruction Fields:

nc...

#n=bit number=bbbbb, D=destination register=DDDDDD xxxx=16-bit Absolute Address in extension word

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Destination Register D D D D D D Bit Number bbbbb

4 registers in Data ALU 0 0 0 1 D D 00000 8 accumulators in Data ALU 0 0 1 D D D 8 address registers in AGU 0 1 0 T T T 10111 8 address offset registers in AGU 0 1 1 N N N 8 address modifier registers in AGU 1 0 0 F F F 8 program controller registers 1 0 1 G G G

See A.9 INSTRUCTION ENCODING and Table A-18 for specific register encodings.

Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words

•

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BCLR Bit Test and Clear BCLR

Operation: Assembler Syntax:

D[n] ➞ C; BCLR #n,X:ea

0 ➞ D[n]

D[n] ➞ C; BCLR #n,X:aa

0 ➞ D[n]

D[n] ➞ C; BCLR #n,X:pp

0 ➞ D[n]

nc...

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D[n] ➞ C; BCLR #n,Y:ea

0 ➞ D[n]

D[n] ➞ C; BCLR #n,Y:aa

0 ➞ D[n]

D[n] ➞ C; BCLR #n,Y:pp

0 ➞ D[n]

D[n] ➞ C; BCLR #n,D

0 ➞ D[n]

Description: Test the n the destination location. The state of the n code register. After the test, the n

bit of the destination operand D, clear it and store the result in

bit is stored in the carry bit C of the condition

bit of the destination location is cleared. The bit to be tested is selected by an immediate bit number from 0–23. This instruction performs a read-modify-write operation on the destination location using two destination accesses before releasing the bus. This instruction provides a test-and-clear capability which is useful for synchronizing multiple processors using a shared memory. This instruction can use all memory alterable addressing modes.

Example:

BCLR #$E,X:<<$FFE4 ;test and clear bit 14 in I/O Port B Data Reg.

Before Execution After Execution

X:$FFE4

MOTOROLA DSP56000/DSP56001 USER’S MANUAL A - 37

$FFFFFF

$0300

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X:$FFE4

$FFBFFF

$0301

Page 38

nc...

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BCLR Bit Test and Clear BCLR

Explanation of Example: Prior to execution, the 24-bit X location X:$FFE4 (I/O port B

data register) contains the value $FFFFFF. The execution of the BCLR #$E,X:<<$FFE4 instruction tests the state of the 14th bit in X:$FFE4, sets the carry bit C accordingly, and then clears the 14th bit in X:$FFE4.

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CCR Condition Codes:

For destination operand SR:

L — Changed if bit 6 is specified. Not affected otherwise.

For other destination operands:

C — Set if bit tested is set. Cleared otherwise. V — Not affected Z — Not affected N — Not affected U — Not affected E —Not affected L —Not affected

S1 S0 I1 I0

MR CCR

LEUNZVC

MR Status Bits:

For destination operand SR:

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BCLR Bit Test and Clear BCLR

For other destination operands:

I0 — Not affected I1 — Not affected S0 — Not affected S1 — Not affected T — Not affected LF — Not affected

Instruction Format:

nc...

BCLR #n,X:ea BCLR #n,Y:ea

cale Semiconductor,

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Opcode:

23 16 15 8 7 0

0000101001MMMRRR0S0bbbbb

OPTIONAL EFFECTIVE ADDRESS EXTENSION

Instruction Fields:

#n=bit number=bbbbb, ea=6-bit Effective Address=MMMRRR

Effective

Addressing Mode M M M R R R Memory SpaceS Bit Number bbbbb

(Rn)-Nn 0 0 0 r r r X Memory 0 00000 (Rn)+Nn 0 0 1 r r r Y Memory 1 (Rn)- 0 1 0 r r r (Rn)+ 0 1 1 r r r • (Rn) 1 0 0 r r r 10111 (Rn+Nn) 1 0 1 r r r

-(Rn) 1 1 1 r r r Absolute address 1 1 0 0 0 0

•

where “rrr” refers to an address register R0-R7

Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words

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BCLR Bit Test and Clear BCLR

Instruction Format:

BCLR #n,X:aa BCLR #n,Y:aa

Opcode:

23 16 15 8 7 0 0000101000aaaaaa0S0bbbbb

Instruction Fields:

#n=bit number=bbbbb, aa=6-bit Absolute Short Address=aaaaaa

nc...

Absolute Short Address aaaaaa Memory SpaceS Bit Number bbbbb

cale Semiconductor,

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000000 X Memory 0 00000

• Y Memory 1 •

• 10111

111111

Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words

Instruction Format:

BCLR #n,X:pp BCLR #n,Y:pp

Opcode:

23 16 15 8 7 0 0000101000pppppp0S0bbbbb

Instruction Fields:

#n=bit number=bbbbb, ea=6-bit I/O Short Address=pppppp

I/O Short Address pppppp Memory SpaceS Bit Number bbbbb

000000 X Memory 0 00000

• Y Memory 1 •

• 10111

111111

Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words

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BCLR Bit Test and Clear BCLR

Instruction Format:

BCLR #n,D

Opcode:

23 16 15 8 7 0 0000101011DDDDDD010bbbbb

Instruction Fields:

nc...

#n=bit number=bbbbb, D=destination register=DDDDDD xxxx=16-bit Absolute Address in extension word

cale Semiconductor,

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Destination Register D D D D D D Bit Number bbbbb

See A.9 INSTRUCTION ENCODING and Table A-18 for specific register encodings.

Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words

•

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BSET Bit Test and Clear BSET

Operation: Assembler Syntax:

D[n] ➞ C; BSET #n,X:ea

1 ➞ D[n]

D[n] ➞ C; BSET #n,X:aa

1 ➞ D[n]

D[n] ➞ C; BSET #n,X:pp

1 ➞ D[n]

nc...

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D[n] ➞ C; BSET #n,Y:ea

1 ➞ D[n]

D[n] ➞ C; BSET #n,Y:aa

1 ➞ D[n]

D[n] ➞ C; BSET #n,Y:pp

1 ➞ D[n]

D[n] ➞ C; BSET #n,D

1 ➞ D[n]

Description: Test the nth bit of the destination operand D, set it, and store the result in the

destination location. The state of the n code register. After the test, the n tested is selected by an immediate bit number from 0–23. This instruction performs a read-modify-write operation on the destination location using two destination accesses before releasing the bus. This instruction provides a test-and-set capability which is useful for synchronizing multiple processors using a shared memory. This instruction can use all memory alterable addressing modes.

Example:

BSET #$0,X:<<$FFE5;test and clear bit 14 in I/O Port B Data Reg.

bit is stored in the carry bit C of the condition

bit of the destination location is set. The bit to be

Before Execution After Execution

X:$FFE5

A - 42 DSP56000/DSP56001 USER’S MANUAL MOTOROLA

$000000

$0300

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X:$FFE5

$000001

$0300

Page 43

nc...

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BSET Bit Test and Clear BSET

Explanation of Example: Prior to execution, the 24-bit X location X:$FFE5 (I/O port C

data register) contains the value $000000. The execution of the BSET #$0,X:<<$FFE5 instruction tests the state of the 0 then sets the 0th bit in X:$FFE5.

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

MR CCR

CCR Condition Codes:

For destination operand SR:

L — Changed if bit 6 is specified. Not affected otherwise.

For other destination operands:

C — Set if bit tested is set. Cleared otherwise. V — Not affected Z — Not affected N — Not affected U — Not affected E —Not affected L —Not affected

bit in X:$FFE5, sets the carry bit C accordingly, and

S1 S0 I1 I0

LEUNZVC

MR Status Bits:

For destination operand SR:

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BSET Bit Test and Clear BSET

For other destination operands:

I0 — Not affected I1 — Not affected S0 — Not affected S1 — Not affected T — Not affected LF — Not affected

Instruction Format:

nc...

BSET #n,X:ea BSET #n,Y:ea

cale Semiconductor,

Frees

Opcode:

23 16 15 8 7 0

0000101001MMMRRR0S1bbbbb

OPTIONAL EFFECTIVE ADDRESS EXTENSION

Instruction Fields:

#n=bit number=bbbbb, ea=6-bit Effective Address=MMMRRR

Effective

Addressing Mode M M M R R R Memory SpaceS Bit Number bbbbb

(Rn)-Nn 0 0 0 r r r X Memory 0 00000 (Rn)+Nn 0 0 1 r r r Y Memory 1 (Rn)- 0 1 0 r r r (Rn)+ 0 1 1 r r r • (Rn) 1 0 0 r r r 10111 (Rn+Nn) 1 0 1 r r r

-(Rn) 1 1 1 r r r Absolute address 1 1 0 0 0 0

•

where “rrr” refers to an address register R0-R7

Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words

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BSET Bit Test and Clear BSET

Instruction Format:

BSET #n,X:aa BSET #n,Y:aa

Opcode:

23 16 15 8 7 0

00001010010aa aaaa 0 S1bbbbb

Instruction Fields:

#n=bit number=bbbbb, aa=6-bit Absolute Short Address=aaaaaa

nc...

Absolute Short Address aaaaaa Memory SpaceS Bit Number bbbbb

cale Semiconductor,

Frees

000000 X Memory 0 00000

• Y Memory 1 •

• 10111

111111

Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words

Instruction Format:

BSET #n,X:pp BSET #n,Y:pp

Opcode:

23 16 15 8 7 0 0000101010pppppp0S1bbbbb

Instruction Fields:

#n=bit number=bbbbb, ea=6-bit I/O Short Address=pppppp

I/O Short Address pppppp Memory SpaceS Bit Number bbbbb

000000 X Memory 0 00000

• Y Memory 1 •

• 10111

111111

Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words

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BSET Bit Test and Set BSET

Instruction Format:

BSET #n,D

Opcode:

23 16 15 8 7 0

0000101011DDDDDD011bbbbb

Instruction Fields:

#n=bit number=bbbbb,

nc...

D=destination register=DDDDDD xxxx=16-bit Absolute Address in extension word

cale Semiconductor,

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Destination Register D D D D D D Bit Number bbbbb

See A.9 INSTRUCTION ENCODING and Table A-18 for specific register encodings.

Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words

•

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BTST Bit Test and Set BTST

Operation: Assembler Syntax:

D[n] ➞ C; BTST #n,X:ea D[n] ➞ C; BTST #n,X:aa D[n] ➞ C; BTST #n,X:pp D[n] ➞ C; BTST #n,Y:ea D[n] ➞ C; BTST #n,Y:aa D[n] ➞ C; BTST #n,Y:pp

nc...

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D[n] ➞ C; BTST #n,D

Description: Test the n

bit of the destination operand D. The state of the nth bit is stored in the carry bit C of the condition code register. The bit to be tested is selected by an immediate bit number from 0–23. This instruction is useful for performing serial to parallel conversion when used with the appropriate rotate instructions. This instruction can use all memory alterable addressing modes.

Example:

BTST #$0,X:<<$FFEE ;read SSI serial input flag IF1 into C bit ROL A ;rotate carry bit C into LSB of A1

Before Execution After Execution

X:$FFEE

$000002

$0300 $0301

X:$FFEE

$000002

Explanation of Example: Prior to execution, the 24-bit X location X:$FFEE (I/O SSI status register) contains the value $000002. The execution of the BTST #$1,X:<<$FFEE instruction tests the state of the 1st bit (serial input flag IF1) in X:$FFEE and sets the carry bit C accordingly. This instruction sequence illustrates serial to parallel conversion using the carry bit C and the 24-bit A1 register.

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BTST Bit Test and Set BTST

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

CCR Condition Codes:

C — Set if bit tested is set. Cleared otherwise. V — Not affected Z — Not affected

nc...

N — Not affected U — Not affected E —Not affected L —Not affected

S1 S0 I1 I0

MR CCR

LEUNZVC

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MR Status bits are not affected. SP — Stack Pointer:

For destination operand SSH: SP — Decrement by 1. For other destination operands:

Instruction Format:

BTST #n,X:ea BTST #n,Y:ea

Opcode:

23 16 15 8 7 0

0000101101MMMRRR0S1bbbbb

OPTIONAL EFFECTIVE ADDRESS EXTENSION

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BTST Bit Test BTST

Instruction Fields:

#n=bit number=bbbbb, ea=6-bit Effective Address=MMMRRR

Effective

Addressing Mode M M M R R R Memory SpaceS Bit Number bbbbb

(Rn)-Nn 0 0 0 r r r X Memory 0 00000 (Rn)+Nn 0 0 1 r r r Y Memory 1 (Rn)- 0 1 0 r r r (Rn)+ 0 1 1 r r r •

nc...

(Rn) 1 0 0 r r r 10111 (Rn+Nn) 1 0 1 r r r

-(Rn) 1 1 1 r r r Absolute address 1 1 0 0 0 0

•

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Frees

where “rrr” refers to an address register R0-R7

Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words Instruction Format:

BTST #n,X:aa BTST #n,Y:aa

Opcode:

23 16 15 8 7 0 0000101100aaaaaa0S1bbbbb

Instruction Fields:

#n=bit number=bbbbb, aa=6-bit Absolute Short Address=aaaaaa

Absolute Short Address aaaaaa Memory SpaceS Bit Number bbbbb

000000 X Memory 0 00000

• Y Memory 1 •

• 10111

111111

Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words

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BTST Bit Test BTST

Instruction Format:

BTST #n,X:pp BTST #n,Y:pp

Opcode:

23 16 15 8 7 0

0000101110pppppp0S1bbbbb

Instruction Fields:

nc...

#n=bit number=bbbbb, ea=6-bit I/O Short Address=pppppp

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I/O Short Address pppppp Memory SpaceS Bit Number bbbbb

000000 X Memory 0 00000

• Y Memory 1 •

• 10111

111111

Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words

Instruction Format:

BTST #n,D

Opcode:

23 16 15 8 7 0

0000101111DDDDDD011bbbbb

Instruction Fields:

#n=bit number=bbbbb, D=destination register=DDDDDD, xxxx=16-bit Absolute Address in extension word

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BTST Bit Test BTST

Destination Register D D D D D D Bit Number bbbbb

4 registers in Data ALU 0 0 0 1 D D 00000 8 accumulators in Data ALU 0 0 1 D D D • 8 address registers in AGU 0 1 0 T T T 10111 8 address offset registers in AGU 0 1 1 N N N 8 address modifier registers in AGU 1 0 0 F F F 8 program controller registers 1 0 1 G G G

See A.9 INSTRUCTION ENCODING and Table A-18 for specific register encodings.

nc...

Timing: 4+mvb oscillator clock cycles

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Memory: 1+ea program words

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CLR Clear Accumulator CLR

Operation: Assembler Syntax:

0 ➞D (parallel move) CLR D (parallel move)

Description: Clear the destination accumulator. This is a 56-bit clear instruction. Example:

CLR A #$7F,N ;clear A, set up N0 addr. reg.

nc...

cale Semiconductor,

Frees

Before Execution After Execution

$12:345678:9ABCDE $00:000000:000000

Explanation of Example: Prior to execution, the 56-bit A accumulator contains the value $12:345678:9ABCDE. The execution of the CLR A instruction clears the 56-bit A accumulator to zero.

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

S1 S0 I1 I0

MR CCR

LEUNZVC

L — Set if data limiting has occurred during parallelmove E — Always cleared U — Always set N — Always cleared Z— Always set V — Always cleared

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CLR Clear Accumulator CLR

Instruction Format:

CLR D

Opcode:

23 8 7 4 3 0

DATA BUS MOVE FIELD

OPTIONAL EFFECTIVE ADDRESS EXTENSION

nc...

Instruction Fields:

0001

d011

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A0 B1

Timing: 2+mv oscillator clock cycles Memory: 1+mv program words

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CMP Compare CMP

Operation: Assembler Syntax:

S2 – S1(parallel move) CMP S1, S2 (parallel move)

Description: Subtract the source one operand, S1, from the source two accumulator, S2, and update the condition code register. The result of the subtraction operation is not stored.

Note: This instruction subtracts 56-bit operands. When a word is specified as S1, it is sign extended and zero filled to form a valid 56-bit operand. For the carry to be set cor-

nc...

rectly as a result of the subtraction, S2 must be properly sign extended. S2 can be improperly sign extended by writing A1 or B1 explicitly prior to executing the compare so that A2 or B2, respectively, may not represent the correct sign extension. This note particularly applies to the case where it is extended to compare 24-bit operands such as X0 with A1.

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Example:

CMP Y0,B X0,X:(R6)+N6 Y1,Y:(R0)– ;comp. Y0 and B, save X0, Y1

Before Execution After Execution

B B

$00:000020:000000

$000024

$0300

$00:000020:000000

$000024

$0319

Explanation of Example: Prior to execution, the 56-bit B accumulator contains the value $00:000020:000000 and the 24-bit Y0 register contains the value $000024. The execution of the CMP Y0,B instruction automatically appends the 24-bit value in the Y0 register with 24 LS zeros, sign extends the resulting 48-bit long word to 56 bits, subtracts the result from the 56-bit B accumulator and updates the condition code register.

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CMP Compare CMP

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

nc...

Z— Set if A or B result equals zero V — Set if overflow has occurred in A or B result C — Set if a carry (or borrow) occurs from bit 55 of A or B result.

S1 S0 I1 I0

MR CCR

LEUNZVC

cale Semiconductor,

Frees

Note: The definition of the E and U bits varies according to the scaling mode being used. Refer to A.4 CONDITION CODE COMPUTATION for complete details.

Instruction Format:

CMP S1, S2

Opcode:

23 8 7 4 3 0

DATA BUS MOVE FIELD

OPTIONAL EFFECTIVE ADDRESS EXTENSION

0JJJ

d101

Instruction Fields:

S1,S2 J J J d S1,S2 J J J d

B,A 0 0 0 0 Y0,B 1 0 1 1 A,B 0 0 0 1 X1,A 1 1 0 0 X0,A 1 0 0 0 X1,B 1 1 0 1 X0,B 1 0 0 1 Y1,A 1 1 1 0 Y0,A 1 0 1 0 Y1,B 1 1 1 1

Timing: 2+mv oscillator clock cycles Memory: 1+mv program words

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CMPM Compare Magnitude CMPM

Operation: Assembler Syntax:

|S2| – |S1|(parallel move) CMPM S1, S2 (parallel move)

Description: Subtract the absolute value (magnitude) of the source one operand, S1, from the absolute value of the source two accumulator, S2, and update the condition code register. The result of the subtraction operation is not stored.

Note: This instruction subtracts 56-bit operands. When a word is specified as S1, it is sign extended and zero filled to form a valid 56-bit operand. For the carry to be set cor-

nc...

cale Semiconductor,

Frees

Example:

CMPM X1,A BA,L:–(R4) ;comp. Y0 and B, save X0, Y1

Before Execution After Execution

A A

X1 X1

SR SR

$00:000006:000000

$FFFFF7

$0300 $0319

$00:000006:000000

$FFFFF7

Explanation of Example: Prior to execution, the 56-bit A accumulator contains the value $00:000006:000000, and the 24-bit X1 register contains the value $FFFFF7. The execution of the CMPM X1,A instruction automatically appends the 24-bit value in the X1 register with 24 LS zeros, sign extends the resulting 48-bit long word to 56 bits, takes the absolute value of the resulting 56-bit number, subtracts the result from the absolute value of the contents of the 56-bit A accumulator, and updates the condition code register.

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CMPM Compare Magnitude CMPM

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

nc...

Z— Set if A or B result equals zero V — Set if overflow has occurred in A or B result C — Set if a carry (or borrow) occurs from bit 55 of A or B result.

S1 S0 I1 I0

MR CCR

LEUNZVC

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Note: The definition of the E and U bits varies according to the scaling mode being used. Refer to A.4 CONDITION CODE COMPUTATION for complete details.

Instruction Format:

CMPM S1, S2

Opcode:

23 8 7 4 3 0

DATA BUS MOVE FIELD

OPTIONAL EFFECTIVE ADDRESS EXTENSION

0JJJ

d111

Instruction Fields:

S1,S2 J J J d S1,S2 J J J d S1,S2 J J J d

B,A 0 0 0 0 X0,B 1 0 0 1 X1,A 1 1 0 0 A,B 0 0 0 1 Y0,A 1 0 1 0 X1,B 1 1 0 1 X0,A 1 0 0 0 Y0,B 1 0 1 1 Y1,A 1 1 1 0

Y1,B 1 1 1 1

Timing: 2+mv oscillator clock cycles Memory: 1+mv program words

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DIV Divide Interation DIV

Operation: If D[55]⊕S[23]=1,

55 47 23 0

nc...

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then

Destination Accumulator D

55 47 23 0

else

Destination Accumulator D

where ⊕ denotes the logical exclusive OR operator

Assembler Syntax: DIV S,D Description:

Divide the destination operand D by the source operand S and store the result in the destination accumulator D. The 48-bit dividend must be a positive fraction which has

been sign extended to 56-bits and is stored in the full 56-bit destination accumulator D. The 24-bit divisor is a signed fraction and is stored in the source operand S.

Each DIV iteration calculates one quotient bit using a nonrestoring fractional division algorithm (see description on the next page). After the execution of the first DIV instruction, the destination operand holds both the partial remainder and the formed quotient. The partial remainder occupies the high-order portion of the destination accumulator D and is a signed fraction. The formed quotient occupies the low-order portion of the destination accumulator D (A0 or B0) and is a positive fraction. One bit of the formed quotient is shifted into the LS bit of the destination accumulator at the start of each DIV iteration. The formed quotient is the true quotient if the true quotient is positive. If the true quotient is negative, the formed quotient must be negated. Valid results are obtained only when |D| < |S| and the operands are interpreted as fractions. Note that this condition ensures that the magnitude of the quotient is less than one (i.e., is fractional) and precludes division by zero.

C+S

C–S

The DIV instruction calculates one quotient bit based on the divisor and the previous partial remainder. To produce an N-bit quotient, the DIV instruction is executed N times where N is the number of bits of precision desired in the quotient, 1;leN;le24. Thus, for a full-precision (24 bit) quotient, 24 DIV iterations are required. In general, executing the DIV instruction N times produces an N-bit quotient and a 48-bit remainder which has (48–N) bits of precision and whose N MS bits are zeros. The partial remainder is not a true remainder and must be corrected due to the nonrestoring nature of the division algo-

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DIV Divide Interation DIV

rithm before it may be used. Therefore, once the divide is complete, it is necessary to reverse the last DIV operation and restore the remainder to obtain the true remainder.

The DIV instruction uses a nonrestoring fractional division algorithm which consists of the following operations (see the previous Operation diagram):

1. Compare the source and destination operand sign bits: An exclusive OR operation is performed on bit 55 of the destination operand D and bit 23 of the source operand S;

2. Shift the partial remainder and the quotient: The 55-bit destination accumu-

nc...

lator D is shifted one bit to the left. The carry bit C is moved into the LS bit (bit

0) of the accumulator;

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3. Calculate the next quotient bit and the new partial remainder: The 24-bit source operand S (signed divisor) is either added to or subtracted from the MSP portion of the destination accumulator (A1 or B1), and the result is stored back into the MSP portion of that destination accumulator. If the result of the exclusive OR operation previously described was a ‘‘1’’ (i.e., the sign bits were different), the source operand S is added to the accumulator. If the result of the exclusive OR operation was a ‘‘0’’ (i.e., the sign bits were the same), the source operand S is subtracted from the accumulator. Due to the automatic sign extension of the 24-bit signed divisor, the addition or subtraction operation correctly sets the carry bit C of the condition code register with the next quotient bit.

Example:

SAVEQUO TFR X0,B B0,X1 ;save quo. in X1, get signed divisor

DONE . . . . . . .

(4-Quadrant division, 24-bit signed quotient, 48-bit signed remainder)

ABS A A,B ;make dividend positive, copy A1 to B1 EOR X0,B B,X:$0 ;save rem. sign in X:$0, quo. sign in N AND #$FE,CCR ;clear carry bit C (quotient sign bit) REP #$18 ;form a 24-bit quotient DIV X0,A ;form quotient in A0, remainder in A1 TFR A,B ;save quotient and remainder in B1,B0 JPL SAVEQUO ;go to SAVEQUO if quotient is positive NEG B ;complement quotient if N bit set

ABS B ;get absolute value of signed divisor ADD A,B ;restore remainder in B1 JCLR #23,X:$0,DONE ;go to DONE if remainder is positive MOVE #$0,B0 ;clear LS 24 bits of B NEG B ;complement remainder if negative

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DIV Divide Interation DIV

Before Execution After Execution

A A

$00:0E66D7:F2832C

$FF:EDCCAA:654321

X0 X0

X1 X1

B B

nc...

Explanation of Example: Prior to execution, the 56-bit A accumulator contains the 56-

$00:000000:000000 $00:000100:654321

$123456

$000000

$123456

$654321

bit, sign-extended fractional dividend D (D=$00.0E66D7:F2832C=0.112513535894635 approx.) and the 24-bit X0 register contains the 24-bit, signed fractional divisor S (S=$123456=0.142222166061401). Since |D|<|S|, the execution of the previous divide routine stores the correct 24-bit signed quotient in the 24-bit X1 register (A/ X0=0.79111111164093=$654321=X1). The partial remainder is restored by reversing the last DIV operation and adding back the absolute value of the signed divisor in X0 to the partial remainder in A1. This produces the correct LS 24 bits of the 48-bit signed remained in the 24-bit B1 register. Note that the remainder is really a 48-bit value which has 24 bits of precision. Thus, the correct 48-bit remainder is $000000:000100 which equals 0.0000000000018190 approximately.

Note that the divide routine used in the previous example assumes that the sign-

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extended 56-bit signed fractional dividend is stored in the A accumulator and that the 24bit signed fractional divisor is stored in the X0 register. This routine produces a full 24-bit

signed quotient and a 48-bit signed remainder.

Frees

This routine may be greatly simplified for the case in which only positive, fractional operands are used to produce a 24-bit positive quotient and a 48-bit positive remainder, as shown in the following example:

1-Quadrant division, 24-bit unsigned quotient, 48-bit unsigned remainder

AND #$FE,CCR ;clear carry bit C (quotient sign bit) REP #$18 ;form a 24-bit quotient and remainder DIV X0,A ;form quotient in A0, remainder in A1 ADD X0,A ;restore remainder in A1

Note that this routine assumes that the 56-bit positive, fractional, sign-extended dividend is stored in the A accumulator and that the 24-bit positive, fractional divisor is stored in

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DIV Divide Interation DIV

the X0 register. After execution, the 24-bit positive fractional quotient is stored in the A0 register; the LS 24 bits of the 48-bit positive fractional remainder are stored in the A1 register.

There are many variations possible when choosing a suitable division routine for a given application. The selection of a suitable division routine normally involves specification of the following items:

1. the number of bits of precision in the dividend;

nc...

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Frees

2. the number of bits of precision N in the quotient;

3. whether the value of N is fixed or is variable;

4. whether the operands are unsigned or signed;

5. whether or not the remainder is to be calculated.

A complete discussion of the various division routines is beyond the scope of this manual. For a more complete discussion of these routines, refer to the application note entitled Fractional and Interger Arithmetic Using the DSP56001.

For extended precision division (i.e., for N-bit quotients where N>24), the DIV instruction is no longer applicable, and a user-defined N-bit division routine is required. For further information on division algorithms, refer to pages 524–530 of Theory and Application of Digital Signal Processing by Rabiner and Gold (Prentice-Hall, 1975), pages 190–199 of Computer Architecture and Organization by John Hayes (McGraw-Hill, 1978), pages 213–223 of Computer Arithmetic: Principles, Architecture, and Design by Kai Hwang (John Wiley and Sons, 1979), or other references as required.

Condition Codes

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

S1 S0 I1 I0

MR CCR

LEUNZVC

L — Set if overflow bit V is set V — Set if the MS bit of the destination operand is changed as a result of the instruction’s

left shift operation

C — Set if bit 55 of the result is cleared.

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DIV Divide Iteration DIV

Instruction Format:

DIV S,D

Opcode:

23 16 15 8 7 0

000000011000000001JJd000

Instruction Fields:

S,D J J d S,D J J d

nc...

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Frees

X0,A 0 0 0 X1,A 1 0 0 X0,B 0 0 1 X1,B 1 0 1 Y0,A 0 1 0 Y1,A 1 1 0 Y0,B 0 1 1 Y1,B 1 1 1

Timing: 2 oscillator clock cycles Memory: 1 program word

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DO Start Hardware Loop DO

Operation: Assembler Syntax:

SP+1 ➞ SP;LA ➞ SSH;LC ➞ SSL;X:ea ➞ LC DO X:ea,expr SP+1 ➞ SP;PC ➞ SSH;SR ➞ SSL;expr –1 ➞ LA 1 ➞ LF

SP+1 ➞ SP;LA ➞ SSH;LC ➞ SSL;X:aa ➞ LC DO X:aa,expr SP+1 ➞ SP;PC ➞ SSH;SR ➞ SSL;expr –1 ➞ LA 1 ➞ LF

SP+1 ➞ SP;LA ➞ SSH;LC ➞ SSL;Y:ea ➞ LC DO Y:ea,expr

nc...

SP+1 ➞ SP;PC ➞ SSH;SR ➞ SSL;expr –1 ➞ LA 1 ➞ LF

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SP+1 ➞ SP;LA ➞ SSH;LC ➞ SSL;Y:aa ➞ LC DO Y:aa,expr SP+1 ➞ SP;PC ➞ SSH;SR ➞ SSL;expr –1 ➞ LA 1 ➞ LF

SP+1 ➞ SP;LA ➞ SSH;LC ➞ SSL;#xxx ➞ LC DO #xxx,expr SP+1 ➞ SP;PC ➞ SSH;SR ➞ SSL;expr –1 ➞ LA 1 ➞ LF

SP+1 ➞ SP;LA ➞ SSH;LC ➞ SSL;S ➞ LC DO S,expr SP+1 ➞ SP;PC ➞ SSH;SR ➞ SSL;expr –1 ➞ LA 1 ➞ LF

End of Loop: SSL(LF) ➞ SR;SP–1 ➞ SP SSH ➞ LA;SSL ➞ LC;SP – 1 ➞ SP

Description: Begin a hardware DO loop that is to be repeated the number of times specified in the instruction’s source operand and whose range of execution is terminated by the destination operand (previously shown as ‘‘expr’’). No overhead other than the execution of this DO instruction is required to set up this loop. DO loops can be nested and the loop count can be passed as a parameter.

During the first instruction cycle, the current contents of the loop address (LA) and the loop counter (LC) registers are pushed onto the system stack. The DO instruction’s source operand is then loaded into the loop counter (LC) register. The LC register contains the remaining number of times the DO loop will be executed and can be accessed from inside the DO loop subject to certain restrictions. If LC equals zero, the DO loop is executed 65,536 times. All address register indirect addressing modes may be used to generate the effective address of the source operand. If immediate short data is speci-

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DO Start Hardware Loop DO

fied, the 12 LS bits of LC are loaded with the 12-bit immediate value, and the four MS bits of LC are cleared.

During the second instruction cycle, the current contents of the program counter (PC) register and the status register (SR) are pushed onto the system stack. The stacking of the LA, LC, PC, and SR registers is the mechanism which permits the nesting of DO loops. The DO instruction’s destination operand (shown as ‘‘expr’’) is then loaded into the loop address (LA) register. This 16-bit operand is located in the instruction’s 24-bit absolute address extension word as shown in the opcode section. The value in the program counter (PC) register pushed onto the system stack is the address of the first

nc...

instruction following the DO instruction (i.e., the first actual instruction in the DO loop). This value is read (i.e., copied but not pulled) from the top of the system stack to return to the top of the loop for another pass through the loop.

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During the third instruction cycle, the loop flag (LF) is set. This results in the PC being repeatedly compared with LA to determine if the last instruction in the loop has been fetched. If LA equals PC, the last instruction in the loop has been fetched and the loop counter (LC) is tested. If LC is not equal to one, it is decremented by one and SSH is loaded into the PC to fetch the first instruction in the loop again. If LC equals one, the ‘‘end-of-loop’’ processing begins.

When executing a DO loop, the instructions are actually fetched each time through the loop. Therefore, a DO loop can be interrupted. DO loops can also be nested. When DO loops are nested, the end-of-loop addresses must also be nested and are not allowed to be equal. The assembler generates an error message when DO loops are improperly nested. Nested DO loops are illustrated in the example.

Note: The assembler calculates the end-of-loop address to be loaded into LA (the absolute address extension word) by evaluating the end-of-loop expression ‘‘expr’’ and subtracting one. This is done to accommodate the case where the last word in the DO loop is a two-word instruction. Thus, the end-of-loop expression ‘‘expr’’ in the source code must represent the address of the instruction AFTER the last instruction in the loop as shown in the example.

During the ‘‘end-of-loop’’ processing, the loop flag (LF) from the lower portion (SSL) of SP is written into the status register (SR), the contents of the loop address (LA) register are restored from the upper portion (SSH) of (SP–1), the contents of the loop counter (LC) are restored from the lower portion (SSL) of (SP–1) and the stack pointer (SP) is decremented by two. Instruction fetches now continue at the address of the instruction following the last instruction in the DO loop. Note that LF is the only bit in the status register (SR) that is restored after a hardware DO loop has been exited.

Note: The loop flag (LF) is cleared by a hardware reset.

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DO Start Hardware Loop DO

Restrictions: The ‘‘end-of-loop’’ comparison previously described actually occurs at

instruction fetch time. That is, LA is being compared with PC when the instruction at LA– 2 is being executed. Therefore, instructions which access the program controller registers and/or change program flow cannot be used in locations LA–2, LA–1, or LA.

Proper DO loop operation is not guaranteed if an instruction starting at address LA–2, LA–1, or LA specifies one of the program controller registers SR, SP, SSL, LA, LC, or (implicitly) PC as a destination register. Similarly, the SSH program controller register may not be specified as a source or destination register in an instruction starting at address LA–2, LA–1, or LA. Additionally, the SSH register cannot be specified as a source register in the DO instruction itself and LA cannot be used as a target for jumps

nc...

to subroutine (i.e., JSR, JScc, JSSET, or JSCLR to LA). A DO instruction cannot be repeated using the REP instruction.

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Frees

The following instructions cannot begin at the indicated position(s) near the end of a DO loop:

At LA–2, LA–1, and LA DO

MOVEC from SSH MOVEM from SSH MOVEP from SSH MOVEC to LA, LC, SR, SP, SSH, or SSL MOVEM to LA, LC, SR, SP, SSH, or SSL MOVEP to LA, LC, SR, SP, SSH, or SSL ANDI MR ORI MR Two-word instructions which read LC, SP, or SSL

At LA–1 Single-word instructions (except REP) which read LC,

SP, or SSL, JCLR, JSET, two-word JMP, two-word Jcc

At LA any two-word instruction*

Jcc REP JCLR RESET JSET RTI JMP RTS JScc STOP JSR WAIT

*This restriction applies to the situation in which the DSP56000/DSP56001 simulator’s single-line assembler is used to change the last instruction in a DO loop from a one-word instruction to a two-word instruction.

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DO Start Hardware Loop DO

Other Restrictions: DO SSH,xxxx

JSR to (LA) whenever the loop flag (LF) is set

JScc to (LA) whenever the loop flag (LF) is set

JSCLR to (LA) whenever the loop flag (LF) is set

JSSET to (LA) whenever the loop flag (LF) is set

A DO instruction cannot be repeated using the REP instruction. Note: Due to pipelining, if an address register (R0–R7, N0–N7, or M0–M7) is changed

using a move-type instruction (LUA, Tcc, MOVE, MOVEC, MOVEM, MOVEP, or parallel move), the new contents of the destination address register will not be available for use

nc...

during the following instruction (i.e., there is a single instruction cycle pipeline delay). This restriction also applies to the situation in which the last instruction in a DO loop changes an address register and the first instruction at the top of the DO loop uses that same address register. The top instruction becomes the following instruction because of the loop construct.

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Similarly, since the DO instruction accesses the program controller registers, the DO instruction must not be immediately preceded by any of the following instructions:

Immediately before DO MOVEC to LA, LC, SSH, SSL, or SP

MOVEM to LA, LC, SSH, SSL, or SP

MOVEP to LA, LC, SSH, SSL, or SP

MOVEC from SSH

MOVEM from SSH

MOVEP from SSH

Example:

DO #cnt1, END1 ;begin outer DO loop

DO #cnt2, END2 ;begin inner DO loop

: :

MOVE A,X:(R0);p ;last instruction in inner loop

: ;(in outer loop)

END2 ;last instruction in outer loop

ADD A,B X:(R1)+,X0 first instruction after outer loop

END1 :

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DO Start Hardware Loop DO

Explanation of Example: This example illustrates a nested DO loop. The outer DO loop

will be executed ‘‘cnt1’’ times while the inner DO loop will be executed (‘‘cnt1’’ * ‘‘cnt2’’) times. Note that the labels END1 and END2 are located at the first instruction past the end of the DO loop, as mentioned above, and are nested properly.

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

S1 S0 I1 I0

MR CCR

LEUNZVC

nc...

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Frees

LF — Set when a DO loop is in progress L— Set if data limiting occurred [see Note 2]

Instruction Format:

DO X:ea, expr DO Y:ea, expr

Opcode:

23 20 19 16 15 8 7 0 0000011 001MMMRRR0 S000000

ABSOLUTE ADDRESS EXTENSION

Instruction Fields:

ea=6-bit Effective Address=MMMRRR, expr=16-bit Absolute Address in 24-bit extension word

Effective

Addressing Mode M M M R R R Memory SpaceS

(Rn)-Nn 0 0 0 r r r X Memory 0 (Rn)+Nn 0 0 1 r r r Y Memory 1 (Rn)- 0 1 0 r r r (Rn)+ 0 1 1 r r r (Rn) 1 0 0 r r r (Rn+Nn) 1 0 1 r r r

-(Rn) 1 1 1 r r r where “rrr” refers to an address register R0-R7

Timing: 6+mv oscillator clock cycles Memory: 2 program words

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DO Start Hardware Loop DO

Instruction Format:

DO X:aa, expr DO Y:aa, expr

Opcode:

23 20 19 16 15 8 7 0

0000011000aaaaaa0S000000

ABSOLUTE ADDRESS EXTENSION

Instruction Fields:

nc...

ea=6-bit Effective Short Address=aaaaaa, expr=16-bit Absolute Address in 24-bit extension word

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Absolute Short Address aaaaaa Memory SpaceS

000000 X Memory 0

• Y Memory 1

•

111111

Timing: 6+mv oscillator clock cycles Memory: 2 program words

Instruction Format:

DO #xxx, expr

Opcode:

23 20 19 16 15 8 7 0 00000110iiiiiiii1000hhhh

ABSOLUTE ADDRESS EXTENSION

Instruction Fields:

#xxx=12-bit Immediate Short Data = hhhhiiiiiiii, expr=16-bit Absolute Address in 24-bit extension word

Immediate Short Data hhhh i i i i i i i i

000000000000

•

111111111111

Timing: 6+mv oscillator clock cycles

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DO Start Hardware Loop DO

Memory: 2 program words Instruction Format:

DO S, expr

Opcode:

23 20 19 16 15 8 7 0 0000011011DDDDDDD0000000

ABSOLUTE ADDRESS EXTENSION

Instruction Fields:

nc...

S=6-bit Source operand = DDDDDD, expr=16-bit Absolute Address in 24-bit extension word

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Frees

Source D D D D D D S/L Source D DDDDD

X0 000100 no SR 111001 X1 000101 no OMR 111010 Y0 000110 no SP 111011 [see Note 1] Y1 000111 no SSL 111101 [see Note 1] A0 001000 no LA 111110 B0 001001 no LC 111111 A2 oo1o1o no R0-R7 010r r r B2 001100 no N0-N7 011nnn A1 001101 no M0-M7 100mmm A 001110 yes [see Note 2] B 001111 yes [see Note 2]

where rrr=Rn register where nnn=Nn register where mmm=Mn register

Note 1:

For DO SP, expr The actual value that will be loaded into the loop

counter (LC) is the value of the stack pointer (SP)

before the execution of the DO instruction, incre-

mented by 1.

Thus, if SP=3, the execution of the DO SP,expr instruction will load the loop counter (LC) with the value LC=4.

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DO Start Hardware Loop DO

For DO SSL, expr The loop counter (LC) will be loaded with its previous

value which was saved on the stack by the DO instruc-

tion itself.

Note 2:

If A or B is specified as a source operand, the accumulator value is optionally shifted according to the scaling mode bits in the status register. If the data out of the shifter indicates that the accumulator extension is in use, the 24-bit data is limited to a maximum positive or negative saturation constant. The shifted and limited value is loaded into LC,

nc...

although A or B remain unchanged. Timing: 6+mv oscillator clock cycles

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Memory: 2 program words

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NDDO End Current DO Loop ENDDO

Operation: Assembler Syntax:

SSL(LF) ➞ SR;SP – 1➞ SP ENDDO SSH ➞ LA; SSL ➞ LC;SP –1 ➞ SP

Description: Terminate the current hardware DO loop before the current loop counter (LC)

equals one. If the value of the current DO loop counter (LC) is needed, it must be read before the execution of the ENDDO instruction. Initially, the loop flag (LF) is restored from the system stack and the remaining portion of the status register (SR) and the program counter (PC) are purged from the system stack. The loop address (LA) and the loop

nc...

counter (LC) registers are then restored from the system stack.

Restrictions: Due to pipelining and the fact that the ENDDO instruction accesses the pro-

gram controller registers, the ENDDO instruction must not be immediately preceded by any of the following instructions:

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Frees

Immediately before ENDDO MOVEC to LA, LC, SR, SSH, SSL, or SP

MOVEM to LA, LC, SR, SSH, SSL, or SP MOVEP to LA, LC, SR, SSH, SSL, or SP MOVEC from SSH MOVEM from SSH MOVEP from SSH ORI MR ANDI MR

Also, the ENDDO instruction cannot be the last (LA) instruction in a DO loop.

Example:

DO Y0,NEXT ;exec. loop ending at NEXT (Y0) times

: MOVEC LC,A ;get current value of loop counter (LC) CMP Y1,A ;compare loop counter with value in Y1 JNE ONWARD ;go to ONWARD if LC not equal to Y1 ENDDO ;LC equal to Y1, restore all DO registers JMP NEXT ;go to NEXT

ONWARD : ;LC not equal to Y1, continue DO loop

: ;(last instruction in DO loop)

NEXT MOVE #$123456,X1 ;(first instruction AFTER DO loop)

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ENDDO End Current DO Loop ENDDO

Explanation of Example: This example illustrates the use of the ENDDO instruction to

terminate the current DO loop. The value of the loop counter (LC) is compared with the value in the Y1 register to determine if execution of the DO loop should continue. Note that the ENDDO instruction updates certain program controller registers but does not automatically jump past the end of the DO loop. Thus, if this action is desired, a JMP instruction (i.e., JMP NEXT as previously shown) must be included after the ENDDO instruction to transfer program control to the first instruction past the end of the DO loop.

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

nc...

S1 S0 I1 I0

MR CCR

LEUNZVC

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The condition codes are not affected by this instruction.

Instruction Format:

ENDDO

Opcode:

23 16 15 8 7 0

000000000000000010001100

Instruction Fields:

None

Timing: 2 oscillator clock cycles Memory: 1 program word

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EOR Logical Exclusive OR EOR

Operation: Assembler Syntax:

⊕ D[47:24] ➞D[47:24] (parallel move) EOR S,D (parallel move)

where

⊕ denotes the logical Exclusive OR operator

Description: Logically exclusive OR the source operand S with bits 47–24 of the destination operand D and store the result in bits 47–24 of the destination accumulator. This instruction is a 24-bit operation. The remaining bits of the destination operand D are not affected.

nc...

Example:

EOR Y1,B (R2)+ ;Exclusive OR Y1 with B1, update R2

Before Execution After Execution

$000003

$00:000005:000000 $00:000006:000000

$000003

Explanation of Example: Prior to execution, the 24-bit Y1 register contains the value $000003, and the 56-bit B accumulator contains the value $00:000005:000000. The

cale Semiconductor,

EOR Y1,B instruction logically exclusive ORs the 24-bit value in the Y1 register with bits 47–24 of the B accumulator (B1) and stores the result in the B accumulator with bits 55– 48 and 23–0 unchanged.

Frees

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

S1 S0 I1 I0

MR CCR

LEUNZVC

I — Set if data limiting has occurred during parallel move N — Set if bit 47 of A or B result is set Z— Set if bits 47 - 24 of A or B result are zero V — Always cleared

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EOR Logical Exclusive OR EOR

Instruction Format:

EOR S,D

Opcode:

23 8 7 4 3 0

DATA BUS MOVE FIELD

OPTIONAL EFFECTIVE ADDRESS EXTENSION

nc...

Instruction Fields:Instruction Fields:

S J J D d

01JJ

d011

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X0 0 0 A 0 X1 1 0 B 1 Y0 0 1 Y1 1 1

Timing: 2+mv oscillator clock cycles

Memory: 1+mv program words

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ILLEGAL Illegal Instruction Interrupt ILLEGAL

Operation: Assembler Syntax:

Begin Illegal Instruction ILLEGAL

exception processing

Description: The ILLEGAL instruction is executed as if it were a NOP instruction. Normal instruction execution is suspended and illegal instruction exception processing is initiated. The interrupt vector address is located at address P:$3E. The interrupt priority level (I1, I0) is set to 3 in the status register if a long interrupt service routine is used. The purpose of the ILLEGAL instruction is to force the DSP into an illegal instruction excep-

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tion for test purposes. If a fast interrupt is used with the ILLEGAL instruction, an infinite loop will be formed (an illegal instruction interrupt normally returns to the illegal instruction) which can only be broken by a hardware reset. Therefore, only long interrupts should be used. Exiting an illegal instruction is a fatal error. The long exception routine should indicate this condition and cause the system to be restarted.

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If the ILLEGAL instruction is in a DO loop at LA and the instruction at LA–1 is being interrupted, then LC will be decremented twice due to the same mechanism that causes LC to be decremented twice if JSR, REP, etc. are located at LA. This is why JSR, REP, etc. at LA are restricted. Clearly restrictions cannot be imposed on illegal instructions.

Since REP is uninterruptable, repeating an ILLEGAL instruction results in the interrupt not being initiated until after completion of the REP. After servicing the interrupt, program control will return to the address of the second word following the ILLEGAL instruction. Of course, the ILLEGAL interrupt service routine should abort further processing, and the processor should be reinitialized.

Example:

ILLEGAL ;begin ILLEGAL exception processing

Explanation of Example: The ILLEGAL instruction suspends normal instruction execution and initiates ILLEGAL exception processing.

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The condition codes are not affected by this instruction.

MOTOROLA DSP56000/DSP56001 USER’S MANUAL A - 75

S1 S0 I1 I0

MR CCR

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ILLEGAL Illegal Instruction Interrupt ILLEGAL

Instruction Format:

ILLEGAL

Opcode:

23 16 15 8 7 0

000000000000000010000101

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Instruction Fields:

None

Timing: 8 oscillator clock cycles Memory: 1 program word

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Jcc Jump Conditionally Jcc

Operation: Assembler Syntax:

If cc, then 0xxx ➞PC Jcc xxx

else PC+1 ➞PC

If cc, then ea ➞PC Jcc xxx

else PC+1 ➞PC

Description: Jump to the location in program memory given by the instruction’s effective address if the specified condition is true. If the specified condition is false, the program

nc...

counter (PC) is incremented and the effective address is ignored. However, the address register specified in the effective address field is always updated independently of the specified condition. All memory alterable addressing modes may be used for the effective address. A Fast Short Jump addressing mode may also be used. The 12-bit data is zero extended to form the effective address. See A.8 INSTRUCTION SEQUENCE RESTRICTIONS for restrictions. The term ‘‘cc’’ may specify the following conditions:

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‘‘cc’’ Mnemonic Condition

CC (HS) — carry clear (higher or same) C=0 CS (LO) — carry set (lower) C=1 EC — extension clear E=0 EQ — equal Z=1 ES — extension set E=1 GE — greater than or equal N GT — greater than Z+(N LC — limit clear L=0 LE — less than or equal Z+(N LS — limit set L=1 LT — less than N MI — minus N=1 NE — not equal Z=0 NR — normalized Z+(U PL — plus N=0 NN — not normalized Z+(U

where

denotes the logical complement of U,

+ denotes the logical OR operator,

• denotes the logical AND operator, and ⊕ denotes the logical Exclusive OR operator

⊕ V=0

⊕ V)=0 ⊕ V)=1

⊕ V=1

•E)=1

•E)=0

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Jcc Jump Conditionally Jcc

Restrictions: A Jcc instruction used within a DO loop cannot begin at the address LA

within that DO loop. A Jcc instruction cannot be repeated using the REP instruction.

Example:

JNN – (R4) ;jump to P:(R4) –1 if not normalized

Explanation of Example: In this example, program execution is transferred to the

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address P:(R4)–1 if the result is not normalized. Note that the contents of address register R4 are predecremented by 1, and the resulting address is then loaded into the program counter (PC) if the specified condition is true. If the specified condition is not true, no jump is taken, and the program counter is incremented by one.

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Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

S1 S0 I1 I0

MR CCR

LEUNZVC

The condition codes are not affected by this instruction.

Instruction Format:

Jcc xxx

Opcode:

23 16 15 8 7 0 00001110CCCCaaaaaaaaaaaa

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Jcc Jump Conditionally Jcc

Instruction Fields:

cc=4-bit condition code=CCCC, xxx=12-bit Short Jump Address=aaaaaaaaaaaa

Mnemonic C C C C Mnemonic C C C C

CC (HS) 0 0 0 0 CS (LO) 1 0 0 0 GE 0 001 LT 1001 NE 0 010 EQ 1010 PL 0011 MI 1011 NN 0 100 NR 1100 EC 0 101 ES 1101

nc...

LC 0 110 LS 1110 GT 0 111 LE 1111

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Timing: 4+jx oscillator clock cycles Memory: 1+ea program words Instruction Format:

Jcc ea

Opcode:

23 16 15 8 7 0

0000101011MMMRRR1010CCCC

OPTIONAL EFFECTIVE ADDRESS EXTENSION

Instruction Fields:

cc=4-bit condition code=CCCC, ea=6-bit Effective Address=MMMRRR

Effective

Addressing Mode M M M R R R

(Rn)-Nn 0 0 0 r r r (Rn)+Nn 0 0 1 r r r (Rn)- 0 1 0 r r r (Rn)+ 0 1 1 r r r (Rn) 1 0 0 r r r (Rn+Nn) 1 0 1 r r r

-(Rn) 1 1 1 r r r Absolute Address 1 1 0 0 0 0

where “rrr” refers to an address register R0-R7

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Jcc Jump Conditionally Jcc

Mnemonic C C C C Mnemonic C C C C

CC (HS) 0 0 0 0 CS (LO) 1 0 0 0 GE 0 001 LT 1001 NE 0 010 EQ 1010 PL 0011 MI 1011 NN 0 100 NR 1100 EC 0 101 ES 1101 LC 0 110 LS 1110

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GT 0 111 LE 1111 Timing: 4+jx oscillator clock cycles

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Memory: 1+ea program words

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JCLR Jump if Bit Clear JCLR

Operation: Assembler Syntax:

If S[n]=0, then xxxx➞PC JCLR #n,X:ea,xxxx

else PC+1➞PC

If S[n]=0, then xxxx ➞PC JCLR #n,X:aa,xxxx

else PC+1 ➞PC

If S[n]=0, then xxxx ➞PC JCLR #n,X:pp,xxxx

else PC+1 ➞PC

nc...

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If S[n]=0, then xxxx ➞PC JCLR #n,Y:ea,xxxx

else PC+1 ➞PC

If S[n]=0, then xxxx ➞PC JCLR #n,Y:aa,xxxx

else PC+1 ➞PC

If S[n]=0, then xxxx ➞PC JCLR #n,Y:pp,xxxx

else PC+1 ➞PC

If S[n]=0, then xxxx ➞PC JCLR #n,S,xxxx

else PC+1 ➞PC

Description: Jump to the 16-bit absolute address in program memory specified in the instruction’s 24-bit extension word if the n be tested is selected by an immediate bit number from 0–23. If the specified memory bit is not clear, the program counter (PC) is incremented and the absolute address in the extension word is ignored. However, the address register specified in the effective address field is always updated independently of the state of the n ister indirect addressing modes may be used to reference the source operand S. Absolute Short and I/O Short addressing modes may also be used.

bit of the source operand S is clear. The bit to

bit. All address reg-

Restrictions: A JCLR instruction cannot be repeated using the REP instruction. A JCLR located at LA, LA–1, or LA–2 of the DO loop cannot specify the program control-

ler registers SR, SP, SSH, SSL, LA, or LC as its target. JCLR SSH or JCLR SSL cannot follow an instruction that changes the SP.

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JCLR Jump if Bit Clear JCLR

Example:

JCLR #$5,X:<<$FFF1,$1234 ;go to P:$1234 if bit 5 in SCI SSR is clear

: Explanation of Example: In this example, program execution is transferred to the address P:$1234 if bit 5 (PE) of the 8-bit read-only X memory location X:$FFF1 (I/O SCI interface status register) is a zero. If the specified bit is not clear, no jump is taken, and the program counter (PC) is incremented by one.

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

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S1 S0 I1 I0

MR CCR

LEUNZVC

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The condition codes are not affected by this instruction.

Instruction Format:

JCLR #n,X:ea,xxxx JCLR #n,Y:ea,xxxx

Opcode:

23 16 15 8 7 0

0000101001MMMRRR1S0bbbbb

ABSOLUTE ADDRESS EXTENSION

Instruction Fields:

#n=bit number=bbbbb, ea=6-bit Effective Address=MMMRRR xxxx=16-bit Absolute Address in extension word

Effective

Addressing Mode M M M R R R Memory SpaceS Bit Number bbbbb

(Rn)-Nn 0 0 0 r r r X Memory 0 00000 (Rn)+Nn 0 0 1 r r r Y Memory 1

•

(Rn)- 0 1 0 r r r • (Rn)+ 0 1 1 r r r • (Rn) 1 0 0 r r r 10111 (Rn+Nn) 1 0 1 r r r

-(Rn) 1 1 1 r r r where “rrr” refers to an address register R0-R7

Timing: 6+jx oscillator clock cycles Memory: 2 program words

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JCLR Jump if Bit Clear JCLR

Instruction Format:

JCLR #n,X:aa,xxxx JCLR #n,Y:aa,xxxx

Opcode:

23 16 15 8 7 0

0000101000a aaaaa1S0bbbbb

ABSOLUTE ADDRESS EXTENSION

nc...

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Instruction Fields:

#n=bit number=bbbbb, aa=6-bit Absolute Short Address=aaaaaa xxxx=16-bit Absolute Address in extension word

Absolute Short Address aaaaaa Memory SpaceS Bit Number bbbbb

000000 X Memory 0 00000

• Y Memory 1 •

• 10111

111111

Timing: 6+jx oscillator clock cycles Memory: 2 program words

Instruction Format:

JCLR #n,X:pp,xxxx JCLR #n,Y:pp,xxxx

Opcode:

23 16 15 8 7 0

0000101010p ppppp1S0bbbbb

ABSOLUTE ADDRESS EXTENSION

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JCLR Jump if Bit Clear JCLR

Instruction Fields:

#n=bit number=bbbbb, pp=6-bit I/O Short Address=pppppp xxxx=16-bit Absolute Address in extension word

I/O Short Address pppppp Memory SpaceS Bit Number bbbbb

000000 X Memory 0 00000

• Y Memory 1 •

• 10111

111111

nc...

Timing: 6+jx oscillator clock cycles

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Memory: 2 program words

Instruction Format:

JCLR #n,S,xxxx

Opcode:

23 16 15 8 7 0

0000101011DDDDDD000bbbbb

ABSOLUTE ADDRESS EXTENSION

Instruction Fields:

#n=bit number=bbbbb, S=source register=DDDDDD xxxx=16-bit Absolute Address in extension word

Destination Register D D D D D D Bit Number bbbbb

•

See A.9 INSTRUCTION ENCODING and Table A-18 for specific register encodings.

Timing: 6+jx oscillator clock cycles Memory: 2 program words

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JMP Jump JMP

Operation: Assembler Syntax:

0xxx

➞ PC JMP xxx

ea ➞ PC JMP ea

Description: Jump to the location in program memory given by the instruction’s effective address. All memory alterable addressing modes may be used for the effective address. A Fast Short Jump addressing mode may also be used. The 12-bit data is zero extended to form the effective address.

Restrictions: A JMP instruction used within a DO loop cannot begin at the address LA

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within that DO loop.

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A JMP instruction cannot be repeated using the REP instruction.

Example:

JMP (R1+N1) ;jump to program address P:(R1+N1)

: Explanation of Example: In this example, program execution is transferred to the pro-

gram address P:(R1+N1).

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

The condition codes are not affected by this instruction.

S1 S0 I1 I0

MR CCR

LEUNZVC

MOTOROLA DSP56000/DSP56001 USER’S MANUAL A - 85

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JMP Jump JMP

Instruction Format:

JMP xxx

Opcode:

23 16 15 8 7 0

000011000000aaaaaaaaaaaa

Instruction Fields:

xxx=12-bit Short Jump Address=aaaaaaaaaaaa

Timing: 4+jx oscillator clock cycles

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Memory: 1+ea program words

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Instruction Format:

JMP ea

Opcode:

23 16 15 8 7 0 0000101 011MMMRRR1 0 000000

OPTIONAL EFFECTIVE ADDRESS EXTENSION

Instruction Fields:

ea=6-bit Effective Address=MMMRRR

Effective

Addressing Mode M M M R R R

(Rn)-Nn 0 0 0 r r r (Rn)+Nn 0 0 1 r r r (Rn)- 0 1 0 r r r (Rn)+ 0 1 1 r r r (Rn) 1 0 0 r r r (Rn+Nn) 1 0 1 r r r

-(Rn) 1 1 1 r r r Absolute address 1 1 0 0 0 0

where “rrr” refers to an address register R0-R7

Timing: 4+jx oscillator clock cycles Memory: 1+ea program words

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JScc Jump to Subroutine Conditionally JScc

Operation: Assembler Syntax:

If cc, then SP+1➞SP; PC➞SSH; SR➞SSL; 0xxx➞PC JScc xxx

else PC+1➞PC

If cc, then SP+1➞SP; PC➞SSH; SR➞SSL; ea➞PC JScc ea

else PC+1➞PC

Description: Jump to the subroutine whose location in program memory is given by the instruction’s effective address if the specified condition is true. If the specified condition is true, the address of the instruction immediately following the JScc instruction (PC) and the system status register (SR) are pushed onto the system stack. Program execution then continues at the specified effective address in program memory. If the specified condition is false, the program counter (PC) is incremented, and any extension word is ignored. However, the address register specified in the effective address field is always updated independently of the specified condition. All memory alterable addressing modes may be used for the effective address. A fast short jump addressing mode may also be used. The 12-bit data is zero extended to form the effective address. The term ‘‘cc’’ may specify the following conditions:

‘‘cc’’ Mnemonic Condition

⊕ V=0

⊕ V)=0 ⊕ V)=1

⊕ V=1

•E)=1

•E)=0

where U denotes the logical complement of U,

+ denotes the logical OR operator,

• denotes the logical AND operator, and ⊕ denotes the logical Exclusive OR operator

MOTOROLA DSP56000/DSP56001 USER’S MANUAL A - 87

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JScc Jump to Subroutine Conditionally JScc

Restrictions: A JScc instruction used within a DO loop cannot specify the loop address (LA) as its target.

A JScc instruction used within in a DO loop cannot begin at the address LA within that DO loop.

A JScc instruction cannot be repeated using the REP instruction.

Example:

JSLS (R3+N3) ;jump to subroutine at P:(R3+N3) if limit set (L=1)

: Explanation of Example: In this example, program execution is transferred to the sub-

routine at address P:(R3+N3) in program memory if the limit bit is set (L=1). Both the return address (PC) and the status register (SR) are pushed onto the system stack prior to transferring program control to the subroutine if the specified condition is true. If the specified condition is not true, no jump is taken and the program counter is incremented by 1.

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The condition codes are not affected by this instruction.

Instruction Format:

JScc xxx

Opcode:

23 16 15 8 7 0

00001111CCCCaaaaaaaaaaaa

S1 S0 I1 I0

MR CCR

LEUNZVC

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JScc Jump to Subroutine Conditionally JScc

Instruction Fields:

cc=4-bit condition code=CCCC, xxx=12-bit Short Jump Address=aaaaaaaaaaaa

Mnemonic C C C C Mnemonic C C C C

CC (HS) 0 0 0 0 CS (LO) 1 0 0 0 GE 0 001 LT 1001 NE 0 010 EQ 1010 PL 0011 MI 1011 NN 0 100 NR 1100 EC 0 101 ES 1101

nc...

LC 0 110 LS 1110 GT 0 111 LE 1111

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Timing: 4+jx oscillator clock cycles Memory: 1+ea program words Instruction Format:

JScc ea

Opcode:

23 16 15 8 7 0

0000101111MMMRRR1010CCCC

OPTIONAL EFFECTIVE ADDRESS EXTENSION

Instruction Fields:

cc=4-bit condition code=CCCC, ea=6-bit Effective Address=MMMRRR

Effective

Addressing Mode MMMRR R Mnemonic C C C C Mnemonic C C C C

(Rn)–Nn 000r r r CC (HS) 0 0 0 0 CS (LO) 1 0 0 0 (Rn)+Nn0 001rr r GE 0001 LT 100 1 (Rn)– 010r r r NE 0010 EQ 101 0 (Rn)+ 011r r r PL 0011 MI 101 1 (Rn) 100r r r NN 0100 NR 110 0 (Rn+Nn) 101r r r EC 0101 ES 110 1 –(Rn) 111r r r LC 0110 LS 1 11 0 Absolute address 110000 GT 0111 LE 1 11 1

where ‘‘rrr’’ refers to an address register R0–R7

Timing: 4+jx oscillator clock cycles Memory: 1+ea program words

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JSCLR Jump to Subroutine if Bit Clear JSCLR

Operation: Assembler Syntax

If S[n]=0, JSCLR #n,X:ea,xxxx then SP+1➞SP; PC➞SSH; SR➞SSL; xxxx ➞PC

else PC+1 ➞PC

I f S[n]=0, JSCLR #n,X:aa,xxxx

then SP+1➞SP; PC➞SSH; SR➞SSL; xxxx➞PC

else PC+1➞PC

nc...

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If S[n]=0, JSCLR #n,X:pp,xxxx then SP+1➞SP; PC➞SSH; SR➞SSL; xxxx➞PC

else PC+1➞PC

If S[n]=0, JSCLR #n,Y:ea,xxxx then SP+1➞SP; PC➞SSH; SR➞SSL; xxxx➞PC

else PC+1➞PC

If S[n]=0, JSCLR #n,Y:aa,xxxx then SP+1➞SP; PC➞SSH; SR➞SSL; xxxx➞PC

else PC+1➞PC

If S[n]=0, JSCLR #n,Y:pp,xxxx then SP+1➞SP; PC➞SSH; SR➞SSL; xxxx➞PC

else PC+1➞PC

If S[n]=0, JSCLR #n,S,xxxx then SP+1➞SP; PC➞SSH; SR➞SSL; xxxx➞PC

else PC+1➞PC

Description: Jump to the subroutine at the 16-bit absolute address in program memory specified in the instruction’s 24-bit extension word if the n clear. The bit to be tested is selected by an immediate bit number from 0–23. If the n of the source operand S is clear, the address of the instruction immediately following the JSCLR instruction (PC) and the system status register (SR) are pushed onto the system stack. Program execution then continues at the specified absolute address in the instruction’s 24-bit extension word. If the sepcified memory bit is not clear, the program counter (PC) is incremented and the extension word is ignored. However, the address register specified in the effective address field is always updated independently of the state of the

bit. All address register indirect addressing modes may be used to reference the

bit of the source operand S is

bit

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JSCLR Jump to Subroutine if Bit Clear JSCLR

source operand S. Absolute short and I/O short addressing modes may also be used.

Restrictions: A JSCLR instruction used within a DO loop cannot specify the loop address (LA) as its target.

A JSCLR located at LA, LA–1, or LA–2 of a DO loop, cannot specify the program controller registers SR, SP, SSH, SSL, LA, or LC as its target.

JSCLR SSH or JSCLR SSL cannot follow an instruction that changes the SP. A JSCLR instruction cannot be repeated using the REP instruction.

nc...

Example:

JSCLR #$1,Y:<<$FFE3,$1357 ;go sub. at P:$1357 if bit 1 in Y:$FFE3 is clear

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Explanation of Example: In this example, program execution is transferred to the subroutine at absolute address P:$1357 in program memory if bit 1 of the external I/O location Y:<<$FFE3 is a zero. If the specified bit is not clear, no jump is taken and the program counter (PC) is incremented by 1.

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

The condition codes are not affected by this instruction.

S1 S0 I1 I0

MR CCR

LEUNZVC

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JSCLR Jump to Subroutine if Bit Clear JSCLR

Instruction Format:

JSCLR #n,X:ea,xxxx JSCLR #n,Y:ea,xxxx

Opcode:

23 16 15 8 7 0

0000101101MMMRRR1S0bbbbb

ABSOLUTE ADDRESS EXTENSION

Instruction Fields:

nc...

#n=bit number=bbbbb, ea=6-bit Effective Address=MMMRRR, xxxx=16-bit Absolute Address in extension word

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Effective

Addressing Mode M M M R R R Memory SpaceS Bit Number bbbbb

(Rn)-Nn 0 0 0 r r r X Memory 0 00000 (Rn)+Nn 0 0 1 r r r Y Memory 1 (Rn)- 0 1 0 r r r • (Rn)+ 0 1 1 r r r • (Rn) 1 0 0 r r r 10111 (Rn+Nn) 1 0 1 r r r

-(Rn) 1 1 1 r r r where “rrr” refers to an address register R0-R7

Timing: 6+jx oscillator clock cycles Memory: 2 program words Instruction Format:

JSCLR #n,X:aa,xxxx JSCLR #n,Y:aa,xxxx

Opcode:

23 16 15 8 7 0

0000101100a aaaaa1S0bbbbb

•

ABSOLUTE ADDRESS EXTENSION

Instruction Fields:

#n=bit number=bbbbb, aa=6-bit Absolute Short Address=aaaaaa, xxxx=16-bit Absolute Address in extension word

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JSCLR Jump to Subroutine if Bit Clear JSCLR

Absolute Short Address aaaaaa Memory SpaceS Bit Number bbbbb

000000 X Memory 0 00000

• Y Memory 1 •

• 10111

111111

Timing: 6+jx oscillator clock cycles Memory: 2 program words Instruction Format:

nc...

JSCLR #n,X:pp,xxxx JSCLR #n,Y:pp,xxxx

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Opcode:

23 16 15 8 7 0

0000101110p ppppp1S0bbbbb

ABSOLUTE ADDRESS EXTENSION

Instruction Fields:

#n=bit number=bbbbb, pp=6-bit I/O Short Address=pppppp, xxxx=16-bit Absolute Address in extension word

I/O Short Address aaaaaa Memory SpaceS Bit Number bbbbb

000000 X Memory 0 00000

• Y Memory 1 •

• 10111

111111

Timing: 6+jx oscillator clock cycles Memory: 2 program words

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JSCLR Jump to Subroutine if Bit Clear JSCLR

Instruction Format:

JSCLR #n,S,xxxx

Opcode:

23 16 15 8 7 0

0000101111DDDDDD000bbbbb

ABSOLUTE ADDRESS EXTENSION

nc...

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Instruction Fields:

#n=bit number=bbbbb, S=source register=DDDDDD, xxxx=16-bit Absolute Address in extension word

Destination Register D D D D D D Bit Number bbbbb

See A.9 INSTRUCTION ENCODING and Table A-18 for specific register encodings.

Timing: 6+jx oscillator clock cycles Memory: 2 program words

•

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JSET Jump if Bit Set JSET

Operation: Assembler Syntax:

If S[n]=0, then xxxx➞PC JSET #n,X:ea,xxxx

else PC+1➞PC

If S[n]=1, then xxxx➞PC JSET #n,X:ea,xxxx

else PC+1➞PC

If S[n]=1, then xxxx➞PC JSET #n,X:aa,xxxx

else PC+1➞PC

If S[n]=1, then xxxx ➞PC JSET #n,X:pp,xxxx

nc...

else PC+1➞PC

cale Semiconductor,

Frees

If S[n]=1, then xxxx➞PC JSET #n,Y:ea,xxxx

else PC+1➞PC

If S[n]=1, then xxxx ➞PC JSET #n,Y:aa,xxxx

else PC+1➞PC

If S[n]=1, then xxxx➞PC JSET #n,Y:pp,xxxx

else PC+1➞PC

If S[n]=1, then xxxx➞PC JSET #n,S,xxxx

else PC+1➞PC

Description: Jump to the 16-bit absolute address in program memory specified in the instruction’s 24-bit extension word if the n be tested is selected by an immediate bit number from 0–23. If the specified memory bit is not set, the program counter (PC) is incremented, and the absolute address in the extension word is ignored. However, the address register specified in the effective address field is always updated independently of the state of the n ister indirect addressing modes may be used to reference the source operand S. Absolute short and I/O short addressing modes may also be used.

bit of the source operand S is set. The bit to

bit. All address reg-

Restrictions: A JSET instruction used within a DO loop cannot specify the loop address (LA) as its target.

A JSET located at LA, LA–1, or LA–2 of a DO loop cannot specify the program controller registers SR, SP, SSH, SSL, LA, or LC as its target.

JSET SSH or JSET SSL cannot follow an instruction that changes the SP. A JSET instruction cannot be repeated using the REP instruction.

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JSET Jump if Bit Set JSET

Example:

JSET #12,X:<<$FFF2,$4321 ;$4321➞(PC) if bit 12 (SCI COD) is set

: Explanation of Example: In this example, program execution is transferred to the

address P:$4321 if bit 12 (SCI COD) of the 16-bit read/write I/O register X:$FFF2 is a one. If the specified bit is not set, no jump is taken and the program counter (PC) is incremented by 1.

Condition Codes:

nc...

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

S1 S0 I1 I0

MR CCR

LEUNZVC

cale Semiconductor,

Frees

The condition codes are not affected by this instruction.

Instruction Format:

JSET #n,X:ea,xxxx JSET #n,Y:ea,xxxx

Opcode:

23 16 15 8 7 0

0000101001MMMRRR1S1bbbbb

ABSOLUTE ADDRESS EXTENSION

Instruction Fields:

#n=bit number=bbbbb, ea=6-bit Effective Address=MMMRRR xxxx=16-bit Absolute Address in extension word

Effective

Addressing Mode M M M R R R Memory SpaceS Bit Number bbbbb

(Rn)-Nn 0 0 0 r r r X Memory 0 00000 (Rn)+Nn 0 0 1 r r r Y Memory 1

•

(Rn)- 0 1 0 r r r • (Rn)+ 0 1 1 r r r • (Rn) 1 0 0 r r r 10111 (Rn+Nn) 1 0 1 r r r

-(Rn) 1 1 1 r r r where “rrr” refers to an address register R0-R7

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JSET Jump if Bit Set JSET

Timing: 6+jx oscillator clock cycles Memory: 2 program words Instruction Format:

JSET #n,X:aa,xxxx JSET #n,Y:aa,xxxx

Opcode:

23 16 15 8 7 0

0000101000a aaaaa1S1bbbbb

nc...

ABSOLUTE ADDRESS EXTENSION

cale Semiconductor,

Frees

Instruction Fields:

#n=bit number=bbbbb, aa=6-bit Absolute Short Address=aaaaaa, xxxx=16-bit Absolute Address in extension word

Absolute Short Address aaaaaa Memory SpaceS Bit Number bbbbb

000000 X Memory 0 00000

• Y Memory 1 •

• 10111

111111

Timing: 6+jx oscillator clock cycles Memory: 2 program words Instruction Format:

JSET #n,X:pp,xxxx JSET #n,Y:pp,xxxx

Opcode:

23 16 15 8 7 0

0000101010p ppppp1S1bbbbb

ABSOLUTE ADDRESS EXTENSION

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JSET Jump if Bit Set JSET

Instruction Fields:

#n=bit number=bbbbb, pp=6-bit I/O Short Address=pppppp, xxxx=16-bit Absolute Address in extension word

I/O Short Address pppppp Memory SpaceS Bit Number bbbbb

000000 X Memory 0 00000

• Y Memory 1 •

• 10111

nc...

Timing: 6+jx oscillator clock cycles

111111

cale Semiconductor,

Frees

Memory: 2 program words Instruction Format:

JSET #n,S,xxxx

Opcode:

23 16 15 8 7 0

0000101011DDDDDD001bbbbb

ABSOLUTE ADDRESS EXTENSION

Instruction Fields:

#n=bit number=bbbbb, S=source register=DDDDDD, xxxx=16-bit Absolute Address in extension word

Destination Register D D D D D D Bit Number bbbbb

•

See A.9 Instruction Encoding and Table A-18 for specific register encodings.

Timing: 6+jx oscillator clock cycles Memory: 2 program words

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JSR Jump to Subroutine JSR

Operation: Assembler Syntax:

SP+1➞SP; PC➞SSH; SR➞SSL; 0xxx➞PC JSR xxx

SP+➞SP; PC➞SSH; SR➞SSL; ea➞PC JSR ea

Description: Jump to the subroutine whose location in program memory is given by the instruction’s effective address. The address of the instruction immediately following the JSR instruction (PC) and the system status register (SR) is pushed onto the system stack. Program execution then continues at the specified effective address in program

nc...

memory. All memory alterable addressing modes may be used for the effective address. A fast short jump addressing mode may also be used. The 12-bit data is zero extended to form the effective address.

cale Semiconductor,

Frees

Restrictions: A JSR instruction used within a DO loop cannot specify the loop address (LA) as its target.

A JSR instruction used within a DO loop cannot begin at the address LA within that DO loop.

A JSR instruction cannot be repeated using the REP instruction.

Example:

JSR (R5)+ ;jump to subroutine at (R5), update R5

: Explanation of Example: In this example, program execution is transferred to the sub-

routine at address P:(R5) in program memory, and the contents of the R5 address register are then updated.

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

S1 S0 I1 I0

MR CCR

LEUNZVC

The condition codes are not affected by this instruction.

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JSR Jump to Subroutine JSR

Instruction Format:

JSR xxx

Opcode:

23 16 15 8 7 0 000011010000aaaaaaaaaaaa

Instruction Fields:

xxx=12-bit Short Jump Address=aaaaaaaaaaaa

nc...

cale Semiconductor,

Frees

Timing: 4+jx oscillator clock cycles Memory: 1+ea program words Instruction Format:

JSR ea

Opcode:

23 16 15 8 7 0

0000101111MMMRRR10000000

OPTIONAL EFFECTIVE ADDRESS EXTENSION

Instruction Fields:

ea=6-bit Effective Address=MMMRRR

Effective

Addressing Mode M M M R R R

(Rn)-Nn 0 0 0 r r r (Rn)+Nn 0 0 1 r r r (Rn)- 0 1 0 r r r (Rn)+ 0 1 1 r r r (Rn) 1 0 0 r r r (Rn+Nn) 1 0 1 r r r

-(Rn) 1 1 1 r r r Absolute address 1 1 0 0 0 0

where “rrr” refers to an address register R0-R7

Timing: 4+jx oscillator clock cycles Memory: 1+ea program words

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Motorola Freescale Semiconductor DSP56000, Freescale Semiconductor DSP56001 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

A.1 INSTRUCTION GUIDE

A.2 NOTATION

A.3 ADDRESSING MODES

A.3.1 Addressing Mode Modifiers

A.4 CONDITION CODE COMPUTATION

A.5 PARALLEL MOVE DESCRIPTIONS

A.6 INSTRUCTION DESCRIPTIONS

4. whether the operands are unsigned or signed;