Motorola Freescale Semiconductor DSP56000, Freescale Semiconductor DSP56001 User Manual

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This appendix contains detailed information about each instruction in the DSP56000/ DSP56001 instruction set. An instruction guide is presented first to help understand the individual instruction descriptions. This guide is followed by sections on notation and addressing modes. Since parallel moves are allowed with many of the instructions, they are discussed before the instructions. The instructions are then discussed in alphabetical order.

A.1 INSTRUCTION GUIDE

The following information is included in each instruction description with the goal of mak-

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ing each description self-contained:

1. Name and Mnemonic: The mnemonic is highlighted in bold type for easy reference.

APPENDIX A

INSTRUCTION SET DETAILS

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2. Assembler Syntax and Operation: For each instruction syntax, the corresponding operation is symbolically described. If there are several operations indicated on a single line in the operation field, those operations do not necessarily occur in the order shown but are generally assumed to occur in parallel. If a parallel data move is allowed, it will be indicated in parenthesis in both the assembler syntax and operation fields. If a letter in the mnemonic is optional, it will be shown in parenthesis in the assembler syntax field.

3. Description: A complete text description of the instruction is given together with any special cases and/or condition code anomalies of which the user should be aware when using that instruction.

4. Example: An example of the use of the instruction is given. The example is shown in DSP56000/DSP56001 assembler source code format. Most arithmetic and logical instruction examples include one or two parallel data moves to illustrate the many types of parallel moves that are possible. The example includes a complete explanation, which discusses the contents of the registers referenced by the instruction (but not those referenced by the parallel moves) both before and after the execution of the instruction. Most examples are designed to be easily understood without the use of a calculator.

5. Condition Codes: The status register is depicted with the condition code bits which can be affected by the instruction highlighted in bold type. Not all bits in the status register are used. Those which are reserved are indicated with a double asterisk and are read as zeros.

6. Instruction Format: The instruction fields, the instruction opcode, and the instruction extension word are specified for each instruction syntax. When the extension

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word is optional, it is so indicated. The values which can be assumed by each of the variables in the various instruction fields are shown under the instruction field’s heading. Note that the symbols used in decoding the various opcode fields of an instruction are completely arbitrary . Furthermore, the opcode symbols used in one instruction are completely independent of the opcode symbols used in a different instruction.

7. Timing: The number of oscillator clock cycles required for each instruction syntax is given. This information provides the user a basis for comparison of the execution times of the various instructions in oscillator clock cycles. Refer to Table A-1 and A.7 INSTRUCTION TIMING for a complete explanation of instruction timing, including the meaning of the symbols ‘‘aio’’, ‘‘ap’’, ‘‘ax’’, ‘‘ay’’, ‘‘axy’’, ‘‘ea’’, ‘‘jx’’, ‘‘mv’’, ‘‘mvb’’, ‘‘mvc’’, ‘‘mvm’’, ‘‘mvp’’, ‘‘rx’’, ‘‘wio’’, ‘‘wp’’, ‘‘wx’’, and ‘‘wy’’.

8. Memory: The number of program memory words required for each instruction syntax is given. This information provides the user a basis for comparison of the number of program memory locations required for each of the various instructions in 24-

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bit program memory words. Refer to Table A-1 and A.7 INSTRUCTION TIMING for a complete explanation of instruction memory requirements, including the meaning of the symbols ‘‘ea’’ and ‘‘mv’’.

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A.2 NOTATION

Each instruction description contains symbols used to abbreviate certain operands and operations. Table A-1 lists the symbols used and their respective meanings. Depending on the context, registers refer to either the register itself or the contents of the register.

A.3 ADDRESSING MODES

The addressing modes are grouped into three categories: register direct, address register indirect, and special. These addressing modes are summarized in Table A-2. All address calculations are performed in the address ALU to minimize execution time and loop overhead. Addressing modes, which specify whether the operands are in registers, in memory, or in the instruction itself (such as immediate data), provide the specific address of the operands.

The register direct addressing mode can be subclassified according to the specific register addressed. The data registers include X1, X0, Y1, Y0, X, Y, A2, A1, A0, B2, B1, B0, A, and B. The control registers include SR, OMR, SP, SSH, SSL, LA, LC, CCR, and MR.

Address register indirect modes use an address register Rn (R0–R7) to point to locations in X, Y, and P memory. The contents of the Rn address register (Rn) is the effective address (ea) of the specified operand, except in the ‘‘indexed by offset’’ mode where the effective address (ea) is (Rn+Nn). Address register indirect modes use an address modifier register Mn to specify the type of arithmetic to be used to update the address register Rn. If an addressing mode specifies an address offset register Nn, the given address offset register is used to update the corresponding address register Rn. The Rn address register may only use the corresponding address offset register Nn and the corresponding address modifier register Mn. For example, the address register R0 may only use the

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Table A-1 Instruction Description Notation

Data ALU Registers Operands

Xn Input Register X1 or X0 (24 Bits) Yn Input Register Y1 or Y0 (24 Bits) An Accumulator Registers A2, A1, A0 (A2 — 8 Bits, A1 and A0 — 24 Bits) Bn Accumulator Registers B2, B1, B0 (B2 — 8 Bits, B1 and B0 — 24 Bits) X Input Register X = X1: X0 (48 Bits) Y Input Register Y = Y1: Y0 (48 Bits) A Accumulator A = A2: A1: A0 (56 Bits)*

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B Accumulator B = B2: B1: B0 (56 BIts)* AB Accumulators A and B = A1: B1 (48 Bits)* BA Accumulators B and A = B1: A1 (48 Bits)* A10 Accumulator A = A1: A0 (48 Bits) B10 Accumulator B= B1:B0 (48 bits) * NOTE: In data move operations , shifting and limiting are perf ormed when this register is speciﬁed

as a source operand. When speciﬁed as a destination operand, sign extension and possib ly zeroing are performed.

Address ALU Registers Operands

Rn Address Registers R0 - R7 (16 Bits) Nn Address Offset Registers N0 - N7 (16 Bits) Mn Address Modiﬁer Registers M0 - M7 (16 Bits)

N0 address offset register and the M0 address modifier register during actual address computation and address register update operations. This unique implementation is extremely powerful and allows the user to easily address a wide variety of DSP-oriented data structures. All address register indirect modes use at least one set of address registers (Rn, Nn, and Mn), and the XY memory reference uses two sets of address registers, one for the X memory space and one for the Y memory space.

The special addressing modes include immediate and absolute addressing modes as well as implied references to the program counter (PC), the system stack (SSH or SSL), and program (P) memory.

Addressing modes may also be categorized by the ways in which they may be used.

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Table A-1 Instruction Description Notation (Continued)

Program Controller Registers Operands

PC Progr am Counter Register (16 Bits) MR Mode Register (8 Bits) CCR Condition Code Register (8 Bits) SR Status Register = MR:CCR (16 Bits) OMR Operating Mode Register (8 Bits) LA Hardware Loop Address Register (16 Bits) LC Hardware Loop Counter Register (16 Bits) SP System Stack P ointer Register (6 Bits)

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SSH Upper Portion of the Current Top of the Stack (16 Bits)

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SSL Lower P ortion of the Current Top of the Stack (16 Bits) SS System Stack RAM = SSH: SSL (15 Locations b y 32 Bits)

Address Operands

ea Effective Address eax Effective Address for X Bus eay Effective Address for Y Bus xxxx Absolute Address (16 Bits) xxx Short Jump Address (12 Bits) aa Absolute Short Address (6 Bits, Zero Extended) pp I/O Short Address (6 Bits, Ones Extended) <. . .> Speciﬁies the Contents of the Speciﬁed Address X: X Memory Reference Y: Y Memory Reference L: Long Memory Reference = X:Y P: Program Memory Reference

Table A-3 shows the various categories to which each addressing mode belongs. The following classifications will be used in the instruction descriptions.

Table A-3. DSP56000/DSP56001 Addressing Mode Encoding These addressing mode categories may be combined so that additional, more restrictive

classifications may be defined. For example, the instruction descriptions may use a

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Table A-1 Instruction Description Notation (Continued)

Miscellaneous Operands

S, Sn Source Operand Register D , Dn Destination Operand Register D [n] Bit n of D Destination Operand Register #n Immediate Short Data (5 Bits) #xx Immediate Short Data (8 Bits) #xxx Immediate Short Data (12 Bits) #xxxxxx Immediate Data (24 Bits)

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Unary Operators

- Negation Operator — Logical NOT Operator PUSH Push Speciﬁed Value onto the System Stack (SS) Operator PULL Pull Speciﬁed Value from the System Stack (SS) Operator READ Read the Top of the System Stack (SS) Operator PURGE Delete the Top Value on the System Stac k (SS) Oper ator | | Absolute Value Operator

Binary Operators

+ Addition Operator

- Subtraction Operator * Multiplication Oper ator ÷, / Division Operator + Logical Inclusive OR Operator

• Logical AND Operator ⊕ Logical Exclusive OR Operator ➨ “Is T ransferred To” Operator : Concatenation Operator

memory alterable classification, which refers to addressing modes that are both mem-

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Table A-1 Instruction Description Notation (Continued)

Addressing Mode Operators

<< I/O Short Addressing Mode Force Operator < Short Addressing Mode Force Operator > Long Addressing Mode Force Operator # Immediate Addressing Mode Operator #> Immediate Long Addressing Mode Force Oper ator #< Immediate Short Addressing Mode Force Operator

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Mode Register (MR) Symbols

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LF Loop Flag Bit Indicating When a DO Loop is in Progress T Trace Mode Bit Indicating if the Tracing Function has been Enabled S1, S0 Scaling Mode Bits Indicating the Current Scaling Mode I1, I0 Interrupt Mask Bits Indicating the Current Interrupt Priority Level

Condition Code Register (CCR) Symbols

Standard Definitions (Table A - 3 Describes Exceptions)

L Limit Bit Indicating Arithmetic Ov erﬂo w and/or Data Shifting/Limiting E Extension Bit Indicating if the Integer Portion of A or B is in Use U Unnormalized Bit Indicating if the A or B Result is Unnormalized N Negativ e Bit Indicating if Bit 55 of the A or B Result is Set Z Zero Bit Indicating if the A or B Result Equals Zero V Overﬂow Bit Indicating if Arithmetic Overﬂo w has Occurred in A or B C Carry Bit Indicating if a Carry or Borrow Occurred in A or B Result

ory addressing modes and alterable addressing modes. Thus, memory alterable addressing modes use address register indirect and absolute addressing modes.

The address register indirect addressing modes require that the offset register number be the same as the address register number. However, future family members may allow the offset register number to be different from the address register number. The assembler syntax ‘‘Nn’’ supports the future feature. The assembler syntax ‘‘N’’ may be used

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Table A-1 Instruction Description Notation (Continued)

Instruction Timing Symbols

aio Time Required to Access an I/O Operand ap Time Required to Access a P Memory Operand ax Time Required to Access an X Memory Operand ay Time Required to Access a Y Memory Operand axy Time Required to Access XY Memory Operands ea Time or Number of W ords Required for an Effective Address jx Time Required to Execute Part of a Jump-Type Instruction mv Time or Number of W ords Required f or a Mo ve-Type Operation

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mvb Time Required to Execute P art of a Bit Manipulation Instruction

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mvc Time Required to Execute Part of a MOVEC Instruction mvm Time Required to Execute P art of a MO VEM Instruction mvp Time Required to Execute P art of a MO VEP Instruction rx Time Required to Execute P art of an TR TI or RTS Instruction wio Number of W ait States Used in Accessing External I/O wp Number of Wait States Used in Accessing External P Memory wx Number of W ait States Used in Accessing External X Memory wy Number of W ait States Used in Accessing External Y Memory

Other Symbols

( ) Optional Letter, Operand, or Operation

(. . . . .) An y Arithmetic or Logical Instruction Which Allo ws Parallel Moves

EXT Extension Register Portion of an Accumulator (A2 or B2) LS Least Signiﬁcant LSP Least Signiﬁcant Portion of an Accumulator (A0 or B0) MS Most Signiﬁcant MSP Most Signiﬁcant Portion of a n Accumulator (A1 or B1) r Rounding constant S/L Shifting and/or Limiting on a Data ALU Register Sign Ext Sign Externsion of a Data ALU Register Zero Zeroing of a Data ALU Register

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Table A-2 DSP 56000/56001 Addressing Modes

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Addressing Mode

Data or Control Register No X X X Address Register Rn No X Address Modiﬁer Register

Mn Address Offset Register Nn No X

No Update Yes XXXXX Postincrement b y 1 Yes XXXXX Postdecrement b y 1 Yes XXXXX Postincrement b y Offset Nn Yes XXXXX Postdecrement b y Offset Nn Yes XXXX Indexed b y Offset Nn Yes XXXX Predecrement by 1 Yes XXXX

Immediate Data No X Absolute Address No XXXX Immediate Short Data No X Short Jump Address No X Absolute Short Address No XXXX I/O Short Address No X X Implicit No X X X

Uses Mn

Modiﬁer

No X

Address Register Indirect

SCDAPXYLXY

Special

Operand Reference

NOTE:S = System Stack Reference X = X Memory Reference

C = Program Controller Register Reference Y = Y Memory Reference D = Data ALU Register Reference L = L Memory Reference A = Address ALU Register Reference XY = XY Memory Reference P = Program Memory Reference

instead of ‘‘Nn’’ in the address register indirect memory addressing modes. If ‘‘N’’ is specified, the offset register number is the same as the address register number.

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Table A-3 DSP56000/56001 Addressing Mode Encoding

Addressing Mode

Data or Control Register — — X (SeeTable A-1) Address Register — — X Rn Address Offset Register — — X Nn Address Modiﬁer Register — — X Mn

No Update 100 Rn X X X (Rn)

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Postincrement b y 1 011 Rn XXXX (Rn) + Postdecrement b y 1 010 Rn XXXX (Rn) Postincrement b y Offset Nn 001 Rn XXXX (Rn) + Nn Postdecrement b y Offset Nn 000 Rn X X X (RN) - Nn Indexed b y Offset Nn 101 Rn X X (Rn + Nn) Predecrement by 1 111 Rn X X - (Rn)

Immediate Data 110 100 X #xxxxxx Absolute Address 110 000 X X xxxx Immediate Short Data — — #xx Short Jump Address — — X xxx Absolute Short Address — — X aa I/O Short Address — — X pp

Mode

MMM

Address Register Indirect

Reg

RRR

Special

Addressing Categories

UPMA

Assembler

Syntax

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Implicit — — X

Update Mode (U) The update addressing mode is used to modify address registers without any

associated data move.

Parallel Mode (P) The parallel addressing mode is used in instructions where two effective

addresses are required.

Memory Mode (M) The memory addressing mode is used to refer to operands in memory using an

effective addressing ﬁeld.

Alterable Mode (A) The alterable addressing mode is used to refer to alter able or writable registers or

memory .

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A.3.1 Addressing Mode Modifiers

The addressing mode selected in the instruction word is further specified by the contents of the address modifier register Mn. The addressing mode update modifiers (M0–M7) are shown in Table A-4. There are no restrictions on the use of modifier types with any address register indirect addressing mode.

Table A-4 Addressing Mode Modifier Summary

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16-Bit Modiﬁer Reg. (M0 - M7)

MMMMMMMMMMMMMMMM*

0000000000000000 Reverse Carry (Bit Reversed) 0000000000000001 Modulo 2 0000000000000010 Modulo 3

•••

••• 0111111111111110 Modulo 32767 0111111111111111 Modulo 32768 1000000000000000 Undeﬁned

••• 1111111111111110 Undeﬁned 1111111111111111 Linear (Modulo 65536)

*MMMMMMMMMMMMMMMM = 16-Bit Modiﬁer Reg. Contents

A.4 CONDITION CODE COMPUTATION

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

** T ** S1 S0 I1 I0 ** LEUNZVC

MR CCR

Address Calculation Arithmetic

The condition code register (CCR) portion of the status register (SR) consists of seven defined bits:

L — Limit Bit Z — Zero Bit E — Extension Bit V — Overflow Bit U — Unnormalized Bit C — Carry Bit N — Negative Bit

The E, U, N, Z, V, and C bits are true condition code bits that reflect the condition of the result of a data ALU operation . These condition code bits are not latched and are not affected by address ALU calculations or by data transfers over the X, Y, or global data buses. The L bit is a latching overflow bit which indicates that an overflow has occurred in the data ALU or that data limiting has occurred when moving the contents of the Aand/or[lz B accumulators.

The standard definition of the condition code bits is as follows. Exceptions to these standard definitions are given in Table A-5.

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L (Limit Bit) Set if the overflow bit V is set or if the data shifter/limiters perform a limiting operation. Not affected otherwise. This bit is latched and must be reset by the user.

⊕

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E (Extension Bit) Cleared if all the bits of the signed integer portion of the A or B result are the same =m i.e., the bit patterns are either 00 . . . 00 or 11 . . . 11. Set otherwise. The signed integer portion is defined

by the scaling mode as shown in the following table:

S1 S0 Scaling Mode Signed Integer Portion

0 0 No Scaling Bits 55, 54, . . . . 48, 47

0 1 Scale Down Bits 55, 54, . . . . 49, 48

1 0 Scale Up Bits 55, 54, . . . . 47, 46

Note that the signed integer portion of an accumulator IS NOT necessarily the same as the extension register portion of that accumulator. The signed integer portion of an accumulator consists of the MS 8, 9, or 10 bits of that accumulator, depending on the scaling mode being used. The extension register portion of an accumulator (A2 or B2) is always the MS 8 bits of that accumulator. The E bit refers to the signed integer portion of an accumulator and NOT the extension register portion of that accumulator. For example, if the current scaling mode is set for no scaling (i.e., S1=S0=0), the signed integer portion of the A or B accumulator consists of bits 47 through 55 . If the A accumulator contained the signed 56-bit value $00:800000:000000 as a result of a data ALU oper-

ation , the E bit would be set (E=1) since the 9 MS bits of that accumulator were not all the same (i.e., neither 00 . . 00 nor 11 . . 11). This means that data limiting will occur if that 56-bit value is specified as a source operand in a move-type operation. This limiting

operation will result in either a positive or negative, 24-bit or 48-bit saturation constant being stored in the specified destination. The only situation in which the signed integer portion of an accumulator and the extension register portion of an accumulator are the same is in the ‘‘Scale Down’’ scaling mode (i.e., S1=0 and S0=1).

U (Unnormalized Bit) Set if the two MS bits of the MSP portion of the A or B result are the same. Cleared otherwise. The MSP portion is defined by the scaling mode. The U bit is computed as follows:

S1 S0 Scaling Mode U Bit Computation

0 0 No Scaling U=(Bit 47 ⊕ Bit 46) 0 1 Scale Down U=(Bit 48 ⊕ Bit 47 1 0 Scale Up U=(Bit 46

N (Negative Bit) Set if the MS bit 55 of the A or B result is set. Cleared otherwise.

Z (Zero Bit) Set if the A or B result equals zero. Cleared otherwise.

V (Overflow Bit) Set if an arithmetic overflow occurs in the 56-bit A or B result. This indicates that the result cannot be represented in the 56-bit accumulator; thus, the accumulator has overflowed. Cleared other-

C (Carry Bit) Set if a carry is generated out of the MS bit of the A or B result of an addition or if a borrow is generated out of the MS bit of the A or B result of a subtraction. The carry or borrow is generated out

Table A-5 details how each instruction affects the condition codes. The convention for the notation that is used is shown at the bottom of Table A-5.

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of bit 55 of the A or B result. Cleared otherwise.

Bit 45

) )

A.5 PARALLEL MOVE DESCRIPTIONS

Many of the instructions in the DSP56000/DSP56001 instruction set allow optional parallel data bus movement. A.6 INSTRUCTION DESCRIPTIONS indicates the parallel move option in the instruction syntax with the statement ‘‘(parallel move)’’. The MOVE instruction is equivalent to a NOP with parallel moves. Therefore, a detailed description of each parallel move is given with the MOVE instruction details in A.6 INSTRUCTION DESCRIPTIONS.

A.6 INSTRUCTION DESCRIPTIONS

The following section describes each instruction in the DSP56000/DSP56001 instruction set in complete detail. The format of each instruction description is given in A.1 INSTRUCTION GUIDE. Instructions which allow parallel moves include the notation ‘‘(parallel move)’’ in both the Assembler Syntax and the Operation fields. The example given with each instruction discusses the contents of all the registers and memory locations referenced by the opcode-operand portion of that instruction but not those referenced by the parallel move portion of that instruction. Refer to A.5 PARALLEL MOVE DESCRIPTIONS for a complete discussion of parallel moves, including examples which discuss the contents of all the registers and memory locations referenced by the parallel move portion of an instruction.

Whenever an instruction uses an accumulator as both a destination operand for a data ALU operation and as a source for a parallel move operation, the parallel move operation will use the value in the accumulator prior to execution of any data ALU operation.

Whenever a bit in the condition code register is defined according to the standard definition given in A.4 CONDITION CODE COMPUTATION, a brief definition will be given in normal text in the Condition Code section of that instruction description. Whenever a bit in the condition code register is defined according to a cerning its use.

special definition for some particular instruction, the complete special definition of that bit will be given in the Condition Code section of that instruction in bold text to alert the user to any special conditions con-

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Table A-5 Condition Code Computations

Mnemonic L E U N Z V C Notes Mnemonic L E U N Z V C Notes

ABS ******—MAC******— ADC ******* MACR ******— ADD ******* MOVE * —————— ADDL *****?* 1 MOVEC ??????? 13 ADDR ******* MOVEM ??????? 13 AND * ——??0— 8, 9 MOVEP ??????? 13 ANDI ??????? 2 MPY ******— ASL *****? ? 1, 3 MPYR ******— ASR *****0 ? 4 NEG ******— BCHG ? —————? 5, 14 NOP ——————— BCLR ? —————? 5, 14 NORM *****?— 1 BSET ? —————? 5, 14 NOT * — — ? ? 0 — 8, 9 BTST ? —————? 5, 14 OR * — — ? ? 0 — 8, 9 CLR *****0— ORI ??????? 6 CMP ******* REP * —————— CMPM ******* RESET ——————— DIV * ————? ? 1, 7 RND ******— DO * —————— ROL * — — ? ? 0 ? 8, 9, 10 ENDDO ——————— ROR * — — ? ? 0 ? 8, 9, 11 EOR * ——??0— 8, 9 RTI ??????? 12 Jcc ——————— RTS * —————— JCLR ——————— SBC ******* JMP ——————— STOP ——————— JScc ——————— SUB ******* JSCLR ——————— SUBL *****?* 1 JSET ——————— SUBR ******* JSR ——————— SWI ——————— JSSET ——————— Tcc ——————— LSL * ——??0?8, 9, 10TFR *—————— LSR * ——??0?8, 9, 11TST *****0— LUA ——————— WAIT ——————— where: * Set according to the standard deﬁnition of the operation

NOTES:

— Not affected by the operation ? Set according to a special deﬁnition and can be a 0 or 1 0 The V bit is cleared

1 V Set if an arithmetic overﬂow occurs in the 56-bit result. Also set if the MS bit of the destination oper and is changed as a result of

the left shift. Cleared otherwise. 2 ? Cleared if the corresponding bit in the immediate data is cleared when the operand is the CCR. Not affected otherwise. 3 C Set if bit 55 of the source operand is set. Cleared otherwise. 4 C Set if bit 0 of the source operand is set. Cleared otherwise. 5 C Set if bit #n of the source operand is set. Cleared otherwise. 6 ? Set if the corresponding bit in the immediate data is set when the operand is the CCR. Not affected otherwise. 7 C Set if bit 55 of the result is cleared. Cleared otherwise. 8 N Set if bit 47 of the result is set. Cleared otherwise. 9 Z Set if bits 47 - 24 of the result are zero. Cleared otherwise. 10 C Set if bit 47 of the source operand is set. Cleared otherwise . 11 C Set if bit 24 of the source operand is set. Cleared otherwise . 12 ? Set according to the value pulled from the stack. 13 ? If the status register (SR) is speciﬁed as a destination operand, set according to the corresponding bit of the source operand. If

SR is not speciﬁed as a destination operand, the L bit is set if data limiting occurred. All ? bits are not aff ected otherwise . 14 ? Set if limiting occurs, not affected otherwise.

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The definition and thus the computation of both the E (extension) and U (unnormalized) bits of the condition code register (CCR) varies according to the scaling mode being used. Refer to A.4 CONDITION CODE COMPUTATION for complete details.

The signed integer portion of an accumulator is NOT necessarily the same as either the A2 or B2 extension register portion of that accumulator. The signed integer portion of an accumulator is defined according to the scaling mode being used and can consist of the MS 8, 9, or 10 bits of an accumulator. Refer to A.4 CONDITION CODE COMPUTATION for complete details.

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ABS Absolute Value ABS

Operation: Assembler Syntax:

| D | ➞ D (parallel move) ABS D (parallel move)

Description: Take the absolute value of the destination operand D and store the result in the destination accumulator.

Example:

ABS A #$123456,X0 A,Y0 ;take abs. value, set up X0, save value

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Before Execution After Execution

A A

$FF:FFFFFF:FFFFF2 $00:000000:00000E

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Explanation of Example: Prior to execution, the 56-bit A accumulator contains the value $FF:FFFFFF:FFFFF2. Since this is a negative number, the execution of the ABS instruction takes the twos complement of that value and returns $00:000000:00000E.

Note: For the case in which the D operand equals $80:000000:000000 (-256.0), the ABS instruction will cause an overflow to occur since the result cannot be correctly expressed using the standard 56-bit, fixed-point, twos-complement data representation. Data limiting does not occur (i.e., A is not set to the limiting value of $7F:FFFFFF:FFFFFF).

Condition Codes

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

S1 S0 I1 I0

MR CCR

LEUNZVC

L — Set if limiting (parallel move) or overflow has occurred in result E — Set if the signed integer portion of A or B result is in use U — Set if A or B result is unnormalized N — Set if bit 55 of A or B result is set Z— Set if A or B result equals zero V — Set if overflow has occurred in A or B result

Note: The definition of the E and U bits varies according to the scaling mode being used. Refer to A.4 CONDITION CODE COMPUTATION for complete details.

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ABS Absolute Value ABS

Instruction Format:

ABS D

Opcode:

23 8 7 4 3 0

DATA BUS MOVE FIELD

OPTIONAL EFFECTIVE ADDRESS EXTENSION

0010

d110

nc...

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Instruction Fields:

D d

A 0 B 1

Timing: 2+mv oscillator clock cycles

Memory: 1+mv program words

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ADC Add Long with Carry ADC

Operation: Assembler Syntax:

S+C+D ➞ D (parallel move) ADC S,D (parallel move)

Description: Add the source operand S and the carry bit C of the condition code register to the destination operand D and store the result in the destination accumulator. Long words (48 bits) may be added to the (56-bit) destination accumulator.

Note: The carry bit is set correctly for multiple precision arithmetic using long-word operands if the extension register of the destination accumulator (A2 or B2) is the sign extension of bit 47 of the destination accumulator (A or B).

nc...

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Frees

Example:

: MOVE L:<$0,X ;get a 48-bit LS long-word operand in X MOVE L:<$1,A ;get other LS long word in A (sign ext.) MOVE L:<$2,Y ;get a 48-bit MS long-word operand in Y ADD X,A L:<$3,B ;add LS words; get other MS word in B ADC Y,B A10,L:<$4 ;add MS words with carry, save LS sum MOVE B10,L:<$5 ;save MS sum

Before Execution After Execution

A A

X X

B B

Y Y

$FF:800000:000000 $FF:000000:000000

$800000:000000 $800000:000000

$00:000000:000001 $00:000000:000003

$000000:000001 $000000:000001

Explanation of Example: This example illustrates long-word double-precision (96-bit) addition using the ADC instruction. Prior to execution of the ADD and ADC instructions, the double-precision 96-bit value $000000:000001:800000:000000 is loaded into the Y and X registers (Y:X), respectively. The other double-precision 96-bit value $000000:000001:800000:000000 is loaded into the B and A accumulators (B:A), respectively. Since the 48-bit value loaded into the A accumulator is automatically sign extended to 56 bits and the other 48-bit long-word operand is internally sign extended to 56 bits during instruction execution, the carry bit will be set correctly after the execution of the ADD X,A instruction. The ADC Y,B instruction then produces the correct MS 56-bit result. The actual 96-bit result is stored in memory using the A10 and B10 operands (instead of A and B) because shifting and limiting is not desired.

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ADC Add Long with Carry ADC

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

nc...

V — Set if overflow has occurred in A or B result C — Set if a carry (or borrow) occurs from bit 55 of A or B result.

S1 S0 I1 I0

MR CCR

LEUNZVC

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Frees

Note: The definition of the E and U bits varies according to the scaling mode being used. Refer to A.4 CONDITION CODE COMPUTATION for complete details.

Instruction Format:

ADC S,D

Opcode:

23 8 7 4 3 0

DATA BUS MOVE FIELD

OPTIONAL EFFECTIVE ADDRESS EXTENSION

001J

d001

Instruction Fields:

S,D J d

X,A 0 0 X,B 0 1 Y,A 1 0 Y,B 1 1

Timing: 2+mv oscillator clock cycles Memory: 1+mv program words

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ADD Add ADD

Operation: Assembler Syntax:

S+D➞D (parallel move ADD S,D (parallel move)

Description: Add the source operand S to the destination operand D and store the result in the destination accumulator. Words (24 bits), long words (48 bits), and accumulators (56 bits) may be added to the destination accumulator.

Note: The carry bit is set correctly using word or long-word source operands if the extension register of the destination accumulator (A2 or B2) is the sign extension of bit 47

nc...

of the destination accumulator (A or B). Thus, the carry bit is always set correctly using accumulator source operands, but can be set incorrectly if A1, B1, A10, or B10 are used as source operands and A2 and B2 are not replicas of bit 47.

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Frees

Example:

ADD X0,A A,X1 A,Y:(R1)+l ;24-bit add, set up X1, save prev. result

Before Execution After Execution

X0 X0

A A

$00:000100:000000 $00:0000FF:000000

$FFFFFF

Explanation of Example: Prior to execution, the 24-bit X0 register contains the value $FFFFFF and the 56-bit A accumulator contains the value $00:000100:000000. The ADD instruction automatically appends the 24-bit value in the X0 register with 24 LS zeros, sign extends the resulting 48-bit long word to 56 bits, and adds the result to the 56-bit A accumulator. Thus, 24-bit operands are added to the MSP portion of A or B (A1 or B1) because all arithmetic instructions assume a fractional, twos complement data representation. Note that 24-bit operands can be added to the LSP portion of A or B (A0 or B0) by loading the 24-bit operand into X0 or Y0, forming a 48-bit word by loading X1 or Y1 with the sign extension of X0 or Y0 and executing an ADD X,A or ADD Y,A instruction.

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

A - 18 DSP56000/DSP56001 USER’S MANUAL MOTOROLA

S1 S0 I1 I0

MR CCR

LEUNZVC

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ADD Add ADD

L — Set if limiting (parallel move) or overflow has occurred in result E — Set if the signed integer portion of A or B result is in use U — Set if A or B result is unnormalized N — Set if bit 55 of A or B result is set Z — Set if A or B result equals zero V — Set if overflow has occurred in A or B result C — Set if a carry (or borrow) occurs from bit 55 of A or B result.

Note: The definition of the E and U bits varies according to the scaling mode being

nc...

used. Refer to A.4 CONDITION CODE COMPUTATION for complete details.

Instruction Format:

ADD S,D

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Opcode:

23 8 7 4 3 0

DATA BUS MOVE FIELD

OPTIONAL EFFECTIVE ADDRESS EXTENSION

Instruction Fields:

S,D J J J d S,D J J J d S,D J J J d

B,A 0 0 1 0 X0,A 1 0 0 0 Y1,A 1 1 1 0 A,B 0 0 1 1 X0,B 1 0 0 1 Y1,B 1 1 1 1 X,A 0 1 0 0 Y0,A 1 0 1 0 X,B 0 1 0 1 Y0,B 1 0 1 1 Y,A 0 1 1 0 X1,A 1 1 0 0 Y,B 0 1 1 1 X1,B 1 1 0 1

Timing: 2+mv oscillator clock cycles Memory: 1+mv program words

0JJJ

d000

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ADDL Shift Left and Add Accumulators ADDL

Operation: Assembler Syntax:

S+2

∗D➞D (parallel move) ADDL S,D (parallel move)

Description: Add the source operand S to two times the destination operand D and store the result in the destination accumulator. The destination operand D is arithmetically shifted one bit to the left, and a zero is shifted into the LS bit of D prior to the addition operation. The carry bit is set correctly if the source operand does not overflow as a result of the left shift operation. The overflow bit may be set as a result of either the shifting or addition operation (or both). This instruction is useful for efficient divide and deci-

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mation in time (DIT) FFT algorithms.

Example:

ADDL A,B #$0,R0 ;A+2

∗B➞B, set up addr. reg. R0

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Frees

Before Execution After Execution

$00:000000:000123

$00:005000:000000 $00:00A000:000123

$00:000000:000123

Explanation of Example: Prior to execution, the 56-bit accumulator contains the value $00:000000:000123, and the 56-bit B accumulator contains the value $00:005000:000000. The ADDL A,B instruction adds two times the value in the B accumulator to the value in the A accumulator and stores the 56-bit result in the B accumulator.

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

S1 S0 I1 I0

MR CCR

LEUNZVC

operand is changed as a result of the instruction’s left shift

C — Set if a carry (or borrow) occurs from bit 55 of A or B result.

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ADDL Shift Left and Add Accumulators ADDL

Note: The definition of the E and U bits varies according to the scaling mode being

used. Refer to A.4 CONDITION CODE COMPUTATION for complete details.

Instruction Format:

ADDL S,D

Opcode:

23 8 7 4 3 0

DATA BUS MOVE FIELD

nc...

OPTIONAL EFFECTIVE ADDRESS EXTENSION

0001

d010

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Frees

Instruction Fields:

S,D d

B,A 0 A,B 1

Timing: 2+mv oscillator clock cycles Memory: 1+mv program words

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ADDR Shift Right and Add Accumulators ADDR

Operation: Assembler Syntax:

S+D / 2➞D (parallel move) ADDR S,D (parallel move)

Description: Add the source operand S to one-half the destination operand D and store the result in the destination accumulator. The destination operand D is arithmetically shifted one bit to the right while the MS bit of D is held constant prior to the addition operation. In contrast to the ADDL instruction, the carry bit is always set correctly, and the overflow bit can only be set by the addition operation and not by an overflow due to the initial shifting operation. This instruction is useful for efficient divide and decimation in

nc...

time (DIT) FFT algorithms.

Example:

ADDR B,A X0,X:(R1)+N1 Y0,Y:(R4)– ;B+A / 2➞A, save X0 and Y0

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Frees

Before Execution After Execution

A A

B B

$80:000000:2468AC

$00:013570:000000 $00:013570:000000

$C0:013570:123456

Explanation of Example: Prior to execution, the 56-bit A accumulator contains the value $80:000000:2468AC, and the 56-bit B accumulator contains the value $00:013570:000000. The ADDR B,A instruction adds one-half the value in the A accumulator to the value in the B accumulator and stores the 56-bit result in the A accumulator.

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

S1 S0 I1 I0

MR CCR

LEUNZVC

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ADDR Shift Right and Add Accumulators ADDR

Note: The definition of the E and U bits varies according to the scaling mode being

used. Refer to A.4 CONDITION CODE COMPUTATION for complete details.

Instruction Format:

ADDR S,D

Opcode:

23 8 7 4 3 0

DATA BUS MOVE FIELD

nc...

OPTIONAL EFFECTIVE ADDRESS EXTENSION

0000

d010

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Frees

Instruction Fields:

S,D d

B,A 0 A,B 1

Timing: 2+mv oscillator clock cycles Memory: 1+mv program words

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AND Logical AND AND

Operation: Assembler Syntax:

• D[47:24]➞D[47:24] (parallel move) AND S,D (parallel move)

where

Description: Logically AND the source operand S with bits 47–24 of the destination operand D and store the result in bits 47–24 of the destination accumulator. This instruction is a 24-bit operation. The remaining bits of the destination operand D are not affected.

•denotes the logical AND operator

nc...

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Example:

AND X0,A (R5)–N5 ;AND X0 with A1, update R5 using N5

Before Execution After Execution

X0 X0

A A

$00:123456:789ABC $00:120000:789ABC

$FF0000

Explanation of Example: Prior to execution, the 24-bit X0 register contains the value $FF0000, and the 56-bit A accumulator contains the value $00:123456:789ABC. The AND X0,A instruction logically ANDs the 24-bit value in the X0 register with bits 47–24 of the A accumulator (A1) and stores the result in the A accumulator with bits 55–48 and 23–0 unchanged.

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

S1 S0 I1 I0

MR CCR

LEUNZVC

L — Set if data limiting has occurred during parallel move N — Set if bit 47 of A or B result is set Z— Set if bits 47–24 of A or B result are zero V — Always cleared

Instruction Format:

AND S,D

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AND Logical AND AND

Opcode:

23 8 7 4 3 0

DATA BUS MOVE FIELD

OPTIONAL EFFECTIVE ADDRESS EXTENSION

Instruction Fields:

S J J D d

nc...

X,0 0 0 A 0 (only A1 is changed) X,1 1 0 B 1 (only B1 is changed) Y,0 0 1 Y,1 1 1

01JJ

d110

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Timing: 2+mv oscillator clock cycles Memory: 1+mv program words

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ANDI AND Immediate with Control Register ANDI

Operation: Assembler Syntax:

#xx

• D➞D AND(I) #xx,D

where

Description: Logically AND the 8-bit immediate operand (#xx) with the contents of the destination control register D and store the result in the destination control register. The condition codes are affected only when the condition code register (CCR) is specified as the destination operand.

• denotes the logical AND operator

nc...

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Restrictions:The ANDI #xx,MR instruction cannot be used immediately before an ENDDO or RTI instruction and cannot be one of the last three instructions in a DO loop (at LA-2, LA-1, or LA).

The ANDI #xx,CCR instruction cannot be used immediately before an RTI instruction.

Example:

AND #$FE,CCR ;clear carry bit C in cond. code register

Before Execution After Execution

CCR

$31 $30

CCR

Explanation of Example: Prior to execution, the 8-bit condition code register (CCR) contains the value $31. The AND #$FE,CCR instruction logically ANDs the immediate 8bit value $FE with the contents of the condition code register and stores the result in the condition code register.

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

S1 S0 I1 I0

MR CCR

LEUNZVC

For CCR Operand:

L — Cleared if bit 6 of the immediate operand is cleared E — Cleared if bit 5 of the immediate operand is cleared U — Cleared if bit 4 of the immediate operand is cleared N — Cleared if bit 3 of the immediate operand is cleared Z— Cleared if bit 2 of the immediate operand is cleared

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ANDI AND Immediate with Control Register ANDI

V — Cleared if bit 1 of the immediate operand is cleared C — Cleared if bit 0 of the immediate operand is cleared

For MR and OMR Operands: The condition codes are not affected using these operands.

Instruction Format:

AND(I) #xx,D

Opcode:

nc...

23 16 15 8 7 0

00000000iiiiiiii101110EE

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Instruction Fields:

#xx=8-bit Immediate Short Data — i i i i i i i i

DE E

MR 0 0 CCR 0 1 OMR 1 0

Timing: 2 oscillator clock cycles Memory: 1 program word

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ASL Arithmetic Shift Accumulator Left ASL

55 47 23 0

Operation:

0 (parallel move)

Assembler Syntax: ASL D (parallel move)

Description: Arithmetically shift the destination operand D one bit to the left and store

the result in the destination accumulator. The MS bit of D prior to instruction execution is shifted into the carry bit C and a zero is shifted into the LS bit of the destination accumu-

nc...

lator D. If a zero shift count is specified, the carry bit is cleared. The difference between ASL and LSL is that ASL operates on the entire 56 bits of the accumulator and therefore sets the V bit if the number overflowed.

Example:

ASL A (R3)– ;multiply A by 2, update R3

Before Execution After Execution

SR SR

$A5:012345:012345

$0300 $0373

$4A:02468A:02468A

Explanation of Example: Prior to execution, the 56-bit A accumulator contains the

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value $A5:012345:012345. The execution of the ASL A instruction shifts the 56-bit value in the A accumulator one bit to the left and stores the result back in the A accumulator.

Condition Codes:

Frees

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

S1 S0 I1 I0

MR CCR

LEUNZVC

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ASL Arithmetic Shift Accumulator Left ASL

Note: The definition of the E and U bits varies according to the scaling mode being

used. Refer to A.4 CONDITION CODE COMPUTATION for complete details.

Instruction Format:

ASL D

Opcode:

23 8 7 4 3 0

DATA BUS MOVE FIELD

nc...

OPTIONAL EFFECTIVE ADDRESS EXTENSION

0011

d010

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Frees

Instruction Fields:

A0 B1

Timing: 2+mv oscillator clock cycles Memory: 1+mv program words

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ASR Arithmetic Shift Accumulator Right ASR

55 47 23 0

Operation:

Assembler Syntax: ASR D (parallel move)

Description: Arithmetically shift the destination operand D one bit to the right and store

the result in the destination accumulator. The LS bit of D prior to instruction execution is shifted into the carry bit C, and the MS bit of D is held constant.

C (parallel move)

nc...

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Example:

ASR B X:–(R3),R3 ;divide B by 2, update R3, load R3

Before Execution After Execution

B B

SR SR

$A8:A86420:A86421

$0300 $0329

$D4:543210:543210

Explanation of Example: Prior to execution, the 56-bit B accumulator contains the value $A8:A86420:A86421. The execution of the ASR B instruction shifts the 56-bit value in the B accumulator one bit to the right and stores the result back in the B accumulator.

Condition Codes:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LF

S1 S0 I1 I0

MR CCR

LEUNZVC

Note: The definition of the E and U bits varies according to the scaling mode being used.

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+ 96 hidden pages

Motorola Freescale Semiconductor DSP56000, Freescale Semiconductor DSP56001 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

A.1 INSTRUCTION GUIDE

A.2 NOTATION

A.3 ADDRESSING MODES

A.3.1 Addressing Mode Modifiers

A.4 CONDITION CODE COMPUTATION

A.5 PARALLEL MOVE DESCRIPTIONS

A.6 INSTRUCTION DESCRIPTIONS