Motorola APX 5000, APX 6000XE, APX 6000, SRX 2200 Service Manual

APX™ TWO-WAY RADIOS

APX 5000/ APX 6000/
APX 6000XE/ SRX 2200
Detailed Service
Manuals

ASTRO® APXTM5000/ APXTM6000/

APX

TM

6000XE/ SRX 2200

VHF/700–800 MHz/UHF1/UHF2

Digital Portable Radios

Detailed Service Manual

Motorola Solutions
1303 E. Algonquin Rd.
Schaumburg, IL 60196-1078 U.S.A.

68012002028-C

Foreword

The information contained in this manual relates to all ASTRO® APXTM5000/ APXTM6000/ APXTM6000XE/ SRX2200
digital portable radios, unless otherwise specified. This manual provides sufficient information to enable qualified service
shop technicians to troubleshoot and repair an ASTRO APX 5000/ APX 6000/ APX 6000XE/ SRX2200 digital portable
radio to the component level.

For details on the operation of the radio or level 1 or 2 maintenance procedures, refer to the applicable manuals, which are
available separately. A list of related publications is provided in the section, “Related Publications,” on page ix.

Product Safety and RF Exposure Compliance

Before using this product, read the operating instructions
for safe usage contained in the Product Safety and RF
Exposure booklet enclosed with your radio.

ATTENTION!

This radio is restricted to occupational use only to satisfy FCC RF energy exposure requirements.
Before using this product, read the RF energy awareness information and operating instructions in the
Product Safety and RF Exposure booklet enclosed with your radio (Motorola Publication part number
6881095C98) to ensure compliance with RF energy exposure limits.

For a list of Motorola-approved antennas, batteries, and other accessories, visit the following web site
which lists approved accessories: www.motorolasolutions.com/APX

Manual Revisions

Changes which occur after this manual is printed are described in FMRs (Florida Manual Revisions). These FMRs provide
complete replacement pages for all added, changed, and deleted items, including pertinent parts list data, schematics, and
component layout diagrams. To obtain FMRs, contact the Customer Care and Services Division (refer to “Appendix A

Replacement Parts Ordering”).

Computer Software Copyrights

The Motorola products described in this manual may include copyrighted Motorola computer programs stored in
semiconductor memories or other media. Laws in the United States and other countries preserve for Motorola certain
exclusive rights for copyrighted computer programs, including, but not limited to, the exclusive right to copy or reproduce in
any form the copyrighted computer program. Accordingly, any copyrighted Motorola computer programs contained in the
Motorola products described in this manual may not be copied, reproduced, modified, reverse-engineered, or distributed in
any manner without the express written permission of Motorola. Furthermore, the purchase of Motorola products shall not
be deemed to grant either directly or by implication, estoppel, or otherwise, any license under the copyrights, patents or
patent applications of Motorola, except for the normal non-exclusive license to use that arises by operation of law in the
sale of a product.

Document Copyrights

No duplication or distribution of this document or any portion thereof shall take place without the express written permission
of Motorola. No part of this manual may be reproduced, distributed, or transmitted in any form or by any means, electronic
or mechanical, for any purpose without the express written permission of Motorola.

Disclaimer

The information in this document is carefully examined, and is believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, Motorola reserves the right to make changes to any products herein to improve
readability, function, or design. Motorola does not assume any liability arising out of the applications or use of any product
or circuit described herein; nor does it cover any license under its patent rights nor the rights of others.

Trademarks

MOTOROLA, MOTO, MOTOROLA SOLUTIONS and the Stylized M logo are trademarks or registered trademarks of
Motorola Trademark Holdings, LLC and are used under license. All other trademarks are the property of their respective
owners. ©2011–2012 Motorola Solutions, Inc. All rights reserved.

Document History iii

Document History

The following major changes have been implemented in this manual since the previous edition:

Edition Description Date

68012002028-A Initial edition Aug 2011

68012002028-B Added APX 5000 info Sept 2011

68012002028-C Added UHF2 info

Added UHF1: NUE7369A
Added APX 6000XE and SRX 2200 info

Jun 2012

iv Document History

Notes

Table of Contents v

Table of Contents

Foreword.........................................................................................................ii

Product Safety and RF Exposure Compliance ............................................................................................ii

Manual Revisions ........................................................................................................................................ii

Computer Software Copyrights ...................................................................................................................ii

Document Copyrights ..................................................................................................................................ii

Disclaimer....................................................................................................................................................ii

Trademarks .................................................................................................................................................ii

Document History .........................................................................................iii

List of Tables ...............................................................................................viii

List of Figures ................................................................................................x

Commercial Warranty ..................................................................................xv

Limited Warranty ....................................................................................................................................... xv

Chapter 1 Introduction ......................................................................... 1-1

1.1 General .......................................................................................................................................... 1-1

1.2 Notations Used in This Manual...................................................................................................... 1-2

Chapter 2 Radio Power ........................................................................ 2-1

2.1 General .......................................................................................................................................... 2-1

2.2 DC Power Routing – Transceiver Board........................................................................................ 2-2

2.3 DC Power Routing – VOCON Board ............................................................................................. 2-3

Chapter 3 Theory of Operation............................................................ 3-1

3.1 Transceiver Board ......................................................................................................................... 3-3

3.2 Controller ..................................................................................................................................... 3-24

3.3 Global Positioning Sytem (GPS).................................................................................................. 3-60

3.4 Accelerometer.............................................................................................................................. 3-62

3.5 Bluetooth...................................................................................................................................... 3-65

Chapter 4 Troubleshooting Procedures ............................................. 4-1

4.1 Handling Precautions..................................................................................................................... 4-1

4.2 Recommended Service Tools........................................................................................................ 4-2

4.3 Standard Bias Table ...................................................................................................................... 4-3

vi Table of Contents

4.4 Power-Up Self-Check Errors.......................................................................................................... 4-4

4.5 Power-Up Self-Check Diagnostics and Repair (Not for Field Use) ................................................4-5

Chapter 5 Troubleshooting Charts ..................................................... 5-1

5.1 List of Troubleshooting Charts .......................................................................................................5-1

5.2 Main Troubleshooting Flowchart.................................................................................................... 5-3

5.3 Power-Up Failure ........................................................................................................................... 5-4

5.4 DC Supply Failure........................................................................................................................5-15

5.5 Top/CID Display Failure............................................................................................................... 5-22

5.6 Main Display Failure .................................................................................................................... 5-23

5.7 Volume Set Error ......................................................................................................................... 5-24

5.8 Channel Select Error.................................................................................................................... 5-25

5.9 Keypad Error................................................................................................................................5-26

5.10 Side Button Error ......................................................................................................................... 5-27

5.11 VOCON RX Audio Error............................................................................................................... 5-28

5.12 VOCON RX Audio Error............................................................................................................... 5-29

5.13 VOCON TX Audio Error ...............................................................................................................5-30

5.14 VOCON TX Audio Error ...............................................................................................................5-31

5.15 Keyload Failure ............................................................................................................................5-32

5.16 Secure Hardware Failure ............................................................................................................. 5-33

5.17 eMMC Memory Failure ................................................................................................................ 5-34

5.18 RX RF Failure ..............................................................................................................................5-35

5.19 FGU Failure ................................................................................................................................. 5-46

5.20 FGU Power Failure ...................................................................................................................... 5-47

5.21 GPS Failure ................................................................................................................................. 5-48

5.22 Bluetooth Failure.......................................................................................................................... 5-49

5.23 PA Failure ....................................................................................................................................5-55

Chapter 6 Troubleshooting Waveforms ............................................. 6-1

6.1 List of Waveforms ..........................................................................................................................6-1

6.2 Clocks ............................................................................................................................................ 6-3

6.3 Audio SSI ....................................................................................................................................... 6-8

6.4 RX SSI ......................................................................................................................................... 6-12

6.5 TX SSI.......................................................................................................................................... 6-15

6.6 SPI ............................................................................................................................................... 6-18

6.7 I2C BUS ....................................................................................................................................... 6-22

6.8 One Wire......................................................................................................................................6-25

6.9 GCAI ............................................................................................................................................ 6-26

6.10 USB.............................................................................................................................................. 6-28

6.11 UART ...........................................................................................................................................6-30

6.12 SDRAM ........................................................................................................................................ 6-32

6.13 FLASH CONTROL.......................................................................................................................6-34

6.14 Expandable Memory (eMMC) ......................................................................................................6-39

6.15 Receive Baseband Signals ..........................................................................................................6-48

6.16 GPS .............................................................................................................................................6-49

6.17 Bluetooth Troubleshooting Waveforms........................................................................................ 6-52

6.18 Bluetooth Steady-State ................................................................................................................ 6-72

6.19 LF CW on Spectrum Analyzer ..................................................................................................... 6-77

Table of Contents vii

Chapter 7 Troubleshooting Tables ..................................................... 7-1

7.1 List of Board and IC Signals .......................................................................................................... 7-1

Chapter 8 Schematics, Boards Overlays, and Parts Lists................ 8-1

8.1 List of Transceiver Schematics and Board Overlays ..................................................................... 8-1

8.2 List of VOCON Schematics and Board Overlays........................................................................... 8-2

8.3 List of Expansion Board Schematics and Overlays ....................................................................... 8-2

8.4 Transceiver (RF) Boards: VHF ...................................................................................................... 8-3

8.5 Transceiver (RF) Boards: UHF1 .................................................................................................. 8-25

8.6 Transceiver (RF) Boards: UHF2 .................................................................................................. 8-61

8.7 Transceiver (RF) Boards: 700–800 MHz ..................................................................................... 8-81

8.8 Controller Board......................................................................................................................... 8-129

8.9 Expansion Board ....................................................................................................................... 8-157

Appendix A Replacement Parts Ordering..............................................A-1

A.1 Basic Ordering Information ............................................................................................................ A-1

A.2 Transceiver Board, VOCON Board and Expander Board Ordering Information............................A-1

A.3 Motorola Online ............................................................................................................................. A-1

A.4 Mail Orders ....................................................................................................................................A-1

A.5 Telephone Orders..........................................................................................................................A-1

A.6 Fax Orders..................................................................................................................................... A-2

A.7 Parts Identification ......................................................................................................................... A-2

A.8 Product Customer Service............................................................................................................. A-2

Glossary......................................................................................... Glossary-1

Index..................................................................................................... Index-1

viii List of Tables

List of Tables

Table 2-1. Batteries ................................................................................................................................ 2-1

Table 2-2. Transceiver Voltage Regulators ............................................................................................2-3

Table 3-1. Battery Connector M101 ....................................................................................................... 3-5

Table 3-2. VOCON Connector J1001 ....................................................................................................3-5

Table 3-3. Port Expander Pin Settings .................................................................................................3-20

Table 3-4. DC Supplies and Sources for Controller .............................................................................3-28

Table 3-5. MAKO’s LDO and Supplies................................................................................................. 3-29

Table 3-6. Pulse Switching Combination .............................................................................................3-31

Table 3-7. VOCON Clock Distribution ..................................................................................................3-33

Table 3-8. Color Schemes ................................................................................................................... 3-48

Table 3-9. Key Map Matrix ................................................................................................................... 3-51

Table 3-10. P1 Pin Assignment..............................................................................................................3-54

Table 3-11. GCAI Connector Pin Assignment........................................................................................3-54

Table 3-12. Encryption Algorithms and Corresponding Kit Numbers..................................................... 3-58

Table 3-13. Power and I/O Pins for NI5500 ........................................................................................... 3-61

Table 3-14. SPI Interface ....................................................................................................................... 3-63

Table 3-15. Register Address Map ........................................................................................................ 3-64

Table 3-16. Bluetooth Host Processor UART I/O................................................................................... 3-71

Table 3-17. SPI I/O ................................................................................................................................ 3-72

Table 3-18. USB I/O............................................................................................................................... 3-72

Table 3-19. GPIO I/O ............................................................................................................................. 3-73

Table 4-1. Recommended Service Tools ...............................................................................................4-2

Table 4-2. Standard Operating Bias – DC Voltages ............................................................................... 4-3

Table 4-3. Standard Operating Bias – Clock Sources............................................................................4-3

Table 4-4. Power-Up Self-Check Error Codes .......................................................................................4-4

Table 4-5. Power-Up Self-Check Diagnostic Actions ............................................................................. 4-5

Table 5-1. Troubleshooting Charts......................................................................................................... 5-1

Table 6-1. List of Waveforms ................................................................................................................. 6-1

Table 6-2. Bluetooth Command to TX.................................................................................................. 6-52

Table 6-3. Bluetooth Command to RX ................................................................................................. 6-53

Table 6-4. Low Frequency Command to TX ........................................................................................ 6-53

Table 6-5. Low Frequency Command to RX ........................................................................................6-53

Table 6-6. Bluetooth Test Points .......................................................................................................... 6-54

Table 7-1. List of Tables of Board and IC Signals .................................................................................. 7-1

Table 7-2. VOCON board to RF board connector Interface PIN-OUT ................................................... 7-2

Table 7-3. VOCON board to EXPANSION board connector Interface PIN-OUT ................................... 7-4

Table 7-4. VOCON board to Control Top with Top Display Interface PIN-OUT...................................... 7-7

Table 7-5. VOCON board to Front Display Interface PIN-OUT.............................................................. 7-9

Table 7-6. VOCON board to Keypad Interface PIN-OUT ..................................................................... 7-10

Table 7-7. EXPANSION board to Accessory Connector (GCAI) Interface PIN-OUT ........................... 7-11

Table 7-8. EXPANSION board to Side Buttons Interface PIN-OUT .....................................................7-12

Table 7-9. EXPANSION board to Speaker and Microphones Interface PIN-OUT................................7-13

Table 7-10. EXPANSION board to AVR / JTAG Interface PIN-OUT ...................................................... 7-14

Table 7-11. Primary IC reference designators ....................................................................................... 7-15

Table 7-12. Overall GPIO pin functions across multiple boards.............................................................7-16

Table 8-1. List of Transceiver Schematics and Board Overlays ............................................................ 8-1

Table 8-2. List of VOCON Schematics and Board Overlays.................................................................. 8-2

Table 8-3. List of VOCON Schematics and Board Overlays.................................................................. 8-2

List of Tables ix

Related Publications

APX 6000 User Guide Model 1 ................................................................................................ 68012001081

APX 6000 User Guide Model 2 ................................................................................................ 68012001080

APX 6000 User Guide Model 3 ................................................................................................ 68012001079

APX 6000 Quick Reference Card Model 1.................................................................................PMLN5715_

APX 6000 Quick Reference Card Model 2.................................................................................PMLN5716_

APX 6000 Quick Reference Card Model 3.................................................................................PMLN5717_

APX 5000/ APX 6000/ APX 6000Li/ APX 6000XE Digital Portable Radios Basic Service

Manual...................................................................................................................................... 68012002028

APX 6000/ APX 7000 Digital Portable Radios User Guide (CD)................................................ PMLN5335_

APX 5000 Digital Portable Radios User Guide (CD)..................................................................NNTN7930_

SRX 2200 User Guide Model 1.5 .............................................................................................68012005050

SRX 2200 User Guide Model 3 ................................................................................................68012005051

SRX 2200 Quick Reference Card Model 1.5.............................................................................. PMLN6131_

SRX 2200 Quick Reference Card Model 3................................................................................. PMLN6132_

SRX 2200 Digital Portable Radios User Guide (CD).................................................................. PMLN6045_

SRX 2200 Basic Service Manual ............................................................................................. 68012005052

x List of Figures

List of Figures

Figure 2-1. DC Power Distribution........................................................................................................... 2-2

Figure 3-1. APX 5000/ APX 6000/ APX 6000XE/ SRX 2200 Overall Block Diagram.............................. 3-2

Figure 3-2. Transceiver (VHF) Block Diagram (Power and Control Omitted)..........................................3-3

Figure 3-3. Transceiver (UHF1 and UHF2) Block Diagram (Power and Control Omitted) ...................... 3-4

Figure 3-4. Transceiver (7/800) Block Diagram (Power and Control Omitted)........................................ 3-4

Figure 3-5. Receiver Block Diagram (VHF)............................................................................................. 3-7

Figure 3-6. Receiver Block Diagram (UHF1 and UHF2) ......................................................................... 3-8

Figure 3-7. Receiver Block Diagram (7/800) ...........................................................................................3-8

Figure 3-8. Transmitter Block Diagram (VHF) ....................................................................................... 3-11

Figure 3-9. Transmitter Block Diagram (UHF1 and UHF2) ................................................................... 3-11

Figure 3-10. Transmitter Block Diagram (7/800) ..................................................................................... 3-12

Figure 3-11. Synthesizer Block Diagram (VHF) ......................................................................................3-17

Figure 3-12. Synthesizer Block Diagram (UHF1 and UHF2)................................................................... 3-17

Figure 3-13. Synthesizer Block Diagram (7/800)..................................................................................... 3-18

Figure 3-14. Controller Interconnection Diagram ....................................................................................3-24

Figure 3-15. Controller Electrical Overview ............................................................................................. 3-26

Figure 3-16. Controller DC Block Diagram .............................................................................................. 3-27

Figure 3-17. V_SW_1.4 Switched Power Supply .................................................................................... 3-30

Figure 3-18. 5V Switched Power Supply ................................................................................................. 3-31

Figure 3-19. Power-up Timing Regulators............................................................................................... 3-32

Figure 3-20. VOCON Clock Architecture................................................................................................. 3-33

Figure 3-21. Overview of OMAP Interconnection with VOCON Peripherals ...........................................3-34

Figure 3-22. OMAP Memory Interface.....................................................................................................3-35

Figure 3-23. Timing of power-up and initialization of eMMC ................................................................... 3-37

Figure 3-24. eMMC Topography.............................................................................................................. 3-38

Figure 3-25. Block Diagram of VOCON and EXPANSION boards as related to eMMC ......................... 3-39

Figure 3-26. RX / TX SSI Configuration ..................................................................................................3-40

Figure 3-27. Audio SSI Configuration...................................................................................................... 3-40

Figure 3-28. SPI and I2C Configuration .................................................................................................. 3-41

Figure 3-29. CPLD Block Diagram .......................................................................................................... 3-42

Figure 3-30. Audio TX Path Block Diagram............................................................................................. 3-43

Figure 3-31. VOCON RX Audio Path Block Diagram .............................................................................. 3-44

Figure 3-32. Control Top Block Diagram ................................................................................................. 3-45

Figure 3-33. Display Circuit Detail Overview Block Diagram................................................................... 3-46

Figure 3-34. Lighting Controller Overview ...............................................................................................3-49

Figure 3-35. Lighting Controller – SRX 2200 .......................................................................................... 3-50

Figure 3-36. Keypad Interface Outline..................................................................................................... 3-51

Figure 3-37. GCAI Signal Configuration ..................................................................................................3-53

Figure 3-38. GCAI Connector.................................................................................................................. 3-53

Figure 3-39. GCAI Connector – Back View ............................................................................................. 3-55

Figure 3-40. VOCON to RF Board Interface........................................................................................

Figure 3-41. APX 5000/ APX 6000/ APX 6000XE/ SRX 2200 Encryption Architecture .......................... 3-57

Figure 3-42. GPS Block Diagram (VHF/700–800 MHz) .......................................................................... 3-61

Figure 3-43. GPS Block Diagram (UHF1 and UHF2) .............................................................................. 3-62

Figure 3-44. Directions of the Detectable Accelerations .........................................................................3-62

Figure 3-45. Accelerometer Block Diagram............................................................................................. 3-63

Figure 3-46. Relation of Bluetooth Antenna Assembly to Expansion Board ........................................... 3-65

Figure 3-47. Bluetooth Connection Flowchart .........................................................................................3-66

Figure 3-48. Bluetooth/Controller Interface with Clock Sources..............................................................3-67

Figure 3-49. Bluetooth Functional Block Diagram ................................................................................... 3-67

.... 3-56

List of Figures xi

Figure 3-50. Bluetooth Low-Frequency Circuit Block Diagram ............................................................... 3-68

Figure 3-51. Bluetooth Low-Frequency Pairing Data Path...................................................................... 3-68

Figure 3-52. Detailed Low-Frequency Transmit/Receive Paths.............................................................. 3-69

Figure 3-53. Chip Power-Up/Power-Down Sequence (Exernal Input/Output Shown) ............................ 3-69

Figure 3-54. Current Distribution Tree for Bluetooth Circuitry ................................................................. 3-70

Figure 3-55. Bluetooth LF UART Connection Block Diagram ................................................................. 3-71

Figure 3-56. Bluetooth USB Interface Too Main VOCON........................................................................ 3-73

Figure 6-1. 32 kHz Clock Waveform ....................................................................................................... 6-3

Figure 6-2. 4 MHz Clock Waveform ........................................................................................................ 6-4

Figure 6-3. 12 MHz Clock Waveform ...................................................................................................... 6-5

Figure 6-4. 16.8 MHz Clock Waveform ................................................................................................... 6-6

Figure 6-5. 24 MHz Clock Waveform ...................................................................................................... 6-7

Figure 6-6. Audio SSI – Red Tx Waveform ............................................................................................. 6-8

Figure 6-7. Audio SSI – Red Rx Waveform............................................................................................. 6-9

Figure 6-8. Audio SSI – Sync. Waveform.............................................................................................. 6-10

Figure 6-9. Audio SSI – BCLK. Waveform ............................................................................................ 6-11

Figure 6-10. RX SSI – CLK. Waveform................................................................................................... 6-12

Figure 6-11. RX SSI – DA Waveform...................................................................................................... 6-13

Figure 6-12. RX SSI – FSync. Waveform................................................................................................ 6-14

Figure 6-13. TX SSI – TX CLK. Waveform.............................................................................................. 6-15

Figure 6-14. TX SSI – DA Waveform ...................................................................................................... 6-16

Figure 6-15. TX SSI – FSync. Waveform ................................................................................................ 6-17

Figure 6-16. SPI – CLK Waveform.......................................................................................................... 6-18

Figure 6-17. MOSI Waveform ................................................................................................................. 6-19

Figure 6-18. MISO Waveform ................................................................................................................. 6-20

Figure 6-19. CS Waveform...................................................................................................................... 6-21

Figure 6-20. I2C Bus – SCA Waveform .................................................................................................. 6-22

Figure 6-21. I2C Bus – SCA 5V Waveform ............................................................................................. 6-23

Figure 6-22. I2C Bus – SDA Waveform .................................................................................................. 6-24

Figure 6-23. 1-Wire Waveform ................................................................................................................ 6-25

Figure 6-24. GCAI – GPIO0 Waveform................................................................................................... 6-26

Figure 6-25. GCAI – GPIO4 Waveform................................................................................................... 6-27

Figure 6-26. USB – D- Waveform ........................................................................................................... 6-28

Figure 6-27. USB – D+ Waveform........................................................................................................... 6-29

Figure 6-28. UART – RX Waveform........................................................................................................ 6-30

Figure 6-29. UART – TX Waveform ........................................................................................................ 6-31

Figure 6-30. SDRAM – CLK Waveform................................................................................................... 6-32

Figure 6-31. SDRAM – CLKX Waveform ................................................................................................ 6-33

Figure 6-32. FLASH CONTROL – ADV Waveform ................................................................................. 6-34

Figure 6-33. FLASH CONTROL – CS3 Waveform ................................................................................. 6-35

Figure 6-34. FLASH CONTROL – OE Waveform ................................................................................... 6-36

Figure 6-35. FLASH CONTROL – RDY Waveform................................................................................. 6-37

Figure 6-36. FLASH CONTROL – WE Waveform................................................................................... 6-38

Figure 6-37. eMMC: Power-On until Final Initialization Waveforms........................................................ 6-39

Figure 6-38. eMMC: Correct Detection, Configuration and Initialization Waveforms .............................. 6-40

Figure 6-39. eMMC: Failure to Properly Detect, Configure and Initialize Waveforms............................. 6-41

Figure 6-40. MMC_CLK @ < 400 kHz during “Clock Frequency Identification Mode” ............................ 6-42

Figure 6-41. MMC_CLK @ < 24 MHz during “Clock Frequency Data Transfer Mode” ........................... 6-43

Figure 6-42. MMC_CMD actual waveform when probing with active probes; short wires;

GND pin soldered ............................................................................................................... 6-44

Figure 6-43. MMC_CMD misleading waveform when probing with passive probe; long wires;

GND clip ............................................................................................................................. 6-45

Figure 6-44. MMC_DAT0, MMC_DAT1, MMC_DAT2, MMC_DAT3 data lines during data

transmission between eMMC and OMAP ........................................................................... 6-46

xii List of Figures

Figure 6-45. F2_TIMER_OUT clock from CPLD into OMAP for eMMC operation .................................. 6-47

Figure 6-46. Received Baseband Waveforms.........................................................................................6-48

Figure 6-47. GPS TCXO Waveforms ...................................................................................................... 6-49

Figure 6-48. GPS RTC Waveforms ......................................................................................................... 6-50

Figure 6-49. GPS UART DATA Waveforms.............................................................................................6-51

Figure 6-50. Startup Waveforms – Vmax of TP16 ................................................................................... 6-55

Figure 6-51. Startup – Timing Difference of TP9 to TP16........................................................................ 6-56

Figure 6-52. Startup – Timing Difference of TP5 to TP16 and Voltage Statistics .................................... 6-57

Figure 6-53. Startup – Timing Difference of TP4 to TP16 and Time Statistics ........................................6-58

Figure 6-54. Startup – Timing Difference of TP4 to TP5 and Time Statistics ..........................................6-59

Figure 6-55. Startup – Vmax of TP5 and Time Statistics ......................................................................... 6-60

Figure 6-56. Startup – Vmax of TP4 and Time Statistics ......................................................................... 6-61

Figure 6-57. Startup – Vmax of TP5 and Voltage Statistics..................................................................... 6-62

Figure 6-58. Startup – Vmax of TP9 and Voltage Statistics..................................................................... 6-63

Figure 6-59. Startup – Vmax of TP10 and Time Statistics.......................................................................6-64

Figure 6-60. Startup – Vmax of TP16 and Voltage Statistics................................................................... 6-65

Figure 6-61. Startup – Vmax of TP13 and Voltage Statistics................................................................... 6-66

Figure 6-62. Startup – Vmax of TP11 and Voltage Statistics ................................................................... 6-67

Figure 6-63. Startup – Timing Difference of TP13 to TP16 and Time Statistics ......................................6-68

Figure 6-64. Startup – Timing Difference of TP10 to TP13 and Time Statistics ...................................... 6-69

Figure 6-65. Startup – Timing Difference of TP11 to TP13 and Time Statistics.......................................6-70

Figure 6-66. Bluetooth CW on Spectrum Analyzer.................................................................................. 6-71

Figure 6-67. Expansion Board – USB D+ Vmax and Packet Timing with Statistics ................................ 6-72

Figure 6-68. Expansion Board – USB D- Vmax and Packet Timing with Statistics................................. 6-73

Figure 6-69. Expansion Board – VSW_3.6 Voltage Statistics ................................................................. 6-74

Figure 6-70. Expansion Board – 32 kHz clock Vmax with Statistics........................................................ 6-75

Figure 6-71. Expansion Board – LF Coil with TX and RX Waveform Measured by a Conducted

Cable on LF Coil ................................................................................................................. 6-76

Figure 6-72. LF CW on Spectrum Analyzer............................................................................................. 6-77

Figure 8-1. NUD7120A Transceiver (RF) Board Overall Circuit Schematic ............................................ 8-3

Figure 8-2. NUD7120A Harmonic Filter Circuit .......................................................................................8-4

Figure 8-3. NUD7120A GPS Circuit ........................................................................................................ 8-5

Figure 8-4. NUD7120A Miscellaneous Connector Circuit ....................................................................... 8-6

Figure 8-5. NUD7120A Receiver Front End Circuit.................................................................................8-7

Figure 8-6. NUD7120A Receiver Back End Circuit .................................................................................8-8

Figure 8-7. NUD7120A DC Power Circuit ............................................................................................... 8-9

Figure 8-8. NUD7120A Transmitter and Automatic Level Control Circuits............................................ 8-10

Figure 8-9. NUD7120A Frequency Generation Unit (Synthesizer) Circuit – 1 of 2 ............................... 8-11

Figure 8-10. NUD7120A Frequency Generation Unit (VCO) Circuit – 2 of 2 .......................................... 8-12

Figure 8-11. NUD7120A Mixer and IF Filter Circuits ...............................................................................8-13

Figure 8-12. NUD7120A Power Amplifier Circuit..................................................................................... 8-14

Figure 8-13. NUD7120A Transceiver (RF) Board Layout – Side 1 .........................................................8-15

Figure 8-14. NUD7120A Transceiver (RF) Board Layout – Side 2 .........................................................8-16

Figure 8-15. NUE7365A/ NUE7369A Transceiver (RF) Board Overall Circuit Schematic ...................... 8-25

Figure 8-16. NUE7365A/ NUE7369A UHF1 Harmonic Filter Circuit .......................................................8-26

Figure 8-17. NUE7365A/ NUE7369A GPS Circuit .................................................................................. 8-27

Figure 8-18. NUE7365A/ NUE7369A Miscellaneous Connector Circuit.................................................. 8-28

Figure 8-19. NUE7365A Receiver Front End Circuit ............................................................................... 8-29

Figure 8-20. NUE7365A/ NUE7369A Receiver Back End Circuit ........................................................... 8-30

Figure 8-21. NUE7365A/ NUE7369A DC Power Circuit..........................................................................8-31

Figure 8-22. NUE7365A/ NUE7369A Transmitter and Automatic Level Control Circuits........................ 8-32

Figure 8-23. NUE7365A Frequency Generation Unit (Synthesizer) Circuit – 1 of 2................................8-33

Figure 8-24. NUE7365A Frequency Generation Unit (VCO) Circuit – 2 of 2...........................................8-34

Figure 8-25. NUE7365A/ NUE7369A Mixer and IF Filter Circuits ...........................................................8-35

List of Figures xiii

Figure 8-26. NUE7365A Power Amplifier Circuit..................................................................................... 8-36

Figure 8-27. NUE7365A Transceiver (RF) Board Layout – Side 1 ......................................................... 8-37

Figure 8-28. NUE7365A Transceiver (RF) Board Layout – Side 2 ......................................................... 8-38

Figure 8-29. NUE7369A Receiver Front End Circuit............................................................................... 8-48

Figure 8-30. NUE7369A Frequency Generation Unit (Synthesizer) Circuit – 1 of 2 ............................... 8-49

Figure 8-31. NUE7369A Frequency Generation Unit (VCO) Circuit – 2 of 2 .......................................... 8-50

Figure 8-32. NUE7369A Power Amplifier Circuit..................................................................................... 8-51

Figure 8-33. NUE7369A Transceiver (RF) Board Layout – Side 1 ......................................................... 8-52

Figure 8-34. NUE7369A Transceiver (RF) Board Layout – Side 2 ......................................................... 8-53

Figure 8-35. NUE7366A Transceiver (RF) Board Overall Circuit Schematic .......................................... 8-61

Figure 8-36. NUE7366A UHF2 Harmonic Filter Circuit ........................................................................... 8-62

Figure 8-37. NUE7366A GPS Circuit ...................................................................................................... 8-63

Figure 8-38. NUE7366A Miscellaneous Connector Circuit ..................................................................... 8-64

Figure 8-39. NUE7366A Receiver Front End Circuit............................................................................... 8-65

Figure 8-40. NUE7366A Receiver Back End Circuit ............................................................................... 8-66

Figure 8-41. NUE7366A DC Power Circuit ............................................................................................. 8-67

Figure 8-42. NUE7366A Transmitter and Automatic Level Control Circuits............................................ 8-68

Figure 8-43. NUE7366A Frequency Generation Unit (Synthesizer) Circuit – 1 of 2 ............................... 8-69

Figure 8-44. NUE7366A Frequency Generation Unit (VCO) Circuit – 2 of 2 .......................................... 8-70

Figure 8-45. NUE7366A Mixer and IF Filter Circuits ...............................................................................8-71

Figure 8-46. NUE7366A Power Amplifier Circuit..................................................................................... 8-72

Figure 8-47. NUE7366A Transceiver (RF) Board Layout – Side 1 ......................................................... 8-73

Figure 8-48. NUE7366A Transceiver (RF) Board Layout – Side 2 ......................................................... 8-74

Figure 8-49. NUF6750A Transceiver (RF) Board Overall Circuit Schematic .......................................... 8-81

Figure 8-50. NUF6750A Harmonic Filter Circuit...................................................................................... 8-82

Figure 8-51. NUF6750A GPS Circuit ...................................................................................................... 8-83

Figure 8-52. NUF6750A Miscellaneous Connector Circuit...................................................................... 8-84

Figure 8-53. NUF6750A Receiver Front End Circuit ............................................................................... 8-85

Figure 8-54. NUF6750A Receiver Back End Circuit ............................................................................... 8-86

Figure 8-55. NUF6750A DC Power Circuit.............................................................................................. 8-87

Figure 8-56. NUF6750A Transmitter and Automatic Level Control Circuits............................................ 8-88

Figure 8-57. NUF6750A Frequency Generation Unit (Synthesizer) Circuit – 1 of 2................................ 8-89

Figure 8-58. NUF6750A Frequency Generation Unit (VCO) Circuit – 2 of 2........................................... 8-90

Figure 8-59. NUF6750A Mixer and IF Filter Circuits ...............................................................................8-91

Figure 8-60. NUF6750A Power Amplifier Circuit..................................................................................... 8-92

Figure 8-61. NUF6750A Transceiver (RF) Board Layout – Side 1.......................................................... 8-93

Figure 8-62. NUF6750A Transceiver (RF) Board Layout – Side 2.......................................................... 8-94

Figure 8-63. HLN5979B/ HLN5960AController Board Overall Schematic ............................................ 8-129

Figure 8-64. HLN5979B/ HLN5960A Controller Board Display, Controls and JTAG Schematics......... 8-130

Figure 8-65. HLN5979B Controller Board Display/Keypad Lighting Control Circuits ............................ 8-131

Figure 8-66. HLN5979B/ HLN5960A Controller Board LCD and Keypad Connector Circuits............... 8-132

Figure 8-67. HLN5979B/ HLN5960A Controller Board Expansion Board Interface Circuits ................. 8-133

Figure 8-68. HLN5979B Controller Board CPLD Circuit ....................................................................... 8-134

Figure 8-69. HLN5979B/ HLN5960A Controller Board OMAP User Interface Circuit ........................... 8-135

Figure 8-70. HLN5979B/ HLN5960A Controller Board Memory Interface Circuit ................................. 8-136

Figure 8-71. HLN5979B/ HLN5960A Controller Board Audio Circuit .................................................... 8-137

Figure 8-72. HLN5979B/ HLN5960A Controller Board MAKO/DC Circuits........................................... 8-138

Figure 8-73. HLN5979B/ HLN5960A Controller Board Serial Interface Circuit ..................................... 8-139

Figure 8-74. HLN5979B/ HLN5960A Controller Board RF Interface Circuit.......................................... 8-140

Figure 8-75. HLN5979B Controller Board Layout – Side 1 ................................................................... 8-141

Figure 8-76. HLN5979B Controller Board Layout – Side 2 ................................................................... 8-142

Figure 8-77. HLN5960A Controller Board Display/Keypad Lighting Control Circuits ............................ 8-148

Figure 8-78. HLN5960A Controller Board CPLD Circuit ....................................................................... 8-149

Figure 8-79. HLN5960A Controller Board Layout – Side 1 ................................................................... 8-150

xiv List of Figures

Figure 8-80. HLN5960A Controller Board Layout – Side 2 ................................................................... 8-151

Figure 8-81. HLN5978B Expansion Board Overall Circuit Schematic...................................................8-157

Figure 8-82. HLN5977A/ HLN5978B Audio Circuit ............................................................................... 8-158

Figure 8-83. HLN5977A/ HLN5978B Secure Circuit ............................................................................. 8-159

Figure 8-84. HLN5978B Expandable Memory Circuit ...........................................................................8-160

Figure 8-85. HLN5978B GPS Bluetooth Circuit – 1 of 2 ....................................................................... 8-161

Figure 8-86. HLN5978B GPS Bluetooth Circuit – 2 of 2 ....................................................................... 8-162

Figure 8-87. HLN5977A/ HLN5978B Expansion Board Layout – Side 1 ..............................................8-163

Figure 8-88. HLN5977A/ HLN5978B Expansion Board Layout – Side 2 ..............................................8-164

Commercial Warranty xv

Commercial Warranty

Limited Warranty

MOTOROLA COMMUNICATION PRODUCTS

I. What This Warranty Covers And For How Long

MOTOROLA SOLUTIONS INC. (“MOTOROLA”) warrants the MOTOROLA manufactured
Communication Products listed below (“Product”) against defects in material and workmanship
under normal use and service for a period of time from the date of purchase as scheduled below:

ASTRO APX 5000/ APX 6000/ APX 6000XE/ SRX 2200 Digital Portable Units One (1) Year

Product Accessories One (1) Year

Motorola, at its option, will at no charge either repair the Product (with new or reconditioned parts),
replace it (with a new or reconditioned Product), or refund the purchase price of the Product during
the warranty period provided it is returned in accordance with the terms of this warranty. Replaced
parts or boards are warranted for the balance of the original applicable warranty period. All replaced
parts of Product shall become the property of MOTOROLA.

This express limited warranty is extended by MOTOROLA to the original end user purchaser only
and is not assignable or transferable to any other party. This is the complete warranty for the Product
manufactured by MOTOROLA. MOTOROLA assumes no obligations or liability for additions or
modifications to this warranty unless made in writing and signed by an officer of MOTOROLA.
Unless made in a separate agreement between MOTOROLA and the original end user purchaser,
MOTOROLA does not warrant the installation, maintenance or service of the Product.

MOTOROLA cannot be responsible in any way for any ancillary equipment not furnished by
MOTOROLA which is attached to or used in connection with the Product, or for operation of the
Product with any ancillary equipment, and all such equipment is expressly excluded from this
warranty. Because each system which may use the Product is unique, MOTOROLA disclaims
liability for range, coverage, or operation of the system as a whole under this warranty.

II. General Provisions

This warranty sets forth the full extent of MOTOROLA’s responsibilities regarding the Product.
Repair, replacement or refund of the purchase price, at MOTOROLA’s option, is the exclusive
remedy. THIS WARRANTY IS GIVEN IN LIEU OF ALL OTHER EXPRESS WARRANTIES. IMPLIED
WARRANTIES, INCLUDING WITHOUT LIMITATION, IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE LIMITED TO THE
DURATION OF THIS LIMITED WARRANTY. IN NO EVENT SHALL MOTOROLA BE LIABLE FOR
DAMAGES IN EXCESS OF THE PURCHASE PRICE OF THE PRODUCT, FOR ANY LOSS OF
USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, LOST PROFITS OR SAVINGS
OR OTHER INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
USE OR INABILITY TO USE SUCH PRODUCT, TO THE FULL EXTENT SUCH MAY BE
DISCLAIMED BY LAW.

xvi Commercial Warranty

III. State Law Rights

SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
CONSEQUENTIAL DAMAGES OR LIMITATION ON HOW LONG AN IMPLIED WARRANTY
LASTS, SO THE ABOVE LIMITATION OR EXCLUSIONS MAY NOT APPLY.

This warranty gives specific legal rights, and there may be other rights which may vary from state to
state.

IV. How To Get Warranty Service

You must provide proof of purchase (bearing the date of purchase and Product item serial number)
in order to receive warranty service and, also, deliver or send the Product item, transportation and
insurance prepaid, to an authorized warranty service location. Warranty service will be provided by
Motorola through one of its authorized warranty service locations. If you first contact the company
which sold you the Product, it can facilitate your obtaining warranty service. You can also call
Motorola at 1-888-567-7347 US/Canada.

V. What This Warranty Does Not Cover

A. Defects or damage resulting from use of the Product in other than its normal and customary

manner.

B. Defects or damage from misuse, accident, water, or neglect.

C. Defects or damage from improper testing, operation, maintenance, installation, alteration,

modification, or adjustment.

D. Breakage or damage to antennas unless caused directly by defects in material workmanship.

E. A Product subjected to unauthorized Product modifications, disassemblies or repairs

(including, without limitation, the addition to the Product of non-Motorola supplied equipment)
which adversely affect performance of the Product or interfere with Motorola's normal
warranty inspection and testing of the Product to verify any warranty claim.

F. Product which has had the serial number removed or made illegible.

G. Rechargeable batteries if:

• any of the seals on the battery enclosure of cells are broken or show evidence of
tampering.

• the damage or defect is caused by charging or using the battery in equipment or service
other than the Product for which it is specified.

H. Freight costs to the repair depot.

I. A Product which, due to illegal or unauthorized alteration of the software/firmware in the

Product, does not function in accordance with MOTOROLA’s published specifications or the
FCC certification labeling in effect for the Product at the time the Product was initially
distributed from MOTOROLA.

J. Scratches or other cosmetic damage to Product surfaces that does not affect the operation of

the Product.

K. Normal and customary wear and tear.

Commercial Warranty xvii

VI. Patent And Software Provisions

MOTOROLA will defend, at its own expense, any suit brought against the end user purchaser to the
extent that it is based on a claim that the Product or parts infringe a United States patent, and
MOTOROLA will pay those costs and damages finally awarded against the end user purchaser in
any such suit which are attributable to any such claim, but such defense and payments are
conditioned on the following:

A. that MOTOROLA will be notified promptly in writing by such purchaser of any notice of such

claim;

B. that MOTOROLA will have sole control of the defense of such suit and all negotiations for its

settlement or compromise; and

C. should the Product or parts become, or in MOTOROLA’s opinion be likely to become, the

subject of a claim of infringement of a United States patent, that such purchaser will permit
MOTOROLA, at its option and expense, either to procure for such purchaser the right to
continue using the Product or parts or to replace or modify the same so that it becomes
noninfringing or to grant such purchaser a credit for the Product or parts as depreciated and
accept its return. The depreciation will be an equal amount per year over the lifetime of the
Product or parts as established by MOTOROLA.

MOTOROLA will have no liability with respect to any claim of patent infringement which is based
upon the combination of the Product or parts furnished hereunder with software, apparatus or
devices not furnished by MOTOROLA, nor will MOTOROLA have any liability for the use of ancillary
equipment or software not furnished by MOTOROLA which is attached to or used in connection with
the Product. The foregoing states the entire liability of MOTOROLA with respect to infringement of
patents by the Product or any parts thereof.

Laws in the United States and other countries preserve for MOTOROLA certain exclusive rights for
copyrighted MOTOROLA software such as the exclusive rights to reproduce in copies and distribute
copies of such Motorola software. MOTOROLA software may be used in only the Product in which
the software was originally embodied and such software in such Product may not be replaced,
copied, distributed, modified in any way, or used to produce any derivative thereof. No other use
including, without limitation, alteration, modification, reproduction, distribution, or reverse
engineering of such MOTOROLA software or exercise of rights in such MOTOROLA software is
permitted. No license is granted by implication, estoppel or otherwise under MOTOROLA patent
rights or copyrights.

VII. Governing Law

This Warranty is governed by the laws of the State of Illinois, USA.

xviii Commercial Warranty

Notes

Chapter 1 Introduction

1.1 General

This manual includes all the information needed to maintain peak product performance and
maximum working time for the ASTRO APX 5000/ APX 6000/ APX 6000XE/ SRX 2200 radio. This
detailed level of service (component level) is typical of the service performed by some service
centers, self-maintained customers, and distributors.

Use this manual in conjunction with the ASTRO APX 5000/ APX 6000/ APX 6000XE/ SRX 2200
VHF (136–174 MHz), UHF1 (380–470 MHz), UHF2 (450–520 MHz) and 764–870 MHz Digital
Portable Radios Basic Service Manual (Motorola part number 68012002028), which can help in
troubleshooting a problem to a particular printed circuit (PC) board.

Conduct the basic performance checks outlined in the basic service manual first to verify the need to
analyze the radio and to help pinpoint the functional problem area. In addition, you will become
familiar with the radio test mode of operation, which is a helpful tool. If any basic receive or transmit
parameters fail to be met, the radio should be aligned according to the radio alignment procedure.

Included in other areas of this manual are functional block diagrams, detailed theory of operation,
troubleshooting charts and waveforms, schematics, and parts lists. You should become familiar with
these sections to aid in determining circuit problems. Also included are component location diagrams
to aid in locating individual circuit components and some IC diagrams, which identify some
convenient probe points.

“Chapter 3, Theory of Operation,” on page 3-1, contains detailed descriptions of the operations of

many circuits. Once you locate the problem area, review the troubleshooting flowchart for that circuit
to fix the problem.

1-2 Introduction: Notations Used in This Manual

1.2 Notations Used in This Manual

Throughout the text in this publication, you will notice the use of warnings, cautions, and notes.
These notations are used to emphasize that safety hazards exist, and care must be taken and
observed.

NOTE: An operational procedure, practice, or condition that is essential to emphasize.

CAUTION indicates a potentially hazardous situation which, if
not avoided, might

WARNING indicates a potentially hazardous situation
which, if not avoided, could

result in equipment damage.

result in death or injury.

DANGER indicates an imminently hazardous
situation which, if not avoided, will

result in death or

injury.

Chapter 2 Radio Power

This chapter provides a detailed circuit description of the power distribution of an ASTRO APX 5000/
APX 6000/ APX 6000XE/ SRX 2200 radio.

2.1 General

In the ASTRO APX 5000/ APX 6000/ APX 6000XE/ SRX 2200 radio, power (B+) is distributed to two
boards: the transceiver (RF) board and the VOCON board (see Figure 2-1 on page 2-2).

Power for the radio is provided through a battery supplying a nominal 7.5 Vdc directly to the
transceiver. The following battery types and capacities are available:

Table 2-1. Batteries

Part Number Description

NNTN7033 4100 mAh IMPRES Li-Ion, Intrinsically Safe, Rugged

NNTN7034 4200 mAh IMPRES Li-Ion, Rugged

NNTN7035 2000 mAh IMPRES NiMH, Intrinsically Safe, Rugged

NNTN7036 2000 mAh IMPRES NiMH, Intrinsically Safe, IP67

NNTN7037 2100 mAh IMPRES NiMH, IP67

NNTN7038 2900 mAh IMPRES Li-Ion, IP67

NNTN7573 2100 mAh IMPRES NiMH, Rugged

NNTN8092 2300 mAh IMPRES Li-Ion, Intrinsically Safe, Rugged

NNTN8182 2900 mAh Li-Ion, Rugged, Military

PMNN4403 2150 mAh IMPRES Li-Ion, Slim, IP67

2-2 Radio Power: DC Power Routing – Transceiver Board

Battery

7.5 Volts
(Nominal)

M101

BATT

RAW B+

5Vdc

3Vdc

1.8 Volts

1.5Vdc

1.5Volts

Expansion Board

Audio PA

3.3Vdc

2.8Vdc

RF Board VOCON Board

PMOS

Fuse

5Vdc

3.3Vdc

2.8Vdc

FB+

P101

1.85Vdc

3Vdc

1.8Vdc

2.8Vdc

5.4Vdc

5.4Vdc

1.4Vdc

1.85Vdc

3.6Vdc

5.4Vdc

3.6Vdc

2.775Vdc

1.85Vdc

FB+

Switch

External SW

External SW

External LDO

1.875Vdc

1.55Vdc

2.775Vdc

2.775Vdc

2.8Vdc

3.0Vdc

3.3Vdc

5Vdc

5Vdc

5Vdc

SW_B +

MAKO

SW2

LD02

LDO3

LD04

LD06

LD07

LD09

LDO10

VBUS1

VBUS2

LD08

External

SW

External

LDO

3.6Vdc

2.23Vdc

2.23Vdc

2.23Vdc

3.6Vdc

3.6Vdc

3.6Vdc

3.6Vdc

3.6Vdc

5.4Vdc

5.4Vdc

SW_B +

Figure 2-1. DC Power Distribution

B+ from the battery is electrically switched to most of the radio, rather than routed through the On/
Off/volume control knob, S2. The electrical switching of B+ supports a keep-alive mode. Under
software control, even when the On/Off/volume control knob has been turned to the Off position,
power remains on until the MCU completes its power-down, at which time the radio is physically
powered down.

2.2 DC Power Routing – Transceiver Board

NOTE: Refer to Table 8-1, “List of Transceiver Schematics and Board Overlays,” on page 8-1 for a

listing of schematics showing the transceiver board DC power routing components.

Connector M101, the B-plus assembly, connects the battery to the transceiver board. Component
E200 forms a power-line filter for signal DC_ RAW_B+, which supplies battery voltage to the
transmitter section. Fuse F200 and filter C202, L200, C203 supply fused B plus to the VOCON
board.

In turn, the VOCON board supplies VSW1 regulated 3.6 Vdc, 2.78 Vdc, and 1.85 Vdc. The

3.6 Vdc supplies regulator U201 and controls switch Q201 which supplies fuse B+ to regulator U200.
Regulator U201 supplies regulator U202 which in turn supplies regulator U203. The 2.78 Vdc
supplies the Trident IC U702, 16.8 MHz crystal circuit and Logic Expander IC U703. The 1.85 sets
the logic level for the SPI and SSI data.

The transceiver board has four regulators 5 Vdc (U200), 3 Vdc (U201), 1.8 Vdc (U202) and 1.5 Vdc
(U203). The 5 volt regulator supplies the FGU section, transmitter ALC and receiver back end. The
3 volt regulator supplies dc for the receiver front ends, mixer, receiver back end and GPS.
The 1.8 volt regulator supplies dc for the receiver front end and mixer. The 1.5 volt regulator supplies
dc for the buffers in the FGU section.

Radio Power: DC Power Routing – VOCON Board 2-3

The transceiver regulated power supplies are summarized in Table 2-2.

Table 2-2. Transceiver Voltage Regulators

Reference

Designator

U200 LP2989 DC_LIN_5V Regulated 5.0 Vdc

U201 LP5900 DC_LIN_3V Regulated 3.0 Vdc

U202 LP5900 DC_LIN_1_8V Regulated 1.8 Vdc

U203 LP5952 DC_LIN_1_5V Regulated 1.5 Vdc

IC

Name

Output

Signal Name

2.3 DC Power Routing – VOCON Board

NOTE: Refer to Table 8-2, “List of VOCON Schematics and Board Overlays,” on page 8-2 for a listing

of schematics showing the VOCON board DC power routing components.

Refer to “3.2.2 DC Distribution” on page 3-27 for details on DC Power Routing for VOCON Board.

Description

2-4 Radio Power: DC Power Routing – VOCON Board

Notes

Chapter 3 Theory of Operation

This chapter provides a detailed circuit description of the ASTRO APX 5000/ APX 6000/
APX 6000XE/ SRX 2200 transceiver and VOCON boards. When reading the theory of operation,
refer to the appropriate schematic and component location diagrams located in the back of this
manual. This detailed theory of operation can help isolate the problem to a particular component.

The ASTRO APX 5000/ APX 6000/ APX 6000XE radio, which is a single-band synthesized radio, is
available in the VHF (136–174 MHz), 7/800 (764–870 MHz), UHF1 (380–470 MHz) and
UHF2 (450–520 MHz) frequency bands. The ASTRO SRX 2200 radio is available in the
VHF (136–174 MHz) and UHF1 (380–470 MHz) frequency bands. The UHF1 band SRX 2200 is
available with a low power setting that limits the transmit power to 0.25 watt.

All ASTRO APX 5000/ APX 6000/ APX 6000XE/ SRX 2200 radios are capable of both analog
operation (12.5 kHz or 25 kHz bandwidths), ASTRO mode operation (12.5 kHz digital only), and
X2-TDMA mode (25 kHz only).

The ASTRO APX 5000/ APX 6000/ APX 6000XE/ SRX 2200 radio (Figure 3-1) consists of the
following:

• VOCON Board – contains a dual-core processor which includes both the microcontroller unit

(MCU) and a digital signal processor (DSP) core, the processor's memory devices, an audio
and power supply support integrated circuit (IC), a digital support IC, and an external audio
power amplifier.

• Transceiver (XCVR) Board – contains all transmit, receive, and frequency generation circuitry,

including the digital receiver back-end IC and the reference oscillator.

• Expansion Board

- Standard – contains the internal audio power amplifier circuitry and a Type III secure IC.

- Full-Feature – contains the internal audio power amplifier circuitry, a combination Global
Positioning System (GPS)/Bluetooth 2.1 IC and support circuitry, a 3-axes digital
accelerometer, an e-MMC NAND flash, and a Type III secure IC.

• Top Display – 112 pixels x 32 pixels, transflective monochrome liquid crystal display (LCD).

• Control Top – contains five switches: On/Off & Volume Knob, a 16 position Channel/Frequency

Knob with concentric 2 position switch (for Secure Enable/Disable operation), a 3 position
toggle switch for Zone Selection, and a push button switch used for Emergency calling. The
control top also includes a TX/RX LED that is solid amber upon receive, red on PTT, and blinks
amber on secure TX/RX.

• Front Display (Dual-Display Version only) – 130 pixels x 130 pixels, transflective color LCD.

• Keypad (Dual-Display Version Only) – Limited keypad version has a 3 x 2 Menu keypad with

a 4-way navigation button; Full keypad version also has a 3 x 4 alphanumeric keypad.

3-2 Theory of Operation:

Bluetooth

Antenna

Antenna

Transceiver

Board

Expansion

Board

80

40

VOCON

Board

16

22

20

50 20

30

External Accessory Connector
External Antenna

Front Display

Keypad

Top Display

Controls Top

Figure 3-1. APX 5000/ APX 6000/ APX 6000XE/ SRX 2200 Overall Block Diagram

Theory of Operation: Transceiver Board 3-3

3.1 Transceiver Board

The transceiver (XCVR) board performs the transmitter and receiver functions necessary to translate
between voice and data from the VOCON board and the modulated radio-frequency (RF) carrier at
the antenna. The transceiver board contains all the radio’s RF circuits for the following major
components:

• Receiver

• Transmitter

• Frequency Generation Unit (FGU)

Figure 3-2 illustrates the VHF transceiver board block diagram, Figure 3-3 and Figure 3-4 illustrates

the UHF1, UHF2 and 7/800 transceiver block diagrams.

FGU
Transmitter

Log
Amp

Receiver

Indicates Sub-shield

SP3T Rf Switch

SP3T

Atten

Harmonic
Filter

FET

VHF

Driver
Amplifier

GPS

Rev

Power

Detector

Digital

RF Atten

coupler

*

VHF LNA

16.8MHz

16.8MHz
BUFFER

TRIDENT IC

LOGIC

EXPANDER

2

÷

PRESCALAR

BUFFER

LOOP

FILTER

Mixer

PRE

BUFFER

RX LO

VHF TX

VHF RX

VHF TX

Abacus

*

BUFFER

2nd

LO

Figure 3-2. Transceiver (VHF) Block Diagram (Power and Control Omitted)

TX

TX LO

RX SSI Data

RX SSI Clock

RX SSI Frame Sync

3-4 Theory of Operation: Transceiver Board

FGU
Transmitter

Log
Amp

Receiver

Indicates Sub-shield

SP3T Rf Switch

SP3T

Atten

Harmonic
Filter

FET

UHF

Driver
Amplifier

GPS

GPS

SP2T

Aux

Rev

Power

Detector

Digital

RF Atten

coupler

*

UHF LNA

16.8MHz

16.8MHz
BUFFER

TRIDENT IC

LOGIC

EXPANDER

PRESCALAR

BUFFER

LOOP
FILTER

Mixer

PRE

BUFFER

RX LO

UHF TX

UHF RX

Abacus

2nd

LO

TX

*

BUFFER

RX SSI Data

RX SSI Frame Sync

TX LO

RX SSI Clock

Figure 3-3. Transceiver (UHF1 and UHF2) Block Diagram (Power and Control Omitted)

FGU
Transmitter

Log
Amp

Receiver

Indicates Sub-shield

SP3T Rf Switch

SP3T

Atten

Harmonic
Filter

FET

7/800

Driver
Amplifier

GPS

SP2T

Aux

Rev

Power

Detector

Digital

RF Atten

coupler

*

700

800

7/800 LNA1

16.8MHz

16.8MHz
BUFFER

TRIDENT IC

LOGIC

EXPANDER

PRESCALAR

BUFFER

LNA2

LOOP
FILTER

Mixer

PRE

BUFFER

RX LO

7/800 TX

7/800 RX

Abacus

2nd

LO

TX

*

BUFFER

RX SSI Data

RX SSI Frame Sync

TX LO

Figure 3-4. Transceiver (7/800) Block Diagram (Power and Control Omitted)

RX SSI Clock

Theory of Operation: Transceiver Board 3-5

3.1.1 Interconnections

This section describes the various interconnections for the transceiver board.

3.1.1.1 Battery Connector M101

Battery connector M101 solders to the transceiver printed circuit board. The connector has 5 gold
plated contacts that mate with the battery, two contacts for positive, two for negative and one for the
Dig_Battery_Data. Signal descriptions are in Table 3-1.

Table 3-1. Battery Connector M101

Pin No. Signal Description

1 DC_BATT Battery positive terminal, nominally 7.5 Vdc

2 Dig_Battery_Data Battery status, from battery to VOCON

3 Ground Battery negative terminal, tied to PCB ground

3.1.1.2 VOCON Connector J1001

VOCON connector J1001 is a 40 pin board to board connector that connects to XCVR board
connector P101. This is a digital interface carrying DC power, control, and data between the XCVR
and VOCON boards.

Table 3-2 lists the connector pins, their signals, and functions. SPI refers to serial peripheral

interface, which is the control bus from the microprocessor. SSI is the serial synchronous interface
bus for data to and from the DSP. There is a RX SSI bus for demodulated data from the receiver and
a TX SSI bus for modulation data to the transmitter.

Table 3-2. VOCON Connector J1001

Pin
No.

1 GROUND GROUND – – –

2 EEPROM_SPI_CS DIG_CTRL_SPI_EEPROM_PE I spi SPI EEprom chip select

3 16.8_MHZ_SINEWAVE CLK_16_8MHZ O rf 16.8 MHz reference clock

4 GROUND GROUND – – –

5 GROUND GROUND – – –

6 V_EXT_1.85 DC_LIN_1_875_D I dc Regulated 1.85 V

7 RF_BRD_RSTB DIG_CTRL_RSTB I/O control Reset

VOCON Signal XCVR Signal

XCVR

I/O

Type Description

8 V_2.8_RF DC_LIN_2_775V I dc Regulated 2.775 V

9 DMCS DIG_CTRL_SSI_TRIGGER I ssi SSI Trigger

10 F2_PARAMP DIG_CTRL_IO49 I control TX Slot enable

11 RX_FSYNC DIG_DATA_SSI_RX_FS O ssi RX SSI frame sync

3-6 Theory of Operation: Transceiver Board

Table 3-2. VOCON Connector J1001 (Continued)

Pin

No.

12 TX_INH DIG_CTRL_TX_INHIBIT_TYPE_1 I control TX inhibit control for

13 RX_DA DIG _DATA _SSI _RX _DOUTA O ssi RX SSI data

14 RF_DAC_SPI_CS DIG_CTRL_SPI_DAC_PE I spi SPI DAC chip select

15 RX_CLK CLK_SSI_RX O ssi RX SSI clock

16 ISET ANA_CTRL_ISET I control MAKO Ramp

17 TX_FSYNC DIG_TX_SSI_FS I ssi TX SSI frame sync

18 TX_DA_CONN DIG_DATA_TX_SSI I ssi TX SSI data

19 TX_CLK DIG_TX_SSI_CLK I ssi TX SSI clock

20 V_Coin_Cell V_Coin_Cell – dc Coin cell battery

21 GPS_ANT RF_GPS O rf GPS_RF signal

22 ABACUS_SPI_CS DIG_CTRL_SPI_ABACUS_PE I spi SPI Abacus chip select

23 F2_SYNCB DIG_SYNCB I control Synchronize RX SSI data

24 GROUND GROUND – – –

VOCON Signal XCVR Signal

XCVR

I/O

Typ e Description

secure

25 LOCK_DET_A DIG_CTRL_LOCK O status FGU lock detect

26 BSTAT DIG_BATTERY_DATA I/O 1 wire IMPRES Battery status

27 TRIDENT_SPI_CS DIG_CTRL_SPI_TRIDENT_PE I spi SPI Trident chip select

28 UNSW_B+ DC_FUSED _B+ O dc Fused B+ to VOCON

29 SPI_DSP_MISO DIG_DATA_SPI_MISO O spi SPI data out

30 UNSW_B+ DC_FUSED _B+ O dc Fused B+ to VOCON

31 SPI_DSP_MOSI DIG_DATA_SPI_MOSI I/O spi SPI data I/O

32 UNSW_B+ DC_FUSED _B+ O dc Fused B+ to VOCON

33 SPI_DSP_CLK DIG_SPI_CLK I spi SPI clock

34 UNSW_B+ DC_FUSED _B+ O dc Fused B+ to VOCON

35 GROUND GROUND – – –

36 UNSW_B+ DC_FUSED _B+ O dc Fused B+ to VOCON

37 VCC_SW_3.6 DC_SW1_3_6V I dc Regulated 3.6 V

38 GROUND GROUND – – –

39 GROUND GROUND – – –

40 GROUND GROUND – – –

Theory of Operation: Transceiver Board 3-7

3.1.1.3 Antenna Port J101

Antenna port J101 is a surface-mount, miniature coaxial connector for the antenna cable.

3.1.1.4 Serial EEPROM

The electrically erasable programmable memory (EEPROM), U101, holds all of the transceiver
tuning data. This allows transceivers to be tuned in the factory and installed in the field without
retuning.

3.1.1.5 Power Conditioning Components

DC power-conditioning components include zener diodes, capacitors, ferrite beads, a power
inductor, and the fuse. Diodes VR200 and VR101 provide over-voltage protection. Ferrite beads
(designated E, etc.) and capacitors suppress electromagnetic interference from the transceiver.

The power-line filter consisting of L200, C202, and C203 suppresses digital noise from the VOCON
board switching power supplies that could degrade the transmitter spectral purity.

Ground clips M103 and M104 make contact between the transceiver board ground and the radio
chassis. The chassis connection is a necessary electrical reference point to complete the antenna
circuit path. Shields SH1 through SH14 appear on the schematic to show their connection to ground.

3.1.2 Receiver

In the VHF radio, the RF signal is received at the antenna and is routed through a Receive/Transmit
Multi Switch (SP3T). In the UHF1, UHF2 and 7/800 radio, the signal goes from the antenna and is
routed through an Auxiliary Switch before the Multi Switch (SP3T) IC. After the switch, the RF signal
passes through a diplexer circuit and a controllable external 15 dB attenuator. The output of the
attenuator leads to the receiver front end section.

• VHF band (See Figure 3-5.)

• UHF1 and UHF2 bands (See Figure 3-6.)

• 7/800 band (See Figure 3-7.)

PER

DPLXR

SP3T

VHF

GPS

Dec.

To
RF/Vocon
Connector

ADC ΣΔ

Filter

2nd

LO

LO

CLK

Abacus III

SSI

18Mhz

CLK

Figure 3-5. Receiver Block Diagram (VHF)

3-8 Theory of Operation: Transceiver Board

AUX

GPS

PER

DPLXR

SP3T

UHF

To
RF/Vocon
Connector

Figure 3-6. Receiver Block Diagram (UHF1 and UHF2)

2nd

LO

Dec.

ADC ΣΔ

Filter

LO

CLK

Abacus III

SSI

18Mhz

CLK

AUX

GPS

PER

DPLXR

SP3T

700/800

Dec.

ADC ΣΔ

Filter

SSI

To
RF/Vocon
Connector

Figure 3-7. Receiver Block Diagram (7/800)

2nd

LO

LO

CLK

Abacus III

18Mhz

CLK

Theory of Operation: Transceiver Board 3-9

3.1.2.1 VHF Front-End

From the attenuator, U1149, a VHF signal is routed to the first pre-selector filter followed by a Low
Noise Amplifier (LNA) and a second pre-selector filter. Both filters are discrete and fixed designs and
are used to band limit the incoming energy and suppress known spurious responses such as Image
and the ½ IF spur. The LNA active device is an NPN transistor (U302) with active bias provided by
transistor pair Q302.

The output of the second pre-selector filter is applied to the RF port of the Mixer IC via balun
transformer, T503. The Mixer IC, U506, is driven by a Local Oscillator (LO) signal generated by the
Trident synthesizer IC, U702, at the LO port to down-convert the RF signal to a 109.65 MHz
intermediate frequency (IF). It is a passive, high linearity design with balanced inputs at the RF and
IF ports and internal LO buffer. The down converted IF signal is passed through a 3-pole crystal filter,
FL501, and an IF amplifier, Q503, which drive the input of the Analog to Digital Converter IC, U601

3.1.2.2 UHF1 Front-End

From the attenuator, U1149, a UHF1 signal is routed to the first pre-selector filter followed by a Low
Noise Amplifier (LNA) and a second pre-selector filter. Both filters are discrete and tunable designs
and are used to band limit the incoming energy and suppress known spurious responses such as
Image spur. The LNA active device is an NPN transistor (U2032) with active bias provided by
transistor pair Q2022. The output of the second pre-selector filter is applied to a discrete Low Pass
Filter (LPF). The output of the LPF is applied to the RF port of the Mixer IC via a balun transformer,
T503. The Mixer IC, U506, is driven by a Local Oscillator (LO) signal generated by the Trident
synthesizer IC, U702, at the LO port to down-convert the RF signal to a 109.65 MHz intermediate
frequency (IF). It is a passive, high linearity design with balanced inputs at the RF and IF ports and
internal LO buffer. The down converted IF signal is passed through a 3-pole crystal filter, FL501, and
an IF amplifier, Q503, which drives the input of the Analog to Digital Converter IC, U601.

3.1.2.3 UHF2 Front-End

From the attenuator, U1149, a UHF2 signal is routed to the first pre-selector filter followed by a Low
Noise Amplifier (LNA) and a second pre-selector filter. Both filters are discrete and tunable designs
and are used to band limit the incoming energy and suppress known spurious responses such as
Image spur. The LNA active device is an NPN transistor (U2032) with active bias provided by
transistor pair Q2022. The output of the second pre-selector filter is applied to a discrete Low Pass
Filter (LPF). The output of the LPF is applied to the RF port of the Mixer IC via a balun transformer,
T503. The Mixer IC, U506, is driven by a Local Oscillator (LO) signal generated by the Trident
synthesizer IC, U702, at the LO port to down-convert the RF signal to a 109.65 MHz intermediate
frequency (IF). It is a passive, high linearity design with balanced inputs at the RF and IF ports and
internal LO buffer. The down converted IF signal is passed through a 3-pole crystal filter, FL501, and
an IF amplifier, Q503, which drives the input of the Analog to Digital Converter IC, U601.

3-10 Theory of Operation: Transceiver Board

3.1.2.4 700/800 Front-End

From the attenuator, U1149, a 700 MHz or 800 MHz band signal is routed to an SPST band select
switch, U402, which selects the 700 or the 800 band signal and routes it to the appropriate first pre­selector filter, FL401. A second band select switch, U404, selects the output of the appropriate filter
and applies it to an LNA followed by a similar pre-selector filter/ band-select switch circuit. The signal
is then routed to second LNA, U407, whose output is applied to a discrete image filter. Both
preselector filters are Surface Acoustic Wave designs (EPCOS B4232) used to band limit the
received energy and suppress known spurious responses such as Image and the ½ IF spur. The
output of the discrete image filter is applied to the RF port of the Mixer IC, U506, via a balun
transformer, T503. The Mixer IC is driven by an LO signal generated by the Trident synthesizer IC,
U702, and applied to the LO port to down-convert the RF signal to a 109.65 MHz intermediate
frequency (IF). The IF signal is passed through a crystal filter, FL501, and an IF amplifier, Q503,
which drive the input of the Analog to Digital Converter IC, U601.

3.1.2.5 Analog To Digital Converter

The ADC used in APX/ SRX is the AD9864 IC, U601, from Analog Devices. The IC front end down
converts the first IF to a second IF, a 2.25 MHz signal, by mixing a 107.4 MHz LO signal generated
by an integrated synthesizer and external VCO with active device U602 and resonator L604. The
second IF is sampled at 18 MHz, a signal generated by an integrated clock synthesizer and VCO
device with external resonator L605.

The sampled signal is decimated by a factor of 900 to 20 kHz and converted to SSI format at the
ADC's output. The Serial Synchronous Interface (SSI) serial data waveform is composed of a 16 bit
in-phase word (I) followed by a 16 bit Quadrature word (Q). A 20 kHz Frame Synch and 1.2MHz
clock waveform are used to synchronize the SSI IQ data transfer to the Digital Signal Processor IC
(OMAP) for post-processing and demodulation. The clock frequency is adjustable and is selected
automatically by software to prevent self quieting.

3.1.3 Transmitter

The transmitter takes modulated RF from the FGU and amplifies it to the rated output power to
produce the modulated carrier at the antenna.

NOTE: Refer to Table 8-1, “List of Transceiver Schematics and Board Overlays,” on page 8-1 for a

listing of transmitter-related schematics that will aid in the following discussion.

The transmitter (Figure 3-8 on page 3-11) for the VHF radio consists of one LDMOS high power
transistor for the VHF band. The same topology applied for the 7/800 radio
(Figure 3-10 on page 3-12) where one LDMOS high power transistor is used for the 7/800 MHz
band. Similarly for UHF1 and UHF2 radios, one LDMOS transistor is used to cater for the UHF1/
UHF2 band which is depicted by Figure 3-9 on page 3-11. The high power transistor is driven by an
RF driver IC that receives its input signal from the voltage controlled oscillator. Transmitter power is
controlled by a discrete power control circuit that senses the output of a directional coupler and
adjusts PA control voltage to maintain the correct power level. The TX signals pass through their
respective harmonic filters, a TX/RX switch, and embedded directional coupler, a RF switch and then
the antenna. The SP2T switch just before the antenna does not exist on the VHF radio.

The UHF1 SRX 2200 is available with a low power setting that limits the transmit power to 0.25 watt.
The rest of the APX 5000/ APX 6000 radios and the SRX 2200 VHF radio are able to be limited to
1 watt minimum output power.

Theory of Operation: Transceiver Board 3-11

Log Amp Power Detector

TX Buffer Amp

RF Switch Matrix

TX Buffer Amp

TX Driver Amplifier

TX VCO

Module

RX VCO

Module

Figure 3-8. Transmitter Block Diagram (VHF)

TX Driver Amplifier

Transmitter FET VHF

Loop Filter

Transmitter FET UHF

SP3T RF Switch

Harmonic LP Filter

Trident IC

Synthesizer

SP3T RF Switch

Harmonic LP Filter

Digital RF Attenuator

Directional
Coupler

To RX

Reverse Power Detection

Ref. Oscillator

S

TX SSI from VOCON

Log Amp Power Detector

Digital RF Attenuator

Directional
Coupler

Antenna Connector

SP2T

To Antenna

To RMT Port

TX VCO

Module

RX VCO

Module

RF Switch Matrix

Figure 3-9. Transmitter Block Diagram (UHF1 and UHF2)

Loop Filter

Trident IC

Synthesizer

To RX

Reverse Power Detection

Ref. Oscillator

S

TX SSI from VOCON

3-12 Theory of Operation: Transceiver Board

Log Amp Power Detector

TX Buffer Amp

RF Switch Matrix

TX Driver Amplifier

TX VCO

Module

RX VCO

Module

Figure 3-10. Transmitter Block Diagram (7/800)

Transmitter FET 7/800

Loop Filter

SP3T RF Switch

Harmonic LP Filter

Trident IC

Synthesizer

Digital RF Attenuator

Directional
Coupler

To RX

Reverse Power Detection

Ref. Oscillator

S

TX SSI from VOCON

SP2T

To Antenna

To RMT Port

Theory of Operation: Transceiver Board 3-13

3.1.3.1 Driver Amplifier

The driver amplifier IC (VHF – U902, UHF1 – U1602, UHF2 – U1500 and 7/800 – U1002) contains
one LDMOS FET amplifier stages and an internal resistor bias networks. Pin 16 is the RF input.
Modulated RF from the FGU, at a level of +3 dBm ±2 dB, is coupled through a blocking capacitor to
the gate of FET-1. An LC inter-stage matching network connects the first stage output VD1 to the
second stage input G2. The RF output from the drain of FET-2 is pin 6 (RFOUT1). Gain control is
provided by a voltage applied to pin 1 (VCNTRL). Typical output power is about +27 dBm (500 mW)
with VCNTRL at 5.5 V.

VHF: L901 and C904 are the components for the inter-stage matching network. Components C907,
C910, L904, C913, C914, L905 and C916 provide the match to the final device Q901. C907 also
serves as a DC block.

UHF1: L1601 and C1604 is the inter-stage matching network of the driver amplifier IC, C1607,
C1610, L1604, C1613, C1614, L1605 and C1616 serve as matching circuit of the driver IC to the
final device of Q1601. Capacitor C1607 also works as DC block to the circuit.

UHF2: L1501 and C1504 is the inter-stage matching network of the driver amplifier IC. C1508,
C1509, C1510, C1511, L1502, L1503, and L1504 serve as matching circuit of the driver IC to the
final device of Q1500. Capacitor C1510 also works as DC block to the circuit.

700–800 MHz: L1002, C1002 and C1004 are the inter-stage matching network. Components C1013
and C1023 match the output impedance to the input of the final device (Q1001); capacitor C1013
also serves as the DC block.

3.1.3.2 Power Amplifier Transistor

The power amplifier transistors, Q901, Q1013, Q1500 and Q1601 are LDMOS FETs housed in a
high-power, surface-mount, ring package. To prevent thermal damage, it is essential that the heat
sink of the power module be held in place against the radio chassis using the RF board screw. All
FETs are matched using a lowpass topology. Drain bias is applied through L906 for the VHF, L1606
for UHF1, L1505 for UHF2 and L1007 for the 7/800 MHz. Gain is dynamically controlled by adjusting
the gate bias. The gate is insulated from the drain and source so that gate bias current is essentially
zero

VHF: The output match consists of elements L907, C920, C921, L908, C922, L909, C924, L910,
C923 and C928. Gate bias is applied through R903, R904, R905, C915 and C917.

UHF1: C1620, C1621, C1622, L1609, C1624, L1610, C1623, C1628 and C1625 are the elements of
the output matching network apart from a transmission-line structure. The Gate biasing is applied
through a biasing network consists of R1603, R1604, R1605, C1615 and C1617.

UHF2: C1516, C1517, C1518, C1520, C1521, C1527, and L1507 are the elements of the output
matching network apart from a transmission-line structure. The Gate biasing is applied through a
biasing network consists of R1502, R1503, R1504 and C1522.

700–800 MHz: The input impedance-matching network is C1013 and C1023. A transmission-line
structure and C1019, C1020, L009 and C1021 form the output-matching network. Gate bias applied
through R1003, R1004, C1015 and R1005.

3.1.3.3 Directional Coupler

A directional coupler senses the transmitter forward and reverse power as control signals in the
transmitter's automatic level control (ALC) loop. Isolated ports are terminated with external resistors.

VHF/UHF1/UHF2/700–800 MHz: The directional coupler consists of three embedded transmission
lines.

3-14 Theory of Operation: Transceiver Board

3.1.3.4 Harmonic Filter

The harmonic filter is a high-power, low-loss, low-pass filter. Its purpose is to suppress transmitter
harmonics. The filter also improves receiver out-of-band rejection. The appropriate shield over the
filter must be in place to achieve the required stop band rejection.

VHF: The harmonic filter uses discrete components. The pass band is up to 190 MHz, and the stop
band is above 260 MHz.

UHF1: The harmonic filter applies discrete components as the circuit line up. The pass band is up to
470 MHz while the stop band is above 740 MHz.

UHF2: The harmonic filter applies discrete components as the circuit line up. The pass band is up to
520 MHz while the stop band is above 1000 MHz.

700–800 MHz: The harmonic filter uses both discrete components and transmission lines. The pass
band is up to 870 MHz, and the stop band is above 1500 MHz.

3.1.3.5 Antenna Switch

NOTE: Refer to Table 8-1, “List of Transceiver Schematics and Board Overlays,” on page 8-1 for a

listing of schematics that will aid in the following discussion.

The antenna switch consists of a single pole triple-throw IC designated U1102. The IC is connected
to the output of the two harmonic filters and it is connected to the receiver. The output of the switch is
connected to the directional coupled via the inductor L1108. Control lines V1_V2 and V3 control the
routing of the signal paths. During Rx operation, V3 is set high and V1_V2 is low. During Tx
operation, V3 is set low and V1_V2 is high. This is the same case for VHF, UHF1, UHF2 and 7/800
radios.

There is a second IC designated U1111 at the output of the radio. This switch routes RF power to the
main antenna or to the accessory GCAII connector on the side of the radio. This switch is controlled
by control line DIG_CNTRL_RMT which connects to pin 13 of the IC. When this signal level is high,
the power is routed to the antenna and when it is low the power is routed to the accessory connector.

NOTE: This switch does not exist on VHF radios.

3.1.3.6 Reverse Power Protection

The radio, while in receive mode is constantly monitoring the input power from the antenna. This
power is sensed by the directional coupler and channeled into an RF detector U1106. The matching
network between the coupler and the detector consists of R1107, L1102, C1105 and C1107. Once
the input RF level exceeds a certain limit the detector trips a logic circuit then enables attenuation to
protect the RF front end. This serves as to protect the front end from large signal damage.

3.1.3.7 Transmitter Power Control

In TX mode, the transmitter Automatic Level Control (ALC) section enables the transmitter and
controls TX power in all modes. Power control is based on a unique dual control loop approach
which utilizes voltage control in one loop and current control in the other. The voltage control loop is
normally used in all transmit modes. The only time the current control loop controls TX power is
during the end of a TX slot in TDMA (Phase 2) mode in the event transmitter saturation is detected.
Several other functions included in the TX ALC section of the radio are RX/TX switching, thermal
cutback of power, current cutback of power, and reverse power detection with a means to disable the
receiver in the event of high reverse power at the antenna port.

Theory of Operation: Transceiver Board 3-15

3.1.3.7.1 Voltage Control Mode

The heart of the voltage control loop is a logarithmic amplifier based power control IC, U1105. Quad
DAC, U1125, receives the power tuning values via the SPI bus and converts them into a voltage at
“VOUTB.” Resistors, R1121 and R1122, form a voltage divider to set the full-scale value of the DAC,
in this case approximately 1.4V. This power set voltage is then fed to the power control IC through
the current cutback op amp, U1130, and then into a lesser-of-two voltage decision circuit, consisting
of U1126 and U1127. This circuit, used exclusively in voltage control mode, provides the important
function of combining the MAKO ramp output with the DAC power set voltage to permit power
leveling since the MAKO DAC max amplitude cannot be controlled during TDMA mode. In all other
TX modes, the MAKO output is a fixed voltage, approximately 1.5V, which is always higher than the
DAC control voltage. The lesser-of-two circuit will then select the smaller input, the set voltage from
U1125, resulting in immediate TX turn on in analog or ASTRO mode. IN TDMA mode, the MAKO line
is a piecewise linear ramp whose timing is in accordance with Phase 2 requirements. At t = 0, the
ramp line is smaller than the TX set voltage so the MAKO ramp will control the TX power level,
resulting in a slower ramping up of the TX power. This continues until the MAKO ramp output
reaches the level of the power tuning DAC (which is always lower than the MAKO ramp maximum)
which causes control of TX power to be turned over to the power tuning DAC.

The output of the selector circuit passes through a 2nd order low pass filter (U1142) and then to the
log amp, U1105. The low pass filter performs the dual function of improving transient ACPR by
transforming a linear ramp with corners into a smooth second order waveform and by acting as a
reconstruction filter for the DAC. The log amp converts RF power fed back from the TX PA into a
current which is summed with the current from the conversion of the setpoint voltage from DAC
U1125. Any imbalance between the RF input level and the level corresponding to the setpoint
voltage is corrected at the VAPC output of the log amp which in turn drives the control voltage input
of the RFPA. The setpoint voltage effectively nulls the error in the loop caused by changes in the RF
level fed back to the log amp. RF from the RFPA is coupled through a directional coupler embedded
in the PC board and passed through a LC equalizer and then to digital attenuator, U1112, which is
used to implement thermal cutback in the event of an over-temperature condition.

Current protection and limiting in voltage control mode is provided by cascaded difference amplifiers,
U1129 and U1130. A fixed threshold is provided by voltage divider, R1169 and R1170. SPDT switch,
U1144, changes the current limit threshold based on the type of battery present. This threshold is
based on the conversion characteristic of the current shunt monitor circuit of U1101. The output of
the current shunt monitor is fed to the first stage of the difference amplifier. The setpoint voltage for
the log amp is fed through the second stage of the difference amplifier. When the current shunt
monitor voltage exceeds the fixed threshold, the first stage produces an output greater than 0V.
Once the output of the first stage (U1129) is greater than zero, this value is subtracted from the
setpoint voltage to the log amp in the second stage (U1130), resulting in a progressive cutback of
power in the event PA current continues to climb above the threshold.

3.1.3.7.2 Thermal Cutback

Thermal cutback works only in voltage control mode, which is the primary mode of TX power control.
Temperature is sensed by IC U1103 and is located next to both RFPA finals. Comparators, U1113
and U1114, establish two temperature trip points. The combined logic of the comparators and logic
gate, U1121, together with the truth table of the digital attenuator IC, U1112, determine the amount of
attenuation of the RF feedback to the log amp. Rated TX power is achieved with the attenuator at its
maximum attenuation of 7 dB. The first temperature threshold will subtract 3 dB of TX power and the
next (highest) trip point an additional 3 dB for 6 dB total.

3-16 Theory of Operation: Transceiver Board

3.1.3.7.3 Current Control Mode

In TDMA mode, excessive transient adjacent channel splatter caused by the RFPA, when it is under
a greater degree of compression than is expected at nominal supply voltage, is mitigated through a
system of saturation detection and switching of the TX power control mode from the voltage control
loop to the current control loop. Comparator U1131 compares the log amp output in voltage control
mode to a threshold voltage from DAC “C”, which sets the threshold for handover to current control
mode and establishes the upper supply rail for the output of current loop integrator, U1104. This
threshold is tuned in the factory to correspond to transmitter rated power which means that the
threshold for handover occurs at a level corresponding to rated power minus 6% (9% for VHF radios)
which is set by divider R1162 and R1163. When PA saturation exceeds this threshold and the MAKO
T/R control signal (DIG_GPIO49) and DIG_DMCS combine logically to signal the end of the data
portion of the TX slot, D-flip flop U1132 latches which in turn switches (via U1133 SPDT switch) the
output of the current loop integrator, U1104, as a control voltage to the PA of the radio.

Integrator, U1104, acts as a PI (Proportional Integral) controller in current mode. Current feedback
from the PA is obtained through current shunt resistor R1103 and sent to the current shunt monitor/
current to voltage converter, U1101. U1101 has a known gain characteristic for the current-to-voltage
conversion. The MAKO ramp is passed through a RC low pass filter for smoothing and on to the
current control integrator where it is proportioned with the voltage output of the current shunt monitor.
The integrator supply voltage comes from DAC “C” of the Quad DAC, U1125. By way of tuning the
DAC “C” value to match TX rated (tuned) power, this approach fixes the upper limit of the control
voltage in current control mode to correspond to the tuned power level, further reducing excess
adjacent channel splatter.

3.1.3.7.4 PA Offset, Control Voltage Gain Scaling

An offset voltage is applied to the control voltage at a summing junction made up of R1174 and
R1154 as a means of further improving transient adjacent channel splatter in the VHF band by
pre-biasing the PA. The output of DAC “A” is summed with either the output of the log amp or the
integrator through R1174.

The value for DAC “A” has been established and fixed in the firmware. This offset value is padded to
the control voltage and is sent to a non-inverting, gain-scaling amplifier, U901 (VHF) or U1601
(UHF1) or U1501 (UHF2) or U1001 (7/800 MHz) and then to the PA driver and final.

3.1.4 Frequency Generation Unit (FGU)

The frequency-generation function is performed by several ICs; multiple voltage-controlled
oscillators (VCOs); and associated circuitry. The reference oscillator provides a frequency standard
to the Trident IC, which controls the VCOs via the port expander. There are also buffers that amplify
the VCO signal to the correct level for the next stage. Figure 3-11 below shows a block diagram of
the FGU Section.

VHF: Two VCOs are employed: one to generate the first RX LO and the other to generate the
transmit injection signals.

UHF1: Two VCOs generate the first Rx LO and two VCOs generate the transmit-injection signals.

UHF2: Two VCOs generate the first Rx LO and two VCOs generate the transmit-injection signals.

700–800 MHz: Two VCOs generate the first RX LO and three VCOs generate the transmit-injection

signals.

NOTE: Refer to Table 8-1, “List of Transceiver Schematics and Board Overlays,” on page 8-1 for a

listing of FGU-related schematics that will aid in the following discussion.

Theory of Operation: Transceiver Board 3-17

VHF DIVIDE-BY-2

ND

HARMONIC FILTER

2

16.8MHz

16.8MHz

BUFFER

TRIDENT IC

2

LOOP

FILTER

VHF TX

TX

BUFFER

TX LO

16.8MHz

LOGIC

EXPANDER

16.8MHz

BUFFER

TRIDENT IC

LOGIC

EXPANDER

PRE

BUFFER

PRESCALAR

BUFFER

VHF RX

Figure 3-11. Synthesizer Block Diagram (VHF)

LOOP

FILTER

PRE

BUFFER

PRESCALAR

BUFFER

UHF TX

UHF RX

RX LO

TX

BUFFER

TX LO

RX LO

Figure 3-12. Synthesizer Block Diagram (UHF1 and UHF2)

3-18 Theory of Operation: Transceiver Board

16.8MHz

16.8MHz

BUFFER

TRIDENT IC

LOOP

FILTER

TX

BUFFER

TX LO

LOGIC

EXPANDER

Figure 3-13. Synthesizer Block Diagram (7/800)

3.1.4.1 Reference Oscillator Y701

The radio's frequency stability and accuracy is derived from the Voltage-Controlled Temperature­Compensated Crystal Oscillator (VCTCXO), Y701. This 16.8 MHz oscillator is controlled by the
voltage from the AUX_DAC pin of the Trident IC, U702, that can be programmed through a serial
peripheral interface (SPI). The oscillator output at pin 3 is coupled through capacitor C736 to the
Trident IC reference oscillator input. This reference is then passed through an internal buffer and is
then coupled to the external BJT buffer (comprised of U746 and supporting circuitry) via C739.
These buffers provide isolation for the 16.8 MHz output to the VOCON board and ABACUS IC.
Components L753 and C754 form a low-pass filter to reduce the harmonics of the 16.8 MHz.

3.1.4.2 Trident IC U702

The Trident IC, U702, is a multiple protocol, multiple band transceiver Motorola-proprietary, CMOS
IC, with built-in dual-port modulation. The Trident IC incorporates frequency division and comparison
circuitry to keep the VCO signals stable. The Trident IC is controlled by the MCU through a serial
bus. All of the synthesizer circuitry is enclosed in rigid metal cans on the transceiver board to reduce
interference effects. Separate power supply inputs are used for the various functional blocks on the
IC. Inductors L727, L733, L735, L738 and L741 provide isolation between the IC and the different
power supplies. Host control is through a four-wire, smart SPI interface (pins D8, D9, D10 and C11).
Some of the Trident IC functions include frequency synthesis, reference clock generation,
modulation control, voltage multiplication and filtering, near-integer spurious reduction, RF
divide-by-two and auxiliary SPI.

PRESCALAR

BUFFER

PRE

BUFFER

7/800 TX

7/800 RX

RX LO

3.1.4.3 Synthesizer

Frequency synthesis functions include a low band and high band mode prescaler, a phase detector,
a programmable loop divider and its control logic, a charge pump, and a lock detector output.
Fractional-N synthesizer principles of operation are covered in detail in the manufacturers' literature.
No similar discussion will be attempted here.

3.1.4.4 Clocks

U702, pin K5 (REF_IN), is the 16.8 MHz reference oscillator input from the VCTCXO (Y701).

Theory of Operation: Transceiver Board 3-19

3.1.4.5 Modulation

To support many voice, data, and signaling protocols, APX 5000/APX 6000/APX 6000XE/SRX 2200
radios must modulate the transmitter carrier frequency over a wide audio frequency range, from less
than 10 Hz up to more than 6 kHz. The Trident IC supports audio frequencies down to zero Hz by
using dual-port modulation. The digital audio signal at pin F11 (TXD) is transferred to the Trident
baseband circuitry via the TX Serial Synchronous Interface (SSI) bus. The data is then internally
divided into high and low-frequency components, which modify both the synthesizer dividers and the
external VCOs through a signal on HP_MOD_OUT (pin L9). The DSP scaling is adjusted to achieve
a flat modulation frequency response during the transmitter modulation balance calibration.

3.1.4.6 Voltage Multiplier and Superfilter

Pins H10 (VMULT2) and H11 (VMULT1) together with diode arrays D722 and D723 and their
associated capacitors form the voltage multiplier. The voltage multiplier generates 10.625 Vdc to
supply the phase detector and charge-pump output stage at pin F1 (MN_CP_VCC).

The superfilter is an active filter that provides a low-noise supply for the VCOs. The input is a
regulated 5 Vdc from DC_LIN_5V at pin K4 (SF_SPLY). The output is a superfiltered voltage at pin
J5 (SF_OUT).

3.1.4.7 Loop Filter

The components connected to pins G3 (MN_CP) and G2 (MN_ADAPT_CP) form a 4th-order, RC
low-pass filter. Current from the charge-pump output, MN_CP, is transformed to voltage
ANA_VTUNE, which modulates the VCOs. Extra current is supplied by MN_ADAPT_CP for rapid
phase-lock acquisition during frequency changes. The lock detector output pin B4
(TEST1_LCKDET) goes to a logic “1” to indicate when the phase-lock loop is in lock.

3-20 Theory of Operation: Transceiver Board

3.1.4.8 Port Expander

U703 is a port expander that is controlled by the auxiliary SPI of the Trident IC; pins A7
(ASPI_DATA), B7 (ASPI_CLK) and C6 (ACE1_GPO7). Data sent on the main SPI bus with a specific
header, tells the Trident IC to pass the data (via the auxiliary SPI lines) onto the port expander SPI
lines, pins 32 (SCLK), 33 (DIN) and 34 (CS). The port expander then translates this auxiliary SPI
data and turns on and off the select lines for the various VCOs, switches (that select the correct RF
path for either VHF, UHF Range 1 or 7/800) and other logic external to the FGU. Table 3-3 below
shows the logic settings for the port expander for the various bands.

Table 3-3. Port Expander Pin Settings

PIN NO.1234567 8 9 10 12 13 14 15

VHF TX

LOGIC 000000H H000000

PIN NO. 16 17 18 19 21 22 23 24 25 26 27 28 29 30

LOGIC 0 H00 0H H H0H0000

VHF RX

700 TX

700 RX

7/800 TX

800 TX

PIN NO.

LOGIC H H H H0000000000

PIN NO.161718192122 23 24 25 26 27 28 29 30

LOGIC 00000H00000000

PIN NO. 1 2 3 4

LOGIC 0 0 0 0 H000H00000

PIN NO.161718192122 23 24 25 26 27 28 29 30

LOGIC 00000H0000H H00

PIN NO. 1 2

LOGIC 0 0 H0H0000H0000

PIN NO.161718192122 23 24 25 26 27 28 29 30

LOGIC 00000H0000000H

PIN NO.

LOGIC H0 00 0H00000000

PIN NO.161718192122 23 24 25 26 27 28 29 30

LOGIC 00000H0000H H00

PIN NO. 1 2 3 4

LOGIC 0 0 0 0 H0000H0000

PIN NO.161718192122 23 24 25 26 27 28 29 30

LOGIC 00000H0000H H00

1 2 3 4 5 6 7 8 9 1012131415

56789 1012131415

345678910 12 13 14 15

1234567891012131415

5678910 12 13 14 15

800 RX

PIN NO. 1 2

LOGIC 0 0 H0H000H00000

PIN NO.161718192122 23 24 25 26 27 28 29 30

LOGIC 00000H00H0000H

3456789 1012131415

Theory of Operation: Transceiver Board 3-21

Table 3-3. Port Expander Pin Settings (Continued)

UHF

UHF R1 TX

(380–445)

PIN NO.12345678910

LOGIC 0000000000H00 0

PIN NO. 16 17 18 19 21 22 23 24 25 26 27 28 29 30

LOGIC 0 H000H H H0 0H0H0

12 13 14 15

UHF R1 TX

(445–470)

UHF R1 RX

(380–449.65)

UHF R1 RX

(449.65–470)

UHF R2 TX

(450–520)

PIN NO.1234567891012

LOGIC 00000000000H00

PIN NO. 16 17 18 19 21 22 23 24 25 26 27 28 29 30

LOGIC 0 H000H H H0 0H0H0

PIN NO. 1

LOGIC 0 H H0 00H H000000

PIN NO.161718192122 23 24 25 26 27 28 29 30

LOGIC 0 0 0 0 0 H H0000000

PIN NO. 1

LOGIC 0 H H0 00H000000H

PIN NO.161718192122 23 24 25 26 27 28 29 30

LOGIC 0 0 0 0 0 H H0000000

PIN NO.1234567891012

LOGIC 00000000000

PIN NO. 16 17 18 19 21 22 23 24 25 26 27 28 29 30

LOGIC 0 H000H H H0 0H0H0

2 34567 8 9 10 12 13 14 15

2 34567 8 9 1012131415

13 14 15

13 14 15

H00

PIN NO. 1

UHF R2 RX

(450–520)

LOGIC 0 H H0 00H000000H

PIN NO.161718192122 23 24 25 26 27 28 29 30

LOGIC 0 0 0 0 0 H H0000000

2 34567 8 9 1012131415

3-22 Theory of Operation: Transceiver Board

3.1.4.9 Buffers and VCOs

Q774 and surrounding circuitry is the prescalar buffer that takes the output of the VCOs and feeds
the prescalar input to the Trident IC, pin G1 (M_PRSC).

Q713 and surrounding circuitry is a buffer that provides the correct drive level to the receiver section
(via the transmission line TL_RX_LO) and to the input to the TX buffer (Q842 and surrounding
circuitry). Q712 and surrounding circuitry provide the bias to the buffer. The buffer formed by Q713
and its associated circuitry is called a “pre-buffer” at this stage.

R712, R713 and R714 help provide some extra isolation to the receiver.

Q842 and surrounding circuitry is the transmit injection buffer. The transmit injection buffer provide
the correct drive level to the transmitter section (via the transmission line TL_TX_LO). Q703 and
surrounding circuitry provide the bias to the transmit injection buffer.

VHF: The TX and RX VCOs used for the VHF band are contained in Y704 and Y707 respectively. To
select the VHF TX VCO, pin 3 (SEL1) must be at a high logic level and pin 5 (SEL2) at a low logic
level, on Y704. The VHF TX output of Y704, pin 1 (POUT) goes to pin 4 (RF1) of U709. The output of
U709, pin 1 (RFC), is then split into two signals. One to the prescalar buffer input and the other to the
pre-buffer. The output of the prebuffer is then fed to pin 1 (RFC) of U710. The VHF TX signal then
goes to the divide-by-two circuitry in the Trident IC, pin J2 (ESC_IN). Resistors R703, R704 and
capacitors C705, C748 and C747 provide the correct bias for the divide-by-two output. The output of
the divide-by-two circuitry, pin K1 (ESCD2_OUT) then goes through a 'second harmonic filter'
(comprised of C800, C801, C803 and L802) and attenuator (comprised of R709, R710 and R711).
The output of the attenuator is then fed to the transmit buffer (Q842 and surrounding circuitry). The
output of the transmit injection buffer, then goes to the transmit section via the TL_TX_LO
transmission line.

To select the VHF RX VCO, pin 3 (SEL1) must be at a high logic level and pin 5 (SEL2) at a low logic
level, on Y707. The output of the VHF RX VCO, pin 1 (POUT) of Y707 goes to pin 8 (RF3) of U709.
The output of U709, pin 1 (RFC) is split into two signals, one to the prescalar buffer (Q774) and the
other to the pre-buffer. The output of the pre-buffer is then fed to pin 1 (RFC) of U710. The output of
U710, pin 5 (RF2) then goes to the attenuator (comprised of R712, R713 and R714) and then fed to
the receiver section via the TL_RX_LO transmission line.

UHF1: The TX and RX VCOs used for UHF1 are contained in Y705 and Y704. To select the UHF RX
VCO from (380–450 MHz), pin 3 (SEL1) must be at a high logic level and pin 5 (SEL 2) at a low logic
level, on Y704. To select UHF RX VCO (450–470 MHz), pin 3 (SEL1) must be at a low logic level
and pin 5 (SEL 2) at a high logic level, on Y704. The UHF RX VCO output of Y704, pin 1 (POUT), is
then fed to pin 4 (RF1) of switch U709. The output of U709, pin 1 (RFC), is then split into two signals.
One to the prescalar buffer input and the other to the pre-buffer. The output of the prebuffer is then
fed to pin 1 (RFC) of U710. The output of U710, pin 5 (RF2) then goes to the attenuator (comprised
of R712, R713 and R714) and then fed to the receiver section via the TL_RX_LO transmission line.

To select the UHF TX VCO (380–445 MHz), pin 3 (SEL1) must be at a high logic level and pin 5
(SEL2) at a low logic level, on Y705. To select the UHF TX VCO (445–470 MHz), pin 3 (SEL1) must
be at a low logic level and pin 5 (SEL2) at a high logic level, on Y705. The UHF TX VCO output of
Y705, pin 1 (POUT), is then fed to pin 5 (RF2) of switch U709. The output of U709, pin 1 (RFC), is
then split into two signals. One to the prescalar buffer input and the other to the pre-buffer. The
output of the prebuffer is then fed to pin 1 (RFC) of U710. The output of U710, pin 4 (RF1) then goes
to the transmit injection buffer (comprised of Q842 and surrounding circuitry).

Theory of Operation: Transceiver Board 3-23

UHF2: The TX and RX VCOs used for UHF2 are contained in Y705 and Y704. To select UHF RX

VCO (450–520 MHz), pin 3 (SEL1) must be at a low logic level and pin 5 (SEL 2) at a high logic level,
on Y704. The UHF RX VCO output of Y704, pin 1 (POUT), is then fed to pin 4 (RF1) of switch U709.
The output of U709, pin 1 (RFC), is then split into two signals. One to the prescalar buffer input and
the other to the pre-buffer. The output of the prebuffer is then fed to pin 1 (RFC) of U710. The output
of U710, pin 5 (RF2) then goes to the attenuator (comprised of R712, R713 and R714) and then fed
to the receiver section via the TL_RX_LO transmission line.

To select the UHF TX VCO (450–520 MHz), pin 3 (SEL1) must be at a low logic level and pin 5
(SEL2) at a high logic level, on Y705. The UHF TX VCO output of Y705, pin 1 (POUT), is then fed to
pin 5 (RF2) of switch U709. The output of U709, pin 1 (RFC), is then split into two signals. One to the
prescalar buffer input and the other to the pre-buffer. The output of the prebuffer is then fed to pin 1
(RFC) of U710. The output of U710, pin 4 (RF1) then goes to the transmit injection buffer (comprised
of Q842 and surrounding circuitry).

700–800 MHz: The TX and RX VCOs used for 700–800 MHz are contained in Y706 and Y707. To
select the 700 RX VCO, pin 5 (SEL2) must be at a high logic level and pin 3 (SEL1) at a low logic
level, on Y706. The 700 RX VCO output of Y706, pin 1 (POUT), is then fed to pin 5 (RF2) of switch
U709. The output of U709, pin 1 (RFC), is then split into two signals. One to the prescalar buffer
input and the other to the pre-buffer. The output of the prebuffer is then fed to pin 1 (RFC) of U710.
The output of U710, pin 5 (RF2) then goes to the attenuator (comprised of R712, R713 and R714)
and then fed to the receiver section via the TL_RX_LO transmission line.

To select the 800 RX VCO, pin 3 (SEL1) must be at a high logic level and pin 5 (SEL2) at a low logic
level, on Y706. The 800 RX VCO output of Y706, pin 1 (POUT), is then fed to pin 5 (RF2) of switch
U709. The output of U709, pin 1 (RFC), is then split into two signals. One to the prescalar buffer
input and the other to the pre-buffer. The output of the prebuffer is then fed to pin 1 (RFC) of U710.
The output of U710 (RF2) then goes to the attenuator (comprised of R712, R713 and R714) and
then fed to the receiver section via the TL_RX_LO transmission line.

To select the 700 TX VCO, pin 3 (SEL1) must be at a high logic level and pin 5 (SEL2) at a low logic
level, on Y706. The 700 TX VCO output of Y706, pin 1 (POUT), is then fed to pin 5 (RF2) of switch
U709. The output of U709, pin 1 (RFC), is then split into two signals. One to the prescalar buffer
input and the other to the pre-buffer. The output of the prebuffer is then fed to pin 1 (RFC) of U710.
The output of U710, pin 4 (RF1) then goes to the transmit injection buffer (comprised of Q842 and
surrounding circuitry). The output of the transmit buffer, then goes to the transmit section via the
TL_TX_LO line.

To select the 800 TX VCO, pin 5 (SEL2) must be at a high logic level and pin 3 (SEL1) at a low logic
level, on Y706. The 800 TX VCO output of Y706, pin 1 (POUT), is then fed to pin 5 (RF2) of switch
U709. The output of U709, pin 1 (RFC), is then split into two signals. One to the prescalar buffer
input and the other to the pre-buffer. The output of the prebuffer is then fed to pin 1 (RFC) of U710.
The output of U710, pin 4 (RF1) then goes then goes to the transmit injection buffer (comprised of
Q842 and surrounding circuitry). The output of the transmit injection buffer, then goes to the transmit
section via the TL_TX_LO line.

To select the 7/800 TX VCO, pin 5 (SEL2) must be at a high logic level and pin 3 (SEL1) at a low
logic level, on Y707. The 7/800 talk around VCO output of Y707, pin 1 (POUT), is then fed to pin 8
(RF3) of switch U709. The output of U709, pin 1 (RFC), is then split into two signals. One to the
prescalar buffer input and the other to the pre-buffer. The output of the prebuffer is then fed to pin 1
(RFC) of U710. The output of U710, pin 4 (RF1) then goes then goes to the transmit injection buffer
(comprised of Q842 and surrounding circuitry). The output of the transmit injection buffer, then goes
to the transmit section via the TL_TX_LO line

3-24 Theory of Operation: Controller

3.2 Controller

3.2.1 Controller Overview

This section provides a detailed circuit description of the APX 5000/APX 6000/APX 6000XE/
SRX 2000 controller design. The controller design consists of the following board and flexes:

Printed Circuit Boards

• VOCON Board

• Expansion Board

• GCAI Connector Board

Flexes

• Control Top (Top Display, Buttons, Knobs)

• Front Chassis Display

• Front Chassis Keypad

• GCAI (Global Core Accessory Interface)

• Side Controls

• Audio Side Microphone / Speaker / Bluetooth Antenna

• Data Side Microphone

The controller interconnection diagram (Figure 3-14) shows the various physical components of the
design, along with how they are all connected. It also shows the key distinguishes between a flex
connection and a board-to-board connection. A brief description of each of the components is
provided below.

KEY

= Flex

= Board to Board

Keypad

Front

Display

Top Display

VOCON

Board

Top

Controls

Expansion

Board

Side

Controls

Audioside
Speaker
& Mic;
BT Antenna

Figure 3-14. Controller Interconnection Diagram

Data

Mic

GCAI

RF Board

Theory of Operation: Controller 3-25

3.2.1.1 Main Controller Components and Connections

3.2.1.1.1 VOCON Board

The VOCON Board contains the OMAP1710 dual-core processor, FLASH and SDRAM memory,
Audio circuitry (MAKO and CODEC IC's), a Complex Programmable Logic Device (CPLD), and
interfaces to the other components in the controller design.

Connectors

• RF Board – J1001

• Control Top – J2101

• Keypad – J2303

• Front Display – J2304

• Expansion Board – J4001

3.2.1.1.2 Expansion Board

The expansion board contains the Class D internal audio power amplifier with speaker connections,
a Global Positioning System (GPS)/Bluetooth 2.1 combination IC and support circuitry, a 3-axes
digital accelerometer, a Type III encryption IC, a 4GB e-MMC NAND flash, and connector interfaces
to the GCAI board and side controls flex.

Connectors

• VOCON Board – P2001

• Side Controls – J2005

• GCAI – J2004

3.2.1.1.3 GCAI Connector / Board

The GCAI Connector Board contains the side connector pins, and interfaces to the expansion board
through a flex. The board has this flex connector, along with components for ESD protection.

3.2.1.2 Top Controls / Flex

The control top contains the top display, the main RF antenna, and five switches: On/Off & Volume
Knob, a 16-position Channel/Frequency Switch with concentric 2-position switch (for secure enable/
disable operation), a 3 position toggle switch for Zone Selection, and a toggle switch used for
Emergency Calling. The control top also includes an TX/RX LED that is solid amber upon receive,
red on PTT, and blinking amber on secure RX.

3.2.1.2.1 Top Display

The Top Display is a FSTN transflective monochrome liquid crystal display (LCD) with a multi-color
backlight (White, Red, Green, and Amber), which connects to the Control Top Flex (see Section

3.2.1.2: "Top Controls / Flex").

3.2.1.2.2 Front Display

The Front Display is a QVGA transflective color LCD, 130 pixels x 130 pixels with a white backlight.
The display connects through a flex directly to a 22-pin connector located on the VOCON board.

3.2.1.2.3 Keypad / Flex

The keypad flex features a 3 x 2 Menu keypad with 4- way navigation button, and a 3 x 4
alphanumeric keypad. The keypad connects through a flex directly to a 20-pin connector on the
VOCON board.

3-26 Theory of Operation: Controller

3.2.1.2.4 Data-Side Microphone

The data-side microphone is mounted on the front chassis and connects directly to the VOCON
board through a set of pogo pins mounted on the VOCON board.

3.2.1.2.5 Side Controls Flex

The side controls flex contains the PTT, Side Top button, Side Middle button and Side Bottom button.
The flex connects to the Expansion Board through a 10-pin connector.

3.2.1.2.6 Audio-Side Microphone, Speaker, and Bluetooth Antenna

The audio-side microphone and speaker flex assembly connects to the expansion board through
spring clips. The Bluetooth antenna is also part of this flex assembly and also connects to the
expansion board through spring clips.

3.2.1.2.7 RF Board

The RF board connects to the VOCON through a 40-pin board to board connector.

NOTE: See Table 7-2 on page 7-2 for pin assignments

3.2.1.3 Controller Electrical Architecture

An overview of the Controller electrical architecture is shown in Figure 3-15 below. The major
components and electrical interfaces are shown.

e-MMC

Flash Memory

GPS/ BT Chipset

(TINL5500)

FLASH

64 MB

SDRAM

32 MB

Keypad /
Switches

Front

Display

Top Display

SDIO 2

UART 2

EMIFS

EMIFF

Keypad

SoSSI

SPI

32 kHz ClkEMIFS

4.096 MHz Clk

SSI

Audio SSI 1

USB / UART

SPI

GPS/BT Module

ATMEL AVR32)

MACE

Secure

IC

(TINL5500 &

Lighting

Controller

CPLD

I2C

OMAP 1710

Processor

SPI GPIOSSI

RF Board

Figure 3-15. Controller Electrical Overview

SPI

Side
Conn -

GCAI

MAKO IC

Codec

Class D

Audio P A

Radio
Battery

+

-

Access ory

Audio

Microphones

Dual

Speaker

Main

VOCON
Expansion
Module

GCAI

Theory of Operation: Controller 3-27

The functional blocks of the controller are:

• DC Distribution

• Clock Sources

• Processor / Memory

• e-MMC Expandable Memory (expansion board)

•CPLD

• Audio – Internal and External

• MAKO

• User Interfaces

• RF Board Interface

• Type III Encryption Processor (expansion board)

• GPS/Bluetooth Combination IC (expansion board)

3.2.2 DC Distribution

SW_B+ supply comes from a pass FET (Q6501) that is powered by UNSW_B+ (battery voltage).
The FET is activated once the power switch is in its on position. SW_B+ supplies the power for the
entire controller. SW_B+ supplies MAKO and the external regulators. MAKO and the external
regulators then regulate the voltage to the desired level. (See Figure 3-16.)

OMAP's core is supplied by VCC_SW_1.4 (U6507). 1.85 LDO supplies OMAP's IO, FLASH, CPLD,
DDR, and MACE. See 3-4Table 3-4. for DC supplies and sources.

Ext LDO

TPS73601

Ext LDO

LP38693

EXSW_1.4V
800mA M ax

V_SW_3.6

V_EXT_1.85

SW_B+

SW_B+

MAKO

SW_B+

SW_B+

SW1_3.6V

SW1

SW2

LDO2

LDO3

LDO4

LDO6

LDO7

LDO9

LDO10

SW5

VBUS1

VBUS2

LDO8

External SW

TPS62110

External SW

TPS62050

2.23V
400mA M ax

Ext SW

TPS62050

3.6V
800mA M ax

1.875V
120mA M ax

1.55V
150mA M ax

2.775V
100mA M ax

2.775V
50mA M ax

2.775V

100mA M ax

3.0V
50mA M ax

3.3V
70mA M ax

5.0V

500mA M ax

5.0V

500mA M ax

5.0V

25mA M ax

1.5A Max
SW5_5.4V

External S witcher Repl aced
Switcher MAKO’s Switchr 5

Figure 3-16. Controller DC Block Diagram

3-28 Theory of Operation: Controller

Table 3-4. DC Supplies and Sources for Controller

VBUS1

VBUS2

V_1.875

V_SW_3.60

V_SW_1.4

V_EXT_1.85

V_SW_5

V_2.75D

OMAP CORE X

OMAP IO X

DDR X

FLASH X

CPLD X

MACE X

CODEC X X

GPS

LGHT FRNT X X X

V_3.0A

V_2.775

SW_B+

LGHT TOP X X

RF BOARD X X X

MAKO X X X

CLASS D PA X

TOP DSPLY X X

FRNT DSPLY X X

USB SPLY X

16.8 SQR X

Theory of Operation: Controller 3-29

3.2.2.1 DC Distribution Major Components

The controller's DC section is made up of MAKO and external regulators. This section will give an
overview of the schematics and circuitry that makes up the major supplies of the DC architecture.

3.2.2.1.1 MAKO

MAKO (U6501) is a custom power management IC manufactured by Atmel. MAKO controls almost
all of the LDO supplies to the controller. Table 3-5 illustrates all of MAKO's LDO and the supplies that
feed them. Figure 3-16 shows all of MAKO's LDOs their voltage level and components that can be
accessed to verify operation. Figure 3-16 also shows where the battery supply and on off switch can
be accessed. MAKO is also responsible for the timing sequence for the enabling of the regulators
which is discussed further in section 3.1.3.7.1 and section 3.1.3.7.3 on pages 3-15 and

3-16.

Table 3-5. MAKO’s LDO and Supplies

Name Ref Description Level

ON_OFF_SWITCH F_MECH_SW ON/OFF Switch. Radio on when GND GND

UNSW_B+ F_UNSW_B+ Radio Battery Voltage 9 – 6 V

SW_B+ R6593 Radio Supply Voltage 9 – 6 V

V_SAVE C6538 LDO Output Present When Battery is Attached 2.5 V

V_1.875 C6581 LDO Output 1.875 V

V_1.55 R6561 LDO Output 1.55 V

V_2.775D R6563 LDO Output 2775 V

V_2.775_EXP R6562 LDO Output 2.775 V

V_2.8_RF R6564 LDO Output 2.8 V

V_5.0A R6565 LDO Output 5.0 V

V_3.3 R6566 LDO Output 3.3 V

V_3.0A R6567 LDO Output 3.0 V

3-30 Theory of Operation: Controller

3.2.2.1.2 External Regulators: V_SW_1.4, V_SW_3.60

The controller board contains two TPS62050 regulators in order to regulate voltages of 1.4V and

3.6V. The TPS62050 is a synchronous step-down adjustable regulator. The switching regulator is
capable of sourcing 800mA. Its output can be adjusted by using a voltage divider tied to the feedback
pin. The regulators are powered from SW_B+. Figure 3-17 is the schematic for the V_SW_1.4
regulator that illustrates the supporting circuitry for the TPS62050.

R6547

C6569

10UF

SW_B+

0

VCC_SW1.4_VIN

R6552
100K

Figure 3-17. V_SW_1.4 Switched Power Supply

V_1.55

R6554
0

R6548

DNP

V_SW_1.4

SW1V4_FB

C6582

L6505

10UH

6.8PF

U6507
TPS62050

1

VIN

PGND

10

LBO

SW

4

PG

9
26

8

EN

5

FB
LBI

7

SYNC

GND

R6558

165K

0

3

10UF

R6568
301K

C6586C6584

4.7UF

C6570
330PF

Theory of Operation: Controller 3-31

3.2.2.1.3 External Switcher 5

The controller board uses an external TI regulator (TPS62110, U6505) to regulate to 5.4V. The
TPS62110 is a 1.5A capable synchronous step down converter. The output is adjusted using a
voltage divider to the feedback pin. The regulator is powered from SW_B+. Figure 3-18 illustrates the
SW5 circuitry. The SW5 circuit also includes or-gate logic that facilitates implementation of current
saving PFM mode when the radio is in standby mode.

SW_B+

V_SW_5

L6504

29

VOUT

30

C6560

C6567

BGAP_COMP

C6567

VIN

EN

U6505

TPS62110

SYNC

PA_SHTDN

5V_PWM_EN

Figure 3-18. 5V Switched Power Supply

APX 5000/APX 6000/APX 6000XE/SRX 2200 has Pulse Switching option.
Mode 1: Pulse Frequency Modulation (PFM). A relatively noisy but highly efficient pulsing mode for
Switched power supplies.
Mode 2: Pulse Width Modulation (PWM). Pulsing mode that is cleaner than PFM, used when risk of
RF interference is present which includes both transmit and receive radio modes.

Table 3-6. Pulse Switching Combination

PA_SHTDN 5V_PWM_EN SYN MODE

000PFM

011PWM

101PWM

111PWM

3-32 Theory of Operation: Controller

3.2.2.1.4 Power-up Timing

The powering up of the radio starts with the MAKO. Once the radio knob is turned to the 'ON' position
and battery voltage is supplied, a pass FET is activated to deliver battery voltage to MAKO and
external regulators. The external 3.6 V is first turned on then MAKO activates its 24.576 MHz clock,
and the remaining regulators begin to turn on. Once all the regulators have turned on, MAKO
releases its reset. The CPLD is then powered on from the 1.875 V external regulator and takes
MAKO 24.576 MHz clock and divides it to 32.768 kHz in order to provide for OMAP. OMAP starts to
power up upon receiving voltages 1.4 V, 1.85 V, and the 32.768 kHz clock. OMAP than activates it 12
MHz clock and releases its reset. It then starts to run the boot loader stored in flash. A more detailed
timing view of the regulators is shown in Figure 3-19.

fet_en

rcosc_en

rcosc

sw1_enldo

sw1_en

sw1_on

24mhz_clk

extldo_2.23V

v9_on

v4_on

v3_on

extsw_1.4

v8_on

v2_on

extldo_1.85

v6_on

v7_on

v10_on

sys_rstx

20ms

210us

1ms

1ms

4ms

600us

4ms

1ms

1ms

1ms

2ms

1ms

1ms

1ms

1ms

1ms

14ms

Figure 3-19. Power-up Timing Regulators

Theory of Operation: Controller 3-33

3.2.3 Clock Sources

The VOCON board contains multiple crystal clock sources. These sources are active upon power­up. Secondary clock frequencies are derived on the VOCON board from these crystal sources. In
addition to the crystal frequencies, the VOCON receives a 16.8 MHz sine wave from the RF board,
which is shaped into square wave and fed to the OMAP timer input. Screen shots and test points for
these clock signals are shown in Chapter 6.

EXPANSION

RF BOARD

TRIDENT

26 MHz

MACE

VOCON

SQUARING

32.768 kHz

CPLD

GPS

4.096 MHz

16.8 MHz

12 MHz

32.768 kHz

24.576 MHz

Figure 3-20. VOCON Clock Architecture

Table 3-7. VOCON Clock Distribution

OMAP

MAKO

96 MHz

DDR

Clock

Frequency Type Description Clock Recipient Suggested Probe

Source

Y6501 24.576 MHz Crystal

Oscillator

Y6502 32.768 kHz Crystal

MAKO 24 MHz & tapped into

U6501, U6101 R6574

CPLD

MAKO RTC U6501 C6541

Oscillator

Y6601 12 MHz Crystal

OMAP CPU Clock U6302 C6601

Oscillator

U6302 96 MHz OMAP GPIO DDR Clocks

U6301 TP6307 & TP6308

(Complementary signals)

U6101 4.096 MHz CPLD GPIO MACE Clock U2510 (to

Expansion Board)

U6101 32.768 kHz CPLD GPIO OMAP Boot-Up clock & GPS/

Bluetooth digital clock

Y701
(RF

16.8 MHz Crystal
Oscillator

RF Frequency Synthesizer
IC (Trident) TCXO

U6302 & U2401
(Expansion Board)

U6302 R6218

board)

Points

R6113

R6114 (GPS/BT) &
R6115 (OMAP)

3-34 Theory of Operation: Controller

3.2.4 OMAP Processor and Memory

3.2.4.1 OMAP Processor (U6302)

The OMAP1710 dual core processor lies at the center of the VOCON design. The processor
features utilized in the VOCON design include:

• ARM9 CPU core

• C55X DSP core

• 16KB shared internal RAM

• SSI Interfaces

• USB Interfaces

• Timers & Watchdog Timers

• Keyboard Matrix Interface

• 1-Wire Interface

• Multimedia Card

• LCD Controller

• I2C Interface

• SPI interface

• External Memory Synchronous Interface

• External Memory Asynchronous Interface

•UARTs

•GPIOs

e-MMC

Flash Memory

GPS/ BT Chipset

(TINL5500)

FLASH

64 MB

SDRAM

32 MB

Keypad /

Switches

Front

Display

Top Display

SDIO 2

UART 2

EMIFS

EMIFF

Keypad

SoSSI

SPI

Lighting

Controller

I2C

OMAP 1710

Processor

RF Board

CPLD

4.096 MHz Clk

SPI

Side
Conn -

GCAI

MAKO IC

Codec

Class D

Audio PA

VOCON
Expansion
Module

GCAI

SSI

32 kHz ClkEMIFS

Audio SSI 1

USB / UART

SPI

SPI GPIOSSI

MACE

Secure

IC

GPS/BT Module

(TINL5500 &

ATMEL AVR32)

Figure 3-21. Overview of OMAP Interconnection with VOCON Peripherals

Theory of Operation: Controller 3-35

3.2.4.2 Memory

In addition to the internal RAM, the OMAP 1710 Processor (U6302) features three distinct external
memory interfaces. All memory devices except the eMMC memory, is located on the VOCON board,
as elaborated in Figure 3-21. The external memory interface is shown in Figure 3-22.

EMIFF

OMAP

EMIFS

DDR_CTRL_10:0

SADD_15:0

SDATA_15:0

SDCLK

SDCLKX

FADD_25:1

FDATA_15:0

NF_CS3

NF_RP
NF_WE
NF_WP

FCLK

FRDY

NF_ADV

NF_OE

NF_CS1

Figure 3-22. OMAP Memory Interface

DDR_CTRL_10:0

A13:0
DQ15:0

CK

CK#

A24:0
DQ15:0

EN_CE
EN_RST
EN_WE

EN_WP
CLK

WAIT

ADV
EN_WE

ADDR_4:0
DATA_4:0

CPLD_ADV
CPLD_R/W
CPLD_CS

WAIT_SW_EN

SDRAM

DDR

FLASH MEMORY

CPLD

3.2.4.3 Asynchronous External Memory Interface

The EMIFS is used for transferring data between the ARM or DSP cores and the 64 MB External
NOR Flash memory (U6304). The Flash memory is a non-volatile memory unit, primarily used to
store the radio's executable code, along with device configuration values, event logs, and
initialization codes. The flash memory is primarily accessed during the VOCON’s power up and
power down cycles.

3.2.4.4 Flash Memory (6304)

The Flash memory located in close proximity to the OMAP processor is a 64 MB Numonyx 65nm
StrataFlash. The flash interface uses 16 data bits and 25 address bits. The flash IC is enabled by
OMAP processor's CS3 line. The flash IC also features a WAIT line that is capable of halting data
flow between the processor and flash IC while operating in synchronous read mode.

3.2.4.5 CPLD Interface (U6101)

The CPLD (U6101) registers are also mapped to the Asynchronous External Memory Interface.
These registers control the CPLD GPIO pins and enable the OMAP to expand its GPIO capability via
memory mapped IO.

3-36 Theory of Operation: Controller

3.2.4.6 Synchronous External Memory Interface

This interfaces the OMAP to a 32 MB Double Data Rate (DDR) RAM IC (U6301). Upon boot-up
OMAP configures this interface to operate in synchronous mode at 96MHz. This volatile memory unit
is primarily accessed during code execution.

3.2.4.7 Double Data Rate (DDR) Memory (U6301)

The 32MB DDR Synchronous DRAM IC is interfaced to the OMAP using 13 address bits and a 16bit
data bus. The DDR IC is driven by a complementary clock signal originating from the OMAP IC. The
DDR clock is initialized to 96MHz by the OMAP boot code. Additional control signals are also
dedicated for the DRAM interface, as illustrated in Figure 8-70. “ HLN5979B/ HLN5960A Controller

Board Memory Interface Circuit” on page 8-136

.

3.2.4.8 Multi-Media Card (MMC) Interface

The OMAP processor’s MMC interface is used for a 4GB external e-MMC NAND flash memory. This
external memory is located on the expansion board. The VOCON board is connected to the
expansion board through connector J4001.

3.2.4.9 eMMC Memory

The MMC2 port interface on the OMAP processor is configured as a Secure Digital interface used for
memory modules. The memory module uses a 10bit interface, which include 4 bit wide bi-directional
data bus, command line, clock and three direction control bits. The SDIO signals are conveyed to the
expansion board via J4001. A 4GB eMMC is the only size used on the expansion board.

The Micron eMMC is a communication and mass data storage device that includes a
Multi-Media Card (MMC) interface, a NAND Flash component, and a controller on an advanced
11-signal bus, which is compliant with the MMC system specification. Its low cost, small size, Flash
technology independence, and high data throughput make e MMC ideal for smart phones, digital
cameras, PDAs, MP3 players, and other portable applications. The nonvolatile eMMC draws no
power to maintain stored data, delivers high performance across a wide range of operating
temperatures, and resists shock and vibration disruption.

The MMC specification defines the communication protocol between a host and a device. The
protocol is independent of the NAND Flash features included in the device and the device handles its
management functions internally, making them invisible to the host processor.

Micron eMMC incorporates advanced technology for defect and error management. If a defective
block is identified, the device completely replaces the defective block with one of the spare blocks.
This process is invisible to the host and does not affect data space allocated for the user. The device
also includes a built-in error correction code (ECC) algorithm to ensure that data integrity is
maintained.

The card-specific data (CSD) register provides information about accessing the device contents. The
CSD register defines the data format, error correction type, maximum data access time, and data
transfer speed, as well as whether the DS register can be used. The programmable part of the
register (entries marked with W or E in the following table) can be changed by the PROGRAM_CSD
(CMD27) command. The maximum READ and WRITE data block lengths are 512 bytes, and the
device size is 4095.

In order to accurately identify memory that is greater than 1GB, there is an additional register to
consider. The 512-byte extended card-specific data (ECSD) register defines device properties and
selected modes. The most significant 320 bytes are the properties segment. This segment defines
device capabilities and cannot be modified by the host. The lower 192 bytes are the modes segment.
The modes segment defines the configuration in which the device is working. The host can change
the properties of modes segments using the SWITCH command.

Theory of Operation: Controller 3-37

A GPIO named "MMC_RESET" will be used to soft-reset the eMMC card. This will be an output from
CPLD ball C7. This ball is on output high out of reset. On power-up software should drive the pin low
for at least 5ms and then drive it high. After reset is driven high, software needs to wait 250ms before
sending command CMD0 (argument = 0). Refer to the sw code to see how to add delays with
MMC_CLK running for at least 74 clock cycles after any reset occurs. If not, the eMMC will fail to
initialize and will not open since the OMAP does not run the clock continuously, so waiting 250ms
with no clock running will not configure eMMC correctly.

Supply voltage

V

CC,max

Memory field

working

voltage range

V

CC,min

V

CCQ,max

V

CCQ,min

Control logic

working

voltage range

V

CCQ

Power-up time Supply ramp-up time First CMD1 to card ready

Initialization sequence

Initialization delay =

the longest of 1ms, 74 clock cycles,

the supply ramp-up time,

or the boot operation period.

N

CC

Optional repetitions of CMD1

until the card is responding

N

CMD1 CMD1 CMD2CMD1

with busy bit set

CC

Figure 3-23. Timing of power-up and initialization of eMMC

N

CC

3-38 Theory of Operation: Controller

e·MMC

RST_n

CMD

CLK

V

DDI

MMC

controller

Registers

OCR CSD RCA

CID ECSD DSR

V

CC

V

CCQ

DAT[7:0]

*

V

SS

*

V

SSQ

* internally connected.

NAND Flash

Symbol Type Description

CLK Input Clock: Each cycle of the clock directs a transfer on the command line and on the data

line(s). The frequency can vary between the minimum and the maximum clock frequency.

CMD I/O Command: This signal is a bidirectional command channel used for command and

response transfers. The CMD signal has two bus modes: open-drain mode and push-pull
mode (see Operating Modes). Commands are sent from the MMC host to the device, and
responses are sent from the device to the host.

DAT[7:0] I/O Data I/O: These are bidirectional data signals. The DAT signals operate in push-pull

mode. By default, after power-on or assertion of the RST_n signal, only DAT0 is used for
data transfer. The MMC controller can configure a wider data bus for data transfer either
using DAT[3:0] (4-bit mode) or DAT[7:0] (8-bit mode). eMMC includes internal pull-up
resistors for data lines DAT[7:1]. Immediately after entering the 4-bit mode, the device
disconnects the internal pull-up resistors on the DAT[3:1] lines. Upon entering the 8-bit
mode, the device disconnects the internal pull-ups on the DAT[7:1] lines.

RST_n Input Reset: The RST_n signal is used by the host for resetting the device, moving the device

to the pre-idle state. By default, the RST_n signal is temporarily disabled in the device.
The host must set ECSD register byte 162, bits[1:0] to 0x1 to enable this functionality
before the host can use it.

V

V

V

V

V

CC

CCQ

SS

SSQ

DDI

1

Supply VCC: NAND interface (I/F) I/O and NAND Flash power supply.

Supply V

: eMMC controller core and eMMC I/F I/O power supply.

CCQ

Supply VSS: NAND I/F I/O and NAND Flash ground connection.

1

Supply V

: eMMC controller core and eMMC I/F ground connection.

SSQ

Internal voltage node: At least a 0.1μF capacitor is required to connect V

to ground. A

DDI

1μF capacitor is recommended. Do not tie to supply voltage or ground.

NC – No connect: No internal connection is present.

RFU – Reserved for future use: No internal connection is present. Leave it floating externally.

Note: 1. VSS and V

are connected internally.

SSQ

Figure 3-24. eMMC Topography

Theory of Operation: Controller 3-39

MAKO

U6501

CPLD

U6101

OMAP

1710

U6302

V_SW_3.6 V_EXT_1.85v

V4_2775D

F2_Timer_out

AVR_STATUS_1.8

LDO

U6508

jumper

R6562

MMC_CMD
MMC_CLK
EMMC_RESET
MMC_DAT0
MMC_DAT1
MMC_DAT2
MMC_DAT3

V_2.775_EXP

J4001

Expansion Board VOCON Board

VCC_1.85v

VCC_2.775

P2001

Voltage

translator

MMC

AVR_STATUS_3.3

eMMC

AVR

U2415

Figure 3-25. Block Diagram of VOCON and EXPANSION boards as related to eMMC

3-40 Theory of Operation: Controller

3.2.4.10 Peripheral Devices

The OMAP processor is equipped with multiple buses and interfaces that are configured for
peripheral interconnection.

3.2.4.10.1 Receive and Transmit SSI

These two interfaces are dedicated for communicating with the RF deck digital interface, carrying
receive and transmit base band signals. The OMAP processor generates the clock and FSYNC
signals for the receive SSI interface. The RF deck generates these signals for the transmit SSI
interface.

RF BOARD

RX_FSYNC

ABACUS

TRIDENT

RX_CLK

RX_DA

TX_FSYNC

TX_CLK

TX_DA

3.2.4.10.2 Audio SSI

OMAP's McBSP1 interface is configured as a SSI interface dedicated to carry transmit and receive
audio data to peripheral devices. The peripherals connected to this bus include MAKO, Audio
CODEC, MACE and CPLD. The bus also connects to the option board via J3001. MAKO generates
the clock and frame sync signals for this bus.

VOCON BOARD

RX SSI

McBSP 2

3

TX SSI

3

OMAP 1710

McBSP 1

McBSP 2

MAKO

SYNC

BCLK

VC_FSYNC

VC_DCLK

Figure 3-26. RX / TX SSI Configuration

RD 1

TD 1

SSC 1

( Red )

TD 3

MACE

PA 28 (GPIO)
Hi_Sec */Normal

SSC 2

(Sniffer)

SSC 0

(Black)

CPLD

RD 2

RD 0

TD 0

MCLK

WCLK

MACE/CODEC

FSYNC

MACE/

CODEC_CLK

Expansion Board

Vocon Board

TI

CODEC

MACE

RED TX

CODECs

RED RX

0

Mux B

1

0

1

Mux A

CPLD

Figure 3-27. Audio SSI Configuration

BLACK or

RED RX

BLACK or

RED TX

MCBSP1

OMAP

Theory of Operation: Controller 3-41

3.2.4.10.3 ARM SPI

This SPI interface is controlled by OMAP's ARM core. Devices connected to this bus include MAKO,
display controllers and the audio CODEC.

3.2.4.10.4 DSP SPI

This SPI interface is controlled by the DSP core of the OMAP processor. This bus is used to
configure and control devices on the RF deck.

DAC

EEPROM

ABACUS

TRIDENT

RF BOARD

DSP SPI

VOCON BOARD

DSP SPI

DAC_CS

3

SPI_DSP_CLK

SPI_DSP_MOSI

SPI_DSP_MISO

EEPROM_CS

ABACUS_CS

McBSP3 SPIF

SPI_CLK

SPI_MOSI

SPI_MISO

MAKO_CS

TOP_DIS_CS

ARM SPI

MAKO

TOP DISPLAY

OMAP 1710

ABACUS_CS

FRONT DISPLAY

LIGHTING

CONTROLLERS

CODEC_CS

TI CODEC

COLOR_DIS_CS

I2C_SCL

I2C

I2C_SDA

CPLD

Inverter

I2C

3.2.4.10.5 1-Wire

The OMAP's 1-wire line is available on the GCAI pin 16. The signal is routed to the side connector
via J4001.

3.2.4.10.6 USB

The OMAP CPU's USB port is routed to the side connector via J4001. The USB signals on the side
connector are illustrated in Figure 3-21, on page 3-34.

Figure 3-28. SPI and I2C Configuration

3-42 Theory of Operation: Controller

3.2.4.10.7 UARTs

Two of OMAP's UARTs are configured for peripheral interfacing.

The four-wire UART1, which is capable of hardware flow control, is available on the side connector
for accessory devices. The signals are level translated via MAKO and routed to the side connector
via J4001.

OMAP's UART2, which is a two wire interface, capable of software flow control only, is connected to
the GPS receiver IC on the expansion board. The signals are routed to the expansion board via
J4001.

3.2.4.10.8 CPLD (U6101)

The CoolRunner IC is a complex programmable logic device (CPLD) programmed specifically for the
APX/ SRX product line. The CoolRunner IC is flash based and comes pre-programmed. It is
contained in an 8x8mm, 132 BGA package with 0.5mm ball spacing. The primary functions of the
CPLD are clock generation, GPIO expansion, SSI clock and frame sync direction control, F2
multiplexing, secure data control, main display off-loading, and clock inversion.

An external linear regulator, U6508, supplies the CPLD's 1.875 V core voltage. The 1.875 V core
voltage is used for the CPLD’s internal logic and I/O buffers. MAKO's 24.576 MHz clock source is
used by the CPLD to generate a 32.768 kHz clock for OMAP booting, real time clock/timer, and for
GPS. It is also used to generate 4.096 MHz for the MACE IC.

The CPLD is controlled through OMAP's EMIFS interface. It supports 31 configurable GPIOs. It also
supports 20 input only pins that are accessible through an EMIFS read operation. Some of the
GPIOs supported by the CPLD include GCAI_GPIO_0, F2_PARAMP_MON, and USB_CURR_LIM.
Some examples of the inputs the CPLD is programmed to support are some of the top and side
controls buttons (SEC_CLEAR, FREQ_SEL, MON, SIDE_1, SIDE_2, and TG0) and board ID.

Figure 3-29 below shows the basic CPLD interfaces.

MAKO

OMAP 1710

Processor

24MHz

F2 Select

F2 Timer

EMIFS

KEYLD_MISSING

GCAI GPIO0

KL_SWITCH

CPLD

4.096MHz to MACE

32kHz to GPS

32kHz to OMAP

GPIOs

GPIs

Figure 3-29. CPLD Block Diagram

Theory of Operation: Controller 3-43

3.2.5 Audio

The audio section of the VOCON design consists of:

• TI AIC33 voice CODEC

• TI TPA2034D1 class-D audio power amplifier

• MAKO audio sub-block

3.2.5.1 TX Audio path

The TX audio paths begin with three microphones. There are two internal microphones and one
external microphone path going to the GCAI connector.

The internal microphone paths start with two microphones that are embedded within the radio. Both
of the microphones are biased with a 4.7 V supply that is generated by the MAKO IC. This supply is
solely dedicated to biasing the microphones. The microphone signals are AC coupled into the 16 bit
TI AIC33 stereo CODEC on the MIC3R and MIC3L input pins. The TI AIC33 CODEC allows both
microphone signals to be amplified, and simultaneously sampled and converted into digital data. The
data is sent to the OMAP1710's DSP through the McBSP1 port where the DINC (dual input noise
canceller) can process the data for both microphones and provide a high level of noise suppression.
The digital data is sent to the OMAP1710 through the audio SSI (synchronous serial interface) bus
where the MAKO IC is used as the interface's clock and frame sync generator.

OMAP DSP

SSI

MCBSP1

I2C

Reset Out

DSP SPI

Portable TX Audio Architecture

Note: All three microphones will be
routed to the AIC33 CODEC. In Tx

MAKO

SSI

VC_DCLK
VC_FSYNC
VC_TX
VC_RX

Audio Stereo Codec (TI AIC33)

SSI

I2C

Reset

SPI

LEFT

ADC

RIGHT

ADC

MIC BIAS

Line 1L

Mic 3R

Mic 3L

Figure 3-30. Audio TX Path Block Diagram

mode, MAKO will only be used to
generate the microphone bias. Both
internal microphones will be sampled
on adjacent SSI slots. The external
microphone can be sampled on either
slot.

1

4

5

6

External/
Accessory
Microphone

Internal
Microphone 1

Internal
Microphone 2

The external microphone path will also be supported by the TI AIC33 CODEC, using the LINE1LP
pin on the IC. The LINE1LP is multiplexed with the MIC3R within the CODEC, and selected as the
input when the external microphone path is chosen as the TX audio source. Similar to the internal
microphone signals, the TI CODEC amplifies and samples the external microphone signal. The
digital data is also sent to the OMAP1710's DSP through the McBSP1 port using the audio SSI bus.

3-44 Theory of Operation: Controller

3.2.5.2 RX Audio path

The RX audio path supports two internal speakers and one external speaker.

OMAP DSP

SSI

SSI

MCBSP1

ARM SPI SPI

I2C

I2C

DSP

SPI

SPI

MAKO

AB AMP

SSI

Switch

AB AMP

Low-Pass Filter

TI CODEC

RIGHT LINE

OUT

LEFT LINE

OUT

20kHz Corner

7

8

11

12

Class D

TI

TPA2034D1

Shutdown

15

OMAP GPIOs

Figure 3-31. VOCON RX Audio Path Block Diagram

9

10

13

14

External/
Accessory Speaker
~ 16-20 Ohms

Large Internal
Speaker
~ 4 Ohms

Expan Top Board Overlay

VOCON Bot Board Overlay

Test Point Descriptions

The RX internal audio path begins with the digital audio samples being sent from the OMAP1710's
McBSP1 port to the TI AIC33 CODEC through the audio SSI bus. As in the TX audio paths, the
MAKO IC is also used to generate the clock and frame sync for the audio SSI bus. Once the audio
data is received by the TI CODEC, the CODEC proceeds to convert the data to analog and
implements the volume control. The analog signal in the CODEC is then fully differential and gets
sent out to the power amplifier through pins LEFT_LOP and LEFT_LOM. The TI TPA2034D1 Class
D audio power amplifier accepts a fully differential analog input signal and will also drive a
4 Ohm loudspeaker differentially.

The external speaker path is almost identical to the internal speaker path. The digital audio data is
sent from the OMAP1710's McBSP1 port to the TI AIC33 CODEC for digital to analog conversion
and volume control. The external speaker path uses the MAKO IC's class-AB audio power amplifier
to drive 16 Ohm to 28 Ohm external speakers. The input to MAKO IC's audio power amplifier is fully
differential and comes from the TI CODEC's RIGHT_LOP and RIGHT_LOM. The output of the
MAKO IC's audio amplifier is also fully differential and available on pins EXT_SPKR_P and
EXT_SPKR_M.

Theory of Operation: Controller 3-45

pg

3.2.6 User Interface

3.2.6.1 Control Top

The control top contains an On/Off & Volume Knob (S3), a sixteen-position Channel/Frequency
Switch with programmable concentric two-position switch (S2), a three-position (A,B,C)
Programmable Toggle Switch (S4), and an orange programmable Top Button (S1). The Control Top
also includes a TX/RX LED that is solid amber upon receive, red on PTT, and blinks amber on
secure RX. Additionally, the Control Top includes a transflective FSTN display. Control Top
components are mounted on a flex circuit which connects to controller board connector J2101.

When the On/Off & Volume Knob (S3) is switched to the 'ON' position, the switch is grounded and
MECH_SW is pulled low. MECH_SW is an input to MAKO (U6501). The logic low input enables an
external FET (Q6501) gate voltage, FET_ENX, which switches UN_SW_B+ to SW_B+ and turns the
radio on. Volume is also controlled through S3 and is an input to MAKO. The VOL signal is
connected to a potentiometer biased between ground and 2.775 V (R6563) from MAKO. When the
volume knob is turned, the VOL signal level is converted to a code word by MAKO's ADC and read
by OMAP through SPI.

Switch S4 is the three-position, binary-coded, toggle switch typically used for expanded Zone/
Channel Selection. Two outputs of the switch,TOGGLE_0 and TOGGLE_1, are biased to 1.875 V.
The third output is grounded. Two-bit codewords from the switch are read by OMAP through the
CPLD's EMIFS interface and indicate which of the three positions is set.

The orange programmable Top Button (S1) is typically used for emergency. It is also biased to

1.875 V (R6507) and is an input (EMERG_BTN_X) to the CPLD. A button press is detected when
EMERG_BTN_X is pulled low.

Like the three-position switch, the Frequency Switch (S3) is also binary coded. S3's output pins are
connected to GPIO pins of the CPLD which provide a four-bit binary word (signals FREQ_SEL_0,
FREQ_SEL_1, FREQ_SEL_2, and FREQ_SEL_3) to OMAP indicating which of the 16 pins of the
switch is set. This switch provides an additional output, SEC_CLEAR, which is typically used for
coded or clear mode selection. Selecting clear mode pulls this signal to a logic low, and it can be
monitored from R2135.

Frequency Switch

Concentric

ABC
Toggle
Switch

Volume POT

ON/OFF SW

Emergency

Switch

TX/RX

LED

CPLD

MAKO

Intelligent

Lighting

Top

Display

FPC Vocon Bd

Figure 3-32. Control Top Block Diagram

OMAP

3-46 Theory of Operation: Controller

3.2.6.2 APX 5000/ APX 6000/ APX 6000XE/ SRX 2200 LCD Display Modules

3.2.6.2.1 QVGA

The APX 5000/APX 6000/APX 6000XE/SRX 2200 radio can have up to 2 displays (QVGA and
FSTN) depending upon the particular feature set and radio model ordered. The main Transflective

1.6" color display is a QVGA (130 x RGB x 130) active matrix TFT (Thin Film Transistor) LCD. A
display flex connects the front display to the J2304 22-pin connector on VOCON board. The QVGA
display uses the 8-bit Special optimized Screen Interface (SoSSI) for data and commands.

DISPLAY

FLEX CONNECTOR

1.85V

V-RE G

VOUT

J2304 PINS

V_EXT_1.85 (.004mA TYP.)

12

IO87

DNP

IO39

DNP

(V_2.775D)

(BOARD ID)

MAKO

0 Ω

ATOD_5

V06_O

47 Ω

47 Ω

47 Ω

47 Ω

10k Ω

F_DISP_RW

3

F_DISP_DATA_CMD

8

F_DISP_RW_EN (CLK)

18

OMAP_RESET

19

F_DISP_DATA_0

14

F_DISP_DATA_1

4

F_DISP_DATA_2

15

F_DISP_DATA_3

5

F_DISP_DATA_4

16

F_DISP_DATA_5

6

F_DISP_DATA_6

17

F_DISP_DATA_7

7

V_2.775D (.68mA TYP.)

2

F_DISP_BD_ID

22

To display driver (NT39123)
on display module.

(R/W)
(D/C)

(CLK 4MHz)

(RST)

(D0)

(D1)

(D2)
(D3)
(D4)
(D5)
(D6)
(D7)

OMAP

LCD_HSYNC

LCD_PIXEL_0
LCD_PIXEL_1
LCD_PIXEL_2
LCD_PIXEL_3
LCD_PIXEL_4
LCD_PIXEL_5
LCD_PIXEL_6
LCD_PIXEL_7

LCD_AC

CPLD (INVERT)

LCD_PCLK

RST_OUT

Figure 3-33. Display Circuit Detail Overview Block Diagram

The QVGA LCD Module operates using V_2.775D and V_EXT_1.85. The V_2.775D is the module’s
analog supply voltage sourced by LDO6 of MAKO. The V_EXT_1.85 is the module’s IO voltage
sourced by the 1.85V external LDO regulator. An 8-bit parallel bus is used for data and command
communication between OMAP’s SoSSI interface and LCD driver IC. The F_DISP_DATA_CMD
signal indicated the type of data being sent to the driver. A ‘0’ corresponds to command data and a
‘1’ corresponds to display data. Data only travels in one direction, from OMAP to display driver.
Therefore F_DISP_RW line will always be low. Display data is latched on the falling edge of the
F_DISP_RW_EN signal.

The SoSSI interface uses the LCD DMA controller/bus to allow the LCD module to access system
memory. Therefore the transfer of pixel data process will require less CPU processing power. An
initiate DMA transfer command is used and display data is transferred to the LCD module
automatically without intervention thus offloading the processor.

Theory of Operation: Controller 3-47

Prior to the LCD interpreting any commands, the correct display power-up sequence must be
initiated. First the V_EXT_1.85 (1.875 V) and V_2.775D (2.775 V) supplies must be at 90% or above
threshold and stable for 10us, and then reset can be asserted high. After OMAP de-asserts the reset
out signal (OMAP_RESET) the SLPOUT command can be sent. Now configuration commands are
ready to be sent to the LCD module.

The QVGA LCD module is only intended to operate up to +80°C due to ghosting effects. Therefore
software will shut off the display and backlight if the +80°C limit is reached. The display and backlight
will remain off until temperature drops below +75°C. The temperature sensor, U6401, for the display
cut-off is located near the top display connector and is input into MAKO A/D Channel 3, pin M14.

For enhanced display readability, the default backlight is set to a dim state while the radio is in
Standby mode; however, the backlight turns to full brightness through a button press, call receive,
emergency call, and other status indicators. See Section 3.2.6.3: "Intelligent Lighting" for the display
backlight operation.

3.2.6.2.2 FSTN

All APX 5000/APX 6000/APX 6000XE/SRX 2200 Radios are equipped with a caller ID (CID) top
display. This top display is a 1.1", Transflective, FSTN (Film compensated Super Twisted Nematic)
32 row x 112 column LCD with black pixels on a light background. This display is a component of the
control top sub-assembly with all interconnections passing through control top FPC. The display is
controlled via OMAP's 3 wire SPI interface to program the display driver IC registers and send data/
image information to the display. The active low chip select line, T_DISP_SPI_CS, is sent from the
OMAP GPIO_5 pin P3. The T_DISP_DATA_CMD line indicates whether the data being sent across
the SPI bus is register/command settings or if it's data/image information. The display driver contains
internal GRAM, which stores the current display content information, and the data/image information
is only sent when the display content needs to be updated.

Prior to sending any information to the LCD driver, the proper power-up sequence must be
instantiated. First, the V_EXT_1.85 and V_2.775D voltage supplies must be stable for at least 1 ms.
Next, the active low reset line, T_DISP_RESET, to the LCD driver must see a low pulse of 10 usec or
longer prior to communicating to the LCD driver. Then, the register setting information will be sent to
the display driver, followed by the image/data information.

The top LCD contains various LEDs for multiple backlight color combinations depending upon the
mode of operation. The programmable default backlight setting is off in standby mode, but will
illuminate to max brightness during a button push, call receive, receive mode, low battery, out of
range, emergency, etc. The details of the top display backlight settings are listed in Section 3.2.6.3:

"Intelligent Lighting". The top display contains 2 parallel side firing white LEDs and 2 parallel Red-

Green side firing bi-color LEDs.

3-48 Theory of Operation: Controller

3.2.6.3 Intelligent Lighting

The APX 5000/APX 6000/APX 6000XE/SRX 2200 radio is equipped with numerous LEDs to provide
intelligent lighting features. The VOCON board contains 2 lighting controller devices, which
illuminate all the LEDs throughout the radio, as shown in Figure 3-34. The main lighting controller,
U2204, provides white illumination to the main QVGA color display, and white keypad backlights.
The secondary lighting controller, U2201, generates illumination for the top display backlight and TX/
RX indicator lamp. Both lighting controller devices are controlled through OMAPs I2C interface (SCL
and SDA). Some of the intelligent lighting color schemes are shown in Table 3-8.

Table 3-8. Color Schemes

Color

Default White

Out of Range Red

Low Battery Red

Emergency Amber

Call Received Green

Call Paged Green

3.2.6.3.1 Main Lighting Controller

The boost lighting controller, U2204, provides backlight functionality for the main color QVGA
display, and the white backlight on the keypad. Switcher 3.6 (V_SW_3.60) is used as main input
voltage for the controller, while external 1.85 (V_EXT_1.85) is used for IO voltage. The controller
communicates with the OMAP via standard I2C communication protocol. This communication allows
the OMAP chip to enable, disable, and control the brightness of each LED. A reset line issued by
OMAP, OMAP_RESET, can be used to set the device in reset. The charge pump capability of the
lighting controller is currently not used. Refer to Figure 3-34.

The QVGA display has 3 LEDs powered by the external 3.6 regulator, V_SW_3.6. The cathode
output (negative) of each LED is fed back into the LED driver to control the current thus controlling
the brightness of the LEDs. The front display backlights are controlled by bank B of the LED
controller.

The keypad backlighting uses 4 white LEDs for illumination. The keypad backlighting operates
similar to the main QVGA display LEDs. The LEDs are powered by the external 3.6 regulator,
V_SW_3.6. The cathode output (negative) of the LEDs is fed back into bank A of the LED driver to
control the current thus controlling the brightness of the LEDs.

Theory of Operation: Controller 3-49

3.2.6.3.2 Secondary Lighting Controller

As previously mentioned the secondary lighting controller provides illumination to the top display
backlight and Tx/Rx indicator lamp. The lighting controller and LEDs are powered by switcher 5
(V_SW_5). This lighting controller device uses a PWM output to control the dimming modes of
operation for each LED. The device is controlled through the I2C interface, however, the I2C
interface require an input high voltage between 3 V – 5.5 V, thus the level translator (U2202) is used
to boost these signals to 5V logic.

Figure 3-34 shows the major connection scheme to this secondary lighting controller. The white,

green, and red top display LEDs are connected to the lighting controller PWM outputs through ESD
filter inductors L2204, L2203, L2202, respectively. The TX/RX status indicator LED uses a tri-color
red, green, amber (RGA) LED.

OMAP

(I2C) SCL

(I2C) SDA

RST_OUT

1.85V

V_SW_3.6
V-REG

VOUT

V_SW_5
V-REG

VOUT

LEVEL
SHIFT

LED DRIVER

(LM27965)

VIN

SCL
SDIO

RESET

LED DRIVER
(LP3943)

PWR

LED0
LED1
LED2

SCL
SDA

RESET

A0

LED4
LED5

A1

LED6

A2

D1A
D2A
D3A
D4A

D1B
D2B
D3B

KEYPAD

12

15
16
17
18

FRONT DISPLAY

10

20
21
11

TOP DISPLAY

25

26
24
23

1

15
17

8

KEYPAD WHITE
ILLUMINATION

FRONT DISPLAY
WHITE BACKLIGHT

TOP DISPLAY
BACKLIGHT

W

G

R

TX/RX
STATUS

A

G

R

Figure 3-34. Lighting Controller Overview

3-50 Theory of Operation: Controller

3.2.6.3.3 Secondary Lighting Controller – SRX 2200

Figure 3-35

shows the major connection scheme to this secondary lighting controller exclusively for SRX 2200.

A lighting system has been put into place to accommodate night profiles. These profiles shift both
displays and the keypad to a lower brightness. The LM27965 Lighting Controller, which controls the
Front Display and Keypad during normal operation, is disabled during Night Operation/ Night Vision
operation. The LM3943 is the only operating backlight driver during this mode and lower brightness
levels are achieved by routing separate lines and decreasing the duty cycle of its pulse width
modulated signal.

RADIO TOP LIGHTING

V_EXT_1.85 V_LED_TOP

I2C_CLK

LED DRIVERS

F_DISP_KP_NVG_MODE

U2202

PCA9306

C2201

0.1UF

V_LED_TOP

V_SW_5 V_LED_TOP

R2235
0

R2201
200K

C2202

0.1UF

2

7

IC2_TRANS_VREF2

8

EN

VREF1

VREF2

SCL2

SCL1

SDA1

SDA2

GND

1

OMAP_RESET

R2244
10K

3

1

2

63
54

V_EXT_1.85

2

F_DISP_AND_KP_ISET

R2245

12.4K

U2205
2SC5663

SCL_5V
SDA_5VI2C_DATA

Q2202
DTC114YKAF

10K

47K

1

V_EXT_1.85

V_LED_TOP

3

R2204

3.3K

R2243
10K

OMAP_RESET_5V

C2221

0.1UF
DNP

V_SW_3.60

C2217

1UF

IO

R2242
0

V_LED_TOP

IN

OMAP_RESET

I2C_DATA

R2206

3.3K

I2C_CLK

V_LED_TOP

R2207
0

C2203

U2201

0.1UF

LP3943

21

19

SCL

18

RST

20

SDA

22

A0

23

A1

24

A2

9

1

24
10
17

2
7

19

NC

22

NC

20

NC

21

NC

GND1

VIN
RESET
ISET
SDIO
VIO

C1_P
C1_N
C2_P
C2_N

SCL

25

VDD

GND2

LED10
LED11
LED12
LED13
LED14
LED15

LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8
LED9

U2204
LM27965

1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17

GND2

CTGND

GND1

9

18

G1

TOP_DISP_RED_LED
TOP_DISP_GREEN_LED
TOP_DISP_WHITE_LED
TOP_DISP_NVG_W
TX_RX_RED_LED
TX_RX_GREEN_LED
TX_RX_AMBER_LED

TOP_DISP_NVG_R
F_DISP_LED1_NVG
F_DISP_LED2_NVG
F_DISP_LED3_NVG
KP_LED1_NVG
KP_LED2_NVG
KP_LED3_NVG
KP_LED4_NVG

NV PROFILE ALTERNATE
CURRENT DRAIN PATHS

4 KEYPAD
3 FRONT DISPLAY
2 TOP DISPLAY (RED & WHITE)

23

POUT

16

D1A

15

D2A

14

D3A

13

D4A

12

D5A

4

D1B

5

D2B

6

D3B

3

D1C

8

NC1

11

NC2

KP_LED1
KP_LED2
KP_LED3
KP_LED4

F_DISP_LED1_RETURN
F_DISP_LED2_RETURN
F_DISP_LED3_RETURN

NC

NC
NC

R2247
82K

R2215
430

R2255
R2256
R2257
R2258
R2259
R2260
R2261
R2262

11K

7.5K

7.5K

7.5K
11K
11K
11K
11K

V_LED_FRONT

R2241
0

C2220
1UF

ISET SWITCH
LED 7 ON = NV MODE
LED 7 OFF = DEFAULT MODE

Figure 3-35. Lighting Controller – SRX 2200

FRONT DISPLAY AND KEYPAD LIGHTING

Theory of Operation: Controller 3-51

3.2.6.4 Keypad

The Dual Display Model contains a 21 button keypad, which translates to a 5x5 row and column
keypad matrix as shown in Figure 3-36. The keypad also contains LEDs for the backlighting of the
keys, which is described in more detail in Section 3.2.6.3: "Intelligent Lighting". Every key is
assigned a particular row and column to identify the unique key, as shown in keypad mapping Ta bl e

3-9. The keypad flex also contains 2, 6-channel filters that each row and column signal passes

through. Each row of the keypad contains an external pull-up resistor, and all the rows are interrupt
based inputs to OMAP. The columns are driven low by default in OMAP. When a key is pressed, the
corresponding key row and column are shorted together and causes a low level to be input on the
corresponding row in OMAP. Upon receiving the row interrupt, the OMAP IC is then programmed to
scan the column output to determine which corresponding column was selected that generated the
interrupt.

ROW

OMAP

COLUMN

KEYPAD FPC

*FPC = Flexible Printed Circuit

Figure 3-36. Keypad Interface Outline

Table 3-9. Key Map Matrix

Key Row, Column Map Key Row, Column Map

{ 0 , 4 3 3 , 2

| 1 , 4 4 2 , 0

} 2 , 4 5 2 , 1

H 4 , 0 6 2 , 2

< 4 , 1 7 1 , 0
U 0 , 3 8 1 , 1
D 4 , 2 9 1 , 2
> 1 , 3 * 0 , 0

3-52 Theory of Operation: Controller

Table 3-9. Key Map Matrix (Continued)

Key Row, Column Map Key Row, Column Map

P 2 , 3 0 0 , 1

1 3 , 0 # 0 , 2

2

3.2.6.5 Side Controls

The side controls include three programmable, momentary, pushbutton switches (Side Button 1
[SB1], Side Button 2 [SB2], Top Side Button [MON]) and a Push-To-Talk switch [PTT]. These
components interface to the expansion board via connector J2005 through a two-piece, bonded flex
circuit. A board-to-board connection routes the side controls signals from expansion board connector
P2001 to connector J4001 of the controller board. See Chapter 7 for pin out names and numbers.

Side button 1 (R4006), side button 2 (R4007) and the top side button (R6101) are inputs to the CPLD
and are biased to 1.875V. A button press is detected when the OMAP reads a 'LO' state from the
CPLD EMIFS interface. PTT (R4005) is connected directly to OMAP and a button press is detected
when a LO state is read.

3.2.6.6 GCAI

The GCAI (Global Communications Accessory Interface) connector is a 15 pin interface located on
the side of the radio. The connector interfaces the radio with accessories and is used for
programming. When the OMAP (U6501) detects that an accessory has been attached through a
logic low on GPIO0, it will identify the device by reading the GCAI_ONE_WIRE line. Once the device
type is identified, the appropriate signals are multiplexed through MAKO to the GCAI connector for
the particular device. Figure 3-37 is a block diagram of the GCAI interface.

Mounted to the side connector is a printed circuit board that houses ESD protection circuitry and an
auxiliary RF connector. The universal side connector interfaces with the expansion board via the P1
connector of a flex circuit and the J2004 connector of the expansion board. A board-to-board
connection routes universal side connector signals through expansion board connector P2001 to the
controller board. The figures below show the connections and signal assignments from the universal
connector to the controller board.

3 , 1

Theory of Operation: Controller 3-53

GCAI

CONNECTOR

OMAP1710

One-Wire

ONE_WIRE

MAKO

ONE_WIRE_GCAI

BATT_STATUS

USB

PORT 0

UART1_RX

UART1_TX

GPIO

GPIO

CPLD

GPO

TXEN

DAT

SE0

UART1_RX

UART1_TX

VBUS

D+

USB

D-

XCVR

Ext Mic
Preamp

SPKR+

SPKR-

MIC+

MIC-

OPTA_SEL_2

OPTA_SEL_1

OPTA_SEL_0

KEYFAIL

KEYFAIL CONTROL

MACE

OPT_GPIO_3

OPT_GPIO_2

OPT_GPIO_0GPIO

EXT
PA

Figure 3-37. GCAI Signal Configuration

KF Switch

GND

One-Wire

Vbus

D+

D-

GPIO_4

GPIO_0

1

2

3

4

5

6

7

8

GPIO_3

9

10

11

12

A

B C

16

P1

10

12

1

2

3

4

5

6

7

8

9

11

1

Front View Side View

Figure 3-38. GCAI Connector

9

8

3-54 Theory of Operation: Controller

Table 3-10. P1 Pin Assignment

P1 PIN ASSIGNMENT SIDE CONNECTOR SIGNAL

1 GCAI_VBUS_5V

2 GCAI_VBUS_5V

3GND

4 GCAI_USB_P_GPIO1 / TxDc / FillReq

5 GCAI_USB_N_GPIO2 / RxDc / FillData

6GND

7 GCAI_GPIO0 / PwrOn

8 GCAI_CTS_GPIO_4 / KeyFail / FillClk

9GCAI_MIC_P

10 GCAI_MIC_N

11 GCAI_SPKR_N / LineOut-

12 GCAI_SPKR_P / LineOut+

13 GND

14 GCAI_RTS_GPIO_3 / OTG-ID / FillSen

15 GND

16 GCAI_ONE_WIRE

Table 3-11. GCAI Connector Pin Assignment

PIN ASSIGNMENT SIGNAL

AGND

B GCAI_RF_INPUT

CGND

1 GCAI_GPIO0 / PwrOn

2 GCAI_ONE_WIRE

3 GCAI_VBUS_5V

4 GCAI_USB_P_GPIO1 / TxDc / FillReq

5 GCAI_USB_N_GPIO2 / RxDc / FillData

6GND

7 GCAI_SPKR_P / LineOut+

8 GCAI_SPKR_N / LineOut-

9 GCAI_RTS_GPIO_3 / OTG-ID / FillSen

10 GCAI_MIC_P

Theory of Operation: Controller 3-55

Table 3-11. GCAI Connector Pin Assignment (Continued)

PIN ASSIGNMENT SIGNAL

11 GCAI_MIC_N

12 GCAI_CTS_GPIO_4 / KeyFail / FillClk

Figure 3-39. GCAI Connector – Back View

3-56 Theory of Operation: Controller

3.2.7 RF Interface

The VOCON to RF board interface through connector J1001. See Figure 3-40.

RF - VoCon Interface

ABCS

TRCS

EEPROM_CS

LOCK

TX SSI
RX SSI

DMCS

SYNCB

16.8MHz

BATT

VSW1

V2775

RF CONNECTOR

RSTB

TEMP

TUNE

ISET

BSTAT

TXINH

GND

SPI

22

27

2

14

25

19,17,21

15,11,13

9

23

3

28,30,
32,34,36

37

6

8

7

20

18

16

26

12

1,4,5,10,24,

35,38,39,40

3

3

3

C1

D2

5

9

CPLD

N14,P14,AA1733,31,29

Y6,W7,AA5

V7,W6,P10

G19

T19

V15

M20

N18

L13

L12

L3

V6

Y5

L3

N1

L8

56

McBSP3

GPIO59

GPIO17

GPIO28
GPIO61/SPIF_CS2DAC_CS

GPIO56
McBSP2

McBSP2

TIMER.PWM2

GPIO7

TIMER.EXTCLKBUFFER

VDD

VSW1

LDO2LDO2

V6

POR

ATOD_5

FE_TUNE1

PWR_CTRL

ATOD_4

ONE_WIRE_BATT

Figure 3-40. VOCON to RF Board Interface

OMAP

MAKO

OPTION BOARD

TIMER.PWM1

TX_RX

L14

A1 1

The major interfaces are the TX and RX SSI buses, the SPI Bus with associated chip selects, the
synchronization signals (DMCS,SYNCB), the 16.8 MHz clock, MAKO VDDs and I/O's, and the
TX Inhibit from the Option Board.

3.2.7.1 TX SSI

The TX SSI interface provides the SSI data from the OMAP's DSP to the Trident IC on the RF board.
The interface contains 3 signals, the TX frame sync, TX clock, and TX Data signals. The pin
numbers for both the RF connector and OMAP IC are also shown in Figure 3-40.

3.2.7.2 RX SSI

The RX SSI interface provides the SSI data from the Abacus IC on the RF board to the OMAP's
DSP. The interface contains 3 signals, the RX frame sync, RX clock, and RX Data signals. The pin
numbers for both the RF connector and OMAP IC are shown in Figure 3-40.

3.2.7.3 Synchronization

The DMCS and SYNCB signals are used for synchronization between the RF and VOCON boards.
These signals route from the OMAP IC timer outputs through the CPLD to the RF board. The DMCS
signal connects to the Trident IC and the SYNCB connects to the ABACUS IC. The pin numbers for
both of the signals are shown in Figure 3-40.

Theory of Operation: Controller 3-57

3.2.7.4 MAKO Interface

MAKO supplies some DC regulation and I/O support for the RF board. The main battery supply is
provided by the RF board and is connected to MAKO. Regulated DC supplies based on this battery
voltage are then provided by MAKO to the RF board. These supplies are VSW1, LDO2, and V6. The
Power On Reset (POR) reset signal is also provided by MAKO to reset the RF board.

The One-Wire signal from the battery is provided by the RF board to MAKO's One-Wire
segmentation circuit, which then connects the One-Wire data path to the OMAP IC. The TUNE,
ISET, and TEMP signals are also interfaced to the MAKO IC.

3.2.7.5 TX Inhibit

The TX Inhibit I/O is reserved for future Option Board use, and is available at pin 12 for the RF
connector and pin 56 of the option board connector.

3.2.8 Encryption

The encryption circuitry is placed on the expansion board and interfaces to the VOCON through the
J4001-P2001 connector. The encryption circuitry is designed to digitally encrypt and decrypt voice
and ASTRO data in the APX 5000/APX 6000/APX 6000XE/SRX 2200 radio. The Motorola Advanced
Crypto Engine (MACE) IC is the main component in the encryption design, and has some discrete
support circuitry along with the interfaces to the VOCON IC's (CPLD, OMAP, and Audio CODEC).

NOTE: The MACE IC is NOT serviceable. The information contained in this section is only intended

to help determine whether a problem is due to the MACE IC or the radio itself.

Figure 3-41 below shows the Encryption architecture for the APX 5000/APX 6000/APX 6000XE/SRX

2200 radio.

CPLD

CLK SSI GPIO

AUDIO

CODEC

SSI

Key

Retention

Key
Fail

MACE

(Secure IC)

Tamper

SSI

Key

Zeroize

OMAP

Figure 3-41. APX 5000/ APX 6000/ APX 6000XE/ SRX 2200 Encryption Architecture

Vocon Bd

3-58 Theory of Operation: Controller

As shown in Figure 3-41 above, the encryption design consists of 5 blocks:

• MACE IC

• Key Loading

• Key Retention

•Tamper

• Key Zeroize.

3.2.8.1 MACE IC

The encryption module uses the MACE IC and an encryption key variable to perform its encode/
decode function. The encryption key variable is loaded into the MACE IC, via the GCAI (side)
connector, from a hand-held, key variable loader (KVL). The MACE IC contains the particular
encryption algorithm purchased. Table 3-12 lists the encryption algorithms and their corresponding
kit numbers.

Once the MACE IC has its encryption keys and algorithm, it communicates with the radio' s host
processor (OMAP) through the Synchronous Serial Interface (SSI) bus. Both commands and audio
(clear and encrypted) are sent through the SSI bus. A communications failure between the host
processor and the secure module will be indicated as an ERROR 09/10 message on the display.

Table below lists the encryption algorithms and their corresponding kit numbers.

Table 3-12. Encryption Algorithms and Corresponding Kit Numbers

KIT Number Description

NNTN8171_

NNTN8172_

NNTN8173_

NNTN8174_

NNTN8175_

NNTN8176_

NNTN8177_

NNTN8178_

APX 5000/APX 6000/APX 6000XE/SRX 2200 DVP-XL KIT

APX 5000/APX 6000/APX 6000XE/SRX 2200 DVP-XL KIT with Bluetooth

APX 5000/APX 6000/APX 6000XE/SRX 2200 AES KIT

APX 5000/APX 6000/APX 6000XE/SRX 2200 AES KIT with Bluetooth

APX 5000/APX 6000/APX 6000XE/SRX 2200 DES/DES-XL/DES-OFB KIT

APX 5000/APX 6000/APX 6000XE/SRX 2200 DES/DES-XL/DES-OFB KIT with Bluetooth

APX 5000/APX 6000/APX 6000XE/SRX 2200 NO ALGO BASIC VERSION

APX 5000/APX 6000/APX 6000XE/SRX 2200 NO ALGO BASIC VERSION with Bluetooth

The MACE IC relies on a 4 MHz clock source provided by the CPLD, the clock is connected to
MACE's XIN pin (U2510-P5).

3.2.8.2 Key Loading / Fail

Key variables are loaded into the MACE IC through the keyfail line. The signal originates from the
GCAI connector (pin 8 of J2004) and is passed through the expansion board to the VOCON board.
The signal is then selected by a multiplexer (U4003) controlled by CPLD output, KEYFAIL_CTRL,
and the signal is routed back to the expansion board to the MACE's KYLD pin (U2510-B10).

Theory of Operation: Controller 3-59

3.2.8.3 Key Retention

The key variables are retained within the MACE IC's memory (SRAM or FLASH). The keys can be
infinite key retention or 30-seconds key retention, depending on how the codeplug is set up. When
set to infinite key retention, the keys are stored in the FLASH memory inside the MACE IC. When set
to 30-second retention, the keys are stored in SRAM, and will be erased when the radio's battery is
removed (after the 30 second delay). The key retention delay circuit controls this time through a
comparator op-amp circuit (U2526). When the battery is removed, VSAVE (nominally 2.5 V) will
eventually drop to 0V after 30 seconds, which will result in a 0V output from U2526. This output is the
input to the CONT_1.875 regulator (U2525), which is nominally 3.3 V. When the regulator's output is
0 V, the keys in MACE's SRAM will be erased.

3.2.8.4 Tamper

The tamper function is intended to erase the encryption keys in a tampering situation. If the radio
chassis is opened during operation, the tamper signal, which is normally connected to ground
through spring contact M2533, will be disconnected from ground. This will be sensed by MACE
through its tamper pin TPR0 (U2510-M2). Once this condition is sensed, the encryption keys will be
erased.

3.2.8.5 Key Zeroize

The encryption keys can also be manually erased if infinite key retention is not turned on in
codeplug, by holding down the Side Top button and emergency buttons during radio power-up.
These two button inputs both connect to a dual transistor Q2537, which will release the
Key_ZEROIZE signal sensed by MACE's TPR0 (U2510-M2). Once this condition is sensed (floating
high), the encryption keys will be erased.

To troubleshoot the encryption circuitry, refer to the flowcharts in Chapter 5 “Troubleshooting

Charts”.

3-60 Theory of Operation: Global Positioning Sytem (GPS)

3.3 Global Positioning Sytem (GPS)

The APX 6000/APX 6000XE/SRX 2200 GPS architecture employs the Texas Instruments NL5500
GPS IC (U2401) which decodes GPS signals at 1575.42 MHz (L1 band). It is capable of producing a
final position solution including full tracking and data decode capability. The GPS signal is received
by the main RF/GPS combination antenna. The GPS signal is then diplexed at the antenna port via a
series resonant network, C1309 and L1305 which provides a very low capacitive load to the
transceiver. The signal is routed through a low noise amplifier (LNA, U1304) on the RF board (and a
SAW filter, FL1301 for UHF1 and UHF2 radios) and its output is applied to the RF-Vocon interface
connectors (P101 to J1001) where it is eventually routed to the expansion board via the J4001 and
P2001 connectors for processing by the GPS IC. Additional GPS diplexing components include
C1150, L1114, C1122, and L1103 which provide proper termination at the Peregrine switch (U1102)
output to minimize GPS signal leakage at the antenna port tap point at C1301. When the GPS signal
reaches the expansion board, it goes through a SAW filter (FL2401), LNA (U2404), and a second
SAW filter (FL2403), which then connects to the NL5500’s GPS RF input (U2401 pin L2). The
NL5500 IC is connected to the main OMAP processor via UART2. It is a two wire UART interface
(TX and RX with no handshaking).

NOTE: The enable signal for the LNA U1304 on the RF board is generated by the GPS IC, and DC

coupled onto the GPS RF signal which goes through the RF-Vocon-Expansion Interconnect.

The GPS receiver is setup in an autonomous continuous navigation mode where the current position
is updated once per second. The GPS receiver continuously tracks satellites for as long as the radio
is powered on to ensure the best possible accuracy. In the event the radio loses visibility of the
satellites due to terrain or environmental factors such as driving through a tunnel or entering a
building, the GPS will temporarily lose its position fix. If the signal outage is long enough, a power
savings algorithm will then cycle the GPS in and out of a sleep mode to save battery life until the
radio has moved back into an environment where the GPS signal is present.

The following table lists the power, clock, and I/O connections from the GPS IC to various
peripherals.

Theory of Operation: Global Positioning Sytem (GPS) 3-61

A

Table 3-13. Power and I/O Pins for NI5500

Signal Name Type NL5500 ball(s) Source/Destination [ref]

Description

(board

VBAT Power A2, H1, D8 VSW_3.6 [U6504] (Vocon) Main NL5500 power supply

VDDS Power B3, G10, K5, E2 VCC_1.85 [U6508] (Vocon) I/O Power Supply

VDD_TCXO Power G1 VSW_3.6 [U6504] (Vocon) TCXO Power Supply

RTC_CLK Clock H9 CPLD IO74 [U6101] (Vocon) 32kHz RTC

TCXO_CLK_LV Clock F1 TCXO [Y2204] (Expansion) 26MHz TCXO

GPS_nShutdown Input D5 CPLD IO91 [U6101] (Vocon) GPS Reset

GPS_UART_TX Output F5 OMAP pin R9 [U6302]

GPS UART TX to OMAP UART RX

(Vocon)

GPS_UART_RX Input E3 OMAP pin M18 [U6302]

OMAP UART TX to GPS UART RX

(Vocon)

LNA_ENABLE Output H6 LNA [U1304] (RF) + LNA

GPS External LNA Enable

[U2404] (Expansion)

GPS_LNA_IN Input L2 GPS antenna/front-end GPS RF Input from antenna

.

RF-VOCON-Exp

Interconnect

RF Board

nt

LNA Enable

3.0V

LNA

SAW SAW

LNA

External Regulators

2.8V

GPS_EXT_LNA_EN (H6)

GPS_LNA_IN (L2)

3.6V

(VSW_3.6)

VBAT VDDS

GPS IC

(VCC_1.85)

TCXO_CLK_LV (F1)

TI NL5500

GPS_UART_TX (F5)

GPS_UART_RX (E3)

GPS_NSHUTDOWN (D5)

1.8V

VDD_TCXO (G1)

RTC_CLK (H9)

Expansion Board

TCXO

26MHz,

<0.5ppm

GPS Tx
GPS Rx

32kHz RTC

Reset

[OMAP 1710]

UART2 Rx (R9)

UART2 Tx (M18)

[CPLD]

IO74 (E2)

IO91 (D12)

Figure 3-42. GPS Block Diagram (VHF/700–800 MHz)

3-62 Theory of Operation: Accelerometer

A

RF-VOCON-Exp

Interconnect

RF Board

nt

3.0V

SAW

LNA

Figure 3-43. GPS Block Diagram (UHF1 and UHF2)

3.4 Accelerometer

3.4.1 General Overview

Accelerometer capabilities are achieved by the 3-axes “nano” accelerometer IC (LIS331DL) located
on the expansion board. The LIS331DL is a digital output linear accelerometer in a LGA package. It
is powered by the 3.3 LDO regulator placed in the expansion board. The complete device includes a
sensing element and an IC interface to provide the signal to the AVR IC. When acceleration is
applied to the sensor, an imbalance in capacitance is produced. This imbalance is measured and
converted to an analog voltage that is finally available to the user by an analog to digital converter.
The acceleration data is accessed through an SPI interface and presented to the AVR.

LNA Enable

SAW SAW

LNA

External Regulators

2.8V

GPS_EXT_LNA_EN (H6)

GPS_LNA_IN (L2)

3.6V

(VSW_3.6)

VBAT VDDS

TCXO_CLK_LV (F1)

GPS IC

TI NL5500

GPS_UART_TX (F5)

GPS_UART_RX (E3)

GPS_NSHUTDOWN (D5)

1.8V

(VCC_1.85)

VDD_TCXO (G1)

RTC_CLK (H9)

Expansion Board

TCXO

26MHz,

<0.5ppm

GPS Tx
GPS Rx

32kHz RTC

Reset

[OMAP 1710]

UART2 Rx (R9)

UART2 Tx (M18)

[CPLD]

IO74 (E2)

IO91 (D12)

Figure 3-44. Directions of the Detectable Accelerations

NOTE: Please refer to User Guide and CPS for further details.

Y

Z

X

Theory of Operation: Accelerometer 3-63

3.3V LDO

Core

and

I/O

Voltage

SPI

Accelerometer

Accelerometer

LIS331DLH
(Bus Slave)

Data Bus

Interrupts

AVR

AT32UC3A

(Bus Master)

Figure 3-45. Accelerometer Block Diagram

The registers embedded on the LIS331DL are accessed through SPI serial interface. The following
pins are responsible for the SPI communication.

Table 3-14. SPI Interface

Pin Name Pin Description

CS

SPC SPI Serial Port Clock

SDI SPI Serial Data Input

SDO SPI Serial Data Output

SPI Enable

CS is the serial port enable and it is controlled by the AVR (SPI Master). It goes low at the start of the
transmission and toggles high at the end. SPC is the serial port clock and it is also controlled by the
AVR. It is stopped high when the CS is high (no transmission). SDI and SDO are respectively the
serial data input and output. These lines are driven at the falling edge of SPC and should be capture
at the rising edge of SPC.

3-64 Theory of Operation: Accelerometer

The following table provides a list of the registers and their respective addresses used for the
accelerometer IC (LIS331DL).

Table 3-15. Register Address Map

Name Type Register Address Default Comment

Hex Binary

Reserved (do not modify) 00 – 0E Reserved

WHO_AM_I r 0F 000 1111 110010 Dummy register

CTRL_REG1 rw 20 010 0000 111

CTRL_REG2 rw 21 010 0001 0

CTRL_REG3 rw 22 010 0010 0

CTRL_REG4 rw 23 010 0011 0

CTRL_REG5 rw 24 010 0100 0

HP_FILTER_RESET r 25 010 0101 Dummy register

REFERENCE rw 26 010 0110 0

STATUS_REG r 27 010 0111 0

OUT_X_L r 28 010 1000 output

OUT_X_H r 29 010 1001 output

OUT_Y_L r 2A 010 1010 output

OUT_Y_H r 2B 010 1011 output

OUT_Z_L r 2C 010 1100 output

OUT_Z_H r 2D 010 1101 output

Reserved (do not modify) 2E – 2F Reserved

INT1_CFG rw 30 011 0000 0

INT1_SOURCE r 31 011 0001 0

INT1_THS rw 32 011 0010 0

INT1_DURATION rw 33 011 0011 0

INT2_CFG rw 34 011 0100 0

INT2_SOURCE r 35 011 0101 0

INT2_THS rw 36 011 0110 0

INT2_DURATION rw 37 011 0111 0

Reserved (do not modify) 38 – 3F Reserved

NOTE: Refer to the part data sheet for a detailed explanation of the registers.

Theory of Operation: Bluetooth 3-65

3.5 Bluetooth

The Bluetooth feature allows the radio the ability to connect wirelessly to a Bluetooth accessory or
data terminal. This feature is implemented using a combination Bluetooth/GPS integrated circuit (IC,
U2401), a low-frequency receiver (NFC, U2403), and a host controller (U2415) with external 16 MB
SDRAM (U2413) located on the expansion board. The Bluetooth IC sends data to the host controller
processor over an HCI USART link. The host controller processor communicates to the OMAP
processor on the VOCON board through a dedicated USB port.

Each APX accessory that is capable of Bluetooth communication will have its own unique Bluetooth
address. An external audio accessory headset can establish a digital connection using a low-data
rate GFSK modulated signal hopping on 79 x 1 MHz wide Bluetooth channels from 2402 MHz to
2480 MHz in the ISM band. Bluetooth uses a frequency hopping spread spectrum (FHSS) technique
to spread the RF power across the spectrum to reduce the interference and spectral power density.
The frequency hopping allows the channel to change up to 1600 times a second (625 us time slot)
based on a pseudo random sequence. If a packet is not received on one channel, the packet will be
retransmitted on another channel.

The Bluetooth feature is accompanied by a Low-Frequency (LF) detection circuit. Once a radio has
the Bluetooth feature enabled, a user can tap their LF enabled Bluetooth audio accessory with the
radio at the pairing spot to establish a secure Bluetooth connection. The LF circuit provides the
ability of a secure pairing connection with a Bluetooth accessory by sending secure messages
including the BT address of the external accessory during pairing. The LF circuit uses a 125 kHz
signal to communicate the secure pairing information over a dedicated SPI bus between the
Bluetooth accessory and the AVR32 processor.

Low-frequency transmission is done by the host controller itself using a NOR gate. The Bluetooth
antenna is made of a flexible PCB and is a modified PIFA with a 2.5 dBi gain. The Bluetooth antenna
is mounted in the APX 5000/APX 6000/APX 6000XE/SRX 2200 speaker assembly:

Speaker Assembly

BT

Antenna

Speaker

&

Mic

Vocon

Board

80-pin

Expansion

Board

(BT & LF)

= Flex

= Board to Board

= Spring Contact

2-pin

4-pin

KEY

Figure 3-46. Relation of Bluetooth Antenna Assembly to Expansion Board

3-66 Theory of Operation: Bluetooth

To connect a Bluetooth accessory, the blue pairing indicators on the accessory and the radio should
be brought close to each other with the Bluetooth feature enabled and on in the radio. The
LF/Bluetooth connection flow is shown in Figure 3-47.

Radio and Accy Power Up

Not able to

re-establish pairing

Disconnect
sound

Initial NFC Pairing

If Link Breaks

Disconnect
sound

SW tries to re-establish
connection for 'x' mins.

Standby Icon (flashing)

After X min
search - BAD

Icon no longer Solid.

Module requires NFC re-pairing

With radio and accy. already on,

re-attempt pairing procedure.

b

appears.

a

Connect Sound

Able to pair

Connect
sound

appears solid

Reconnect

a

appears solid

Bad

Refer to Bluetooth pairing

flowchart and/or User Guide

Connect sound

Connected

a

appears solid

Figure 3-47. Bluetooth Connection Flowchart

Theory of Operation: Bluetooth 3-67

Bluetooth Block

SW_B+

SW_B+

OPT_BD_GPIO_0_OPT_RST

OPT_BD_GPIO_5(OMAP GPIO7)

OPT_BD_GPIO_2

OPT_BD_GPIO_4

APX 5000/
APX 6000/
APX 6000XE/
SRX2200
VOCON Board
80-pin
connector

GROUND

OMAP P18
OMAP K15

OMAP K14

CPLD GPIO 29

OPT_USB_DP

OPT_USB_DM

SSI_CLK

SSI_FSYNC

SSI_BLACK_RX

SSI_RED_RX

SSI_BLACK_TX

SSI_RED_TX

UC3_RESET
BT_PTT

USB_BOOT
AVR_STATUS_1.8

AC_SPKR_UNMUTE_1.8

OPT_BD_DETECT

BT_SPARE_1.8

VOLTAGE

TRANSLATION

1.8V - 3.3V

VOLTAGE

TRANSLATION

1.8V - 3.3V

BT_SPARE_DIR

D10
B10

E12
D11

D12

M8

J2

A2

C3

F1

RESET_N

PB17 (GPIO49)
PA20 (GPIO20)
PA21 (GPIO21)

PB07 (GPIO39)

PA2 9

PA3 0

VBUS
DP
DM

AUD_CLK

AUD_FSTNC

AUD_IN

AUD_OUT

ATMEL AVR32

AT32UC3A0512

NL5500
BT/GPS

16 MB

SDRAM

12 MHz

32.768
KHz

26 MHz TCXO

Figure 3-48. Bluetooth/Controller Interface with Clock Sources

The Bluetooth IC transceiver is connected to a dedicated Bluetooth antenna. Between the IC and
antenna is a band-pass filter as sown in is shown in Figure 3-49.

SPI0

USART1

TIMER1

GPIO

USART1 TX

TC1 OCA

GPIO

SPI

UART

TX_CLK

WAKEUP

Antenna

NFC

BLOCK

ANTENNA

LF

BT
Antenna

OMAP_GPIO7

APX 5000/ APX 6000/
APX 6000XE/ SRX2200
Expansion Board
80-PIN CONNECTOR

USB1

BT_PTT

USB

ATM EL AV R3 2

GPIO

AT32UC3A0512

USART0 GPIO

BT_HCI

BT_WAKE BT_EN

SSI

Figure 3-49. Bluetooth Functional Block Diagram

PCM_AUD

TI NL5500

Bluetooth/GPS

BT_RF

2.45 GHz BPF

3-68 Theory of Operation: Bluetooth

To verify the Bluetooth transmitter is operational, an RCMP command can be sent to transmit a
constant carrier waveform on a Bluetooth frequency. To verify the LF transmit feature is operational,
an RCMP command can be sent to transmit a constant carrier waveform at 125 kHz. There are
similar RCMP commands for verifying BT/LF RSSI when a CW BT/LF signal is applied near the
antennas of the BT/LF circuitry.

The Low-Frequency block diagram below shows the main connections:

Low-Frequency Block

ATM EL AVR32
AT32UC3A0512

NFC_UART_MAN_CLK

LF TX

Figure 3-50. Bluetooth Low-Frequency Circuit Block Diagram

SPI

UART

125 KHz Clock

UART_TX_Data

SPI0_SCK
SPI0_MOSI
SPI0_MISO

NFC_CS

NFC_INT

NFC_UART_RX

NFC_UART_TX

TC1_OCA

SCL
SDI
SDO

CS

WAKE

DAT

CL_DAT

LF RX

Low Frequency

Receiver

AS3930

LF1P

XIN

LFN

32768 Hz

Clock

LF Coil

SPI
UART

+

ANT_IN

Micro-

Processor

Figure 3-51. Bluetooth Low-Frequency Pairing Data Path

ANTENNA COIL

LF Device

CLK_IN

32 KHz

Theory of Operation: Bluetooth 3-69

32KHZ_3.3V

NFC

L2407M3

6.8 mH

1

ANTENNA

TX path

Figure 3-52. Detailed Low-Frequency Transmit/Receive Paths

3.5.1 Bluetooth Power

Our Bluetooth IC operates from a 3.6V (U6504, VBAT) switching regulator located on the VOCON
board to supply the Bluetooth IC core and a 1.85V (U6508, VDDS) supply for the I/O. It has a
shutdown (U2415 pin L3) that must be high for operation to work. The power-up/down sequence
required for operation is shown in Figure 3-53.

R2457M3
15K

C2475M3
1000PF

O/P

C2454M3

I/P

220PF

1%

R2474M3
270K

C2457M3
18PF

R2475M3
150

RX path

R2476M3

U2412M3
NL17SZ02

4

NFC_CS_INV

GPS_BT_3.3V

100K

R2477M3
100K

USART1_TX

TC1_OCA

C2465M3
1UF

12
11
13
5
4
3

CS
SDI

XIN
LFN
LFP

SCL

7

R24

15

VSS

16

1

U2403M3
AS3930
51009360002

VCC

CL_DAT

DAT

SDO

XOUT

WARE

NC1
NC2

GND

CTGND

G1

1
9

1

6
8

1
2

APX 5000/ APX 6000/
APX 6000XE/ SRX2200
Partial Current Tree

VDDS

VBAT

or

VDD1P8

RTC

Startup

(OR of

nshutdown

pins)

CLK_REQ_POL

Analog PORz (~135 RTC cycles) +

Efuse shifting (~1000 RTC cycles)

TCXO_CLK_REQ

VDD_TCXO

TCXO_CLK

REF_CLK_REQ

<2.5ms

Max 36.5 ms

Hi Z - PD

7.5V Batt

5 ms

Max time from clock request/

voltage to TCXO_CLK availability

Hi Z - PD

Figure 3-53. Chip Power-Up/Power-Down Sequence (Exernal Input/Output Shown)

3-70 Theory of Operation: Bluetooth

The host processor operates from a 3.3V LDO regulator (U2402). The 1.85V regulator enables the

3.3V LDO regulator output. The LF receiver IC is powered from a 3.3V LDO regulator (U2402).

Figure 3-54 is a partial current tree showing the flow of current from the battery to the Bluetooth-

related major components sourced by the 3.6V switching regulator on the VOCON.

7.5V Batt

SW_B+

3.6V Switcher

800mA TPS 62050

V_SW_3.60

2.23V LDO
TPS 73601

J2001 pin 11

1.85V LDO

LP38693SD

TI NL5500

BT/GPS

JTAG

AS3930A

Low Freq.

J4001 pin41

P2001 pin 41

ST LIS3331DL
Accelerometer

Logic & Level

8 x Level Shifters

1 x Inverter

Logic & Level

1 x NOR

J1001 pin 37

VSW_3.6

3.3V LDO

500mA LP2989

GPS_BT_3.3V

12 MHz OSC

AT32UC3A

AVR32

16MB SDRAM

Figure 3-54. Current Distribution Tree for Bluetooth Circuitry

VCP_IN

Vocon

Expansion

3.5.2 Bluetooth Clocks

The Bluetooth IC requires a 26 MHz TCXO (Y2204, TCXO_CLK) for the core and a 32.768 kHz
(U6101 pin E2 on vocon, RTC_CLK) slow clock for the USART. This is the same clock used for the
GPS portion of the BT/GPS combination IC.

The host processor IC requires a 12 MHz crystal oscillator (Y2475) clock. The LF receiver IC
requires a 32.768 kHz (U6101 pin E2 on vocon, RTC_CLK) clock.

Theory of Operation: Bluetooth 3-71

3.5.3 Bluetooth I/Os.

The communication between the Bluetooth IC and the host controller is by a four-wire HCI USART0
bus (RX, TX, CTS, RTS). The Bluetooth IC receives a firmware update over USART0 each time it is
powered on. The LF receiver IC transmits its data over the USART1 s used for displaying debugging
messages.

Table 3-16. Bluetooth Host Processor UART I/O

Signal Name Pad Name GPIO MUX

Function

Expansion Board

Schematic Name

USART0 – RXD PA00 0 A BT_UART_TX_3.3V I

USART0 – TXD PA01 1 A BT_UART_RX_3.3V O

USART0 – RTS PA03 3 A BT_UART_CTS_3.3V O

USART0 – CTS PA04 4 A BT_UART_RTS_3.3V I

USART1 – RXD PA05 5 A USART1_RX I

USART1 – TXD PA06 6 A USART1_TX O

USART1 – CLK PA07 7 A USART1_CLK I

USART2 – RXD PB29 61 A AVR_USART2_RX I

USART2 – TXD PB30 62 A AVR_USART2_TX O

ATMEL AVR32

Pin 19

Pin 20

Pin 12

JTAG Connector

Pin 13

Debug RX

Debug TX

AT32UC3A0512

USART2

K6

PB29

K7

PB30

USART0

PA0 0

PA0 1

PA0 3

PA0 4

USART1

PA0 5

PA0 7

J6

H6

J7

J8

K11

J10

TI NL 5500
Bluetooth/GPS

A4

HCI_TX

B5

HCI_RX

B4

HCI_CTS

B7

HCI_RTS

Low Frequency
Receiver AS3930

9

DAT

10

CL_DAT

I/O

Figure 3-55. Bluetooth LF UART Connection Block Diagram

PA0 6

L12

LF Transmit
(OR Gate)

= Level Translator. 3.3volts on AVR side

3-72 Theory of Operation: Bluetooth

The Bluetooth IC shutdown (U2415 pin L3) and wakeup (U2415 pin K3) pins are also connected to
the host controller. A Bluetooth PTT pin on the host controller (U2415 pin J2) tells the OMAP (U6302
pin Y5) when the user pressed the PTT button on the Bluetooth accessory. As the BT IC I/O is 1.8V,
but the host controller I/O is 3.3V, level shifters are employed for interconnection between the two.

The host processor IC is connected to the LF receiver IC by a four-wire SPI bus. This SPI bus also
communicates with an on-board accelerometer. The LF transmitter circuit uses a 125 kHz signal
(U2415 pin M3) that is turned on and off (OOK) by the USART1_TX signal (U2415 pin L12).

Table 3-17. SPI I/O

Signal Name Pad Name GPIO MUX

Function

SPIP – NPCS[2] PA09 9 B SPIO_CS2 O

SPIP – NPCS[0] PA10 10 A NFC_CS O

SPIP – MISO PA11 11 A SPIO_MISO I

SPIP – MOSI PA12 12 A SPIO_MOSI O

SPIP – SCK PA13 13 A SPIO_CLK O

Expansion Board
Schematic Name

I/O

The host processor is connected to the 3.3V SDRAM using a synchronous interface. The host
processor is connected to the OMAP on the vocon by a full-speed USB (D11 & D12). VBus is a
sense line only.

Table 3-18. USB I/O

Signal Name Pin Name Pad Name Expansion Board

Schematic Name

GPIO19 C12 PA19 USB_BOOT_3.3V I

GPIO20 D10 PA20 ATMEL_BOOT I

DP D11 – BT_AVR_USB_DP I/O

I/O

DM D12 – BT_AVR_USB_DM I/O

VBUS E12 – BT_AVR_VBUS I

Theory of Operation: Bluetooth 3-73

Factory Test Points

Pin 43

Pin 31

Pin 35

Pin 33

Expansion Board 80-pin Connector

APX 5000/ APX 6000/ APX 6000XE/ SRX2200

USB_BOOT

Pin 15

Pin 3

Pin 2

JTAG Connector

ATMEL_BOOT

= Level Translator. 3.3 volts on AVR side

C12

E12

D11

D12

D10

ATMEL AVR32
AT32UC3A0512

PA19

VBUS

DP

DM

PA20

USB

Figure 3-56. Bluetooth USB Interface Too Main VOCON

The ATMEL bootloader is being used as a first stage bootloader that will jump to the Motorola
bootloader, which is a stage two bootloader. GPIO20 is used by the ATMEL bootloader to trap in
Flash mode. GPIO19 will be used by the Motorola bootloader to trap in Flash mode. Both pins are
active low.

The Bluetooth audio is sent over a two-channel PCM/SSI interface to the audio codec (U6405) on
the VOCON board.

Table 3-19. GPIO I/O

Signal Name Pad Name GPIO Expansion Board

Schematic Name

GPIO41 PB09 41 BT_HOST_WAKEUP_3.3V I

GPIO49 PB17 49 BT_PTT_3.3V O

GPIO50 PB18 50 BT_SHUTDOWN_3.3V O

GPIO51 PB19 51 BT_WAKEUP_3.3V O

I/O

3-74 Theory of Operation: Bluetooth

Notes