Datasheet 56F803 Datasheet (MOTOROLA)

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Freescale Semiconductor, Inc.

Technical Data

56F803 16-bit Hybrid Controller

DSP56F803/D

Rev. 13.0, 02/2004

56F803

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• Up to 40 MIPS at 80MHz core frequency

• DSP and MCU functionality in a unified,
C-efficient architecture

• Hardware DO and REP loops

• MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes

•31.5K

• 512

•4K

•2K

•2K

6

3
3

4
4

4

2
2

2

4

× 16-bit words Program Flash

× 16-bit words Program RAM
× 16-bit words Data Flash
× 16-bit words Data RAM
× 16-bit words Boot Flash

PWM Outputs
Current Sense Inputs
Fault Inputs

A/D1
A/D2

ADC

VREF

Quadrature
Decoder 0 /

Quad Timer A

Quad Timer B
Quad Timer C

Quad Timer D

CAN 2.0A/B

SCI

or

GPIO

SPI

or

GPIO

*includes TCS pin which is reserved for factory use and is tied to VSS

PWMA

Interrupt

Controller

Program Memory
32252 x 16 Flash

512 x 16 SRAM

Boot Flash

2048 x 16 Flash

Data Memory

4096 x 16 Flash

2048 x 16 SRAM

COP/

Watchdog

Application-

Specific

Memory &

Peripherals

RESET

IRQB

IRQA

Program Controller

and

Hardware Looping Unit

•

•

•

COP RESET

MODULE CONTROLS

ADDRESS BUS [8:0]

DATA BUS [15:0]

EXTBOOT

PAB
PDB

XDB2
CGDB
XAB1
XAB2

6

JTAG/
OnCE

Port

Address

Generation

Unit

•

•

INTERRUPT
CONTROLS

IPBus Bridge

• Up to 64K

× 16-bit words each of external

Program and Data memory

• 6-channel PWM module

• T w o 4-channel 12-b it ADCs

• Quadrature Decoder

• CAN 2.0 B module

• Serial Communication Interface (SCI)

• Serial Peripheral Interface (SPI)

• Up to two General Purpose Quad Timers

•JTAG/OnCE

TM

port for debugging

• 16 shared GPIO lines

• 100–pin LQFP package

VCAPC VDDVSSV

26 6*

Digital Reg

Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers

Two 36-bit Accumulators

Low Voltage

Supervisor

16-Bit
56800

Core

DDAVSSA

Analog Reg

Manipulation

Clock Gen

Bit

Unit

PLL

•

•

•

IPBB

CONTROLS

16 16

(IPBB)

External

Bus

Interface

Unit

External

Address Bus

Switch

External

Data Bus

Switch

Bus

Control

6

10

16

CLKO

XTAL
EXTAL

A[00:05]
A[06:15] or

GPIO-E2:E3 &
GPIO-A0:A7

D[00:15]
PS Select

DS Select
WR Enable
RD Enable

© Motorola, Inc., 2004. All rights reserved.

Figure 1. 56F803 Block Diagram

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Part 1 Overview

1.1 56F803 Features

1.1.1 Digital Signal Processing Core

• Efficient 16-bit 56800 family hybrid controller engine with dual Harvard architecture

• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency

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• Single-cycle 16

• Two 36

• 16

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Three internal address buse s and one external addre ss bus

• Four internal data buses and one external data bus

• Instruction set supports both DSP and controller functions

• Controller style addressing modes and instructions for compact code

• Efficient C compiler and local variable sup port

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/OnCE debug programming interface

-bit accumulators, including extension bits

-bit bidirectional barrel shifter

× 16-bit parallel Multiplier-Accumulator (MAC)

1.1.2 Memory

• Harvard archi tecture permits as many as thr ee simulta neous access es to Progra m and Data memory

• On-chip memory including a low-cost, high-volume Flash solution
— 31.5K
— 512K
— 4K
— 2K
— 2K

• Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states

× 16-bit words of Program Flash

× 16-bit words of Program RAM
× 16-bit words of Data Flash
× 16-bit words of Data RAM
× 16-bit words of Boot Flash

— As much as 64K
— As much as 64K

× 16 bits of Data memory
× 16 bits of Program memory

1.1.3 Peripheral Circuits for 56F803

• Pulse Width Modulator module (PWM) with six PWM outputs, three Current Sense inputs, and
three Fault inputs, fault-tolerant design with dead time insertion, supports both center- and edge­aligned modes, supports Motorola’s patented dead time distortion correction

• Two 12
ADC and PWM modules can be synchronized

• Quadrature Decoder with four inputs (shares pins with Quad Timer )

2 56F803 Technical Data

-bit Analog-to-Digital Converters (ADCs), which support two simultaneous conversions;

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• Four General Purpose Quad T imers: T imer A (sharing pins with Quad Dec0), T imers B &C wit hout
external pins and Timer D with two pins

• CAN 2.0 B module with 2-pin ports for transmit and receive

• Serial Communication Interface (SCI) with two pins (or two additional GPIO lines)

• Serial Peripheral Interface (SPI) with configurable 4-pin port (or four additional GPIO lines)

• Computer Operating Properly (COP) Watchdog timer

• Two dedicated external interrupt pins

• Sixteen multiplexed General Purpose I/O (GPIO) pins

• External reset input pin for hardware reset

• JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging

• Software -programmable, Phase Locked Loo p-based frequenc y synthesizer for the hy brid controller
core clock

56F803 Description

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1.1.4 Energy Information

• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digit al inputs

• Uses a single 3.3V power supply

• On-chip regulators for digita l and analog c i rcuitry to lower cost and reduce noise

• Wait and Stop modes available

1.2 56F803 Description

The 56F803 is a member of the 56800 core-b ased family of hybrid contr ollers. It combines, on a singl e chip,
the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals
to create an extremely cost-effective solution. Because of its low cost, configuration flexibility , and compact
program code, the 56F803 is well-su ited for many ap plicati ons. The 56F803 inc ludes many periph erals tha t
are especially useful for applications such as motion control, smart appliances, steppers, encoders,
tachometers, limit switches, power supply and control, automotive control, engine management, noise
suppression, remote utility metering, and industrial control for power, lighting, and automation.

The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six opera tions per inst ructi on cycle . The MCU-style programmi ng model and
optimized instruc tion se t allo w straight forw ard gene rati on of ef f icien t, compact DSP and co ntrol code. The
instruction set is also highly efficient for C compilers to enable rapid development of optimized control
applications.

The 56F803 supports pro gra m e xec uti on from either internal or external memories . Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F803 also provides two external
dedicated interrup t lines, a nd up to 16 Gen eral Pu rpose Inpu t/Output ( GPIO) line s, depending on periphe ral
configuration.

The 56F803 controller includes 31.5K words (16-bit) of Program Flash and 4K words of Data Flash (each
programmable through the JTAG port) with 512 words of Program RAM and 2K words of Data RAM. It
also supports program execution from external memory.

A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable
software routines that can be used to program the main Program and Data Flash memory areas. Both

56F803 Technical Data 3

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Program and Data Flash memories can be inde pendently bulk–erased or eras ed i n page siz es of 256 word s.
The Boot Flash memory can also be either bulk- or page

A key application-specific feature of the 56F803 is the inclusion of a Pulse Width Modulator (PWM)
module. This module incorporates three complementary, individually programmable PWM signal outputs
(the module is also capable of suppor ting three i ndependent PWM functi ons, for a to tal of six PWM outpu ts)
to enhance motor control functionality. Complementary operation permits programmable dead time
insertion, distor tion co rrect ion via current sensin g by sof tware, an d separa te top and bottom outp ut pol arit y
control. The up-counter value is programmable to support a continuously variable PWM frequency. Edge­and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The device is
capable of controlling most motor types: ACIM (AC Induction Motors), both BDC and BLDC (Brush and
Brushless DC motors), SRM and VR M (Switch ed and Variable Reluctance Mot ors), and s tepper mo tors.
The PWM incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive
capability to direc tly drive st andard opto-i solators. A “smoke-inhibit”, write-o nce protecti on feature f or key
parameters and patented PWM waveform distortion correction circuit are also provided. The PWM is
double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1

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to 16. The PWM module provides a reference output to synchronize the ADC.
The 56F803 incorpor ates a separa te Quadrature Decode r capable o f capturing all four transit ions on the two -

phase inputs, permitting generation of a number proportional to actual position. Speed computation
capabilities accommodate both fast and slow moving shafts. The integrated watchdog timer in the
Quadratur e Deco de r can be pr ogr amm ed wit h a tim e-out valu e to ala rm wh en no sh aft motio n is det ect ed.
Each input is filtered to ensure only true transitio ns are recorded.

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This controller also provides a full set of standard programmable peripherals that include a Serial
Communications Inte rface (S CI), one Serial Peripher al Inte rface (S PI), an d four Qua d T imer s. Any of t hese
interfaces can be used as General Purpose Input/Outputs (GPIO) if that function is not required. A
Controller Area Network interface (CAN Version 2.0 A/B-compliant) and an internal interrupt controller
are also included on the 56F803.

1.3 State of the Art Development Environment

• Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to­use component-based software application creation with an expert knowledge system.

• The Code Warrior Integrated Deve lopment Enviro nment is a sophi sticated to ol for code na vigation,
compiling, and debuggi ng. A complete set of ev aluation modules ( EVMs) and development s ystem
cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a
complete, scalable tools solution for easy, fast, and efficient development.

4 56F803 Technical Data

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Product Documentation

1.4 Product Documentation

The four docu ments listed in Table 1 are required for a complete description and proper design with the
56F803. Documentation is available from local Motorola distributors, Motorola semiconductor sales
offices, Motorola Literature Distribution Centers, or online at www.motorola.com/semiconductors.

Table 1. 56F803 Chip Documentation

Topic Description Order Number

DSP56800
Family Manual

DSP56F801/803/805/
807 User’s Manual

56F803
Technical Data Sheet

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56F803
Product Brief

56F803
Errata

1.5 Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR

“asserted” A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.

cale Semiconductor,

Examples: Signal/Symbol Logic State Signal State

This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.

Detailed description of the 56800 family architecture, and
16-bit core processor and the instruction set

Detailed description of memory, peripherals, and interfaces
of the 56F801, 56F803, 56F803, and 56F807

Electrical and timing specifications, pin descriptions, and
package descriptions (this document)

Summary descripti on and bl ock diag ram of the 56F803 c ore,
memory, p eripherals and interfaces

Details any chip issues that might be pres en t DSP56F803E/D

PIN

True Asserted VIL/V

DSP56800FM/D

DSP56F801-7UM/D

DSP56F803/D

DSP56F803PB/D

Voltage

OL

1

Frees

PIN False Deasserted VIH/V

PIN True Asserted VIH/V

PIN False Deasserted VIL/V

1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

56F803 Technical Data 5

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OH

OH

OL

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Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F803 are organized into functional groups, as shown in Table 2 and
as illustrated in Figure 2. In Table 3 through Table 18, each table row describes the signal or signals
present on a pin.

Table 2. Functional Group Pin Allocations

Functional Group

Power (V

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Ground (VSS or V

Supply Capacitors 2 Table 5
PLL and Clock 3 Table 6

Address Bus
Data Bus 16 Table 8
Bus Control 4 Table 9
Interrupt and Program Control 4 Table 10
Pulse Width Modulator (PWM) Port 12 Table 11

Serial Peripheral Interface (SPI) Port

Quadrature Decoder Port

Serial Communications Interface (SCI) Port
CAN Port 2 Table 15

DD

or V

1

)7Table 3

DDA

)7Table 4

SSA

1

2

1

Number of

Pins

16 Table 7

4 Table 12

4 Table 13

2 Table 14

Detailed

Description

Frees

Analog to Digital Converter (ADC) Port 9 Table 16
Quad Timer Module Port 2 Table 17
JTAG/On-Chip Emulation (OnCE) 6 Table 18

1. Alternately, GPIO pi ns

2. Alternatel y, Q ua d Tim e r pins

6 56F803 Technical Data

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Power Port

Ground Port

Power Port

Ground Port

Other

Supply

Ports

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Introduction

V

DD

V

SS

V

DDA

V

SSA

VCAPC

6
6*
1
1

2

6
3
3

PWMA0-5
ISA0-2
FAULTA0-2

PWMA
Port

PLL

and

Clock

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External

Address Bus or

GPIO

External

Data Bus

External

Bus Control

Quadrature

Decoder or

Quad Timer A

A6-7 (GPIOE2-E3)

A8-15 (GPIOA0-A7)

PHASEA0 (TA0)
PHASEB0 (TA1)

cale Semiconductor,

EXTAL

XTAL

CLKO

A0-A5

D0–D15

PS
DS

RD

WR

INDEX0 (TA2)
HOME0 (TA3)

1
1
1

6
2
8

16

1
1
1
1

1
1
1
1

56F803

1
1
1
1

1
1

8
1

1
1

SCLK (GPIOE4)
MOSI (GPIOE 5)
MISO (GPIOE6)
SS

(GPIOE7)

TXD0 (GPIOE0)
RXD0 (GPIOE1)

ANA0-7
VREF

MSCAN_RX
MSCAN_TX

SPI Port
or GPIO

SCI0 Port
or GPIO

ADCA
Port

CAN

Frees

TCK

TMS

JTAG/OnCE

*includes TCS pin which is reserved for factory use and is tied to VSS



Port

TDI

TDO

TRST

DE

1
1
1
1
1
1

2

1
1
1
1

TD1-2

IRQA
IRQB
RESET
EXTBOOT

Figure 2. 56F803 Signals Identified by Functional Group

1. Alternate pin functionality is shown in parenthesis.

56F803 Technical Data 7

Quad
Timer D

Interrupt/
Program
Control

1

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2.2 Power and Ground Signals

Table 3. Power Inputs

No. of Pins Signal Name Signal Description

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6 V

1 V

DD

DDA

Power—These pins provide power to the internal structures of the chip, and

should all be attached to V

Analog Power—This pin is a dedicate d powe r pin for the analog portion of the
chip and should be connected to a low noise 3.3V supply.

DD.

Table 4. Grounds

No. of Pins Signal Name Signal Description

5 V

1 V

1 TCS TCS—This Schmitt pin is reserved for factory use and must be tied to VSS for

GND—These pins provide grounding for the internal structures of the chip, and

SS

SSA

should all be attached to V

Analog Ground—This pin supplies an analog ground.

normal use. In block diagrams, this pin is considered an additional V

SS.

Table 5. Supply Capacitors

No. of

Pins

2 VCAPC Supply Supply VCAPC—Connect each pin to a 2.2 µF or greater bypass

Signal

Name

Signal

Type

State During

Reset

Signal Description

capacitor in order to bypass the core logic voltage regulator
(required for proper chip operation). For more information, please
refer to Section 5.2.

2.3 Clock and Phase Locked Loop Signals

Table 6. PLL and Clock

No. of

Pins

1 EXTAL Input Input External Crystal Oscillator Input—This input should be

Signal

Name

Signal

Type

State During

Reset

Signal Description

connected to an 8MHz exte rnal crystal or cera mic resonator. For
more information, please refer to Section 3.5.

SS.

1 XTAL Input/

Output

8 56F803 Technical Data

Chip-driven Crystal Oscillator Output —This output shou ld be conne cted to

an 8MHz external crystal or ceramic resonator. For more
information, please refer to Section 3.5.

This pin can also be connected to an external clock source. For
more information, please refer to Section 3.5.3 .

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Address, Data, and Bus Control S ignals

Table 6. PLL and Clock (Continued)

No. of

Pins

1 CLKO Output Chip-driven Clock Output—This pin outputs a buffered clock signal. By

Signal

Name

Signal

Type

State During

Reset

Signal Description

programming the CLKOSEL[4:0] bits in the CLKO Select
Register (CLKOSR), the user can select between outputting a
version of the signal applied to XTAL and a version of the
device’s master clock at the output of the PLL. The clock
frequency on this pin can also be disabled by programming the
CLKOSEL[4:0] bits in CLKOSR.

2.4 Address, Data, and Bus Control Signals

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No. of

Pins

6 A0–A5 Output Tri-stated Address Bus—A0–A5 specify the address for external Program

2 A6–A7

8 A8–A15

Signal

Name

GPIOE2–

GPIOE3

GPIOA0

GPIOA7

–

Signal

Type

Output

Input/

Output

Output

Input/

Output

Table 7. Address Bus Signals

State During

Reset

or Data memory accesses.

Tri-stated

Input

Tri-stated

Input

Address Bus—A6–A7 specify the address for external Program
or Data memory accesses.

Port E GPIO—These two pins are General Pu rpose I/O (GPIO)
pins that can be i ndi vi dua lly programmed as in put or output pins.

After reset, the default state is Address Bus.
Address Bus—A8–A15 specify the address for external

Program or Da ta memory accesses.
Port A GPIO—These eight p ins are Genera l Purpose I/O (GPIO)

pins that can be i ndi vi dua lly programmed as in put or output pins.
After reset, the default state is Address Bus.

Signal Description

Frees

Table 8. Data Bus Signals

No. of

Pins

16 D0–D15 Input/

56F803 Technical Data 9

Signal

Name

Signal

Type

Output

State During

Reset

Tri-stated Data Bus— D0–D15 specify the data for external Program or

Data memory accesses. D0–D15 are tri-stated when the
external bus is inactive. Internal pull-ups may be active.

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Signal Description

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Table 9. Bus Control Signals

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No. of

Pins

1 PS

1 DS

1 WR

1 RD

Signal

Name

Signal

Type

Output Tri-stated Program Memory Select—PS is asserted low for ex tern al Progra m

Output Tri-stated Data Memory Select—DS is asserted low for external Data memory

Output Tri-stated Write Enable—WR is asse rted during external memory w rite cycles .

Output Tri-stated Read Enable—RD is asserted during external memory read cycles.

State During

Reset

Signal Description

memory access.

access.

When WR
device puts data on the bus. When WR
external data is latched inside the external device. When WR
asserted, it qualifies the A0–A15, PS
connected directly to the WE

When RD
external device is enabled onto the device data bus. When RD
deasserted high, the external data is latched inside the hybrid
controller. When RD is asserted, it qualifies the A0–A15, PS, and DS
pins. RD
ROM.

is asserted low, pins D0–D15 become outputs and the

pin of a Static RAM.

is asserted low, pins D0–D15 become inputs and an

can be connected directly to the OE pin of a Static RAM or

2.5 Interrupt and Program Control Signals

Table 10. Interrupt and Program Control Signals

No. of

Pins

1 IRQA

1 IRQB Input

Signal

Name

Signal

Type

Input

(Schmitt)

(Schmitt)

State During

Reset

Input External Interrupt Request A—The IRQA input is a

synchronized external interrupt request indicating an
external device is requesting service. It can be programmed
to be level-sensitive or negat iv e-ed ge- trig gered.

Input External Interrupt Request B—The IRQB input is an

external interrupt request indicating an external device is
requesting service. It can be programmed to be level­sensitive or negative-edge-triggered.

Signal Description

is deasserted high, the

is

, and DS pins. WR can be

is

10 56F803 Technical Data

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Pulse Width Modulator (PWM ) Signals

Table 10. Interrupt and Program Control Signals (Continued)

No. of

Pins

1 RESET Input

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1 EXTBOOT Input

Signal

Name

Signal

Type

(Schmitt)

(Schmitt)

State During

Reset

Input Reset—This input is a direct hardware reset on the

processor. When RESET
controller is initialized and placed in the Reset state. A
Schmitt trigger input is used for noise immunity. When the
RESET
latched from the EXTBO OT pin . The int ernal re set signa l will
be deasserted synchronous with the internal clocks, after a
fixed number of internal clocks.

To ensure a complete hardware reset, RESET
should be asserted together. The only exception occurs in a
debugging environment when a hardware device reset is
required and it is necess ary not to reset the OnCE/JTAG
module. In this c ase, as se rt RESET

Input External Boot—This input is tied to V

boot from off-chip memory. Otherwise, it is tied to VSS.

pin is deasserted, the initial chip operating mode is

Signal Description

is asserted low, the hybrid

, but do not asse rt TRST.

DD

to force device to

and TRST

2.6 Pulse Width Modulator (PWM) Signals

Table 11. Pulse Width Modulator (PWMA) Signals

No. of

Pins

6
3

cale Semiconductor,

3

Signal

Name

PWMA0

ISA0–2

FAULTA0

–5

Signal

Type

Output Tri-stated

Input

(Schmitt)

–2

Input

(Schmitt)

State During

Reset

Input

Input

Signal Description

PWMA0–5— These are six PWMA output pins.
ISA0–2— These three input current s tatu s pi ns are u sed for

top/bottom pulse widt h corre ction in co mplem entary chan nel
operation for PWMA.

FAULTA0–2— These three fault input pins are used for
disabling selected PWMA outputs in cases where fault
conditions originate off-chip.

Frees

56F803 Technical Data 11

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2.7 Serial Peripheral Interface (SPI) Signals

Table 12. Serial Peripheral Interface (SPI) Signals

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No. of

Pins

1 MISO

1 MOSI

1 SCLK

1 SS

Signal

Name

GPIOE6

GPIOE5

GPIOE4

GPIOE7

Signal

Type

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input/

Output

Input

Input/

Output

State During

Reset

Input

Input

Input

Input

Input

Input

Input

Input

Signal Description

SPI Master In/Slave Out (MISO)—This serial data pin is an

input to a master device and an output from a slave device.
The MISO line of a slave device is placed in the high
impedance state if the slave device is not selected.

Port E GPIO—This General Purpose I/O (GPIO) pin can be
individually programmed as an input or output pin.

After reset, the default state is MISO.
SPI Master Out/Slave In (MOSI)—This serial data pin is an

output from a master device and an input to a slave device.
The master device places data on the MOSI line a half-cycle
before the clock edge that the slave device uses to latch the
data.

Port E GPIO—This General Purpose I/O (GPIO) pin can be
individually programmed as an input or output pin.

After reset, the default state is MOSI.
SPI Serial Clock—In master mode, this pin serves as an

output, clocking slaved listeners. In slave mode, this pin
serves as the data clock input.

Port E GPIO—This General Purpose I/O (GPIO) pin can be
individually programmed as an input or output pin.

After reset, the default state is SCLK.
SPI Slave Select—In master mode, this pin is used to

arbitrate multiple masters. In slave mode, this pin is used to
select the slave.

Port E GPIO—This General Purpose I/O (GPIO) pin can be
individually programmed as an input or output pin.

After reset, the default state is SS

.

12 56F803 Technical Data

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Quadrature Decoder Signals Serial Communications

2.8 Quadrature Decoder Signals Serial Communications

Table 13. Quadrature Decoder (Quad Dec0) Signals

No. of

Pins

1 PHASEA0

1 PHASEB0

1 INDEX0

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1 HOME0

Signal

Name

TA0

TA1

TA2

TA3

Signal

Type

Input

Input/Output

Input

Input/Output

Input

Input/Output

Input

Input/Output

State During

Reset

Input
Input
Input
Input
Input
Input
Input
Input

Signal Description

Phase A—Quadrature Decoder #0 PHASEA input
TA0—Timer A Channel 0
Phase B—Quadrature Decoder #0 PHASEB input
TA1—Timer A Channel 1
Index—Quadrature Decoder #0 INDEX input
TA2—Timer A Channel 2
Home—Quadrature Decoder #0 HOME inpu t
TA3—Timer A Channel 3

2.9 Interface (SCI) Signals

Table 14. Serial Communications Interface (SCI0) Signals

No. of

Pins

1 TXD0

cale Semiconductor,

1 RXD0

Signal

Name

GPIOE0

GPIOE1

Signal Type

Output

Input/Output

Input

Input/Output

State During

Reset

Input
Input

Input
Input

Signal Description

Transmit Data (TXD0)—SCI0 transmit data output
Port E GPIO—This General Purpose I/O (GPIO) pin can

be individually programmed as an input or output pin.
After reset, the default state is SCI output.

Receive Data (RXD0)— SCI0 receive data input
Port E GPIO—This General Purpose I/O (GPIO) pin can

be individually programmed asan input or output pin.

Frees

After reset, the default state is SCI input.

2.10 CAN Signals

Table 15. CAN Module Signals

No. of

Pins

1 MSCAN_ RX Input

1 MSCAN_ TX Output Output MSCAN Transmit Data—MSCAN output. CAN output is

56F803 Technical Data 13

Signal

Name

Signal

Type

(Schmitt)

State During

Reset

Input MSCAN Receive Data—This is the MSCAN input. This

pin has an internal pull-up resistor.

open-drain output and a pull-up resistor is needed.

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Signal Description

Freescale Semiconductor, Inc.

2.11 Analog-to-Digital Converter (ADC) Signals

Table 16. Analog to Digital Converter Signals

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cale Semiconductor,

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No. of

Pins

4
4
1 VREF Input Input VREF—Analog reference voltage for ADC. Must be set to

Signal

Name

–3

ANA0
ANA4–7

Signal

Type

Input Input
Input Input

State During

Reset

Signal Description

ANA0–3—Analog inputs to ADC channel 1
ANA4–7—Analog inputs to ADC channel 2

V

-0.3V for optimal performance.

DDA

2.12 Quad Timer Module Signals

Table 17. Quad Timer Module Signals

No. of Pins Signal Name Signal Type State During Reset Signal Description

2

TD1

–2

Input/Output Input

TD1–2— Timer D Channel 1–2

2.13 JTAG/OnCE

Table 18. JTAG/On-Chip Emulation (OnCE) Signals

No. of

Pins

1 TCK Input

1 TMS Input

1 TDI Input

1 TDO Output Tri-stated Test Data Output—This tri-statable output pin provides a serial

Signal

Name

Signal

Type

(Schmitt)

(Schmitt)

(Schmitt)

State During

Reset

Input, pulled lo w

internally

Input, pulled

high internally

Input, pulled

high internally

Signal Description

Test Clock Input—This input pin provides a gated clock to

synchronize the test logic and shift serial data to the JTAG/OnCE
port. The pin is connected internally to a pull-down resistor.

Test Mode Select Input—This input pin is used to se quence the
JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.

Test Data Input—This input pin provides a serial input data
stream to the JTAG/OnCE port. It is sampled on the rising edge
of TCK and has an on-chip pull-up resistor.

output data stream from the JTAG/OnCE port. It is driven in the
Shift-IR and Shift-DR con troller stat es, and chang es on the fa lling
edge of TCK.

1 TRST

1 DE

14 56F803 Technical Data

Input

(Schmitt)

Output Output Debug Event—DE provides a low pulse on recognized debug

Input, pulled

high internally

Test Reset—As an inpu t, a low signal on this pin provides a reset
signal to the JTAG TAP controller. To ensure complet e hardware
reset, TRST should be asserted at power-up and whenever

is asserted. The only exception occurs in a debugging

RESET
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case,
assert RESET

events.

, but do not assert TRST.

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General Characteristics

Part 3 Specifications

3.1 General Characteristics

The 56F803 is fabrica ted in high-de nsity CMOS with 5- V tolerant TTL-c ompatible d igital i nputs. The te rm
“5-V tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to
withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V-compatible
I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V
normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.

Absolute maximum ratings given in Table 19 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.

± 10% during

nc...

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cale Semiconductor,

Frees

The 56F803 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.

CAUTION

This device contains protective circuitry to guard against damage due
to high static voltage or electrical fields. However, normal precautions
are advised to avoid application of any voltages higher than maximum
rated voltages to this high-impedance circuit. Reliability of operation is
enhanced if unused inputs are tied to an appropriate voltage level.

Table 19. Absolute Maximum Ratings

Characteristic Symbol Min Max Unit

Supply voltage V

All other input voltages, excluding Analog inputs V

DD

IN

V

– 0.3 V

SS

VSS – 0.3 V

+ 4.0 V

SS

+ 5.5V V

SS

Analog inputs ANA0-7 and VREF V

Analog inputs EXTAL and XTAL V

Current drain per pin excluding VDD, VSS, PWM outputs, TCS,
VPP, V

56F803 Technical Data 15

DDA

, V

SSA

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IN

IN

I — 10 mA

V

V

SSA

SSA

– 0.3 V

– 0.3 V

+ 0.3 V

DDA

+ 3.0 V

SSA

Freescale Semiconductor, Inc.

Table 20. Recomended Operating Conditions

Characteristic Symbol Min Typ Max Unit

Supply voltage, digital V

Supply Voltage, analog V

ADC reference voltage VREF 2.7 – V

Ambient operating temperature T

DD

DDA

A

Table 21. Thermal Characte rist ic s

nc...

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Junction to ambient
Natural convection

Junction to ambient (@1m /se c) R
Junction to ambient

Natural convection
Junction to ambient (@1m /se c) Four layer board (2s2p) R
Junction to case R
Junction to center of case Ψ
I/O pin power dissipation P
Power dissipation P

cale Semiconductor,

Junction to center of case P

Characteristic

Notes:

Comments

Four layer board (2s2p) R

3.0 3.3 3.6 V

3.0 3.3 3.6 V

DDA

–40 – 85 °C

6

Value

Symbol

100-pin LQFP

R

θJA

θJMA

θJMA

(2s2p)

θJMA

θJC

JT

I/O

D

DMAX

P D = (IDD x VDD + P

41.7 °C/W 2

37.2 °C/W 2

34.2 °C/W 1,2

32 °C/W 1,2

10.2 °C/W 3

0.8 °C/W 4, 5

User Determined W

)W

I/O

(TJ - TA) /θJA

V

Unit Notes

°C

Frees

1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.
Determined on 2s2p thermal test board.

2. Junction to ambient thermal resistance, Theta-JA (R
JEDEC specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was

also simulated on a thermal test board with two internal planes (2s2p where “s” is the number of
signal layers and “p” is the number of planes) per JESD51-6 and JESD51-7. The correct name for
Theta-JA for forced convection or with the non-single layer boards is Theta-JMA.

3. Junction to case thermal resistance, Theta-JC (R
measured values using the cold plate technique with the cold plate temperature used as the “case”

temperature. The basic cold plate measurement technique is described by MIL-STD 883D, Metho d

1012.1. This is the correct thermal m etric to use to calculate thermal perf ormance when the p ackage
is being used with a heat sink.

4. Thermal Characterization Parameter, Psi-JT (
point thermocouple on top center of case as defined in JESD51-2.
estimate junction temperature in steady state customer environments.

16 56F803 Technical Data

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Ψ

JT

) was simulated to be equivalent to the

θJA

), was simulated to be equivalent to the

θJC

), is the “resistance” from junction to reference

Ψ

is a useful value to use to

JT

Freescale Semiconductor, Inc.

DC Electrical Characteristic

5. Junction temperature is a function of on-ch ip po wer dissipatio n, pa c kag e therm al resistanc e, mo un tin g site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and
board thermal resistance.

See Section 5.1 from more details on thermal design considerations.

6.

3.2 DC Electrical Characteristic

Table 22. DC Electrical Characteristics

nc...

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cale Semiconductor,

Frees

Operating Conditions: V

Characteristic Symbol Min Typ Max Unit

Input high voltage (XTAL/EXTAL) V
Input low voltage (XTAL/EXTAL) V

Input high voltage (Schmitt trigger inputs)
Input low voltage (Schmitt trigger inputs)

Input high voltage (all other digital inputs) V
Input low voltage (all other digital inputs) V
Input current high (pullup/pulldown resistors

disabled, VIN=VDD)
Input current low (pullup/pulldown resistors

disabled, V
Input current high (with pullup resistor, V
Input current low (with pullup resistor, V
Input current high (with pulldown resistor, V
Input current low (with pulldown resistor, V
Nominal pullup or pulldown resistor value R
Output tri-state current low I
Output tri-state current high I

Input current high (analog inputs, VIN=V

IN=VSS

)

SS

= V

= 0 V, VDD = V

SSA

= 3.0–3.6 V, TA = –40° to +85°C, C

DDA

1

1

)I

IN=VDD

)I

IN=VSS

)I

IN=VDD

)I

IN=VSS

2

)

DDA

V
V

PU

IHC

ILC

IHS

ILS

IH

IL

I

IH

I

IL

IHPU

ILPU

IHPD

ILPD

, R

OZL

OZH

I

IHA

PD

≤ 50pF, f

L

2.25 — 2.75 V
0 — 0.5 V

2.2 — 5.5 V

-0.3 — 0.8 V

2.0 — 5.5 V

-0.3 — 0.8 V

-1 — 1 µA

-1 — 1 µA

-1 — 1 µA

-210 — -50 µA

20 — 180 µA

-1 — 1 µA
30 KΩ

-10 — 10 µA

-10 — 10 µA

-15 — 15 µA

= 80MHz

op

2

Input current low (analog inputs, V
Output High Voltage (at IOH) V
Output Low Voltage (at IOL) V
Output source current I
Output sink current I

PWM pin output source current
PWM pin output sink current

56F803 Technical Data 17

IN=VSSA

3

4

)

I

ILA

OH

OL

I

OHP

I

OLP

OH

OL

-15 — 15 µA

VDD – 0.7 —— V

——0.4 V

4 ——mA

4 ——mA
10 ——mA
16 ——mA

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Table 22. DC Electrical Characteristics (Continued)

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cale Semiconductor,

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Operating Conditions: V

Characteristic Symbol Min Typ Max Unit

Input capacitance C
Output capacitance C
V

supply current

DD

6

Run

7

Wait

Stop — 60 84 mA
Low Voltage Interrupt, external power supply
Low Voltage Interrupt, internal power supply
Power on Reset

1. Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, ISA0-2, FAULTA0-3, TCS, TCK, TRST, TMS,
TDI, and MSCAN_RX

2. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.

3. PWM pin output source current measured with 50% duty cycle.

4. PWM pin output sink current measured with 50% duty cycle.

5. I

DDT

6. Run (operating) IDD measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports
configured as inputs; measured with all modules enabled.

7. Wait IDD measured using e xter nal squa re w ave clock so urce (f
no DC loads; less than 50pF o n all outputs. C
linearly affects wait I

8. This low-voltage interrupt monitors the V
potential as V
guaranteed under transient conditions when V
V

interrupt is generated).

EIO

9. This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal
voltage is regulator drops below V
interrupt will not be generated unless the external power supply drops below the minimum specified value (3.0V).

10. Power–on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While
power is ramping up, this signal remains active as long as the internal 2.5V is below 1.5V typical, no matter how long
the ramp-up rate is. The internally regulated voltage is typically 100mV less than VDD during ramp-up, until 2.5V is
reached, at which time it self-regulates.

10

= IDD + I

via separate traces. If V

DD

= V

SS

(Total supply current for VDD + V

DDA

; measured with PLL enabled.

DD

= 0 V, VDD = V

SSA

8

9

= 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance

L

DDA

drops below V

DDA

DDA>VEIO

, an interrupt is generated. Since the core logic supply is internally regulated, this

EIC

= 3.0–3.6 V, TA = –40° to +85°C, C

DDA

IN

OUT

5

I

DDT

V

EIO

V

EIC

V

POR

)

DDA

= 8MHz) into XTAL; all inputs 0.2V from rail;

osc

external power s upply. V

, an interrupt is generated. Functiona lity of th e devic e is

EIO

(between the minimum specified VDD and the point when the

— 8 — pF
— 12 — pF

— 126 152 mA
— 105 129 mA

2.4 2.7 3.0 V

2.0 2.2 2.4 V
— 1.7 2.0 V

is generally connected to the same

DDA

≤ 50pF, f

L

op

= 80MHz

18 56F803 Technical Data

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180

150

120

90

IDD (mA)

60

Freescale Semiconductor, Inc.

IDD Digital

IDD Analog

IDD Total

AC Electrical Characteristics

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cale Semiconductor,

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30

0

20

40

Freq. (MHz)

Figure 3. Maximum Run IDD vs. Frequency (see Note 6. in Table 16)

3.3 AC Electrical Characteristics

Timing waveforms in Section 3.3 ar e tested us ing the VIL and V
table. In Figure 4 the levels of V

Input Signal

Note: The midpoint is VIL + (VIH – VIL)/2.

Midpoint1

Fall Time

and VIL for an input signal are shown.

IH

V

IH

Low High

V

IL

60

levels specified in the DC Characte ristic s

IH

90%

50%

10%

Rise Time

80

Figure 4. Input Signal Measurement References

Figure 5 shows the definitions of the following signal states:

• Active state, when a bus or signal is driven, and enters a low impedance state.

• Tri-stated, when a bus or signal is placed in a high impedance state.

• Data Valid state, when a signal level has reached V

• Data Invalid state, when a signal level is in transition between VOL and V

56F803 Technical Data 19

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OL

or V

OH.

OH.

Freescale Semiconductor, Inc.

Data1 Valid

Data1

Data Invalid State

Data2 Valid

Data2 Data3

Data

Tri-stated

Data Active Data Active

Data3 Valid

Figure 5. Signal States

3.4 Flash Memory Characteristics

Table 23. Flash Memory Truth Table

Mode

nc...

I

Standby L L L L L L L L
Read HHHH L L L L
Word Program H H L L H L L H
Page Erase H L L L L H L H
Mass Erase H L L L L H H H

1. X address enable, all rows are disabled when XE = 0

2. Y address enable, YMUX is disabled when YE = 0

3. Sense amplifier enable

4. Output enable, tr i-state Flash data out bu s when OE = 0

5. Defines program cycle

6. Defines erase cycle

7. Defines mass erase cycle, erase whole block

8. Defines non-volatile store cycle

XE

1

cale Semiconductor,

YE

2

SE

3

OE

4

PROG

5

Table 24. IFREN Truth Table

ERASE

6

MAS1

7

NVSTR

8

Frees

Mode IFREN = 1 IFREN = 0

Read Read information block Read main memory block
Word program Program information block Program main memory block
Page erase Erase information block Erase main memory block
Mass erase Erase both block Erase main memory block

20 56F803 Technical Data

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Flash Memory Characteristics

Table 25. Flash Timing Parameters

Operating Conditions: V

Characteristic Symbol Min Typ Max Unit Figure

Program time
Erase time
Mass erase time

1

Endurance
Data Retention1 @ 5000 cycles

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cale Semiconductor,

PROG/ERASE to NVSTR set
up time

NVSTR hold time
NVSTR hold time (mass erase)
NVSTR to program set up time
Recovery time

Cumulative program
HV period

Program hold time
Address/data set up time
Address/data hold time

1. One cycle is equal to an erase program and read.

2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot
be programmed twice before next erase.

3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.
*The Flash interface unit provides registers for the control of these parameters.

The following parameters should only be used in the Manual Word Programming Mode

2

3

= V

SS

3

3

= 0 V, VDD = V

SSA

Tprog*

Terase*

Tme*

E

CYC

D

RET

Tnv*

Tnvh*

Tnvh1*

Tpgs*

Trcv*

Thv

Tpgh
Tads
Tadh

= 3.0–3.6V, TA = –40° to +85°C, C

DDA

20 ––us Figure 6
20 ––ms Figure 7

100 ––ms Figure 8

10,000 20,000 – cycles

10 30 – years

– 5 – us Figure 6,

– 5 – us Figure 6, Figure 7
– 100 – us Figure 8
– 10 – us Figure6
– 1 – us Figure 6,

– 3 – ms Figure 6

––– Figure 6
––– Figure 6
––– Figure 6

≤ 50pF

L

Figure 7, Figure 8

Figure 7, Figure 8

Frees

56F803 Technical Data 21

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IFREN

XADR

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XE

YADR

YE

DIN

nc...

I

PROG

NVSTR

Tnvs

Tprog

Tpgs

Tads

Thv

Figure 6. Flash Program Cycle

IFREN

XADR

cale Semiconductor,

XE

YE=SE=OE=MAS1=0

Tadh

Tpgh

Tnvh

Trcv

Frees

ERASE

NVSTR

Tnvs

Terase

Tnvh

Trcv

Figure 7. Flash Erase Cycle

22 56F803 Technical Data

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IFREN

XADR

XE

MAS1

YE=SE=OE=0

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External Clock Operation

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ERASE

NVSTR

Tnvs

Tme

Tnvh1

Trcv

Figure 8. Flash Mass Erase Cycle

3.5 External Clock Operation

The 56F803 system clock can be derived from an external crystal or an external system clock signal. To
generate a reference frequency using the internal oscillator, a reference crystal must be connected between
the EXTAL and XTAL pins.

3.5.1 Crystal Oscillator

The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the
frequency range specified for the external crystal in Table 27. In Figure 9 a recommended crystal
oscillator circuit is shown. Follow the crystal supplier’s recommendations when selecting a crystal,
because crystal parameters determine the component values required to provide maximum stability and
reliable start-up. The crystal and associated components should be mounted as close as possible to the
EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. The internal 56F80x
oscillator circuitry is designed to have no external load capacitors present. As shown in Figure 10 no
external load capacito rs should be used.

The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a
capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and
process variations. Usi ng a typical val ue of intern al capacitanc e on these pins of 12pF and a value of 3pF as
a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as
determined by the following equation:

CL1 * CL2

CL =

CL1 + CL2

56F803 Technical Data 23

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12 * 12

+ 3 = 6 + 3 = 9pF

12 + 12

Freescale Semiconductor, Inc.

This is the value load capacitance that should be used when selecting a crystal and determining the actual
frequency of operation of the crystal oscillator circuit.

nc...

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EXTAL XTAL

R

z

f

c

Recommended External Crystal
Parameters:
Rz = 1 to 3 MΩ

= 8MHz (optimized for 8MHz)

f

c

Figure 9. Connecting to a Crystal Oscillator

3.5.2 Ceramic Resonator

It is also possib le to drive the internal os cillator with a cerami c resonator, assuming th e overall system
design can tolerate the reduced signal integrity. In Figure 10, a typical cera m i c res o na tor ci rc uit i s s ho wn .
Refer to supplier’s recommendations when selecting a ceramic resonator and associated components. The
resonator and components should be mounted as close as possible to the EXTAL and XTAL pins. The
internal 56F80x oscillator circuitry is designed to have no external load capacitors present. As shown in

Figure 9 no external load capacitors should be used.

EXTAL XTAL

R

z

f

c

Recommended Ceramic Reson ator
Parameters:

= 1 to 3 MΩ

R

z

f

= 8MHz (optimized for 8MHz)

c

Figure 10. Connecting a Ceramic Resonator

Note: Motorola recommends only two terminal ceramic resonators vs. three terminal
resonators (which contain an internal bypass capacitor to ground).

3.5.3 External Clock Source

The recommended method of connecting an external clock is given in Figure11. The external clock
source is connected to XTAL and the EXTAL pin is grounded.

56F803

XTAL

External

Clock

EXTAL

V

SS

Figure 11. Connecting an External Clock Signal

24 56F803 Technical Data

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External Clock Operation

Table 26. External Clock Operation Timing Requirements

Operating Conditions: V

Characteristic Symbol Min Typ Max Unit

Frequency of operation (external clock driver)

Clock Pulse Width

1. See Figure 11 for details on using the recommended connection of an external clock driver.

2. The high or low pulse width must be no smaller than 6.25ns or the chip will not function.

3. Parameters listed are guaranteed by design.

External

Clock

nc...

I

Note: The midpoint is VIL + (VIH – VIL)/2.

2, 3

50%

10%

90%

SS

t

= V

PW

= 0 V, VDD = V

SSA

= 3.0–3.6 V, TA = –40° to +85°C

DDA

1

f

osc

t

PW

t

PW

0 — 80 MHz

6.25 ——ns

3

V

IH

90%

50%

10%

V

IL

Figure 12. External Clock Timing

cale Semiconductor,

Frees

3.5.4 Phase Locked Loop Timing

Table 27. PLL Timing

Operating Conditions: V

Characteristic Symbol Min Typ Max Unit

External reference crystal frequency for the PLL

PLL output frequency

PLL stabilization time

PLL stabilization time

1. An externally supplied reference cl ock should be as free as possible from any phase ji tter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.

2. ZCLK may not excee d 80MHz . For ad diti onal in formati on on ZCLK and f
in the User Manual. ZCLK = f

3. This is the minimum time required after the PLL set-up is changed to ensure reliable operation.

= V

SS

2

3 0o

to +85oC

3

-40o to 0oC

= 0 V, VDD = V

SSA

op

= 3.0–3.6 V, TA = –40° to +85°C

DDA

1

f

osc

f

/2 40 — 110 MHz

out

t

plls

t

plls

4810MHz

— 110ms

— 100 200 ms

/2, plea se refer to the OCCS chapter

out

56F803 Technical Data 25

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3.6 External Bus Asynchronous Timing

Table 28. External Bus Asynchronous Timing

Operating Conditions: V

Characteristic Symbol

Address Valid to WR

Width Asserted

WR
Wait states = 0
Wait states > 0

Asserted to D0–D15 Out Valid t

WR
Data Out Hold Time from WR

nc...

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Data Out Set Up Time to WR
Wait states = 0
Wait states > 0

RD Deasserted to Address Not Valid t
Address Valid to RD Deasserted

Wait states = 0
Wait states > 0

Input Data Hold to RD
RD

Assertion Width
Wait states = 0
Wait states > 0

Address Valid to Input Data Valid
Wait states = 0
Wait states > 0

Address Valid to RD Asserted t

= V

SS

Asserted t

Deasserted t

Deasserted t

= 0 V, VDD = V

SSA

Deasserted

= 3.0–3.6 V, TA = –40° to +85°C, C

DDA

AWR

t

WR

WRD

DOH

t

DOS

RDA

t

ARDD

DRD

t

RD

t

AD

ARDA

Min

6.5 — ns

7.5

(T*WS) + 7.5

— 4.2 ns

4.8 — ns

2.2

(T*WS) + 6.4

0 — ns

18.7

(T*WS) + 18.7

0 — ns

19

(T*WS) + 19

—
—

-4.4 — ns

cale Semiconductor,

RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0

t

RDD

—
—

1, 2

≤ 50pF, f

L

(T*WS) + 1

(T*WS) + 2.4

op

Max

—
—

—
—

—

—
—

1

2.4

= 80MHz

Unit

ns
ns

ns
ns

ns
ns

ns
ns

ns
ns

ns
ns

Frees

WR Deasserted to RD Asserted t
RD

Deasserted to RD Asserted t
WR Deasserted to WR Asserted t
RD

Deasserted to WR Asserted t

1. Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and

T = Clock Period. For 80MHz operation, T = 12.5ns.

2. Parameters listed are guaranteed by design.

To calculate the required access time for an ex te rnal memory for any frequency < 80Mhz, use this formula:

Top = Clock period @ desired operating fre quency

WS = Number of wait states

Memory Access Time = (Top*WS) + (Top- 11.5)

26 56F803 Technical Data

WRRD

RDRD

WRWR

RDWR

6.8 — ns
0 — ns

14.1 — ns

12.8 — ns

For More Information On This Product,

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A0–A15,

, DS

PS

(See Note)

RD

t

AWR

Freescale Semiconductor, Inc.

Reset, Stop, Wait, Mode Select, and Interrupt Timing

t

ARDD

t

ARDA

t

t

t

WRWR

t

WR

WRRD

RD

t

RDRD

t

RDWR

t

RDA

WR

t

t

DOH

AD

t

WRD

t

DOS

nc...

I

D0–D15

Note: During read-modify-write instructions and internal instructions, the address lines do not change state.

Data Out

t

RDD

Data In

t

DRD

Figure 13. External Bus Asynchronous Timing

3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Table 29. Reset, Stop, Wait, Mode Select, and Interrupt Timing

Operating Conditions: V

Characteristic Symbol Min Max Unit

Assertion to Address, Data and Control

RESET
Signals High Impedance

cale Semiconductor,

Minimum RESET
OMR Bit 6 = 0
OMR Bit 6 = 1

Assertion Duration2

SS

= V

= 0 V, VDD = V

SSA

= 3.0–3.6V, TA = –40° to +85°C, C

DDA

t

RAZ

t

RA

— 21 ns Figure 14

275,000T

128T

≤ 50pF

L

—
—

1, 5

See

Figure

Figure 14

ns
ns

Frees

RESET

De-assertion to First External Address Output t

Edge-sensitive Interrupt Request Width t

IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine

IRQA

, IRQB Assertion to General Purpose Output
Valid, caused by first instruct ion execution in the
interrupt service routine

Low to First Valid Interrupt Vector Address Out

IRQA
recovery from Wait State

IRQA Width Assertion to Recover from Stop State

56F803 Technical Data 27

3

4

RDA

IRW

t

IDM

t

IG

t

IRI

t

IW

33T 34T ns Figure 14

1.5T — ns Figure 15

15T — ns Figure 16

16T — ns Figure 16

13T — ns Figure 17

2T — ns Figure 18

For More Information On This Product,

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Freescale Semiconductor, Inc.

nc...

I

cale Semiconductor,

Frees

Table 29. Reset, Stop, Wait, Mode Select, and Interrupt Timing (Continued)

Operating Conditions: V

Characteristic Symbol Min Max Unit

Delay from IRQA Assertion to F etc h o f fi rst ins tru cti on
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1

Duration for Level Sensitiv e IRQ A
the Fetch of First IRQA
Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1

Delay from Level Sensitive IRQA
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1

1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.

2. Circuit stabilization delay is required during rese t when using an extern al clock or crystal osci llator in two cases:

• After power-on reset

• When recovering from Stop state

3. The minimum is specified for the duratio n of an edge -sensitive IRQA interrup t required to re cover from the Stop state.
This is not the minimum require d so t hat the IRQA interrupt is accepted.

4. The interrupt instruction fetch is visible on the pins only in Mode 3.

5. Parameters listed are guaranteed by design.

RESET

t

A0–A15,

D0–D15

, DS,

PS

RD

, WR

= V

SS

Interrupt Instruction (exiting

RAZ

= 0 V, VDD = V

SSA

Assertion to Cause

Assertion to First

= 3.0–3.6V, TA = –40° to +85°C, C

DDA

t

IF

t

IRQ

t

II

t

RA

—
—

—
—

—
—

≤ 50pF

L

275,000T

12T

275,000T

12T

275,000T

12T

ns
ns

ns
ns

ns
ns

t

RDA

First Fetch

First Fetch

1, 5

See

Figure

Figure 18

Figure 19

Figure 19

Figure 14. Asynchronous Reset Timing

IRQA,
IRQB

t

IRW

Figure 15. External Interrupt Timing (Negative-Edge-Sensitive)

28 56F803 Technical Data

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Freescale Semiconductor, Inc.

A0–A15,

PS

, DS,
, WR

RD

IRQA,

IRQB

General

Purpose

I/O Pin

IRQA

,

nc...

I

IRQB

t

IDM

t

IG

Reset, Stop, Wait, Mode Select, and Interrupt Timing

First Interrupt Instruction Execution

a) First Interrupt Instruction Execution

b) General Purpose I/O

cale Semiconductor,

Frees

IRQA,

IRQB

A0–A15,

PS

, DS,

RD

, WR

IRQA

A0–A15,

PS

, DS,
, WR

RD

Figure 16. External Level-Sensitive Interrupt Timing

t

IRI

Figure 17. Interrupt from Wait State Timing

t

IW

t

IF

First Instruction Fetch

Not IRQA Interrupt Vector

First Interru p t Vector
Instruction Fetch

Figure 18. Recovery from Stop State Using Asynchronous Interrupt Timing

56F803 Technical Data 29

For More Information On This Product,

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IRQA

Freescale Semiconductor, Inc.

t

IRQ

t

II

nc...

I

cale Semiconductor,

Frees

A0–A15

, DS,

PS

RD

, WR

Figure 19. Recovery from Stop State Using IRQA Interrupt Service

3.8 Serial Peripheral Interface (SPI) Timing

1

50
25

—
25

—

100

17.6

12.5

24.1
25

20

0

Operating Conditions: V

Cycle time
Master
Slave

Enable lead time
Master
Slave

Enable lag time
Master
Slave

Clock (SCLK) high time
Master
Slave

Clock (SCLK) low time
Master
Slave

Data set-up time required for inputs
Master
Slave

= V

SS

Characteristic Symbol Min Max Unit S ee Figure

= 0 V, VDD = V

SSA

Table 30. SPI Timing

= 3.0–3.6V, TA = –40° to +85°C, C

DDA

t

C

t

ELD

t

ELG

t

CH

t

CL

t

DS

First IRQA Interrupt

Instruction Fetch

≤ 50pF, f

L

—
—

—
—

—
—

—
—

—
—

—
—

OP

ns
ns

ns
ns

ns
ns

ns
ns

ns
ns

ns
ns

= 80MHz

Figures 20,

21, 22, 23

Figure 23

Figure 23

Figures 20,

21, 22, 23

Figures 20,

21, 22, 23

Figures 20,

21, 22, 23

Data hold time required for inputs
Master
Slave

Access time (time to data active from high-impedance
state)
Slave

30 56F803 Technical Data

t

DH

t

A

0
2

4.8 15 ns

—
—

ns
ns

Figures 20,

21, 22, 23

Figure 23

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Freescale Semiconductor, Inc.

Serial Peripheral Interface (SPI) Timing

Table 30. SPI Timing

Operating Conditions: V

Disable time (hold time to high-impedance state)
Slave

Data Valid for outputs
Master
Slave (after enable edge)

Data invalid
Master
Slave

Rise time
Master

nc...

I

Slave
Fall time

Master
Slave

1. Parameters listed are guaranteed by design .

= V

SS

Characteristic Symbol Min Max Unit S ee Figure

= 0 V, VDD = V

SSA

= 3.0–3.6V, TA = –40° to +85°C, C

DDA

t

D

t

DV

t

DI

t

R

t

F

1

≤ 50pF, f

L

3.7 15.2 ns

—
—

0
0

—
—

—
—

4.5

20.4

—
—

11.5

10.0

9.7

9.0

OP

ns
ns

ns
ns

ns
ns

ns
ns

= 80MHz

Figure 23

Figures 20,

21, 22, 23

Figures 20,

21, 22, 23

Figures 20,

21, 22, 23

Figures 20,

21, 22, 23

cale Semiconductor,

Frees

SS

(Input)

SCLK (CPOL = 0)

(Output)

SCLK (CPOL = 1)

(Output)

MISO

(Input)

MOSI

(Output)

t

DS

SS is held High on master

t

C

t

CL

t

CH

t

CL

t

DH

t

CH

t

R

t

F

t

F

t

R

MSB in Bits 14–1LSB in

t

DI

t

DV

t

DI

(ref)

Master MSB out Bits 14–1 Master LSB out

t

t

F

R

Figure 20. SPI Master Timing (CPHA = 0)

56F803 Technical Data 31

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nc...

I

cale Semiconductor,

Frees

SS

(Input)

SCLK (CPOL = 0)

(Output)

SCLK (CPOL = 1)

(Output)

MISO

(Input)

MOSI

(Output)

SS

(Input)

SCLK (CPOL = 0)

(Input)

SCLK (CPOL = 1)

(Input)

SS is held High on master

t

C

t

CL

t

CH

t

CL

t

CH

t

R

MSB in Bits 14–1LSB in

t

t

(ref)

DV

Master MSB out Bits 14– 1 Master LSB out

DI

t

F

Figure 21. SPI Master Timing (CPHA = 1)

t

C

t

CL

t

CH

t

ELD

t

A

t

CL

t

CH

t

R

t

F

t

DV

t

t

R

t

R

t

F

t

DS

t

DH

t

R

F

t

ELG

t

F

t

D

MISO

(Output)

MOSI

(Input)

t

DS

Slave MSB out Bits 14–1

t

DV

t

DH

MSB in Bits 14–1LSB in

Slave LSB out

t

DI

t

DI

Figure 22. SPI Slave Timing (CPHA = 0)

32 56F803 Technical Data

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SS

(Input)

SCLK (CPOL = 0)

(Input)

Freescale Semiconductor, Inc.

t

ELD

t

C

t

t

CL

t

CH

t

CL

R

t

Quad Timer Timing

F

t

ELG

nc...

I

cale Semiconductor,

Frees

SCLK (CPOL = 1)

(Input)

MISO

(Output)

MOSI

(Input)

t

DV

t

A

Slave MSB out Bits 14–1

t

DS

Figure 23. SPI Slave Timing (CPHA = 1)

3.9 Quad Timer Timing

Table 31. Timer Timing

Operating Conditions: V

Characteristic Symbol Min Max Unit

Timer input period P
Timer input high/low period P
Timer output period P
Timer output high/low period P

1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5 ns.

2. Parameters listed are guaranteed by design.

SS

= V

= 0 V, VDD = V

SSA

t

CH

t

F

t

DV

t

DH

MSB in Bits 14–1LSB in

1, 2

= 3.0–3.6V, TA = –40° to +85°C, C

DDA

IN

INHL

OUT

OUTHL

4T+6 — ns
2T+3 — ns

2T — ns
1T — ns

t

R

Slave LSB out

t

DI

≤ 50pF, f

L

t

D

= 80MHz

OP

56F803 Technical Data 33

For More Information On This Product,

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Freescale Semiconductor, Inc.

Timer Inputs

P

IN

P

INHL

P

INHL

Timer Outputs

P

OUT

P

OUTHL

P

OUTHL

Figure 24. Timer Timing

nc...

I

3.10 Quadrature Decoder Timing

cale Semiconductor,

Frees

Operating Conditions: V

Characteristic Symbol Min Max Unit

Quadrature input period P
Quadrature input high/low period P
Quadrature phase period P

1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12 . ns. VSS = 0 V, VDD = 3.0
– 3.6V, T

2. Parameters listed are guaranteed by design.

= –40° to +85°C, C

A

Phase A

(Input)

Table 32. Quadrature Decoder Timing

SS

= V

= 0 V, VDD = V

SSA

L

≤ 50pF.

= 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz

DDA

IN

HL

PH

P

PHPPHPPH

8T+12 — ns

4T+6 — ns
2T+3 — ns

P

PH

1,2

P

HL

P

HL

P

HL

Phase B

(Input)

P

IN

P

IN

P

HL

Figure 25. Quadrature Decoder Timing

34 56F803 Technical Data

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Serial Communication Interface (SCI) Timing

3.11 Serial Communication Interface (SCI) Timing

Table 33. SCI Timing

4

nc...

I

cale Semiconductor,

Frees

Operating Conditions: V

Characteristic Symbol Min Max Unit

Baud Rate
RXD
TXD3 Pulse Width

SCI receive

1

2

Pulse Width

1. f

2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.

3. The TXD pin in SCI0 is nam ed TXD0 and the TXD pin in SCI1 is name d TXD1.

4. Parameters li s ted are guaranteed by design.

data pin

is the frequency of operation of the system clock in MHz.

MAX

RXD

(Input)

SS

= V

= 0 V, VDD = V

SSA

= 3.0–3.6 V, TA = –40° to +85°C, C

DDA

BR — (f

RXD

TXD

RXD

PW

PW

PW

0.965/BR 1.04/BR ns

0.965/BR 1.04/BR ns

≤ 50pF, f

L

*2.5)/(80) Mbps

MAX

= 80MHz

OP

Figure 26. RXD Pulse Width

TXD

SCI receive

data pin

(Input)

TXD

PW

Figure 27. TXD Pulse Width

3.12 Analog-to-Digital Converter (ADC) Characteristics

Table 34. ADC Characteristics

Operating Conditions: V

performance ) , ADC clo c k = 4MHz, 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz

SS

= V

= 0 V, VDD = V

SSA

= 3.0–3.6 V, V

DDA

= VDD-0.3V, ADCDIV = 4, 9, or 14, (for optimal

REF

Characteristic Symbol Min Typ Max Unit

ADC input voltages V
Resolution R
Integral Non-Linearity

Differential Non-Linearity DNL — +/- 0.9 +/- 1
Monotonicity GUARANTEED
ADC internal clock

Conversion range R

56F803 Technical Data 35

3

5

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ADCIN

ES

INL — +/- 2.5 +/- 4

f

ADIC

AD

1

0

12 — 12 Bits

0.5 — 5MHz

V

SSA

—

— V

V

REF

DDA

2

V

LSB
LSB

V

4

4

Freescale Semiconductor, Inc.

Table 34. ADC Characteristics (Continued)

nc...

I

cale Semiconductor,

Frees

Operating Conditions: V

performance ) , ADC clo c k = 4MHz, 3.0–3.6V, T

Characteristic Symbol Min Typ Max Unit

Power-up time t
Conversion time t
Sample time t
Input capacitance C

Gain Error (transfer gain)
Offset Voltage
Total Harmonic Distortion
Signal-to- Noise plus Distortion
Effective Number of Bits
Spurious Free Dynamic Range

Bandwidth BW — 100 — KHz
ADC Quiescent Current (both ADCs) I

Quiescent Current (both ADCs) I

V

REF

1. For optimum ADC performance, keep the minimum V
a digital output code of 0.

2. V
to V

3. Measured in 10- 90% range.

4. LSB = Least Significant Bit.

5. Guaranteed by characterization.

6. t

5

must be equal to or less than V

REF

-0.3V.

DDA

= 1/f

AIC

ADIC

ADC analog input

= V

SS

5

5

5

= 0 V, VDD = V

SSA

5

5

= 3.0–3.6 V, V

DDA

= –40° to +85°C, CL ≤ 50pF, fOP = 80MHz

A

ADPU

ADC

ADS

ADI

E

GAIN

V

OFFSET

THD 60 64 — dB

SINAD 55 60 — dB

ENOB 9 10 — bit
SFDR 65 70 — dB

ADC

VREF

and must be greater th an 2.7V. For optimal ADC per formance, set V

DDA

— 16 —
— 6 —
— 1 —
— 5 —

0.95 1.00 1.10 —

-80 -15 +20 mV

— 50 — mA
— 12 16.5 mA

value > 25mV. Inputs less than 25mV may convert to

ADCIN

= VDD-0.3V, ADCDIV = 4, 9, or 14, (for optimal

REF

t

AIC

t

AIC

t

AIC

3

cycles
cycles
cycles

6

pF

REF

6

6

6

1

2

4

Figure 28. Equivalent Analog Input Circuit

1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)

2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)

3. Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)

4. Sampling capacitor at the sample and hold circuit. (1pf)

36 56F803 Technical Data

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Controller Area Network (CAN) Timing

3.13 Controller Area Network (CAN) Timing

Table 35. CAN Timing

2

Operating Conditions:

Characteristic Symbol Min Max Unit

Baud Rate BR

Bus Wakeup detection

1. If Wakeup glitch filter is enabled during the design initialization and also CAN is put into SLEEP mode then, any
bus event (on MSCAN_RX pin) whose duration is less than 5 micro seconds is filtered away. However, a valid CAN bus
wakeup detection takes p lace fo r a wak eup p ulse eq ua l to or g reat er tha n 5 micros econ ds . The val ue of 5 micro seco nds
originates from the fact that the CAN wakeup message consists of 5 dominant bits at the highest possible baud rate of
1Mbps.

2. Parameters li s ted are guaranteed by design.

nc...

I

MSCAN_RX

CAN receive

data pin

(Input)

VSS = V

1

= 0 V, VDD = V

SSA

= 3.0–3.6 V, TA = –40° to +85°C, CL

DDA

— 1Mbps

5 — µs

T

WAKEUP

T

CAN

WAKEUP

≤

50pF, MSCAN Cloc k = 3 0M H z

Figure 29. Bus Wakeup Detection

cale Semiconductor,

Frees

56F803 Technical Data 37

For More Information On This Product,

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Freescale Semiconductor, Inc.

3.14 JTAG Timing

f

OP

CY

PW

DS

DH

DV

TS

TRST

DE

1, 3

DC 10 MHz

100 — ns

50 — ns

0.4 — ns

1.2 — ns

— 26.6 ns

— 23.5 ns

50 — ns

4T — ns

t

PW

V

M

Table 36. JTAG Timing

Operating Conditions: V

TCK frequency of operation
TCK cycle time t

TCK clock pulse width t

TMS, TDI data set-up time t

TMS, TDI data hold time t

nc...

I

cale Semiconductor,

TCK low to TDO data valid t

TCK low to TD O tri-state t

TRST assert ion time t

DE assertion time t

1. Timing is both wait state and frequency dependent. For the values listed, T = clock cyc le. For 80MHz
operation, T = 12.5ns.

2. TCK frequency of operation must be less than 1/8 the processor rate.

3. Parameters liste d ar e guaranteed by design.

TCK

(Input)

VM = V

+ (VIH – VIL)/2

IL

= V

SS

Characteristic Symbol Min Max Unit

2

= 0 V, VDD = V

SSA

V

IH

= 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz

DDA

t

CY

t

PW

V

M

V

IL

Frees

Figure 30. Test Clock Input Timing Diagram

38 56F803 Technical Data

For More Information On This Product,

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TCK

(Input)

Freescale Semiconductor, Inc.

t

DS

t

DH

JTAG Timing

TDI

TMS

(Input)

TDO

(Output)

TDO

(Output

nc...

I

(Output)

)

TDO

t

DV

t

TS

t

DV

Input Data Valid

Output Data Valid

Output Data Valid

Figure 31. Test Access Port Timing Diagram

TRST

(Input)

t

TRST

Figure 32. TRST Timing Diagram

cale Semiconductor,

DE

t

DE

Frees

Figure 33. OnCE—Debug Event

56F803 Technical Data 39

For More Information On This Product,

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Freescale Semiconductor, Inc.

Part 4 Packaging

4.1 Package and Pin-Out Information 56F803

This section contai ns pack age and pin-out informati on for the 100-pin LQFP configurat ion of the 56F803.

RXD0

D9D8D7D6D5D4D3

VSSVDDD2D1D0VCAPC

SCLK

MOSI

MISOSSTD2

TD1

CLKODERESET

TXD0

EXTBOOT

D10
D11

nc...

I

cale Semiconductor,

D12
D13
D14

D15

A0

V

DD

VSS

A1
A2

A3
A4
A5
A6
A7
A8

A9

A10
A11
A12
A13
V

DD

PS
DS

PIN 1

PIN 26

ORIENTATION

MARK

Motorola

56F803

PIN 76

PIN 51

PWMA5
PWMA4
PWMA3
PWMA2
PWMA1
PWMA0
HOME0

INDEX0
V

SS

VDD
PHASEB0
PHASEA0

SS

V
VDD
VDD

VDDA
VSSA
EXTAL
XTAL
AN7

AN6
AN5
AN4
AN3

AN2

Frees

A14

A15

VSS

WR

RD

TCS

IRQA

IRQB

TDI

TCK

TMS

TDO

TRST

ISA0

ISA1

VCAPC

ISA2

FAULTA0

FAULTA1

MSCAN_TX

MSCAN_RX

FAULTA2

AN0

VREF

AN1

Figure 34. Top View, 56F803 100-pin LQFP Package

40 56F803 Technical Data

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Package and Pin-Out Information 56F803

Table 37. 56F803 Pin Identification By Pin Number

Pin No. Signal Na me Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name

1 D10 26 A14 51 AN2 76 TXD0
2 D11 27 A15 52 AN3 77 RXD0

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3 D12 28 V

4 D13 29 WR 54 AN5 79 RESET
5 D14 30 RD 55 AN6 80 DE
6 D15 31 IRQA 56 AN7 81 CLKO
7A032IRQB
8V

9VSS34 TCK 59 V

10 A1 35 TMS 60 V

11 A2 36 TDI 6 1 V

12 A3 37 TDO 62 V

13 A4 38 TRST 63 V

14 A5 39 VCAPC 64 PHASEA0 89 D0
15 A6 40 ISA0 65 PHASEB0 90 D1
16 A7 41 ISA1 66 V

17 A8 42 ISA2 67 V

18 A9 43 FAULTA0 68 INDEX0 93 V

19 A10 44 MSCAN_TX 69 HOME0 94 D3
20 A11 45 FAULTA1 70 PWMA0 95 D4
21 A12 46 MSCAN_RX 71 PWMA1 96 D5

DD

33 TCS 58 EXTAL 83 TD2

SS

53 AN4 78 EXTBOOT

57 XTAL 82 TD1

SSA

DDA

DD

DD

SS

DD

SS

84 SS

85 MISO

86 MOSI

87 SCLK

88 VCAPC

91 D2

92 V

DD

SS

22 A13 47 FAULTA2 72 PWMA2 97 D6
23 V

24 PS 49 AN0 74 PWMA4 99 D8
25 DS

56F803 Technical Data 41

DD

48 VREF 73 PWMA3 98 D7

50 AN1 75 PWMA5 100 D9

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C

V

-AB-

E

Freescale Semiconductor, Inc.

S

-T-

-U-

S

AC

A

S

AB

(24X PER SIDE)

R

0.25 (0.010)

GAUGE PLANE

0.15 (0.006) Z

S

T-U

S

AC

S

0.15 (0.006) Z

9

0.15 (0.006) Z

AE

AE

°

M

T-U

T-U

96X

S

S

S

AD

G

0.100 (0.004)

S

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DA TUM PLANE -AB- IS LOCATED A T BOTTOM
OF LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING
LINE.

4. DATUMS -T -, -U-, AND -Z- TO BE DETE RMINED
A T DATUM PLANE -AB-.

5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -AC-.

6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT
DA TUM PLANE -AB-.

7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED

0.350 (0.014). DAMBAR CAN NOT BE LOCA TED
ON THE LOWER RADIUS OR THE FOOT.
MINIMUM SPACE BETWEEN PROTRUSION
AND AN ADJACENT LEAD IS 0.070 (0.003).

8. MINIMUM SOLDER PLA TE THICKN ESS
SHALL BE 0.0076 (0.003).

9. EXACT SHAPE OF EACH CORNER MAY VAR Y
FROM DEPICTION.

DIM MIN MAX MIN MAX

A 13.950 14.050 0.549 0.553
B 13.950 14.050 0.549 0.553
C 1.400 1.600 0.055 0.063
D 0.170 0.270 0.007 0.011
E 1.350 1.450 0.053 0.057
F 0.170 0.230 0.007 0.009

G 0.500 BSC 0.020 BSC

H 0.050 0.150 0.002 0.006
J 0.090 0.200 0.004 0.008
K 0.500 0.700 0.020 0.028

M 12 REF 12 REF

°°

N 0.090 0.160 0.004 0.006

Q 1 5 1 5

°°°°

R 0.150 0.250 0.006 0.010
S 15.950 16.050 0.628 0.632
V 15.950 16.050 0.628 0.632

W 0.200 REF 0.008 REF

X 1.000 REF 0.039 REF

INCHESMILLIMETERS

AC

-Z-

-AC-

SEATING
PLANE

S

T-U

S

AC

B

S

0.15 (0.006) Z

D
F

J

N

H

W

X

DETAIL AD

°

Q

K

0.20 (0.008) Z

M

AC

SECTION AE-AE

T-U

S

S

CASE 842F-01

Figure 35. 100-pin LQPF Mechanical Information

42 56F803 Technical Data

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Thermal Design Considerations

Part 5 Design Considerations

5.1 Thermal Design Considerations

An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:

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Equation 1:

Where:

= ambient temperature °C

T

A

= package junction-to-ambient thermal resistance °C/W

R

θJA

= power dissipation in package

P

D

Historical ly, thermal re sist an c e ha s b e en e xp r esse d as the su m o f a jun ct io n- to- c as e t her m al re s is ta nce an d
a case-to-ambient thermal resistance:

Equation 2:

Where:

= package junction-to-ambient thermal resistance °C/W

R

θJA

= package junction-to-case thermal resistance °C/W

R

θJC

= package case-to-ambient thermal resistance °C/W

R

θCA

R

is device-related and cannot be influenced by the user. The user controls the thermal environment to

θJC

change the case-t o-amb ient t hermal resis tance , R
the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ce ramic packa ges with heat sinks; some 90% of t he heat flow is dissipated th rough
the case to the hea t si nk a nd out to the ambient environment. For ceramic p ackages, in situations wher e the
heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device
thermal performance may need the additional modeling cap ability of a system le vel thermal simulati on tool.

The thermal perfor mance of plastic packages is more depend ent on t he temper ature o f the PCB to which the
package is mounted. Again, if the es timations obtained fro m R
thermal performance is adequate, a system level model may be appropriate.

TJTAPDR

R

θJA

×()+=

R

+=

θJCRθCA

θJA

. For example, the user can ch ange the air f low arou nd

θCA

do not satisfactorily answer whether the

θJA

Definitions:

A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packa ges:

• Measure th e thermal resist ance from the junction t o the outside surfac e of the package (cas e) closest
to the chip mounting area when that surface has a proper heat sink. This is done to minimize
temperature variation across the surface.

• Measure the thermal resistance from the junction to where the leads are attached to the case. This
definition is approximately equal to a junction to board thermal resistance.

56F803 Technical Data 43

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• Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package
case determined by a thermocouple.

The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxie d to the t op cent er of t he packa ge case. The th ermocoup le s hould be positi oned so that
the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple
junction and over about 1mm of wire extending from the junction. The thermocouple wire is placed flat
against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.

When heat sink is used, the j unction temperatu re is determined fr om a thermocouple insert ed at the interface
between the case of the package and the interface material. A clearance slot or hole is normally required in
the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal
performance caused by remov ing par t of t he th erma l int erfac e to t he heat sink. Beca use of the ex perimen tal
difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate
the case temperature using a s eparate mea surement o f the the rmal resi stance of the inte rface. Fr om this cas e
temperature, the junction temperature is determ ined from th e junction-to -case thermal resistanc e.

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5.2 Electrical Design Considerations

CAUTION

This device contains protective circuitry to guard
against damage due to high static voltage or
electrical fields. However, normal precautions are
advised to avoid application of any voltages higher
than maximum rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate voltage level.

Electrical Design Considerations

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Use the following list of considerations to assure correct operation:

• Provide a low-impedance path from the board power supply to each V
controller, and from the board ground to each V

• The minimum bypass requirement is to place 0.1
the package supply pins. The recommended bypass configuration is to place one bypass capacitor
on each of the V

provide better performance tolerances.

• Ensure that capacitor leads and associated printed circuit traces that connect to the chip V

(GND) pins are less than 0.5 inch per capacitor lead.

V

SS

• Bypass the V
grade capacitor such as a tantalum capacitor.

• Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be
minimal.

• Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient curren ts in the V

• Take special care to minimize noise levels on the VREF, V

• Designs that utilize the TRST
development or debugging systems) should allow a means to assert TRST
asserted, as well as a means to assert TRST
power up for proper operation. Designs that do not require debugging functionality, such as
consumer products, TRST

DD

DD/VSS

and V

pairs, including V

layers of the PCB with approximately 100 µF, preferably with a high-

SS

DD

pin for JTAG port or OnCE module functionality (such as

should be tied low.

DDA/VSSA.

and GND circuits.

(GND) pin.

SS

µF capacitors positioned as close as possible to

Ceramic and tantalum capacitors tend to

and V

DDA

independently of RESET. TRST must be asserted at

pin on the hybrid

DD

pins.

SSA

whenever RESET is

DD

and

• Because the Flash memory is programmed thr ough the JTAG/OnCE port, designers should p rovide
an interface to this port to allow in-circuit Flash programming.

56F803 Technical Data 45

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Part 6 Ordering Information

Table 38 lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales

office or authorized distributor to determine availability and to order parts.

Table 38. 56F803 Ordering Information

Part

56F803 3.0–3.6 V Low Profile Plastic Quad Flat Pack

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Supply

Voltage

Package Type

(LQFP)

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Pin

Count

100 80 DSP56F803BU80

Frequency

(MHz)

Order Number

Frees

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56F803 Technical Data 47

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HOW TO REACH US:

USA/EUROPE/LOCATIONS NOT LISTED:

Motorola Literatur e Distribution
P.O. Box 5405, Denver, Colorado 80217
1-800-521-6274 or 480-768-2130

JAPAN:

Motorola Japan Ltd.
SPS, Technical Information Center
3-20-1, Minami-Azabu
Minato-ku
Tokyo 106-8573, Japan
81-3-3440-3569

ASIA/PACIFIC:

Motorola Semiconductors H.K. Ltd.
Silicon Harbour Centre
2 Dai King Street
Ta i P o Ind us tr ial Estate

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Tai Po, N.T. Hong Kong
852-26668334

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Information in this document is provided solely to enable system and software
implementers to use Motorola products. There are no express or implied copyright
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integrated circuits based on the information in this document.

Motorola reserves the right to make changes without further notice to any products
herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters which may be provided in Motorola data sheets
and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts.
Motorola does not convey any license under its patent rights nor the rights of
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names are the property of their respective owners. Motorola, Inc. is an Equal
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© Motorola, Inc. 2004

DSP56F803/D

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