MOTOROLA 56F803 Technical data
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Freescale Semiconductor, Inc.
Technical Data
56F803 16-bit Hybrid Controller
DSP56F803/D
Rev. 13.0, 02/2004
56F803
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• Up to 40 MIPS at 80MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Hardware DO and REP loops
• MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes
•31.5K
• 512
•4K
•2K
•2K
6
3
3
4
4
4
2
2
2
4
× 16-bit words Program Flash
× 16-bit words Program RAM
× 16-bit words Data Flash
× 16-bit words Data RAM
× 16-bit words Boot Flash
PWM Outputs
Current Sense Inputs
Fault Inputs
A/D1
A/D2
ADC
VREF
Quadrature
Decoder 0 /
Quad Timer A
Quad Timer B
Quad Timer C
Quad Timer D
CAN 2.0A/B
SCI
or
GPIO
SPI
or
GPIO
*includes TCS pin which is reserved for factory use and is tied to VSS
PWMA
Interrupt
Controller
Program Memory
32252 x 16 Flash
512 x 16 SRAM
Boot Flash
2048 x 16 Flash
Data Memory
4096 x 16 Flash
2048 x 16 SRAM
COP/
Watchdog
Application-
Specific
Memory &
Peripherals
RESET
IRQB
IRQA
Program Controller
and
Hardware Looping Unit
•
•
•
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
EXTBOOT
PAB
PDB
XDB2
CGDB
XAB1
XAB2
6
JTAG/
OnCE
Port
Address
Generation
Unit
•
•
INTERRUPT
CONTROLS
IPBus Bridge
• Up to 64K
× 16-bit words each of external
Program and Data memory
• 6-channel PWM module
• T w o 4-channel 12-b it ADCs
• Quadrature Decoder
• CAN 2.0 B module
• Serial Communication Interface (SCI)
• Serial Peripheral Interface (SPI)
• Up to two General Purpose Quad Timers
•JTAG/OnCE
TM
port for debugging
• 16 shared GPIO lines
• 100–pin LQFP package
VCAPC VDDVSSV
26 6*
Digital Reg
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Low Voltage
Supervisor
16-Bit
56800
Core
DDAVSSA
Analog Reg
Manipulation
Clock Gen
Bit
Unit
PLL
•
•
•
IPBB
CONTROLS
16 16
(IPBB)
External
Bus
Interface
Unit
External
Address Bus
Switch
External
Data Bus
Switch
Bus
Control
6
10
16
CLKO
XTAL
EXTAL
A[00:05]
A[06:15] or
GPIO-E2:E3 &
GPIO-A0:A7
D[00:15]
PS Select
DS Select
WR Enable
RD Enable
© Motorola, Inc., 2004. All rights reserved.
Figure 1. 56F803 Block Diagram
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Part 1 Overview
1.1 56F803 Features
1.1.1 Digital Signal Processing Core
• Efficient 16-bit 56800 family hybrid controller engine with dual Harvard architecture
• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
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• Single-cycle 16
• Two 36
• 16
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buse s and one external addre ss bus
• Four internal data buses and one external data bus
• Instruction set supports both DSP and controller functions
• Controller style addressing modes and instructions for compact code
• Efficient C compiler and local variable sup port
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/OnCE debug programming interface
-bit accumulators, including extension bits
-bit bidirectional barrel shifter
× 16-bit parallel Multiplier-Accumulator (MAC)
1.1.2 Memory
• Harvard archi tecture permits as many as thr ee simulta neous access es to Progra m and Data memory
• On-chip memory including a low-cost, high-volume Flash solution
— 31.5K
— 512K
— 4K
— 2K
— 2K
• Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states
× 16-bit words of Program Flash
× 16-bit words of Program RAM
× 16-bit words of Data Flash
× 16-bit words of Data RAM
× 16-bit words of Boot Flash
— As much as 64K
— As much as 64K
× 16 bits of Data memory
× 16 bits of Program memory
1.1.3 Peripheral Circuits for 56F803
• Pulse Width Modulator module (PWM) with six PWM outputs, three Current Sense inputs, and
three Fault inputs, fault-tolerant design with dead time insertion, supports both center- and edgealigned modes, supports Motorola’s patented dead time distortion correction
• Two 12
ADC and PWM modules can be synchronized
• Quadrature Decoder with four inputs (shares pins with Quad Timer )
2 56F803 Technical Data
-bit Analog-to-Digital Converters (ADCs), which support two simultaneous conversions;
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• Four General Purpose Quad T imers: T imer A (sharing pins with Quad Dec0), T imers B &C wit hout
external pins and Timer D with two pins
• CAN 2.0 B module with 2-pin ports for transmit and receive
• Serial Communication Interface (SCI) with two pins (or two additional GPIO lines)
• Serial Peripheral Interface (SPI) with configurable 4-pin port (or four additional GPIO lines)
• Computer Operating Properly (COP) Watchdog timer
• Two dedicated external interrupt pins
• Sixteen multiplexed General Purpose I/O (GPIO) pins
• External reset input pin for hardware reset
• JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
• Software -programmable, Phase Locked Loo p-based frequenc y synthesizer for the hy brid controller
core clock
56F803 Description
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1.1.4 Energy Information
• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digit al inputs
• Uses a single 3.3V power supply
• On-chip regulators for digita l and analog c i rcuitry to lower cost and reduce noise
• Wait and Stop modes available
1.2 56F803 Description
The 56F803 is a member of the 56800 core-b ased family of hybrid contr ollers. It combines, on a singl e chip,
the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals
to create an extremely cost-effective solution. Because of its low cost, configuration flexibility , and compact
program code, the 56F803 is well-su ited for many ap plicati ons. The 56F803 inc ludes many periph erals tha t
are especially useful for applications such as motion control, smart appliances, steppers, encoders,
tachometers, limit switches, power supply and control, automotive control, engine management, noise
suppression, remote utility metering, and industrial control for power, lighting, and automation.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six opera tions per inst ructi on cycle . The MCU-style programmi ng model and
optimized instruc tion se t allo w straight forw ard gene rati on of ef f icien t, compact DSP and co ntrol code. The
instruction set is also highly efficient for C compilers to enable rapid development of optimized control
applications.
The 56F803 supports pro gra m e xec uti on from either internal or external memories . Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F803 also provides two external
dedicated interrup t lines, a nd up to 16 Gen eral Pu rpose Inpu t/Output ( GPIO) line s, depending on periphe ral
configuration.
The 56F803 controller includes 31.5K words (16-bit) of Program Flash and 4K words of Data Flash (each
programmable through the JTAG port) with 512 words of Program RAM and 2K words of Data RAM. It
also supports program execution from external memory.
A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable
software routines that can be used to program the main Program and Data Flash memory areas. Both
56F803 Technical Data 3
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Program and Data Flash memories can be inde pendently bulk–erased or eras ed i n page siz es of 256 word s.
The Boot Flash memory can also be either bulk- or page
A key application-specific feature of the 56F803 is the inclusion of a Pulse Width Modulator (PWM)
module. This module incorporates three complementary, individually programmable PWM signal outputs
(the module is also capable of suppor ting three i ndependent PWM functi ons, for a to tal of six PWM outpu ts)
to enhance motor control functionality. Complementary operation permits programmable dead time
insertion, distor tion co rrect ion via current sensin g by sof tware, an d separa te top and bottom outp ut pol arit y
control. The up-counter value is programmable to support a continuously variable PWM frequency. Edgeand center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The device is
capable of controlling most motor types: ACIM (AC Induction Motors), both BDC and BLDC (Brush and
Brushless DC motors), SRM and VR M (Switch ed and Variable Reluctance Mot ors), and s tepper mo tors.
The PWM incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive
capability to direc tly drive st andard opto-i solators. A “smoke-inhibit”, write-o nce protecti on feature f or key
parameters and patented PWM waveform distortion correction circuit are also provided. The PWM is
double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1
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to 16. The PWM module provides a reference output to synchronize the ADC.
The 56F803 incorpor ates a separa te Quadrature Decode r capable o f capturing all four transit ions on the two -
phase inputs, permitting generation of a number proportional to actual position. Speed computation
capabilities accommodate both fast and slow moving shafts. The integrated watchdog timer in the
Quadratur e Deco de r can be pr ogr amm ed wit h a tim e-out valu e to ala rm wh en no sh aft motio n is det ect ed.
Each input is filtered to ensure only true transitio ns are recorded.
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This controller also provides a full set of standard programmable peripherals that include a Serial
Communications Inte rface (S CI), one Serial Peripher al Inte rface (S PI), an d four Qua d T imer s. Any of t hese
interfaces can be used as General Purpose Input/Outputs (GPIO) if that function is not required. A
Controller Area Network interface (CAN Version 2.0 A/B-compliant) and an internal interrupt controller
are also included on the 56F803.
1.3 State of the Art Development Environment
• Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-touse component-based software application creation with an expert knowledge system.
• The Code Warrior Integrated Deve lopment Enviro nment is a sophi sticated to ol for code na vigation,
compiling, and debuggi ng. A complete set of ev aluation modules ( EVMs) and development s ystem
cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a
complete, scalable tools solution for easy, fast, and efficient development.
4 56F803 Technical Data
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Product Documentation
1.4 Product Documentation
The four docu ments listed in Table 1 are required for a complete description and proper design with the
56F803. Documentation is available from local Motorola distributors, Motorola semiconductor sales
offices, Motorola Literature Distribution Centers, or online at www.motorola.com/semiconductors.
Table 1. 56F803 Chip Documentation
Topic Description Order Number
DSP56800
Family Manual
DSP56F801/803/805/
807 User’s Manual
56F803
Technical Data Sheet
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56F803
Product Brief
56F803
Errata
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
“asserted” A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.
cale Semiconductor,
Examples: Signal/Symbol Logic State Signal State
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
Detailed description of the 56800 family architecture, and
16-bit core processor and the instruction set
Detailed description of memory, peripherals, and interfaces
of the 56F801, 56F803, 56F803, and 56F807
Electrical and timing specifications, pin descriptions, and
package descriptions (this document)
Summary descripti on and bl ock diag ram of the 56F803 c ore,
memory, p eripherals and interfaces
Details any chip issues that might be pres en t DSP56F803E/D
PIN
True Asserted VIL/V
DSP56800FM/D
DSP56F801-7UM/D
DSP56F803/D
DSP56F803PB/D
Voltage
OL
1
Frees
PIN False Deasserted VIH/V
PIN True Asserted VIH/V
PIN False Deasserted VIL/V
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
56F803 Technical Data 5
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OH
OH
OL
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Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F803 are organized into functional groups, as shown in Table 2 and
as illustrated in Figure 2. In Table 3 through Table 18, each table row describes the signal or signals
present on a pin.
Table 2. Functional Group Pin Allocations
Functional Group
Power (V
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Ground (VSS or V
Supply Capacitors 2 Table 5
PLL and Clock 3 Table 6
Address Bus
Data Bus 16 Table 8
Bus Control 4 Table 9
Interrupt and Program Control 4 Table 10
Pulse Width Modulator (PWM) Port 12 Table 11
Serial Peripheral Interface (SPI) Port
Quadrature Decoder Port
Serial Communications Interface (SCI) Port
CAN Port 2 Table 15
DD
or V
1
)7Table 3
DDA
)7Table 4
SSA
1
2
1
Number of
Pins
16 Table 7
4 Table 12
4 Table 13
2 Table 14
Detailed
Description
Frees
Analog to Digital Converter (ADC) Port 9 Table 16
Quad Timer Module Port 2 Table 17
JTAG/On-Chip Emulation (OnCE) 6 Table 18
1. Alternately, GPIO pi ns
2. Alternatel y, Q ua d Tim e r pins
6 56F803 Technical Data
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Power Port
Ground Port
Power Port
Ground Port
Other
Supply
Ports
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Introduction
V
DD
V
SS
V
DDA
V
SSA
VCAPC
6
6*
1
1
2
6
3
3
PWMA0-5
ISA0-2
FAULTA0-2
PWMA
Port
PLL
and
Clock
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External
Address Bus or
GPIO
External
Data Bus
External
Bus Control
Quadrature
Decoder or
Quad Timer A
A6-7 (GPIOE2-E3)
A8-15 (GPIOA0-A7)
PHASEA0 (TA0)
PHASEB0 (TA1)
cale Semiconductor,
EXTAL
XTAL
CLKO
A0-A5
D0–D15
PS
DS
RD
WR
INDEX0 (TA2)
HOME0 (TA3)
1
1
1
6
2
8
16
1
1
1
1
1
1
1
1
56F803
1
1
1
1
1
1
8
1
1
1
SCLK (GPIOE4)
MOSI (GPIOE 5)
MISO (GPIOE6)
SS
(GPIOE7)
TXD0 (GPIOE0)
RXD0 (GPIOE1)
ANA0-7
VREF
MSCAN_RX
MSCAN_TX
SPI Port
or GPIO
SCI0 Port
or GPIO
ADCA
Port
CAN
Frees
TCK
TMS
JTAG/OnCE
*includes TCS pin which is reserved for factory use and is tied to VSS
Port
TDI
TDO
TRST
DE
1
1
1
1
1
1
2
1
1
1
1
TD1-2
IRQA
IRQB
RESET
EXTBOOT
Figure 2. 56F803 Signals Identified by Functional Group
1. Alternate pin functionality is shown in parenthesis.
56F803 Technical Data 7
Quad
Timer D
Interrupt/
Program
Control
1
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2.2 Power and Ground Signals
Table 3. Power Inputs
No. of Pins Signal Name Signal Description
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6 V
1 V
DD
DDA
Power—These pins provide power to the internal structures of the chip, and
should all be attached to V
Analog Power—This pin is a dedicate d powe r pin for the analog portion of the
chip and should be connected to a low noise 3.3V supply.
DD.
Table 4. Grounds
No. of Pins Signal Name Signal Description
5 V
1 V
1 TCS TCS—This Schmitt pin is reserved for factory use and must be tied to VSS for
GND—These pins provide grounding for the internal structures of the chip, and
SS
SSA
should all be attached to V
Analog Ground—This pin supplies an analog ground.
normal use. In block diagrams, this pin is considered an additional V
SS.
Table 5. Supply Capacitors
No. of
Pins
2 VCAPC Supply Supply VCAPC—Connect each pin to a 2.2 µF or greater bypass
Signal
Name
Signal
Type
State During
Reset
Signal Description
capacitor in order to bypass the core logic voltage regulator
(required for proper chip operation). For more information, please
refer to Section 5.2.
2.3 Clock and Phase Locked Loop Signals
Table 6. PLL and Clock
No. of
Pins
1 EXTAL Input Input External Crystal Oscillator Input—This input should be
Signal
Name
Signal
Type
State During
Reset
Signal Description
connected to an 8MHz exte rnal crystal or cera mic resonator. For
more information, please refer to Section 3.5.
SS.
1 XTAL Input/
Output
8 56F803 Technical Data
Chip-driven Crystal Oscillator Output —This output shou ld be conne cted to
an 8MHz external crystal or ceramic resonator. For more
information, please refer to Section 3.5.
This pin can also be connected to an external clock source. For
more information, please refer to Section 3.5.3 .
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Address, Data, and Bus Control S ignals
Table 6. PLL and Clock (Continued)
No. of
Pins
1 CLKO Output Chip-driven Clock Output—This pin outputs a buffered clock signal. By
Signal
Name
Signal
Type
State During
Reset
Signal Description
programming the CLKOSEL[4:0] bits in the CLKO Select
Register (CLKOSR), the user can select between outputting a
version of the signal applied to XTAL and a version of the
device’s master clock at the output of the PLL. The clock
frequency on this pin can also be disabled by programming the
CLKOSEL[4:0] bits in CLKOSR.
2.4 Address, Data, and Bus Control Signals
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No. of
Pins
6 A0–A5 Output Tri-stated Address Bus—A0–A5 specify the address for external Program
2 A6–A7
8 A8–A15
Signal
Name
GPIOE2–
GPIOE3
GPIOA0
GPIOA7
–
Signal
Type
Output
Input/
Output
Output
Input/
Output
Table 7. Address Bus Signals
State During
Reset
or Data memory accesses.
Tri-stated
Input
Tri-stated
Input
Address Bus—A6–A7 specify the address for external Program
or Data memory accesses.
Port E GPIO—These two pins are General Pu rpose I/O (GPIO)
pins that can be i ndi vi dua lly programmed as in put or output pins.
After reset, the default state is Address Bus.
Address Bus—A8–A15 specify the address for external
Program or Da ta memory accesses.
Port A GPIO—These eight p ins are Genera l Purpose I/O (GPIO)
pins that can be i ndi vi dua lly programmed as in put or output pins.
After reset, the default state is Address Bus.
Signal Description
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Table 8. Data Bus Signals
No. of
Pins
16 D0–D15 Input/
56F803 Technical Data 9
Signal
Name
Signal
Type
Output
State During
Reset
Tri-stated Data Bus— D0–D15 specify the data for external Program or
Data memory accesses. D0–D15 are tri-stated when the
external bus is inactive. Internal pull-ups may be active.
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Signal Description
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Table 9. Bus Control Signals
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No. of
Pins
1 PS
1 DS
1 WR
1 RD
Signal
Name
Signal
Type
Output Tri-stated Program Memory Select—PS is asserted low for ex tern al Progra m
Output Tri-stated Data Memory Select—DS is asserted low for external Data memory
Output Tri-stated Write Enable—WR is asse rted during external memory w rite cycles .
Output Tri-stated Read Enable—RD is asserted during external memory read cycles.
State During
Reset
Signal Description
memory access.
access.
When WR
device puts data on the bus. When WR
external data is latched inside the external device. When WR
asserted, it qualifies the A0–A15, PS
connected directly to the WE
When RD
external device is enabled onto the device data bus. When RD
deasserted high, the external data is latched inside the hybrid
controller. When RD is asserted, it qualifies the A0–A15, PS, and DS
pins. RD
ROM.
is asserted low, pins D0–D15 become outputs and the
pin of a Static RAM.
is asserted low, pins D0–D15 become inputs and an
can be connected directly to the OE pin of a Static RAM or
2.5 Interrupt and Program Control Signals
Table 10. Interrupt and Program Control Signals
No. of
Pins
1 IRQA
1 IRQB Input
Signal
Name
Signal
Type
Input
(Schmitt)
(Schmitt)
State During
Reset
Input External Interrupt Request A—The IRQA input is a
synchronized external interrupt request indicating an
external device is requesting service. It can be programmed
to be level-sensitive or negat iv e-ed ge- trig gered.
Input External Interrupt Request B—The IRQB input is an
external interrupt request indicating an external device is
requesting service. It can be programmed to be levelsensitive or negative-edge-triggered.
Signal Description
is deasserted high, the
is
, and DS pins. WR can be
is
10 56F803 Technical Data
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Pulse Width Modulator (PWM ) Signals
Table 10. Interrupt and Program Control Signals (Continued)
No. of
Pins
1 RESET Input
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1 EXTBOOT Input
Signal
Name
Signal
Type
(Schmitt)
(Schmitt)
State During
Reset
Input Reset—This input is a direct hardware reset on the
processor. When RESET
controller is initialized and placed in the Reset state. A
Schmitt trigger input is used for noise immunity. When the
RESET
latched from the EXTBO OT pin . The int ernal re set signa l will
be deasserted synchronous with the internal clocks, after a
fixed number of internal clocks.
To ensure a complete hardware reset, RESET
should be asserted together. The only exception occurs in a
debugging environment when a hardware device reset is
required and it is necess ary not to reset the OnCE/JTAG
module. In this c ase, as se rt RESET
Input External Boot—This input is tied to V
boot from off-chip memory. Otherwise, it is tied to VSS.
pin is deasserted, the initial chip operating mode is
Signal Description
is asserted low, the hybrid
, but do not asse rt TRST.
DD
to force device to
and TRST
2.6 Pulse Width Modulator (PWM) Signals
Table 11. Pulse Width Modulator (PWMA) Signals
No. of
Pins
6
3
cale Semiconductor,
3
Signal
Name
PWMA0
ISA0–2
FAULTA0
–5
Signal
Type
Output Tri-stated
Input
(Schmitt)
–2
Input
(Schmitt)
State During
Reset
Input
Input
Signal Description
PWMA0–5— These are six PWMA output pins.
ISA0–2— These three input current s tatu s pi ns are u sed for
top/bottom pulse widt h corre ction in co mplem entary chan nel
operation for PWMA.
FAULTA0–2— These three fault input pins are used for
disabling selected PWMA outputs in cases where fault
conditions originate off-chip.
Frees
56F803 Technical Data 11
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2.7 Serial Peripheral Interface (SPI) Signals
Table 12. Serial Peripheral Interface (SPI) Signals
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No. of
Pins
1 MISO
1 MOSI
1 SCLK
1 SS
Signal
Name
GPIOE6
GPIOE5
GPIOE4
GPIOE7
Signal
Type
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input
Input/
Output
State During
Reset
Input
Input
Input
Input
Input
Input
Input
Input
Signal Description
SPI Master In/Slave Out (MISO)—This serial data pin is an
input to a master device and an output from a slave device.
The MISO line of a slave device is placed in the high
impedance state if the slave device is not selected.
Port E GPIO—This General Purpose I/O (GPIO) pin can be
individually programmed as an input or output pin.
After reset, the default state is MISO.
SPI Master Out/Slave In (MOSI)—This serial data pin is an
output from a master device and an input to a slave device.
The master device places data on the MOSI line a half-cycle
before the clock edge that the slave device uses to latch the
data.
Port E GPIO—This General Purpose I/O (GPIO) pin can be
individually programmed as an input or output pin.
After reset, the default state is MOSI.
SPI Serial Clock—In master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin
serves as the data clock input.
Port E GPIO—This General Purpose I/O (GPIO) pin can be
individually programmed as an input or output pin.
After reset, the default state is SCLK.
SPI Slave Select—In master mode, this pin is used to
arbitrate multiple masters. In slave mode, this pin is used to
select the slave.
Port E GPIO—This General Purpose I/O (GPIO) pin can be
individually programmed as an input or output pin.
After reset, the default state is SS
.
12 56F803 Technical Data
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Quadrature Decoder Signals Serial Communications
2.8 Quadrature Decoder Signals Serial Communications
Table 13. Quadrature Decoder (Quad Dec0) Signals
No. of
Pins
1 PHASEA0
1 PHASEB0
1 INDEX0
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1 HOME0
Signal
Name
TA0
TA1
TA2
TA3
Signal
Type
Input
Input/Output
Input
Input/Output
Input
Input/Output
Input
Input/Output
State During
Reset
Input
Input
Input
Input
Input
Input
Input
Input
Signal Description
Phase A—Quadrature Decoder #0 PHASEA input
TA0—Timer A Channel 0
Phase B—Quadrature Decoder #0 PHASEB input
TA1—Timer A Channel 1
Index—Quadrature Decoder #0 INDEX input
TA2—Timer A Channel 2
Home—Quadrature Decoder #0 HOME inpu t
TA3—Timer A Channel 3
2.9 Interface (SCI) Signals
Table 14. Serial Communications Interface (SCI0) Signals
No. of
Pins
1 TXD0
cale Semiconductor,
1 RXD0
Signal
Name
GPIOE0
GPIOE1
Signal Type
Output
Input/Output
Input
Input/Output
State During
Reset
Input
Input
Input
Input
Signal Description
Transmit Data (TXD0)—SCI0 transmit data output
Port E GPIO—This General Purpose I/O (GPIO) pin can
be individually programmed as an input or output pin.
After reset, the default state is SCI output.
Receive Data (RXD0)— SCI0 receive data input
Port E GPIO—This General Purpose I/O (GPIO) pin can
be individually programmed asan input or output pin.
Frees
After reset, the default state is SCI input.
2.10 CAN Signals
Table 15. CAN Module Signals
No. of
Pins
1 MSCAN_ RX Input
1 MSCAN_ TX Output Output MSCAN Transmit Data—MSCAN output. CAN output is
56F803 Technical Data 13
Signal
Name
Signal
Type
(Schmitt)
State During
Reset
Input MSCAN Receive Data—This is the MSCAN input. This
pin has an internal pull-up resistor.
open-drain output and a pull-up resistor is needed.
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Signal Description
Freescale Semiconductor, Inc.
2.11 Analog-to-Digital Converter (ADC) Signals
Table 16. Analog to Digital Converter Signals
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cale Semiconductor,
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No. of
Pins
4
4
1 VREF Input Input VREF—Analog reference voltage for ADC. Must be set to
Signal
Name
–3
ANA0
ANA4–7
Signal
Type
Input Input
Input Input
State During
Reset
Signal Description
ANA0–3—Analog inputs to ADC channel 1
ANA4–7—Analog inputs to ADC channel 2
V
-0.3V for optimal performance.
DDA
2.12 Quad Timer Module Signals
Table 17. Quad Timer Module Signals
No. of Pins Signal Name Signal Type State During Reset Signal Description
2
TD1
–2
Input/Output Input
TD1–2— Timer D Channel 1–2
2.13 JTAG/OnCE
Table 18. JTAG/On-Chip Emulation (OnCE) Signals
No. of
Pins
1 TCK Input
1 TMS Input
1 TDI Input
1 TDO Output Tri-stated Test Data Output—This tri-statable output pin provides a serial
Signal
Name
Signal
Type
(Schmitt)
(Schmitt)
(Schmitt)
State During
Reset
Input, pulled lo w
internally
Input, pulled
high internally
Input, pulled
high internally
Signal Description
Test Clock Input—This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/OnCE
port. The pin is connected internally to a pull-down resistor.
Test Mode Select Input—This input pin is used to se quence the
JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
Test Data Input—This input pin provides a serial input data
stream to the JTAG/OnCE port. It is sampled on the rising edge
of TCK and has an on-chip pull-up resistor.
output data stream from the JTAG/OnCE port. It is driven in the
Shift-IR and Shift-DR con troller stat es, and chang es on the fa lling
edge of TCK.
1 TRST
1 DE
14 56F803 Technical Data
Input
(Schmitt)
Output Output Debug Event—DE provides a low pulse on recognized debug
Input, pulled
high internally
Test Reset—As an inpu t, a low signal on this pin provides a reset
signal to the JTAG TAP controller. To ensure complet e hardware
reset, TRST should be asserted at power-up and whenever
is asserted. The only exception occurs in a debugging
RESET
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case,
assert RESET
events.
, but do not assert TRST.
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General Characteristics
Part 3 Specifications
3.1 General Characteristics
The 56F803 is fabrica ted in high-de nsity CMOS with 5- V tolerant TTL-c ompatible d igital i nputs. The te rm
“5-V tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to
withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V-compatible
I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V
normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in Table 19 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
± 10% during
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cale Semiconductor,
Frees
The 56F803 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.
CAUTION
This device contains protective circuitry to guard against damage due
to high static voltage or electrical fields. However, normal precautions
are advised to avoid application of any voltages higher than maximum
rated voltages to this high-impedance circuit. Reliability of operation is
enhanced if unused inputs are tied to an appropriate voltage level.
Table 19. Absolute Maximum Ratings
Characteristic Symbol Min Max Unit
Supply voltage V
All other input voltages, excluding Analog inputs V
DD
IN
V
– 0.3 V
SS
VSS – 0.3 V
+ 4.0 V
SS
+ 5.5V V
SS
Analog inputs ANA0-7 and VREF V
Analog inputs EXTAL and XTAL V
Current drain per pin excluding VDD, VSS, PWM outputs, TCS,
VPP, V
56F803 Technical Data 15
DDA
, V
SSA
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IN
IN
I — 10 mA
V
V
SSA
SSA
– 0.3 V
– 0.3 V
+ 0.3 V
DDA
+ 3.0 V
SSA