MOTOROLA 17517 Technical data

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

1.0 A 6.8 V Dual Motor Driver IC

The 17517 is a monolithic triple totem-pole-output power IC designed to be
used in portable electronic applications to control small DC motors and
solenoids. The 17517 can operate efficiently with supply voltages as low as

2.0 V to as high as 6.8 V. Its low R
typical) can provide continuos drive currents of 1.0 A and handle peak currents

up to 3.0 A. It is easily interfaced to low-cost MCUs via parallel 3.0 V- or 5.0 V­compatible logic. The device can be pulse width modulated (PWM-ed) at up to
200 kHz.

The 17517 can drive two motors in two directions one at a time or drive one
motor in two directions and one solenoid with synchronous rectification of
freewheeling currents one at a time. Two-motor operation is accomplished by
hooking one motor between OUTA and OUTB and hooking the other motor
between OUTB and OUTC. Motor plus solenoid operation is accomplished by
hooking a motor between OUTA and OUTB and a solenoid between OUTC
and GND.

This device contains an integrated charge pump and level shifter (for gate
drive voltages), integrated shoot-through current protection (cross-conduction
suppression logic and timing), and undervoltage detection and shutdown
circuitry.

The 17517 has four operating modes: Forward, Reverse, Brake, and
Tri-Stated (High Impedance).

Features

• 2.0 V to 6.8 V Continuous Operation

• Output Current 1.0 A (DC), 3.0 A (Peak)

•MOSFETs < 600mΩ R

• 3.0 V/5.0 V TTL-/CMOS-Compatible Inputs

• PWM Frequencies up to 200 kHz

• Undervoltage Shutdown

DS(ON)

totem-pole output MOSFETs (0.46 Ω

DS(ON)

@ 25°C Guaranteed

Simplified Application Diagram

17517 Simplified Application Diagram

5.0 V 5.0 V

17517

V

DD

C1L
C1H
C2L
C2H

C

RES

EN1

MCU

EN2
IN1
IN2

GND

VM

OUTC

OUTA

OUTB

Document order number: MPC17517

17517

1.0 A 6.8 V DUAL MOTOR
DRIVER IC

DTB SUFFIX

CASE 948F-01

16-LEAD TSSOP

ORDERING INFORMATION

Device

MPC17517DTB/R2 -20°C to 65°C 16 TSSOP

Solenoid

MOTOR

Temperature

Range (T

)

A

Rev 1.0, 03/2004

Package

This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.

© Motorola, Inc. 2004

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C2L

C1H

C

RES

V

EN1

EN2

DD

IN1

IN2

Charge Pump

Low-

Voltage

Shutdown

Level

Shifter

Predriver

Control

Logic

Figure 1. 17517 Simplified Internal Block Diagram

C2H

C1L

VM

OUTC

OUTB

OUTA

GND

17517 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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V

DD

VM

OUTA

C

RES

C2H

C2L

IN1

IN2

TERMINAL FUNCTION DESCRIPTION

Terminal

1 V

2, 13 VM Motor Drive Power Supply Motor power supply voltage input terminals.

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3 OUTA Output A Driver output A terminal.

4 C

5

6 C2L Charge Pump 2L Charge pump bucket capacitor 2 (negative pole).

7 IN1 Input Control 1 Control signal input 1 terminal.

8 IN2 Input Control 2 Control signal input 2 terminal.

9 EN1 Enable Control Signal Input 1 Enable control signal input 1 terminal.

10 EN2 Enable Control Signal Input 2 Enable control signal input 2 terminal.

11 C1L Charge Pump 1L Charge pump bucket capacitor 1 (negative pole).

12 C1H Charge Pump 1H Charge pump bucket capacitor 1 (positive pole).

14 OUTB Output B Driver output B terminal.

15 GND Ground Ground connection.

16 OUTC Output C Driver output C terminal.

Terminal

Name

DD

RES

C2H Charge Pump 2H Charge pump bucket capacitor 2 (positive pole).

Charge Pump Output Capacitor

Formal Name Definition

Control Circuit Power Supply Positive power source connection for control circuit.

Connection

1

2

3

4

5

6

7

8

Charge pump reservoir capacitor terminal.

16

15

14

13

12

11

10

9

OUTC

GND

OUTB

VM

C1H

C1L

EN2

EN1

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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 17517

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MAXIMUM RATINGS

All voltages are with respect to ground unless otherwise noted. Exceeding the ratings may cause a malfunction or permanent
damage to the device.

Rating Symbol Value Unit

Motor Supply Voltage

Charge Pump Output Voltage

Logic Supply Voltage

Signal Input Voltage

Driver Output Current

Continuous

Peak (Note 1)

ESD Voltage

Human Body Model (Note 2)

Machine Model (Note 3)

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Storage Temperature Range

Operating Junction Temperature

Operating Ambient Temperature

Thermal Resistance (Note 4)

Power Dissipation (Note 5)

Soldering Temperature (Note 6)

Notes

1. T

= 25°C, 10 ms pulse width at 200 ms intervals.

A

2. ESD1 testing is performed in accordance with the Human Body Model (C

3. ESD2 testing is performed in accordance with the Machine Model (C

4. 37 mm x 50 mm Cu area (1.6 mm FR-4 PCB).

5. Maximum at T

6. Soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.

= 25°C.

A

T

ZAP

= 200 pF, R

ZAP

V

M

V

C

RES

V

DD

V

IN

I

O

I

OPK

V

ESD1

V

ESD2

T

STG

T

J

T

A

R

JA

θ

P

D

SOLDER

= 100 pF, R

ZAP

= 1500 Ω).

ZAP

= 0 Ω).

-0.5 to 8.0 V

-0.5 to 14 V

-0.5 to 7.0 V

-0.5 to VDD+0.5 V

1.0

3.0

±2000

±100

-65 to 150 °C

-20 to 150 °C

-20 to 65 °C

190 °C/W

657 mW

245 °C

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A

V

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STATIC ELECTRICAL CHARACTERISTICS

Characteristics noted under conditions TA = 25°C, VDD = VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted reflect
the approximate parameter means at T

Characteristic Symbol Min Typ Max Unit

POWER

Motor Supply Voltage

Logic Supply Voltage

Capacitor for Charge Pump

Standby Power Supply Current

Motor Supply Standby Current

Logic Supply Standby Current (Note 7)

Operating Power Supply Current

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Logic Supply Current (Note 8)

Charge Pump Circuit Supply Current

Low-Voltage Detection Circuit

Detection Voltage (V

Driver Output ON Resistance (Note 10)

) (Note 9)

DD

= 25°C under nominal conditions unless otherwise noted.

A

V

M

V

DD

C1, C2, C3 0.01 0.1 1.0 µF

I

V

MSTBY

I

V

DDSTBY

I

V

DD

I

C

RES

V

DET

DD

R

DS(ON)

2.0 5.0 6.8 V

2.7 5.0 5.7 V

–

–

–

–

1.5 2.0 2.5

– 0.46 0.60 Ω

–

–

–

–

1.0

1.0

3.0

0.7

µA

mA

mA

V

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GATE DRIVE

Gate Drive Voltage (Note 11)

No Current Load

Gate Drive Ability (Internally Supplied)

I

C

= -1.0 mA

RES

CONTROL LOGIC

Logic Input Voltage

Logic Input Function (2.7 V < V

High-Level Input Voltage

Low-Level Input Voltage

High-Level Input Current

Low-Level Input Current

Notes

7.IV

8.IV

9. Detection voltage is defined as when the output becomes high-impedance after V

voltage

10. I

O

11. Input logic signal not present.

includes current to the predriver circuit.

DDSTBY

includes current to the predriver circuit.

DD

V

C

is applied from an external source,

RES

= 1.0 A source + sink.

< 5.7 V)

DD

V

C

= 7.5 V.

RES

µA

µA

V

V

V

V

V

C

RES

V

C

RES

load

V

IN

V

IH

V

IL

I

IH

I

IL

drops below the detection threshold. When the gate

DD

12 13 13.5

10 11.2 –

0–VDDV

VDDx0.7

–

–

-1.0

–

–

–

–

–

V

x0.3

DD

1.0

–

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 17517

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DYNAMIC ELECTRICAL CHARACTERISTICS

Characteristics noted under conditions TA = 25°C, VDD = VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values noted reflect
the approximate parameter mean at T

INPUT (IN1, IN2, EN1, EN2)

Pulse Input Frequency

Input Pulse Rise Time (Note 12)

Input Pulse Fall Time (Note 14)

OUTPUT

Propagation Delay Time

Turn-ON Time

Turn-OFF Time

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Charge Pump Wake-Up Time (Note 15)

I

Low-Voltage Detection Time

Characteristic Symbol Min Typ Max Unit

= 25°C under nominal conditions unless otherwise noted.

A

f

IN

t

R

t

F

t

PLH

t

PHL

t

VGON

t

VDDDET

– – 200 kHz

––1.0

––1.0

–

–

–0.13.0ms

––10ms

0.1

0.1

(Note 13)

(Note 13)

0.5

0.5

µs

µs

µs

Notes

12. Time is defined between 10% and 90%.

13. That is, the input waveform slope must be steeper than this.

14. Time is defined between 90% and 10%.

15. When C1 = C2 = C3 = 0.1 µF.

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IN1, IN2,
EN1, EN2

OUTA,
OUTB,
OUTC

t

PLH

50%

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Timing Diagrams

t

VGON

11 V

90%

10%

t

PHL

V

DD

V

C

RES

Figure 2. t

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V

DD

0.8 V/

1.5 V

I

M

DETon

V

DD

t

VDDDET

Figure 3. Low-Voltage Detection Timing

, t

PLH

PHL

2.5 V/3.5 V

50%

, and t

90%

PZH

V

DD

Timing

DEToff

t

VDDDET

0%
(<1.0 µA)

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Figure 4. Charge Pump Timing

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INPUT OUTPUT

IN1 IN2 EN1 EN2 OUTA OUTB OUTC

Shutdown Mode

XXL L Z Z Z

Channel 1 (A–B) Driving Mode

HHHL L L Z

HLHLHL Z

LHHLLH Z

LLHLZZ Z

Channel 2 (B–C) Driving Mode

HHLH Z L L

HLLHZH L

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LHLHZL H

LLLHZZ Z

Half-Bridge (C) Driving Mode

HHHHZ Z Z

HLHHZZ H

LHHHZZ L

LLHHZZ Z

H = High.
L = Low.
Z = High impedance.
X = Don’t care.

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Table 1. Truth Table

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SYSTEM/APPLICATION INFORMATION

INTRODUCTION

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The 17517 is a triple totem-pole output H-Bridge power IC

designed to drive small dc motors used in portable electronics.
The 17517 can operate efficiently with supply voltages as low
as 2.0 V to as high as 6.8 V, and provide continuos motor drive
currents of 1.0 A while handling peak currents up to 3.0 A. It is
easily interfaced to low cost MCUs via parallel 3.0 V- or 5.0 V­compatible logic. The device can be pulse width modulated
(PWM-ed) at up to 200 kHz. The 17517 can drive two motors in
two directions one at a time; or it can drive one motor in two
directions and one solenoid with synchronous rectification of
freewheeling currents one at a time. Two-motor operation is
accomplished by hooking one motor between OUTA and
OUTB, and the other motor between OUTB and OUTC.
Motor + solenoid operation is accomplished by hooking a motor

FUNCTIONAL TERMINAL DESCRIPTION

OUTA, OUTB, and OUTC

These terminals provide the connection to the internal power

MOSFET triple-totem-pole H-bridge of the IC.

GND

Power and signal ground terminal.

C

RES

This terminal provides the connection for the external

reservoir capacitor (output of the charge pump). Alternatively,
this terminal can also be used as an input to supply gate-drive
voltage from an external source via a series current-limiting
resistor.

The voltage at the C

times the V
voltage tripler circuit. The V
supply gate drive for the internal power MOSFETs.

VM

The two VM terminals carry the main supply voltage and

current into the power sections of the IC. This supply then
becomes controlled and/or modulated by the IC as it delivers
the power to the load attached between OUTA and OUTB.

voltage, as the internal charge pump utilizes a

DD

terminal will be approximately three

RES

voltage is used by the IC to

DDRES

between OUTA and OUTB and placing a solenoid between
OUTC and GND. Table 1,
operating states versus the input conditions.

As shown in Figure 1, 17517 Simplified Internal Block

Diagram, page 2, the 17517 is a monolithic triple totem-pole

output bridge with built-in charge pump circuitry. Each of the six
MOSFETs forming the triple totem-pole output has an R

of ≤ 0.6 Ω (guaranteed by design). The IC has an integrated
charge pump and level shifter (for gate drive voltages).
Additionally, the IC has a built-in shoot-through current
protection circuit and undervoltage lockout function. This IC has
four operating modes: Forward, Reverse, Brake, and Tri-Stated
(High Impedance).

The VM terminals must be connected together on the printed
circuit board with as short as possible traces offering as low
impedance as possible between terminals.

IN1, IN1, EN1, and EN2

These terminals are input control terminals used to control
the outputs. These terminals are 3.0 V/ 5.0 V CMOS-compatible
inputs with hysteresis. These terminals work together to control
OUTA, OUTB, and OUTC (refer to Table 1,

C1L and C1H, C2L and C2H

These two pairs of terminals, the C1L and C1H and the C2L
and C2H, connect to the external bucket capacitors required by
the internal charge pump. The typical value for the bucket
capacitors is 0.1 µF.

V

DD

This terminal carries the logic supply voltage and current into
the logic sections of the IC. V

If the supply voltage drops below the undervoltage threshold,
the output power stage switches to a tri-state condition. When
the supply voltage returns to a level that is above the threshold,
the power stage automatically resumes normal operation
according to the established condition of the input terminals.

Truth Table, page 8, describes the

DS(ON)

Truth Table).

has an undervoltage threshold.

DD

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APPLICATIONS

Typical Application

Figure 5 shows a typical application for the 17517. When

applying the gate voltage to the C

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V

C

RES

NC = No Connect

terminal from an external

RES

< 14 V

RG > VC

/0.02 Ω

RES

R

G

MCU

Figure 5. 17517 Typical Application Diagram

0.01 µF

CEMF Snubbing Techniques

Care must be taken to protect the IC from potentially
damaging CEMF spikes induced when commutating currents in
inductive loads. Typical practice is to provide snubbing of
voltage transients by placing a capacitor or zener at the supply
terminal (VM) (see Figure 6

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5.0 V

V

C1L

C1H

C2L

C2H

C

17517

DD

RES

5.0 V

VM

OUT

OUT

GND

).

5.0 V

V

C1L

C1H

C2L

C2H

C

17517

DD

RES

5.0 V

VM

OUT

OUT

GND

NC
NC
NC
NC

source, be sure to connect it via a resistor equal to, or greater

DD

=

G

VM

OUTA

OUTB

OUTC

V

C

/0.02 Ω.

RES

17517

C1L
C1H
C2L
C2H

C

RES

EN1
EN2
IN1
IN1

than, R

5.0 V

V

GND

PCB Layout

When designing the printed circuit board (pcb), connect
sufficient capacitance between power supply and ground
terminals to ensure proper filtering from transients. For all high­current paths, use wide copper traces and shortest possible
distances.

Figure 6. CEMF Snubbing Techniques

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PACKAGE DIMENSIONS

DTB SUFFIX

16-LEAD TSSOP

PLASTIC PACKAGE

CASE 948F-01

ISSUE O

16X REFK

0.10 (0.004) V

S

U0.15 (0.006) T

16

2X L/2

L

PIN 1

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0.10 (0.004)

SEATING

-T-

PLANE

IDENT.

U0.15 (0.006) T

D

1

S

C

A

-V-

M

9

8

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S

H

N

S

J

N

DETAIL E

DETAIL E

J1

0.25 (0.010)

F

K

K1

SECTION N-N

M

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE
ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE -W-.

DIM MIN MAX MIN MAX

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C --- 1.20 --- 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030

-W-

G 0.65 BSC 0.026 BSC
H 0.18 0.28 0.007 0.011
J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

°°°°

INCHESMILLIMETERS

U

T

B

-U-

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Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied
copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product
or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be
provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license
under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for
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MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their
respective owners.

© Motorola, Inc. 2004

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MPC17517