Mitsubishi MH8V64AWZJ-6, MH8V64AWZJ-5 Datasheet
Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI LSIs
MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
DESCRIPTION
The MH8V64AWZJ is 8388608-word x 64-bit dynamic
ram module. This consist of eight industry standard 8M x
8 dynamic RAMs in SOJ and one industry standard
EEPROM is TSSOP.
The mounting of SOJs and TSSOP on a card edge dual
in-line package provides any application where high
densities and large of quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
/RAS
/CAS Address /OE Cycle Power
access
access
access
Type name
MH8V64AWZJ-5
MH8V64AWZJ-6
time
(max.ns)
50
60
time
(max.ns)
13 25 13
15 30
Utilizes industry standard 8M x 8 RAMs in SOJ and industry
standard EEPROM in TSSOP
168-pin (84-pin dual dual in-line package)
Single +3.3V(±0.3V) supply operation
Low stand-by power dissipation
8.64mW(Max) . . . . . . . . . . . . . . . . . . . LVCMOS input level
Low operation power dissipation
MH8V64AWZJ -5 . . . . . . . . . . . . . . . . . . 2.88W(Max)
MH8V64AWZJ -6 . . . . . . . . . . . . . . . . . . 2.60W(Max)
All input are directly LVTTL compatible
All output are three-state and directly LVTTL compatible
Includes(0.22uF x 8) decoupling capacitors
4096 refresh cycle every 64ms
Fast-page mode,Read-modify-write,
/CAS before /RAS refresh,Hidden refresh capabilities
JEDEC standard pin configuration and SPD
Gold plating contact pads
time
(max.ns)
access
time
(max.ns)
15
time
(min.ns)
90
110
dissipation
(typ.W)
2.40
2.00
PIN CONFIGURATION
85pin
94pin
95pin
124pin
BACK SIDE
125pin
1pin
10pin
11pin
40pin
FRONT SIDE
41pin
Row Address
Column Address
A0 ~ A12
A0 ~ A9
APPLICATION
Main memory unit for computers , Microcomputer memory
MIT-DS-0107-0.5
MITSUBISHI
ELECTRIC
1
( / 20 )
168pin
84pin
25/Feb./1997
Preliminary Spec.
Specifications subject to
change without notice.
MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
MITSUBISHI LSIs
PIN CONFIGURATION
Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
MIT-DS-0107-0.5
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
NC
NC
Vss
NC
NC
Vcc
/WE0
/CAS0
/CAS1
/RAS0
/OE0
Vss
A0
A2
A4
A6
A8
A10 A11
A12
Vcc
Vcc
DU
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Vss
/OE2
/RAS2
/CAS2
/CAS3
/WE2
Vcc
NC
NC
NC
NC
Vss
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
DU
NC
Vss
DQ21
DQ22
DQ23
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
NC
NC
NC
SDA
SCL
Vcc
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
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ELECTRIC
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2
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
NC
NC
Vss
NC
NC
Vcc
DU
/CAS4
/CAS5
NC
DU
Vss
A1
A3
A5
A7
A9
NC
Vcc
DU
DU
NC: No Connect
DU: Don't Use
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Vss
DU
NC
/CAS6
/CAS7
DU
Vcc
NC
NC
NC
NC
Vss
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
DU
NC
Vss
DQ53
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
NC
NC
SA0
SA1
SA2
Vcc
25/Feb./1997
Preliminary Spec.
Specifications subject to
change without notice.
BLOCK DIAGRAM
MITSUBISHI LSIs
MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
/RAS0
/WE0
/OE0
/CAS0
/CAS1
/CAS2
/CAS3
M5M467800AJ
D0
M5M467800AJ
D1
M5M467800AJ
D3
M5M467800AJ
D4
/RAS2
/WE2
/OE2
DQ0
/RAS/W/OE
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
/RAS/W/OE
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
/RAS/W/OE
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
/RAS/W/OE
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
/CAS4
/CAS5
/CAS6
/CAS7
M5M467800AJ
D5
M5M467800AJ
D6
M5M467800AJ
D7
M5M467800AJ
D8
DQ32
/RAS/W/OE
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
/RAS/W/OE
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
/RAS/W/OE
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
/RAS/W/OE
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
A0~A12
Vcc
Vss
MIT-DS-0107-0.5
C0~C8
. . .
D0~D8
D0~D8
MITSUBISHI
ELECTRIC
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3
SCL
EEPROM
A0 A1 A2
SA2SA1SA0
SDA
25/Feb./1997
Preliminary Spec.
Specifications subject to
change without notice.
MH8V64AWZJ -5, -6
MITSUBISHI LSIs
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
Serial Presence Detect TABLE
Bytes Function described SPD entry data SPD DATA entry(Hex)
0 Defines # bytes written into serial memory at module mfgr 128 80
1 Total # bytes of SPD memory device 256 Bytes 08
2 Fundamental memory type FPM DRAM 01
3 # Row Addresses on this assembly A0-A12 0D
4 # Column Addresses on this assembly A0-A9 0A
5 # Module Banks on this assembly 1bank 01
6 Data Width of this assembly... x64 40
7 ... Data Width continuation 0 00
8 Voltage interface standard of this assembly 3.3V LVTTL 02
9 RAS# access time of this assembly -5 50ns 32
-6 60ns 3C
10 CAS# access time of this assembly -5 13ns 0D
-6 15ns 0F
11 DIMM Configuration type (Non-parity,Parity,ECC) non parity 00
12 Refresh Rate/Type N/R(15.625uS) 00
13 DRAM width,Primary DRAM x8 08
14 Error Checking DRAM data width N/A 00
15-31 Reserved for future offerings open 00
32-61 Superset Memory type(may be used in future) open 00
62 SPD Data Revision Code Rev 1 01
63 Checksum for bytes 0-62 Check sum for -5 2B
Check sum for -6 37
64-71 Manufacturers JEDEC ID code per JEP-106 MITSUBISHI 1CFFFFFFFFFFFFFF
72 Manufacturing location Miyoshi,Japan 01
Tajima,Japan 02
NC,USA 03
Germany 04
73-90 Manufacturer's Part Number MH8V64AWZJ-5 4D483856363441575A4A2D352D35202020202020
MH8V64AWZJ-6 4D483856363441575A4A2D362D36202020202020
91-92 Revision Code PCB revision rrrr
93-94 Manufacturing date year/week code yy/ww
95-98 Assembly Serial Number serial number ssssssss
99-125 Manufacturer Specific Data open 00
126-127 Reserved open 00
128-255 Open User Free-Form area not defined open 00
MIT-DS-0107-0.5
MITSUBISHI
ELECTRIC
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4
25/Feb./1997
Preliminary Spec.
Specifications subject to
change without notice.
MH8V64AWZJ -5, -6
MITSUBISHI LSIs
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
FUNCTION
The MH8V64AWZJ provide, in addition to normal
read, write, and read-modify-write operations,
Table 1 Input conditions for each mode
Operation
Read
Write (Early write)
Write (Delayed write)
Read-modify-write
/CAS before /RAS refresh
Standby
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open
/RAS /CAS
ACT
ACT
ACT
ACT
ACT
NAC
ACT
ACT
ACT
ACT
ACT
DNC
Inputs Input/Output
/W
NAC
ACT
ACT
ACT
NAC
DNC
a number of other functions, e.g., Fast page mode, /RASonly refresh, and delayed-write. The input conditions for
each are shown in Table 1.
/OE
ACT
DNC
DNC
ACT
DNC
DNC
Row
address
APD
APD
APD
APD
DNC
DNC
Column
address
APD
APD
APD
APD
DNC
DNC
Input
OPN
VLD
VLD
VLD
DNC
DNC
Output
Refresh Remark
VLD
OPN
IVD
VLD
OPN
OPN
YES
YES
YES
YES
YES
NO
Fast page
mode
identical
MIT-DS-0107-0.5
MITSUBISHI
ELECTRIC
( / 20 )
5
25/Feb./1997
Preliminary Spec.
Specifications subject to
change without notice.
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
VI Input Voltage
VO Output Voltage
IO
Pd
Topr
Tstg
Supply voltage
Output current
Power dissipation
Operating temperature
Storage temperature
MITSUBISHI LSIs
MH8V64AWZJ -5, -6
FAST PAGE MODE 536870912 - BIT ( 8388608 - WORD BY 64 - BIT ) DYNAMIC RAM
Parameter Conditions
With respect to Vss
Ta=25°C
Ratings
-0.5~ 4.6
-0.5~ Vcc+0.5
-0.5~ Vcc+0.5
50
8
0~70
-40~125
Unit
V
V
V
mA
W
°C
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Vcc
Vss
VIH
VIL
Note 1 : All voltage values are with respect to Vss
Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage
ELECTRICAL CHARACTERISTICS
Symbol
VOH
VOL
IOZ
I I
I I (CAS)
ICC1 (AV)
ICC2
ICC4(AV)
ICC6(AV)
Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc3 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Under condition of column address being changed once or less while /RAS=VIL and /CAS=VIH
High-level output voltage
Low-level output voltage
Off-state output current
Input current (except /CAS)
Input current (/CAS) 0V≤VIN≤Vcc+0.3, Other input pins=0V
Average supply
current
from Vcc operating
Supply current from Vcc , stand-by
Average supply current
from Vcc
Fast-Page-Mode
Average supply current from
Vcc
/CAS before /RAS refresh
mode
Parameter
Parameter
(Note 3,4,5)
(Note 3,4,5)
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted) (Note 2)
- 5
- 6
- 5
- 6
- 5
(Note 3,5)
- 6
(Ta=0~70°C, unless otherwise noted) (Note 1)
Limits
Min Nom Max
3.6
3.3
3.0
0
0
2.0
-0.3
IOH=-2.0mA
IOL=2.0mA
Q floating 0V ≤VOUT≤ Vcc
0V≤VIN≤Vcc+0.3, Other input pins=0V
/RAS, /CAS cycling
tRC=tWC=min.
output open
/RAS=/CAS =VIH, output open
/RAS=/CAS=WE≥Vcc -0.2, output open
/RAS=VIL,/CAS cycling
tPC=min.
output open
/CAS before /RAS refresh cycling
tRC=min.
output open
Vcc+0.3
0.8
Test conditions
Unit
V
V
0
V
V
Min
2.4
0
-10
-80
-10
Limits
Typ
Max
Vcc
0.4
10
80
10
800
720
820
640
1040
960
Unit
V
V
uA
uA
uA
mA
8
mA
4
mA
mA
CAPACITANCE
Symbol Parameter
CI (/CAS)
C(DQ)
C(SCL)
C(SDA) Input/Output capacitance,SPD DATA
C(SA0~3) Input capacitance, SPD address 7
MIT-DS-0107-0.5
(Ta = 0~70°C, Vcc = 3.3V±0.3V, Vss = 0V, unless otherwise noted)
Test conditions
Input capacitance, /CAS input
Input capacitance, except /CAS input 75
Input/Output capacitance,DATA
Input capacitance, SPD clock 7
VI=Vss
f=1MHZ
Vi=25mVrms
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6
Limits
Min Max
Typ
22
22
7
Unit
pF
pFCI
pF
pF
pF
pF
25/Feb./1997
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