Mitsubishi MH4M36CJD-7, MH4M36CJD-5, MH4M36CJD-6 Datasheet

MITSUBISHI LSIs

MH4M36CJD-5,-6,-7

FAST PAGE MODE ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM

DESCRIPTION

The MH4M36CJD is an 4M word by 36-bit dynamic
RAM module and consists of 8 industry standard
4M X 4 dynamic RAMs in TSOP and 4 industry
standard 4M X 1 dynamic RAMs in TSOP.
The ICs are mounted on both sides of small
ceracom PC boards and form a convenient 64-pin
WDIP package.

FEATURES

RAS

CAS

access

time

(max.ns)

Address

access

time

(max.ns)

35

(max.ns)

Type name

MH4M36CJD-5
MH4M36CJD-6
MH4M36CJD-7

Utilizes industry standard 4M X 4 DRAMs in TSOP package
and 4M X 1 DRAMs in TSOP package
Single 5V ± 10%supply
Low stand-by power dissipation

66mW (Max) . . . . . . . . . . . . . . . . . . . CMOS lnput level

Low operating power dissipation

MH4M36CJD - 5 . . . . . . . . . . . . . . . . . 9.15W (Max)

MH4M36CJD - 6 . . . . . . . . . . . . . . . . . 7.48W (Max)

MH4M36CJD - 7 . . . . . . . . . . . . . . . . . 6.51W (Max)

All inputs, output TTL compatible and low capacitance
2048 refresh cycles every 32ms (A0 ~ A10)
Includes 12 0.22uF decoupling capacitors

APPLICATION

Main memory unit for computers, Microcomputer memory,
Refresh memory for CRT

access

time

(max.ns)

50 13 25 90 724013
6070152030

OE

access

time

15
20

Cycle

time

(min.ns)

110
130

Power

dissipa-

(typ.mW)

tion

5920
5200

PIN CONFIGURATION ( TOP VIEW )

DQ0 1
DQ1 2
DQ2 3
DQ3 4
DQ4 5
DQ5 6

Vss 7
DQ6 8
DQ7 9

DQP0 10

/CAS0 11

DQ8 12
DQ9 13

Vcc 14

DQ10 15
DQ11 16
DQ12 17

DQ13 18

DQ14 19

DQ15 20

Vss 21

DQP1 22

/CAS1 23

A0 24

A1 25
A2 26

A3 27

Vcc 28

A4 29
A5 30
A6 31
A7 32

64 DQ16
63 DQ17
62 DQ18
61 DQ19
60 Vcc
59 DQ20
58 DQ21
57 DQ22
56 DQ23
55 DQP2
54 /CAS2
53 Vss
52 DQ24
51 DQ25
50 DQ26
49 DQ27
48 DQ28
47 DQ29
46 Vcc
45 DQ30
44 DQ31
43 DQP3
42 /CAS3
41 /RAS0
40 RFU
39 Vss
38 /W
37 RFU
36 RFU
35 A10
34 A9
33 A8

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ELECTRIC

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Jun/17/1996MIT-DS-0035-0.0

MITSUBISHI LSIs

MH4M36CJD-5,-6,-7

FAST PAGE MODE ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM

FUNCTION

The MH4M36CJD provide, in addition

e.g., fast page mode, RAS-only refresh.
The input conditions for each are shown in Table 1.

to normal read and write a number of other functions,

Table 1 Input conditions for each mode

Operation

Read
Write (Early write)
RAS-only refresh
Hidden refresh
CAS before RAS refresh

Standby

Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid,APD : applied, OPN : open

RAS CAS OE
ACT

ACT
ACT
ACT
ACT
NAC

ACT
ACT

NAC

ACT

ACT
DNC

Inputs Input/Output

W

NAC
ACT
DNC
DNC
NAC
DNC

ACT
DNC
DNC
ACT
DNC
DNC

BLOCK DIAGRAM

24,25,26,27,29,30,31,32,33,34,35

Add
/W

38

/RAS0

41

/CAS0

11

CAS RAS WE Add OE

M5M417400CTP

DQ0
DQ1
DQ2
DQ3

1
2
3
4

Row

address address

APD
APD
APD
DNC
DNC
DNC

Column

APD
APD
DNC
DNC
DNC
DNC

/CAS254

Input Output

OPN
APD
DNC
OPN
DNC
DNC

VLD
OPN
OPN
VLD
OPN
OPN

CAS RAS WE Add OE

M5M417400CTP

Refresh Remark

Fast page

YES

mode

YES

identical
YES
YES
YES

NO

DQ16
DQ17
DQ18
DQ19

64
63
62
61

CAS RAS WE Add OE

M5M417400CTP

DQ4
DQ5
DQ6
DQ7

5
6
8
9

CAS RAS WE Add OE

10 55

M5M44100CTP M5M44100CTP

DQP0

/CAS123 /CAS342

CAS RAS WE Add OE

M5M417400CTP

CAS RAS WE Add OE

M5M417400CTP

CAS RAS WE Add OE

M5M44100CTP M5M44100CTP

DQ8

12

DQ9

13
15

DQ10
DQ11

16

DQ12

17

DQ13

18

DQ14

19

DQ15

20

DQP1

22 43

CAS RAS WE Add OE

M5M417400CTP

CAS RAS WE Add OE

CAS RAS WE Add OE

M5M417400CTP

CAS RAS WE Add OE

M5M417400CTP

CAS RAS WE Add OE

DQ20
DQ21
DQ22
DQ23

DQP2

DQ24
DQ25
DQ26
DQ27

DQ28
DQ29
DQ30
DQ31

DQP3

59
58
57
56

52
51
50
49

48
47
45
44

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MITSUBISHI LSIs

MH4M36CJD-5,-6,-7

FAST PAGE MODE ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM

ABSOLUTE MAXIMUM RATINGS

Symbol

Vcc
VI
V0
I0
Pd
Topr
Tstg

Supply voltage
Input voltage

Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature

RECOMMENDED OPERATING CONDITIONS

Symbol

Vcc
Vss
VIH
VIL

Note 1 : All voltage values are with respect to Vss

Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage, all inputs

ELECTRICAL CHARACTERISTICS

Symbol

VOH
VOL
IOZ
I I

ICC1 (AV)

ICC2

ICC3 (AV)

ICC4(AV)

ICC6(AV)

Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc3 (AV) , Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.

High-level output voltage
Low-level output voltage
Off-state output current
Input current

Average supply current
from Vcc
operating

Supply current from Vcc , stand-by

Average supply current
from Vcc
refreshing

Average supply current
from Vcc
Fast-Page-Mode

Average supply current
from Vcc
CAS before RAS refresh
mode

CAPACITANCE

Symbol Parameter Test conditions

CI (A)
CI (W)
CI (RAS)
CI (CAS)
CI / O

Input capacitance, address inputs
Input capacitance, write control input
Input capacitance, RAS input
Input capacitance, CAS input
Input/Output capacitance, data ports

Parameter Conditions Ratings Unit

-1 ~ 7

With respect to Vss

Ta=25

C

(Ta=0 ~ 70 °C, unless otherwise noted) (Note 1)

Parameter

(Ta=0 ~ 70 °C, Vcc=5V ± 10%, Vss=0V, unless otherwise noted) (Note 2)

Parameter

MH4M36CJD-5
MH4M36CJD-6

(Note 3,4)

(Note 3)

(Note 3,4)

(Note 3)

(Ta=0 ~ 70 °C , Vcc=5V ± 10%, Vss=0V, unless otherwise noted)

MH4M36CJD-7

MH4M36CJD-5
MH4M36CJD-6

MH4M36CJD-7
MH4M36CJD-5
MH4M36CJD-6
MH4M36CJD-7
MH4M36CJD-5
MH4M36CJD-6
MH4M36CJD-7

Limits

Min Nom Max

5

4.5
0

0

2.4

-1.0

IOH=-5mA
IOL=4.2mA
Q floating 0V ≤ VOUT ≤ 5.5V
0V ≤ VIN ≤ 6.0V, Other inputs pins=0V

RAS, CAS cycling
tRC=tWC=min.
output open

RAS= CAS =VIH, output open
RAS= CAS ≥ Vcc -0.5

RAS cycling, CAS= VIH
tRC=min.
output open

RAS=VIL, CAS cycling
tPC=min.
output open

CAS before RAS refresh cycling
tRC=min.
output open

VI=Vss
f=1MHZ
Vi=25mVrms

5.5
0

6.0

0.8

Test conditions

Unit

V
V
V
V

-1 ~ 7

-1 ~ 7
50

12

0 ~ 70

-40 ~ 125

Limits

Min Max

Typ

2.4
0

-10

-120

Limits

Min Max

Typ

Vcc

0.4
10

120
1660
1360

1180

24

12
1660
1360

1180
1060

900

780

1580

1300

1140

90
130
130

35

20

V
V

V
mA
W

C

C

Unit

V

V
uA
uA

mA

mA

mA

mA

mA

Unit

pF
pF
pF
pF
pF

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MITSUBISHI LSIs

MH4M36CJD-5,-6,-7

FAST PAGE MODE ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM

SWITCHING CHARACTERISTICS

Symbol

Access time from CAS

tCAC

Access time from RAS

tRAC

Columu address access time

tAA
tCPA

Access time from CAS precharge

tCLZ

Output low impedance time from CAS low
Output disable time after CAS high

Note 5: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing a RAS clock such as RAS-Only refresh).
Note the RAS may be cycled during the initial pause . And any 8 RAS or RAS/CAS cycles are required after prolonged periods
(greater than 32 ms) of RAS inactivity before proper device operation is achieved.
6: Measured with a load circuit equivalent to 2TTL loads and 100pF.
7: Assumes that tRCD ≥ tRCD(max) and tASC ≥ tASC(max).
8: Assumes that tRCD ≤ tRCD(max) and tRAD ≤ tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,
tRAC will increase by amount that tRCD exceeds the value shown.
9: Assumes that tRAD ≥ tRAD(max) and tASC ≤ tASC(max).
10: Assumes that tCP ≤ tCP(max) and tASC ≥ tASC(max).
11: tOFF(max) and tOEZ (max) defines the time at which the output achieves the high impedance state ( | IOUT | ≤ 10 uA) and is not reference to
VOH(min) or VOL(max).

Parameter

(Ta=0 ~ 70 °C, Vcc=5V ± 10%, Vss=0V, unless otherwise noted , see notes 5,12,13)

Limits

(Note 6,7)
(Note 6,8)
(Note 6,9)

(Note 6,10)

(Note 6)

(Note 11)tOFF

MH4M36CJD-5 MH4M36CJD-6 MH4M36CJD-7

Min Max

5
0

Min Max Min Max
13
50
25
30

13

15
60
30

35
5
0

15

5
0

Unit

20
70
35
40

15

ns
ns
ns
ns
ns
ns

TIMING REQUIREMENTS (For Read, Write,Refresh, and Fast-Page Mode Cycles)

(Ta=0 ~ 70 °C, Vcc=5V ± 10%, Vss=0V, unless otherwise noted See notes 12,13)

Limits

Symbol

Refresh cycle time

tREF

RAS high pulse width

tRP

Delay time, RAS low to CAS low

tRCD
tCRP

Delay time, CAS high to RAS low

tRPC

Delay time, RAS high to CAS low

tCPN

CAS high pulse width

Column address delay time from RAS low

tRAD
tASR

Row address setup time before RAS low

Column address setup time before CAS low

tASC

Row address hold time after RAS low

tRAH
tCAH

Column address hold time after CAS low
Delay time, data to CAS low

tDZC

Delay time, CAS high to data

tCDD
tT

Transition time

Note 12: The timing requirements are assumed tT =5ns.
13: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
14: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access
time is controlled exclusively by tCAC or tAA. tRCD(min) is specified as tRCD(min) =tRAH(min) +2tH+tASC(min).
15: tRAD(max) is specified as a reference point only. If tRAD ≥ tRAD(max) and tASC ≤ tASC(max), access time is controlled exclusively by tAA.
16: tASC(max) is specified as a reference point only. If tRCD ≥ tRCD(max) and tASC ≥ tASC(max), access time is controlled exclusively by tCAC.
17: Either tDZC or tDZO must be satisfied.
18: Either tCDD or tODD must be satisfied.
19: tT is measured between VIH(min) and VIL(max).

Parameter

(Note14)

(Note15)

(Note16)

(Note17)
(Note18)
(Note19)

MH4M36CJD-5 MH4M36CJD-6

Min Max

30
18
10

0
10
13

0

0

8
13

13 15

1

Min Max Min Max

32

40
20

37

10

0
10
15

25

0

10

0
10

15

00 0
15

50

1

32

45

30

10

50

MH4M36CJD-7

32

50

50

20
10

0

10

35

15

0

10

0

10
15

50

1

Unit

ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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FAST PAGE MODE ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM

Read and Refresh Cycles

Symbol

Read cycle time

tRC

RAS iow pulse width

tRAS

CAS iow pulse width

tCAS
tCSH

CAS hold time after RAS iow

tRSH

RAS hold time after CAS iow

tRCS

Read Setup time after CAS high
Read hold time after CAS iow (Note 20)

tRCH
tRRH (Note 20)

Read hold time after RAS iow

tRAL

Column address to RAS hold time

Note 20: Either tRCH or tRRH must be satisfied for a read cycle.

Parameter

MITSUBISHI LSIs

MH4M36CJD-5,-6,-7

Limits

MH4M36CJD-5 MH4M36CJD-6 MH4M36CJD-7

Min Max

90

10000

50

10000

13
50

13

0
0

10
25

Min Max Min Max

110

60
15
60
15

0
0

10
30

10000
10000

130

20
70
20

10
35

10000

70

10000

0
0

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns

Write Cycle

Symbol

tWC
tRAS
tCAS
tCSH
tRSH
tWCS

tCWL
tRWL
tWP
tDS
tDH

Parameter

Write cycle time
RAS iow pulse width
CAS iow pulse width
CAS hold time after RAS iow
RAS hold time after CAS iow
Write setup time before CAS low
Write hold time after CAS iowtWCH
CAS hold time after W iow
RAS hold time after W iow
Write pulse width
Data setup time before CAS iow or W iow
Data hold time after CAS iow or W iow

Limits

MH4M36CJD-5 MH4M36CJD-6 MH4M36CJD-7

Min Max

90

10000

50

10000

13
50
13

0

8
13
13

8

0

Min Max Min Max

110
60
15
60
15

0

10
15
15
10

0

10

10000
10000

130
70
20
70
20

20
20
15
0
15

10000
10000

0

15

Unit

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns 8

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