Mitsubishi MELSEC-Q, MELSEC-L, MELSEC-QnA Programming Manual

 SAFETY PRECAUTIONS 

(Read these precautions before using this product.)

Before using MELSEC-Q, -L, or -QnA series programmable controllers, please read the manuals included with each product and the relevant manuals introduced in those manuals carefully, and pay full attention to safety to handle the product correctly.

Make sure that the end users read the manuals included with each product, and keep the manuals in a safe place for future reference.

A - 1 A - 1

 CONDITIONS OF USE FOR THE PRODUCT 

(1) Mitsubishi programmable controller ("the PRODUCT") shall be used in conditions;

i) where any problem, fault or failure occurring in the PRODUCT, if any, shall not lead to any major or serious accident; and ii) where the backup and fail-safe function are systematically or automatically provided outside of the PRODUCT for the case of any problem, fault or failure occurring in the PRODUCT.

(2) The PRODUCT has been designed and manufactured for the purpose of being used in general

industries. MITSUBISHI SHALL HAVE NO RESPONSIBILITY OR LIABILITY (INCLUDING, BUT NOT LIMITED TO ANY AND ALL RESPONSIBILITY OR LIABILITY BASED ON CONTRACT, WARRANTY, TORT, PRODUCT LIABILITY) FOR ANY INJURY OR DEATH TO PERSONS OR LOSS OR DAMAGE TO PROPERTY CAUSED BY the PRODUCT THAT ARE OPERATED OR USED IN APPLICATION NOT INTENDED OR EXCLUDED BY INSTRUCTIONS, PRECAUTIONS, OR WARNING CONTAINED IN MITSUBISHI'S USER, INSTRUCTION AND/OR SAFETY MANUALS, TECHNICAL BULLETINS AND GUIDELINES FOR the PRODUCT. ("Prohibited Application") Prohibited Applications include, but not limited to, the use of the PRODUCT in;  Nuclear Power Plants and any other power plants operated by Power companies, and/or any other

cases in which the public could be affected if any problem or fault occurs in the PRODUCT.

 Railway companies or Public service purposes, and/or any other cases in which establishment of a

special quality assurance system is required by the Purchaser or End User.

 Aircraft or Aerospace, Medical applications, Train equipment, transport equipment such as Elevator

and Escalator, Incineration and Fuel devices, Vehicles, Manned transportation, Equipment for Recreation and Amusement, and Safety devices, handling of Nuclear or Hazardous Materials or Chemicals, Mining and Drilling, and/or other applications where there is a significant risk of injury to the public or property.

Notwithstanding the above, restrictions Mitsubishi may in its sole discretion, authorize use of the PRODUCT in one or more of the Prohibited Applications, provided that the usage of the PRODUCT is limited only for the specific applications agreed to by Mitsubishi and provided further that no special quality assurance or fail-safe, redundant or other safety features which exceed the general specifications of the PRODUCTs are required. For details, please contact the Mitsubishi representative in your region.

A - 2 A - 2

REVISIONS

* The manual number is given on the bottom left of the back cover.

Print Date

* Manual Number Revision

Dec., 1999 SH (NA) 080041-A First edition

May, 2001 SH (NA) 080041-B

Partial correction Chapter 1, Section 3.1, Appendix 2

Apr., 2002 SH (NA) 080041-C

Partial correction Chapter 1, 2, Section 3.1, 3.3, 5.1, 5.1.1, 5.1.2, Appendix 2

Mar., 2003 SH (NA) 080041-D

Descriptions on use of MELSAP-3 with the Basic model QCPU whose serial number (first five digits) is "04122" or later have been added. Overall reexamination

Jun., 2004 SH (NA) 080041-E Descriptions on the Redundant CPU have been added.

May, 2005 SH (NA) 080041-F

Partial correction ABOUT MANUALS, Section 4.4.2, 4.4.9, 6.6, Appendix 1.1 Addition Section 3.3.2, 4.8, 4.8.1, 4.8.2 Section number change Section 3.3 Section 3.3.1

Mar., 2006 SH (NA) 080041-G

Partial correction Section 3.1.1, 3.1.2, 3.1.3, Appendix 1.1, 1.2

Apr., 2007 SH (NA) 080041-G New models of the Universal model QCPU have been added.

Model addition Q02UCPU, Q03UDCPU, Q04UDHCPU, Q06UDHCPU

Partial correction ABOUT MANUALS, GENERIC TERMS, Chapter 1, 2, Section 3.1.2,

3.2.2, 3.3.1, 4.2, 4.4.1 to 4.4.11, 4.5 to 4.7, 5.2, 5.2.1, 5.2.2, 5.3.1, 6.6, Appendix 1.1, 1.2, 2, 3

Dec., 2007 SH (NA) 080041-H

Partial correction Section 6.3.2

Feb., 2008 SH (NA) 080041-I New models of the Universal model QCPU have been added.

Model addition Q13UDHCPU, Q26UDHCPU Partial correction GENERIC TERMS, Chapter 2, Section 3.1.2, 3.2.2, 3.3.1, 4.2, 4.2.1,

4.2,8, 4.3.3, 4.4.5, 5.2.2, Appendix 2

May, 2008 SH (NA) 080041-J

New models of the Universal model QCPU and Process CPU have been added. Model addition Q03UDECPU, Q04UDEHCPU, Q06UDEHCPU, Q13UDEHCPU, Q26UDEHCPU Q02PHCPU, Q06PHCPU Partial correction GENERIC TERMS, Chapter 2, Section 3.1.2, 3.3.1, 4.2, 4.2.8, 4.3.3,

4.7.1, 5.2.2, Appendix 2

A - 3 A - 3

Print Date

* Manual Number Revision

Dec., 2008 SH (NA) 080041-K

Jul., 2009 SH (NA) 080041-L

Jan., 2010 SH (NA) 080041-M

Apr., 2010 SH (NA) 080041-N

* The manual number is given on the bottom left of the back cover.

New models of the Universal model QCPU have been added. Model addition Q00UJCPU, Q00UCPU, Q01UCPU, Q10UDHCPU, Q10UDEHCPU, Q20UDHCPU, Q20UDEHCPU Partial correction ABOUT MANUALS, GENERIC TERMS, Section 1.1, 1.2, Chapter 2, Section 3.1.2, 4.3.1, 4.3.3, 5.2.2, Appendix 1, 2

The serial number (first five digits) of the Universal model QCPU has been upgraded to "11043". Partial correction Section 4.1, 4.7.1, 6.1.1

Descriptions on MELSEC-L series modules have been added. Partial correction ABOUT MANUALS, GENERIC TERMS, Chapter 1, Section 1.2, Chapter 2, Section 3.1.2, 3.1.3, 3.2.1, 3.2.2, 3.2.3, 3.2.5, 3.3.1, 4.2,

4.2.2, 4.2.7, 4.2.8, 4.2.9, 4.2.10, 4.2.11, 4.3.1, 4.3.3, 4.3.5, 4.4, 4.4.1,

4.4.2, 4.4.3, 4.4.4, 4.4.5, 4.4.6, 4.4.7, 4.4.8, 4.4.9, 4.4.10, 4.4.11, 4.5,

4.5.3, 4.6, 4.7, 4.7.1, 4.7.3, 4.7.4, 4.7.5, 4.7.6, 4.8.1, 4.8.2, 5.2, 5.2.1,

5.2.2, 5.2.3, 5.3.1, 6.1, 6.1.1, 6.3.1, 6.3.2, 6.4.3, 6.6, Appendix 1.1,

1.2, 3 Addition

CONDITIONS OF USE FOR THE PRODUCT, Section 3.2.4

New models of the Universal model QCPU have been added. Model addition Q50UDEHCPU, Q100UDEHCPU Partial correction GENERIC TERMS, Chapter 2, Section 3.1.2, 3.3.1, 4.2, 4.2.8, 4.3.3,

5.2.2, Appendix 2

Aug., 2010 SH (NA) 080041-O

The serial number (first five digits) of the Universal model QCPU has been upgraded to "12052". Partial correction Section 3.1.2, 3.2.3, 3.3.2, 4.2, 4.2.8, 4.2.9, 4.4, 4.4.6, 4.4.8, 4.4.9,

4.5, 4.7, 4.7.5, 4.8, 4.8.1, 6.6, Appendix 1.1, 1.2 Addition Section 6.6.1, 6.6.2, 6.6.3

Dec., 2010 SH (NA) 080041-P

Partial correction Section 4.3.4

Jul., 2011 SH (NA) 080041-Q New models of the LCPU have been added.

Model addition L02CPU-P, L26CPU-PBT Partial correction GENERIC TERMS, Section 1.2, Chapter 2, Section 3.1.2,

3.2.4, 3.3.1, 4.2, 4.2.8, 4.2.9, 4.3.1, 4.3.3, 5.2.2, Appendix 2

A - 4 A - 4

* The manual number is given on the bottom left of the back cover.

Print Date

Nov., 2011

* Manual Number Revision

SH (NA) 080041-R

The serial number (first five digits) of the Universal model QCPU has been upgraded to "13102". Partial correction

SAFETY PRECAUTIONS, ABOUT MANUALS, Chapter 4, Section 4.4,

4.4.1, 4.4.8, 4.4.10, 6.1, 6.6.3, Appendix 1, 2, 3

Feb., 2013

SH (NA) 080041-S

New models of the Universal model QCPU and LCPU have been added. Model addition

Q03UDVCPU, Q04UDVCPU, Q06UDVCPU, Q13UDVCPU, Q26UDVCPU, L02SCPU, L06CPU, L26CPU Partial correction

GENERIC TERMS, Section 1.2, Chapter 2, Section 3.1.2, 3.2.4, 3.3.1,

4.2, 4.2.8, 4.2.9, 4.3.1, 4.3.3, 5.2.2, 6.6, Appendix 2

Jun., 2013 SH (NA) 080041-T New models of the LCPU have been added.

Model addition L02SCPU-P, L06CPU-P, L26CPU-P Partial correction GENERIC TERMS, Section 1.2, Chapter 2, Section 3.1.2, 3.2.4, 3.3.1,

4.2, 4.2.8, 4.2.9, 4.3.1, 4.3.3, 5.2.2, 6.6, Appendix 2

Jan., 2014 SH(NA) 080041-U The serial number of the LCPU has been upgraded to "15102".

Partial correction Section 3.1.2, 3.2.4, 3.3.2, 4.2, 4.2.8, 4.2.9, 4.7, 4.7.5, 4.8.1, 4.8.2,

6.6, Appendix 1, 2, 3

Japanese Manual Version SH-080023-AB

This manual confers no industrial property rights or any rights of any other kind, nor does it confer any patent licenses. Mitsubishi Electric Corporation cannot be held responsible for any problems involving industrial property rights which may occur as a result of using the contents noted in this manual.

 1999 MITSUBISHI ELECTRIC CORPORATION

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INTRODUCTION

Thank you for purchasing the Mitsubishi MELSEC-Q/L/QnA series programmable controllers. Before using the product, please read this manual carefully and develop familiarity with the functions and performance of the MELSEC-Q/L/QnA series programmable controllers to handle the product correctly. Please make sure that the end users read this manual.

ABOUT MANUALS

The manuals related to this product are listed below. Order each manual as needed, referring to the following lists.

Relevant manuals

Manual name

GX Developer Version 8 Operating Manual (SFC) Describes how to create SFC programs using the software package for creating SFC programs. (Sold separately) GX Works2 Version1 Operating Manual (Common) Describes system configurations, parameter settings, online operations (common to Simple project and Structured project) of GX Works2. (Sold separately) TYPE SW2IVD/NX-GPPQ GPP Software package Operating Manual (SFC) Describes how to create SFC programs using the software package for creating SFC programs. (Supplied with the product)

QnUCPU User's Manual (Function Explanation, Programming Fundamentals) Describes the functions, programming procedures, devices, etc. necessary to create programs using the QCPU. (Sold separately) Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Programming Fundamentals) Describes the functions, programming procedures, devices, etc. necessary to create programs using the QCPU. (Sold separately) MELSEC-L CPU Module User's Manual (Function Explanation, Program Fundamentals) Describes the functions required for programming, programming methods, and devices. (Sold separately) MELSEC-Q/L Programming Manual (Common instruction) Describes how to use sequence instructions, basic instructions, and application instructions. (Sold separately) QnACPU Programming Manual (Common instruction) Describes how to use sequence instructions, basic instructions, and application instructions. (Sold separately) QnACPU Programming Manual (Fundamentals) Describes the programming procedures, device names, parameters, program types, etc. necessary to create programs. (Sold separately)

only for QnACPU

Manual number

(model code)

SH-080374E

(13JU42)

SH-080779ENG

(13JU63)

IB-66776

(13J923)

SH-080807ENG

(13JZ27)

SH-080808ENG

(13JZ28)

SH-080889ENG

(13JZ35)

SH-080809ENG

(13JW10)

SH-080810ENG

(13JW11)

IB-66614 (13JF46)

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GENERIC TERMS

Unless otherwise specified, this manual uses the following generic terms and abbreviations.

Generic term Description

QCPU

QnCPU A generic term for the Q02CPU

QnHCPU A generic term for the Q02HCPU, Q06HCPU, Q12HCPU, and Q25HCPU

QnPHCPU A generic term for the Q02PHCPU, Q06PHCPU, Q12PHCPU, and Q25PHCPU

QnPRHCPU A generic term for the Q12PRHCPU and Q25PRHCPU

QnUDVCPU

QnUD(E)(H)CPU

LCPU

QnACPU

Basic model QCPU

Basic

High Performance model QCPU

High Performance

Process CPU A generic term for the Q02PHCPU, Q06PHCPU, Q12PHCPU, and Q25PHCPU

Redundant CPU A generic term for the Q12PRHCPU and Q25PRHCPU

Universal model QCPU A generic term for the Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU, Q03UDCPU,

Universal

High-speed Universal model QCPU

A generic term for the Basic model QCPU, High Performance model QCPU, Process CPU, Redundant CPU, and Universal model QCPU

A generic term for the Q03UDVCPU, Q04UDVCPU, Q06UDVCPU, Q13UDVCPU, and Q26UDVCPU

A generic term for the Q03UDCPU, Q03UDECPU, Q04UDHCPU, Q04UDEHCPU, Q06UDHCPU, Q06UDEHCPU, Q10UDHCPU, Q10UDEHCPU, Q13UDHCPU, Q13UDEHCPU, Q20UDHCPU, Q20UDEHCPU, Q26UDHCPU, Q26UDEHCPU, Q50UDEHCPU, and Q100UDEHCPU

A generic term for the L02SCPU, L02SCPU-P, L02CPU, L02CPU-P, L06CPU, L06CPU-P, L26CPU, L26CPU-P, L26CPU-BT, and L26CPU-PBT

A generic term for the Q2ASCPU, Q2ASCPU-S1, Q2ASHCPU, Q2ASHCPU-S1, Q2ACPU, Q2ACPU-S1, Q3ACPU, Q4ACPU, and Q4ARCPU

A generic term for the Q00JCPU, Q00CPU, and Q01CPU

A generic term for the Q02CPU, Q02HCPU, Q06HCPU, Q12HCPU, and Q25HCPU

Q03UDVCPU, Q03UDECPU, Q04UDHCPU, Q04UDVCPU, Q04UDEHCPU, Q06UDHCPU, Q06UDVCPU, Q06UDEHCPU, Q10UDHCPU, Q10UDEHCPU, Q13UDHCPU, Q13UDVCPU, Q13UDEHCPU, Q20UDHCPU, Q20UDEHCPU, Q26UDHCPU, Q26UDVCPU, Q26UDEHCPU, Q50UDEHCPU, and Q100UDEHCPU

A generic term for the Q03UDVCPU, Q04UDVCPU, Q06UDVCPU, Q13UDVCPU, and Q26UDVCPU

A - 10 A - 10

MEMO

A - 11 A - 11

1 GENERAL DESCRIPTION

1. GENERAL DESCRIPTION

1

SFC, an abbreviation for "Sequential Function Chart", is a control specification description format in which a sequence of control operations is split into a series of steps to enable a clear expression of the program execution sequence and execution conditions.

This manual describes the specifications, functions, instructions, programming procedures, etc. used to perform programming with an SFC program using MELSAP3.

MELSAP3 can be used with the following CPU modules.

• Basic model QCPU whose serial number (first five digits) is 04122 or later

• High Performance model QCPU

• Process CPU

• Redundant CPU

• Universal model QCPU

• LCPU

• QnACPU

MELSAP3 conforms to the IEC Standard for SFC. In this manual, MELSAP3 is referred to as SFC (program, diagram).

POINT

(1) The following functions cannot be executed if a parameter that sets the "high

speed interrupt cyclic interval" is loaded into a High Performance model QCPU of which the first 5 digits of the serial number are "04012" or later.

• Step transition watch dog timer (see Section 4.6)

• Periodic execution block setting (see Section 4.7.4)

(2) The Qn(H)CPU-A (A mode) cannot use MELSAP3 explained in this manual.

The SFC function that can be used by the Qn(H)CPU-A (A mode) is "MELSAP-II". For MELSAP-II, refer to the "MELSAP-II (SFC) Programming Manual".

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1 GENERAL DESCRIPTION

1.1 Description of SFC Program

The SFC program consists of steps that represent units of operations in a series of machine operations. In each step, the actual detailed control is programmed by using a ladder circuit.

1

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1 GENERAL DESCRIPTION

The SFC program performs a series of operations, beginning from the initial step, proceeding to execute each subsequent step as the transition conditions are satisfied, and ending with the END step.

(1) When the SFC program is started, the “initial” step is executed first.

(2) Execution of the initial step continues until transition condition 1 is satisfied. When this

transition condition is satisfied, execution of the initial step is stopped, and processing proceeds to the step which follows the initial step.

Processing of the SFC program continues from step to step in this manner until the END step has been executed.

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1 GENERAL DESCRIPTION

1.2 SFC (MELSAP3) Features

(1) Easy to design and maintain systems

It is possible to correspond the controls of the entire facility, mechanical devices of each station, and all machines to the blocks and steps of the SFC program on a one-to-one basis. Because of this capability, systems can be designed and maintained with ease even by those with relatively little knowledge of sequence programs. Moreover, programs designed by other programmers using this format are much easier to decode than sequence programs.

Step transition control unit for overall process

Step transition control unit for overall process (block 0)

Transfer machine START (initial step)

Station 1 START (block 1 START)

Station 2 START (block 2 START)

Repeated

Station 3 START (block 3 START)

END (END step)

Station 1 control unit

Station 2 control unit

Station 3 control unit

Transfer machine

Overall system (SFC program)

Station 1 control unit (block 1)

START (initial step)

Pallet clamp (step 1)

Drilling (step 2)

Pallet unclamp (step 3)

(END step)

Station 2 control unit (block 2)

START (initial step)

Pallet clamp (step 1)

Tapping (step 2)

Pallet unclamp (step 3)

(END step)

Station 3 control unit (block 3)

START (initial step)

Pallet clamp (step 1)

Workpiece unloading (step 2)

Pallet unclamp (step 3)

(END step)

(2) Requires no complex interlock circuitry

Interlock circuits are used only in the operation output program for each step. Because no interlocks are required between steps in the SFC program, it is not necessary to consider interlocks with regard to the entire system.

SOL1

SOL2

Clamp

LS-U

MT1-F

MT1-B

Headstock

rotation

MT2-R

(Headstock RETRACT endpoint) LS0

(Machining START) LS1

(Machining END) LS2

(Carriage A DVANCE endpoint) LS-F

Clamp UP endpoint

Clamp DOWN endpoint

LS-D

Carriage

(Carriage RETRACT endpoint)

LS10

LS-R

MTO-F

MTO-B

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1 GENERAL DESCRIPTION

Step 5

Carriage ADVANCE

X3

Carriage ADVANCE endpoint

Y20

Tran

Clamp DOWN

Step 6

Clamp DOWN endpoint

X4

Headstock ADVANCE

Step 7

SFC program

Y21

Tran

Y22

As shown in the SFC program at left, the steps require no “operation completed” interlock contact with the previous step. With a conventional sequence program, carriage FORWARD (Y20) and clamp DOWN (Y21) interlock contacts would be required at the ladder used for the headstock ADVANCE.

Y20

Y21 X3

Interlock contacts

Headstock ADVANCE

X4

Y22

(3) Block and step configurations can easily be changed for new control applications

• A total of 320 blocks

• Up to 512 steps

1 can be created in an SFC program.

1 can be created per block.

• Up to 2k sequence steps can be created for all blocks for operation outputs.

• Each transition condition can be created in only one ladder block. Reduced tact times, as well as easier debugging and trial run operations are possible by dividing blocks and steps as follows:

• Divide blocks properly according to the operation units of machines.

• Divide steps in each block properly.

320 blocks 1

Block 0 Block 1 Block 319

Initial

step

Step 1

1

512 steps

Step 2

Operation output program

X0

T0

X1

Transition condition in only one ladder block

Operation output: 2k sequence steps for all blocks

Y20 K20

T0

Y21

Initial

step

Step 1

Step 2

Initial

step

Step 1

Step 2

REMARKS

1: For the following CPU modules, 128 blocks and 128 steps can be created.

• Basic model QCPU

• Universal model QCPU (Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU)

• LCPU (L02SCPU, L02SCPU-P, L02CPU, L02CPU-P)

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1 GENERAL DESCRIPTION

(4) Creation of multiple initial steps is possible

Multiple processes can easily be executed and combined. Initial steps are linked using a “selection coupling” format. When multiple initial steps (S0 to S3) are active, the step where the transition condition (t4 to t7) immediately prior to the selected coupling is satisfied becomes inactive, and a transition to the next step occurs. Moreover, when the transition condition immediately prior to an active step is satisfied, the next step is executed in accordance with the parameter settings.

: Basic model QCPU, Universal model QCPU, and LCPU cannot be selected in the

parameter setting. It operates in the default "Transfer" mode.

• Wait ............. Transition to the next step occurs after waiting for the next step to become

inactive.

• Transfer ....... Transition to the next step occurs even if the next step is active. (Default)

• Pause .......... An error occurs if the next step is active.

S0

t0

S1

t1

S2

t2

S3

t3

S4

t4

S8

S5

t5

S6

t6

S7

t7

REMARKS

Linked steps can also be changed at each initial step.

S0

t0

S3

t3

S6

t6

S7

S1

t1

S4

t4

S2

t2

S5

t5

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1 GENERAL DESCRIPTION

(5) Program design is easy due to a wealth of step attributes

A variety of step attributes can be assigned to each step. Used singly for a given control operation, or in combination, these attributes greatly simplify program design procedures.

• Types of HOLD steps, and their operations

1) Coil HOLD step (

SC

X0

)

Y10

• After a transition, operation output processing continues (is maintained),

X0

Y10

(Transition condition satisfied)

Step which is active due to transition condition being satisfied

and the coil output status at the time when the transition condition is satisfied is maintained regardless of the ON/OFF status of the interlock condition (X0).

• Transition will not occur even if the transition condition is satisfied again.

• Convenient for maintaining an output until the block in question is completed (hydraulic motor output, pass

2) Operation HOLD step (no transition check) (

X0

Y10

confirmation signal, etc.).

SE

)

• Even after a transition, operation output processing continues (is

X0

Y10

maintained), and when the interlock condition (X0) turns ON/OFF, the coil output (Y10) also turns ON/OFF.

• Transition will not occur if the transition

Step which is active due to transition condition being satisfied

condition is satisfied again.

• Convenient for repeating the same operation (cylinder advance/retract, etc.) while the relevant block is active.

3) Operation HOLD step (with transition check) (

X0

X1

MO

(Transition executed)

Y10

PLS M0

Tran

ST

)

• Even after a transition, operation output processing continues (is maintained), and when the interlock condition (X0) turns ON/OFF, the coil output (Y10) also turns ON/OFF.

• When the transition condition is again satisfied, the transition is executed, and the next step is activated.

• Operation output processing is executed at the reactivated next step. When the

Step which is active due the previous transition condition being satisfied

transition condition is satisfied, transition occurs, and the step is deactivated.

• Convenient for outputs where there is an interlock with the next operation, for example where machining is started on completion of a repeated operation (workpiece transport, etc.).

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1 GENERAL DESCRIPTION

• Reset step (

R

• Types of block START steps, and their operations

1) Block START step (with END check) (

2) Block START step (Without END check) (

R

)

n

When the reset step is

n

activated, a designated step will become inactive

m

X0

Tran

• When a HOLD status becomes unnecessary for machine control, or on selective branching to a manual ladder occurs after an error detection, etc., a reset request can be designated for the HOLD step, deactivating the step in question.

m)

m

• In the same manner as for a subroutine CALL-RET, a START source block transition will not occur until the end of the START destination block is reached.

• Convenient for starting the same block several times, or to use several blocks together, etc.

• A convenient way to return to the START source block and proceed to the next process block when a given process is completed in a processing line, for example.

m)

m

• Even if the START destination block is active, a START source block transition occurs when the transition condition associated with the block START step is satisfied. At this time, the processing of the START destination block will be continued unchanged until the end step is reached.

• By starting another block at a given step, the START destination block can be controlled independently and asynchronously with the START source block until processing of the current block is completed.

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1 GENERAL DESCRIPTION

(6) A given function can be controlled in a variety of ways according to the application in question

Block functions such as START, END, temporary stop, restart, and forced activation and ending of specified steps can be controlled by SFC diagram symbols, SFC control instructions, or by SFC information registers.

• Control by SFC diagram symbols

................. Convenient for control of automatic operations with easy sequential control.

• Control by SFC instructions

................. Enables requests from program files other than the SFC, and is convenient for

error processing, for example after emergency stops, and interrupt control.

• Control by SFC information devices

................. Enables control of SFC peripheral devices, and is convenient for partial

operations such as debugging or trial runs.

Functions which can be controlled by these 3 methods are shown below.

Function

Block START (with END wait) Block START (without END wait)

Block END RST BLm Block START/END bit OFF

Block STOP PAUSE BLm Block STOP/RESTART bit ON

Restart stopped block RSTART BLm Block STOP/RESTART bit OFF

Forced step activation

Forced step END

1) In cases where the same function can be executed by a number of methods, the first control method which has been designated by the request output to the block or step in question will be the effective control method.

2) Functions controlled by a given control method can be canceled by another control method. Example: For block START

The active block started by the SFC diagram ( the SFC control instruction (RST BLm) before the END step ( block START/END bit of the SFC information devices.

(7) A sophisticated edit function simplifies editing operations

A same-screen SFC diagram, operation output, and transition condition ladder display features a zoom function which can split the screen 4 ways (right/left/upper/lower) to simplify program cut-and-paste operations. Moreover, advanced program edit functions such as the SFC diagram or device search function, etc., make program creation and editing operations quick and easy.

Control Method

SFC Diagram

m

m SET BLm Block START/END bit ON

R

n

SFC Control

Instructions



SET Sn

SET BLm\Sn

SCHG Kn

RST Sn

RST BLm\Sn

SCHG Kn

m) can be forcibly ended by executing

SFC Information Registers

) or by turning OFF the

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1 GENERAL DESCRIPTION

(8) Displays with comments for easy understanding

Comments can be entered at each step and transition condition item. Up to 32 characters can be entered.

I0

1

S

2

0 3 4 5

1 6 7

SD3 Wait ateSD4 Wrt <Ins>Ld Step

0

2

(9) An automatic scrolling functions enables quick identification of mechanical system trouble

spots Active (execution) blocks and steps, as well as the execution of operation output/transition condition ladders can be monitored by a peripheral device (with automatic scrolling function). This monitor function enables even those with little knowledge of sequence programs to easily identify trouble spots.

Ready, waiting for start

Mix A SN2

Mix BSN1

2

Wait ste

12

[Mix A ]

Y10

Y20

1 - 10 1 - 10

1 GENERAL DESCRIPTION

(10) Convenient trace function (when using GPPQ with QnACPU)

Blocks can be synchronized and traced, enabling the user to check the operation timing of multiple blocks. Moreover, the trace results display screen can be switched to display the trace result details for each block.

[Trace Results Display]

Block

0

1 2

[Trace Results Display]

1

Block

PgUp:Prev PgDn:Next

-5

11515222015

-5 0

464

05

5

Esc:Close

117 220

400 819 402 819 403 204 404 204

2

6

-32

58

Active step Nos. are displayed (from smallest No.) for each block

Block No. Where trace occurred

Active step No. display

1 - 11 1 - 11

2 SYSTEM CONFIGURATION

2. SYSTEM CONFIGURATION

(1) Applicable CPU modules

CPU module type Model name Restriction

Basic model QCPU Q00JCPU, Q00CPU, Q01CPU

High Performance model QCPU Q02CPU, Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU Process CPU Q02PHCPU, Q06PHCPU, Q12PHCPU, Q25PHCPU Redundant CPU Q12PRHCPU, Q25PRHCPU

Universal model QCPU

LCPU

QnACPU

MELSAP-3 (SFC programs) runs on the following CPU modules.

Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU, Q03UDCPU, Q03UDVCPU, Q03UDECPU, Q04UDHCPU, Q04UDEHCPU, Q04UDVCPU, Q06UDHCPU, Q06UDVCPU, Q06UDEHCPU, Q10UDHCPU, Q10UDEHCPU, Q13UDHCPU, Q13UDVCPU, Q13UDEHCPU, Q20UDHCPU, Q20UDEHCPU, Q26UDHCPU, Q26UDVCPU, Q26UDEHCPU, Q50UDEHCPU, Q100UDEHCPU L02SCPU, L02SCPU-P, L02CPU, L02CPU-P, L06CPU, L06CPU-P, L26CPU, L26CPU-P, L26CPU-BT, L26CPU-PBT Q2ASCPU, Q2ASCPU-S1, Q2ASHCPU, Q2ASHCPU-S1, Q2ACPU, Q2ACPU-S1, Q3ACPU, Q4ACPU, Q4ARCPU

Modules whose serial number (first five digits) is 04122 or later

2

2 - 1 2 - 1

2

2 SYSTEM CONFIGURATION

Peripheral

device

Personal computer

(Windows

compatible)

(2) Peripheral devices for SFC programs

The following peripheral devices can be used to create, edit and monitor SFC programs.

Software package to

be installed in a

personal computer

SW3D5C/

F-GPPW-E

SW4D5C-GPPW-E

or later

GX Developer Version 7.10L

(SW7D5C-GPPW-E)

or later

GX Developer

Version 8

(SW8D5C-GPPW-E)

or later GX Developer Version 8.18U

(SW8D5C-GPPW-E)

or later GX Developer Version 8.48A

(SW8D5C-GPPW-E)

or later GX Developer

Version 8.62Q

(SW8D5C-GPPW-E)

or later GX Developer

Version 8.68W

(SW8D5C-GPPW-E)

®

or later GX Developer

Version 8.78G

(SW8D5C-GPPW-E)

or later GX Developer Version 8.89T

(SW8D5C-GPPW-E)

or later

GX Works2

Version 1.24A

(SW1DNC-GXW2-E)

or later

GX Works2

Version 1.25B

(SW1DNC-GXW2-E)

or later

GX Works2

Version 1.56J

(SW1DNC-GXW2-E)

or later

GX Works2

Version 1.98C

(SW1DNC-GXW2-E)

or later

GX Works2

Version 1.492N

(SW1DNC-GXW2-E)

or later

Basic

model

QCPU

CPU module

High Performance model QCPU

Process

CPU

*2

Redundant

CPU

Universal

model QCPU

*1

*3

*4

*5

*6

LCPU

*8

*7

*9

QnA

CPU

: Available,

: Not available, : Partly available

Remarks

2 - 2 2 - 2

2 SYSTEM CONFIGURATION

Peripheral

device

PC/AT

compatible

personal

computer

Q6PU

Software package to

be installed in a

personal computer

SW2IVD-GPPQ-E

Basic model QCPU

High Performance model QCPU

CPU module

Process

CPU

Redundant

CPU

Universal

model QCPU

LCPU

QnA CPU

• Display is provided in list representation where an SFC diagram has been replaced by instructions.

• SFC diagrams cannot be created or edited. Only creation and correction of ladders associated with operation outputs and transition conditions are allowed.

Remarks

: Available, : Not available, : Partly available *1: Available only with the Q02UCPU, Q03UDCPU, Q04UDHCPU, and Q06UDHCPU *2: Available only with the Q12PHCPU and Q25PHCPU *3: Available only with the Q02UCPU, Q03UDCPU, Q04UDHCPU, Q06UDHCPU, Q13UDHCPU, and

Q26UDHCPU

*4: Available only with the Q02UCPU, Q03UD(E)CPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q13UD(E)HCPU,

and Q26UD(E)HCPU

*5: Available only with the Q00U(J)CPU, Q01UCPU, Q02UCPU, Q03UD(E)CPU, Q04UD(E)HCPU,

Q06UD(E)HCPU, Q10UD(E)HCPU, Q13UD(E)HCPU, Q20UD(E)HCPU, and Q26UD(E)HCPU

*6: Available only with the Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU, Q03UDCPU, Q03UDECPU,

Q04UDHCPU, Q04UDEHCPU, Q06UDHCPU, Q06UDEHCPU, Q10UDHCPU, Q10UDEHCPU, Q13UDHCPU, Q13UDEHCPU, Q20UDHCPU, Q20UDEHCPU, Q26UDHCPU, Q26UDEHCPU,

Q50UDEHCPU, and Q100UDEHCPU *7: Available only with the L02CPU, L02CPU-P, L26CPU-BT, and L26CPU-PBT *8: Available only with the L02CPU and L26CPU-BT *9: Available only with the L02SCPU, L02CPU, L02CPU-P, L06CPU, L26CPU, L26CPU-BT, and L26CPU-PBT

2 - 3 2 - 3

2 SYSTEM CONFIGURATION

MEMO

2 - 4 2 - 4

3 SPECIFICATIONS

3. SPECIFICATIONS

This chapter explains the performance specifications of SFC programs.

3.1 Performance Specifications Related to SFC Programs

3.1.1 When the Basic model QCPU is used

SFC program

*1: SFC program for program management (Section 5.2.3) cannot be created. *2: The maximum number of sequence steps per block depends on an instruction used for operation output or a note editing

setting. The number of steps (2k steps) indicated in the table applies when "Unite (United Note)" is selected for note editing. Note that 2k sequence steps per block may not be secured when "Peripheral (Peripheral Note)" is selected. If note editing is not set, 2k sequence steps or more per block may be secured depending on an instruction used.

(1) Table 3.1 indicates the performance specifications related to SFC programs.

Table 3.1 Performance Specifications Related to SFC Program

Item Q00JCPU Q00CPU Q01CPU Capacity Max. 8k steps Max. 8k steps Max. 14k steps Number of files Number of blocks Max. 128 blocks Number of SFC steps Max. 1024 steps for all blocks, max. 128 steps for one block Number of branches Max. 32

Number of concurrently active steps

Number of operation output sequence steps Number of transition condition sequence steps

Max. 1024 steps for all blocks

Max. 128 steps for one block

Scannable SFC program: 1 file *1

(including HOLD steps)

Max. 2k steps for all blocks *2

No restriction on one step

One ladder block only

3

REMARKS

The step transition watchdog timer, STEP-RUN operation and step trace functions are not available.

3 - 1 3 - 1

3 SPECIFICATIONS

(2) Precautions for creating SFC program

(a) Only one SFC program can be created.

(b) The Basic model QCPU allows creation of a total of two program files: one SFC program

The created SFC program is a "scan execution type program".

and one sequence program. (Two sequence programs or two SFC programs cannot be created.)

Scan execution type program

3

Sequence

program

(c) The created sequence program and SFC program have the following file names. (The file

(d) The SFC program and sequence program are processed in order of "sequence program"

(MAIN.QPG)

SFC program

(MAIN-SFC.QPG)

names cannot be changed.)

• Sequence program: MAIN.QPG

• SFC program: MAIN-SFC.QPG

and "SFC program". (The processing order of the SFC program and sequence program cannot be changed.)

3 - 2 3 - 2

3 SPECIFICATIONS

3.1.2 When the High Performance model QCPU, Process CPU, Redundant CPU, Universal model CPU, or LCPU is used

SFC program

Step transition watchdog timer function Provided (10 timers)

(1) Table 3.2 indicates the performance specifications related to SFC programs.

Table 3.2 Performance Specifications Related to SFC Programs

Q02CPU,

Item

Capacity Max. 28k steps Max. 60k steps Max. 124k steps Max. 252k steps

Number of files

Number of blocks Max. 320 blocks (0 to 319) Number of SFC steps Max. 8192 steps for all blocks, max. 512 steps for one block Number of branches Max. 32 Number of concurrently active steps (including HOLD steps) Number of operation output sequence steps Number of transition condition sequence steps

Q02HCPU

Q02PHCPU Q06PHCPU Q12PHCPU Q25PHCPU

(1 normal SFC program and 1 program execution management SFC program)

Q06HCPU Q12HCPU Q25HCPU

Q12PRHCPU Q25PRHCPU

Scannable SFC program: 2 files

Max. 1280 steps for all blocks

Max. 256 steps for one block

Max. 2k steps for one block 2

No restriction on one step

One ladder block only

Item Q00UJCPU Q00UCPU Q01UCPU Q02UCPU

Table 3.2 Performance Specifications Related to SFC Programs

1

Capacity Max. 10k steps Max. 15k steps Max. 20k steps Number of files Scannable SFC program: 1 (normal SFC program only) Number of blocks Max. 128 blocks (0 to 127) Number of SFC steps Max. 1024 steps for all blocks, max. 128 steps for one block

Number of branches Max. 32 SFC program

Step transition watchdog timer function None

Number of concurrently

active steps

(including HOLD steps)

Number of operation output

sequence steps

Number of transition

condition sequence steps

Max. 1024 steps for all blocks

Max. 128 steps for one block

Max. 2k steps for one block 2

No restriction on one step

One ladder block only

3 - 3 3 - 3

3 SPECIFICATIONS

Item

Capacity

Number of files Scannable SFC program: 1 (normal SFC program only)

Number of blocks Max. 320 blocks (0 to 319)

Number of SFC steps

SFC program

Step transition watchdog timer function None

Number of branches Max. 32

Number of concurrently

active steps

(including HOLD steps)

Number of operation output

sequence steps

Number of transition

condition sequence steps

Table 3.2 Performance Specifications Related to SFC Programs

Q03UD(E)CPU,

Q03UDVCPU

Max. 30k

steps

Q04UD(E)H

CPU,

Q04UDVCPU

Max. 40k

steps

Max. 16384 steps for all blocks

Max. 512 steps for one block

Max. 1280 steps for all blocks

Max. 256 steps for one block

Max. 2k steps for one block 2

Q06UD(E)H

CPU,

Q06UDVCPU

Max. 60k

steps

No restriction on one step

One ladder block only

Item Q20UD(E)HCPU

Capacity Max. 200k steps Max. 260k steps Max. 500k steps Max. 1000k steps

Number of files Scannable SFC program: 1 (normal SFC program only)

Number of blocks Max. 320 blocks (0 to 319)

Number of SFC steps

SFC program

Step transition watchdog timer function None

Number of branches Max. 32

Number of concurrently

active steps

(including HOLD steps)

Number of operation output

sequence steps

Number of transition

condition sequence steps

Table 3.2 Performance Specifications Related to SFC Programs

Q26UD(E)HCPU,

Q26UDVCPU

Max. 16384 steps for all blocks

Max. 512 steps for one block

Max. 1280 steps for all blocks

Max. 256 steps for one block

Max. 2k steps for one block 2

No restriction on one step

One ladder block only

1 Refer to Section 5.2.3 for the program execution management SFC program. 2 The maximum number of sequence steps per block depends on the instruction used for

operation output or a note editing setting. The number of steps (2k steps) indicated in the table applies when "Unite (United Note)" is selected for note editing. Note that 2k sequence steps per block may not be secured when "Peripheral (Peripheral Note)" is selected. If note editing is not set, 2k sequence steps or more per block may be secured depending on the instruction used.

3 For the Universal model QCPU whose serial number (first five digits) is "12051" or earlier,

the maximum number of SFC steps is 8192 for all blocks.

4 For the Universal model QCPU whose serial number (first five digits) is "12052" or later,

the maximum number of SFC steps can be changed by changing the step relay (S) points in the Device tab of the PLC parameter dialog box. For settings, refer to the QnUCPU User’s Manual (Function Explanation, Program Fundamentals).

Q10UD(E)H

CPU

Max. 100k

steps

3 4

Q50UDEHCPU Q100UDEHCPU

3 4

Q13UD(E)H

CPU,

Q13UDVCPU

Max. 130k

steps

3 - 4 3 - 4

3 SPECIFICATIONS

Item

Capacity Max. 20k steps Max. 60k steps Max. 260k steps Number of files Scannable SFC program: 1 (normal SFC program only) Number of blocks Max. 128 blocks (0 to 127) Max. 320 blocks (0 to 319)

Number of SFC steps

SFC Program

Step transition watchdog timer function None

Number of branches Max. 32 Number of concurrently active steps (including HOLD steps) Number of operation output sequence steps Number of transition condition sequence steps

Table 3.2 Performance Specifications Related to SFC programs

L02SCPU, L02SCPU-P,

L02CPU, L02CPU-P

Max. 1024 steps for all blocks

Max. 128 steps for one block

Max. 1024 steps for all blocks

Max. 128 steps for one block

Max. 2K steps for one block 2

No restriction on one step

One ladder block only

1: For the modules whose serial number (first five digits) is "15101" or earlier, the

maximum number of steps is 8,192.

2: The maximum number of sequence steps per block depends on an instruction used for

operation output or a note editing setting. The number of steps (2k steps) indicated in the table applies when "Unite (United Note)" is selected for note editing. Note that 2k sequence steps per block may not be secured when "Peripheral (Peripheral Note)" is selected for not editing. If note editing is not set, 2k sequence steps or more per block may be secured depending on the instruction used.

L26CPU,

L06CPU,

L06CPU-P

Max. 16384 steps for all blocks

Max. 512 steps for one block

Max. 1280 steps for all blocks

Max. 256 steps for one block

L26CPU-P,

L26CPU-BT,

L26CPU-PBT

1

REMARKS

The STEP-RUN operation and step trace functions are not available.

3 - 5 3 - 5

3 SPECIFICATIONS

(2) Precautions for creating SFC program

(a) The SFC programs that can be created are "scan execution type program" and "stand-

by type program".

(b) Two SFC programs (one normal SFC program and one program execution

management SFC program) can be set as a scan execution type program.

(c) More than one SFC program can be set as a stand-by type program.

(d) The stand-by type SFC program is executed in the following procedure.

• The currently executed scan execution type program is switched to the stand-by type

• The stand-by type program to be executed is switched to the scan execution type

program.

Initial execution type program

2

More than one program can be set.

(SFC program cannot be set.)

More than one program can be set.

(Two SFC programs, normal and program execution management, can be set.)

Scan execution type program

Low speed execution type program

The maximum number of program files changes depending on the CPU module type. For details, refer to the User's Manual (Function Explanation, Program Fundamentals) for the CPU module used.

More than one program can be set.

(SFC program cannot be set.)

Stand-by type program

More than one program can be set. (More than one SFC program can be set for normal programs.)

Fixed scan execution type program

1: The Redundant CPU, Universal model QCPU, and LCPU cannot execute the low-speed

execution type program.

2: The program execution management cannot set on the Universal model QCPU and

LCPU.

3 - 6 3 - 6

3 SPECIFICATIONS

REMARKS

Use the PSCAN or POFF instruction to switch the execution type of the program. For details on the PSCAN and POFF instructions, refer to the Programming Manual (Common Instructions) for the CPU module used.

3.1.3 Performance specifications of QnACPU

SFC program

STEP-RUN operation function

Step trace function 2 (Memory card required)

Step transition watchdog timer function Provided (10 timers)

(1) Table 3.3 indicates the performance specifications related to SFC programs.

Table 3.3 Performance Specifications Related to SFC Programs

Break

Continue

Forced execution

Q2ACPU

Item

Capacity Max. 28k steps Max. 60k steps Max. 92k steps Max. 124k steps

Number of files

Number of blocks Max. 320 blocks (0 to 319) Number of SFC steps Max. 8192 steps for all blocks, max. 512 steps for one block Number of branches Max. 32 Number of concurrently active steps Number of operation output sequence steps Number of transition condition sequence steps All-block break Batch break setting for all blocks Designated block break Up to 64 blocks can be set for the designated blocks. Designated step break Up to 64 points can be set for the designated steps. Number of cycles 1 to 255 times Designated block continue Designated step continue Continue from designated step Forced block execution 1 block is set for the designated block. Forced 1 step execution for designated step Forced block end 1 block is set for the designated block. Forced step end 1 point is set for the designated step. Trace memory capacity Max. 48k bytes for all blocks, 1 to 48k bytes for one block (1k byte units) Trace memory capacity after trigger Block designation Max. 12 blocks Trigger step 1 step per block Execution condition Per designated time or per scan

Q2ASCPU

Q2ASHCPU

(1 normal SFC program and 1 program execution management SFC

Max. 1280 steps for all blocks

Max. 256 steps for one block

Q2ACPU-S1

Q2ASCPU-S1

Q2ASHCPU-S1

Scannable SFC program: 2 files

program)

Max. 2k steps for all blocks 3

No restriction on one step

One ladder block only

1 block is set for the designated block.

1 point is set for the designated step.

128 bytes to capacity setting of each block

Q3ACPU

1

(including HOLD steps)

Q4ACPU

Q4ARCPU

1 Refer to Section 5.2.3 for the program execution management SFC program. 2 This function can be executed only when the software package for personal computer is

SW2IVD-GPPW/SW2NX-GPPW.

3 When "Peripheral" is selected for note editing with the operation output (Peripheral Note),

up to 2k steps may not be secured for one block. When note editing is not performed or "Unite" is selected for note editing (United Note), up to 2k steps can be secured for one block.

3 - 7 3 - 7

3 SPECIFICATIONS

(2) Precautions for creating SFC programs

(a) The SFC programs that can be created are "scan execution type program" and "stand-

by type program".

(b) Two SFC programs (one normal SFC program and one program execution

management SFC program) can be set as a scan execution type program.

(c) More than one SFC program can be set as a stand-by type program.

(d) The stand-by type SFC program is executed in the following procedure.

• The currently executed scan execution type program is switched to the stand-by type

• The stand-by type program to be executed is switched to the scan execution type

program.

Initial execution type program

More than one program can be set.

(SFC program cannot be set.)

More than one program can be set.

(Two SFC programs, normal and program execution management, can be set.)

Scan execution type program

Low speed execution type program

The maximum number of program files changes depending on the CPU module type. For details, refer to the User's Manual (Function Explanation, Program Fundamentals) for the CPU module used.

More than one program can be set.

(SFC program cannot be set.)

Stand-by type program

More than one program can be set.

(More than one SFC program can

be set for normal operation only.)

REMARKS

Use the PSCAN or POFF instruction to switch the execution type of the program. For details on the PSCAN and POFF instructions, refer to the Programming Manual (Common

3 - 8 3 - 8

Instructions) for the CPU module used.

3 SPECIFICATIONS

3.2 Device List

3.2.1 Device list of Basic model QCPU

Table 3.4 indicates the devices that can be used for the transition conditions and operation outputs of an SFC program.

Classification Type Device name

Input 2048 X0 to X7FF Hexadecimal

Output 2048 Y0 to Y7FF Hexadecimal

Internal relay 8192 M0 to M8191 Decimal

Latch relay 2048 L0 to L2047 Decimal

Bit device

Internal user device

Word device

Internal system device

Link direct device

Module access device

Index register Word device Index register 10 Z0 to Z9 Decimal N/A

Bit device

Word device

Bit device

Word device

Word device Intelligent function module device 65536 Un\G0 to Un\G65535 *2 Decimal N/A

Annunciator 1024 F0 to F1023 Decimal

Edge relay 1024 V0 to V1023 Decimal

Step relay 2048 S0 to S127/block Decimal

Link relay 2048 B0 to B7FF Hexadecimal

Link speci al relay 1024 SB0 to SB3FF Hexadecimal

Timer *1 512 T0 to T511 Decimal

Retentive timer *1 0 (ST0 to ST511) Decimal

Counter *1 512 C0 to C511 Decimal

Data register 11136 D0 to D11135 Decimal

Link register 2048 W0 to W 7FF Hexadecimal

Link special regis ter 1024 SW 0 to SW3FF Hexadecimal

Function input 16 FX0 to FXF Hexadecimal

Function output 16 FY0 to FYF Hexadecimal

Special relay 1024 SM0 to SM1023 Decimal

Function register 5 FD0 to FD4 Decim al

Special register 1024 SD0 to SD1023 Decimal

Link input 8192 Jn\X0 to Jn\X1FFF Hexadecimal

Link output 8192 Jn\ Y0 to Jn\Y1FFF Hexadecimal

Link relay 16384 Jn\B0 to Jn\B3FFF Hexadecimal

Link speci al relay 512 Jn\SB0 to Jn\SB1FF Hexadecimal

Link register 16384 Jn\W 0 to J n\W3FFF Hexadecimal

Link special regis ter 512 Jn\SW 0 to Jn\SW 1FF Hexadecimal

Table 3.4 Device List

Point Range

Default

Parameter

setting range

Can be

changed within

16.4k words.

(Continued to the next page)

*3

N/A

3 - 9 3 - 9

3 SPECIFICATIONS

Classification Type Device name

File register *5 Word device File register 64k

Nesting

Pointer

Bit device SFC block device 128 BL0 to BL127 Decimal N/A

Others

Constant

Nesting 15 N0 to N14 Decimal N/A

Pointer 300 P0 to P299 Decimal N/A

Interrupt pointer 128 I0 to I127 Decimal

Network No. specification device 239 J1 to J239 Decimal

I/O No. specification device

Macro instruction argument device

Decimal constant K-2147483648 to 2147483647

Hexadecimal constant H0 to HFFFFFFFF

Real constant E 1.17550-38 to E 3.40282+38

Character string constant "ABC", "123" *4

Table 3.4 Device List (continued)

Q00JCPU

Q00CPU, Q01CPU

*1: For the timer, retentive timer, and counter, contact/coil values are stored in bit devices, and current

values are stored in word devices.

*2: The number of points that can be actually used varies depending on the intelligent function module.

For the points in the buffer memory, refer to the manual for the intelligent function module used.

*3: The value can be changed in the PLC parameter dialog box of GX Developer.

(Except for input, output, step relay, link special relay, and link special register. Refer to Section 9.2.)

*4: Character strings can be used only for the $MOV, STR, DSTR, VAL, DVAL, ESTR, and EVAL

instructions. They cannot be used for the other instructions.

*5: Because the Q00JCPU does not have the standard RAM, the file register cannot be used.

Default

Point Range

• R0 to R32767

• ZR0 to ZR65535

U0 to UF Hexadecimal

U0 to U3F Hexadecimal

VD0 to VD

Decimal N/A

setting range

Parameter

N/A

3 - 10 3 - 10

3 SPECIFICATIONS

3.2.2 Device list of High Performance model QCPU, Process CPU, and Redundant CPU

Table 3.5 indicates the devices that can be used for the transition conditions and operation outputs of SFC programs.

Classification Type Device name

Input 8192 X0 to X1FFF Hexadecimal

Output 8192 Y0 to Y1FFF Hexadecimal

Internal relay 8192 M0 to M8191 Decimal

Latch relay 8192 L0 to L8191 Decimal

Bit device

Internal user device

Word device

Bit device

Internal system device

Word device

Bit device

Link direct device

Word device

Module access device

Index register Word device Index register 20 Z0 to Z15 Decim al N/A

File register Word device File register 0

Nesting

Pointer

Word device

Annunciator 2048 F0 to F2047 Decimal

Edge relay 2048 V0 to V2047 Decimal

Step relay 8192 S0 to S511/block Decimal

Link relay 8192 B0 to B1FFF Hexadecimal

Link speci al relay 2048 SB0 to SB7FF Hexadecimal

Timer *1 2048 T0 to T2047 Decimal

Retentive timer *1 0 (ST0 to ST2047) Decimal

Counter *1 1024 C0 to C1023 Decimal

Data register 12288 D0 to D12287 Decimal

Link register 8192 W 0 to W 1FFF Hexadecimal

Link special regis ter 2048 SW0 to SW 7FF Hexadecimal

Function input 16 FX0 to FXF Hexadecimal

Function output 16 FY0 to FYF Hexadecimal

Special relay 2048 SM0 to SM2047 Decimal

Function register 5 FD0 to FD4 Decimal

Special register 2048 SD0 to SD2047 Decimal

Link input 8192 Jn\X0 to X1FFF Hexadecimal

Link output 8192 Jn\Y0 to Y1FFF Hexadecimal

Link relay 16384 Jn\B0 to B3FFF Hexadecimal

Link speci al relay 512 Jn\SB0 to SB 1FF Hexadecimal

Link register 16384 Jn\W0 to W3FFF Hexadecimal

Link special regis ter 512 Jn\SW 0 to SW1FF Hexadecimal

Intelligent function module device 65536 Un\G0 to G65535*2 Decimal N/A

Cyclic transmission area device *4 14336 U3En\G0 to G4095 Decimal

Nesting 15 N0 to N14 Decimal N/A

Pointer 4096 P0 to P4095 Decimal

Interrupt pointer 256 I0 to I255 Decimal

Table 3.5 Device List

Point Range

Default

Parameter

setting range

Can be

changed within

29k words. *3

Setting

available

0 to 1018k

points

(Continued to the next page)

N/A

3 - 11 3 - 11

3 SPECIFICATIONS

Classification Type Device name

Bit device

Others

Constant

*1: For the timer, retentive timer, and counter, contact/coil values are stored in bit devices, and current

*2: The number of points that can be actually used varies depending on the intelligent function module

*3: The value can be changed in the Device setting of the PLC parameter dialog box.

SFC block device

Network No. specification device

I/O No. specification device 255 J1 to J255

Macro instruction argument device

Decimal constant K-2147483648 to 2147483647

Hexadecimal constant H0 to HFFFFFFFF

Real constant

Character string constant "ABC", "123"

values are stored in word devices.

or special function module. For the points in the buffer memory, refer to the manual for the intelligent function module or special function module used.

(Except for input, output, step relay, link special relay, and link special register. Refer to Section 9.2.)

Table 3.5 Device List (continued)

Default

Point Range

320 BL0 to BL319 Decimal

512 TR0 to TR511 Decimal

Hexadecimal

U0 to UFF

Single-precision floating-point data

E

1.17549435-38 to E 3.40282347+38

Double-precision floating-point data

2.2250738585072014-308 to

E

1.7976931348623157+308

Hexadecimal

Parameter

setting range

N/A

3 - 12 3 - 12

3 SPECIFICATIONS

3.2.3 Device list of Universal model QCPU

Table 3.6 indicates the devices that can be used for the transition conditions and operation outputs of SFC programs.

Classification Type Device name

Input 8192 X0 to X1FFF

Output 8192 Y0 to Y1FFF Hexadecimal

Internal relay 8192 *20 M0 to M8191 *21 Decimal

Latch relay 8192 L0 to L8191 Decimal

Annunciator 2048 F0 to F2047 Decimal

Edge relay 2048 V0 to V2047 Decimal

Step relay 8192 S0 to S8191 Decimal

Link relay 8192 B0 to B1FFF Hexadecimal

Link speci al relay 2048 SB0 to SB7FF Hexadecimal

Timer *1 2048 T0 to T2047 Decimal

Retentive timer *1 0 (ST0 to ST2047) Decimal

Counter *1 1024 C0 to C1023 Decimal

Data register 12288 *22 D0 to D12287 *23 Decimal

Link register 8192 W 0 to W 1FFF Hexadecimal

Link special regis ter 2048 SW0 to SW 7FF Hexadecimal

Function input 16 FX0 to FXF Hexadecimal

Function output 16 FY0 to FYF Hexadecimal

Special relay 2048 SM0 to SM2047 Decimal

Function register 5 FD0 to FD4 Decimal

Special register 2048 SD0 to SD2047 Decimal

Link input 16384 *14 Jn\X0 to Jn\X3FFF *15 Hexadecimal

Link output 16384 *1 4 Jn\Y0 to Jn\Y3FFF *15 Hexadecimal

Link relay 32768 Jn\B0 to Jn\B7FFF Hexadecimal

Link speci al relay 512 Jn\SB0 to Jn\SB1FF Hexadecimal

Link register 131072 Jn\W0 to Jn\W1FFFF Hexadecimal

Link special regis ter 512 Jn\SW 0 to Jn\SW1FF Hexadecimal

Intelligent function module device 65536 Un\G0 to Un\G65535 *2 Decimal N/A

Cyclic transmission area device *4

Internal user device

Internal system device

Link direct device

Module access device

Bit device

Word device

Bit device

Word device

Bit device

Word device

Table 3.6 Device List

4096 U3En\G0 to U3En\G4095 Decimal N/A

14336

Default

Point Range

Hexadecimal

U3En\G10000 to U3En\G24335

Decimal

(Continued to the next page)

setting range

changed within

29k words. *3

Parameter

Can be

*19

N/A

Setting

available

3 - 13 3 - 13

3 SPECIFICATIONS

Classification Type Device name

Index register/standard device register

File register *7 Word device File register 0

Extended data register *7 Extended link register *7

Nesting

Pointer

Others

Constant

Word device Index register/standard device register 20 Z0 to Z19 Decimal N/A

Word device Extended data register 0 *16

Word device Extended link register 0

Nesting 15 N0 to N14 Decimal N/A

Pointer 4096 *8 *17 P0 to P4095 *9 *18 Decimal

Interrupt pointer 256 *10 I0 to I255 *11 Decimal

Bit device SFC block device 320 *25 BL0 to BL319 *12 Decimal

Network No. specification device 255 J1 to J255 Decimal

I/O No. specification device 516

Macro instruction argument device 10 VD0 to VD9 Decimal

Decimal constant K-2147483648 to 2147483647

Hexadecimal constant H0 to HFFFFFFFF

Real constant

Character string constant Up to 32 characters (ex. "ABC", "123")

*1: For the timer, retentive timer, and counter, contact/coil values are stored in bit devices, and current

values are stored in word devices.

*2: The number of points that can be actually used varies depending on the intelligent function module.

For the points in the buffer memory, refer to the manual for the intelligent function module used.

*3: The number of points can be changed (except for input, output, and step relay) in the Device tab of

the PLC parameter dialog box. Note that the step relay points can be changed to 0 point for the Universal model QCPU whose serial number (first five digits) is "10042" or later. For the Universal model QCPU whose serial number (first five digits) is "12052" or later, the step relay points can be set in increments of 1k points and up to the following points.

• Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU: 8192 points

• Universal model QCPUs other than the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU: 16384 points

*4: Available only in a multiple CPU system configuration. *5: Up to 15 digits can be entered in GX Developer. *6: The total of the points for the file register, extended data register (D), and extended link register (W) *7: The device cannot be used on the Q00UJCPU. *8: For the Q00UJCPU, Q00UCPU, and Q01UCPU, the number of points is 512. *9: For the Q00UJCPU, Q00UCPU, and Q01UCPU, the range is P0 to P511. *10: For the Q00UJCPU, Q00UCPU, and Q01UCPU, the number of points is 128. *11: For the Q00UJCPU, Q00UCPU, and Q01UCPU, the range is I0 to I127. *12: For the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU, the range is BL0 to BL127.

Table 3.6 Device List (continued)

Default

Point Range

U0 to UFF, U3E0 to U3E3 *13

Single-precision floating-point data:

E

1.17549435-38 to E 3.40282347+38

Double-precision floating-point data *5:

E

2.2250738585072014-308 to

E

1.7976931348623157+308

Hexadecimal

setting range

points *6 *24

Parameter

0 to 4086k

N/A

3 - 14 3 - 14

3 SPECIFICATIONS

*13: The range differs depending on the CPU module: U0 to UF for the Q00UJCPU; U0 to U3F and

U3E0 to 3E2 for the Q00UCPU and Q01UCPU; and U0 to U7F and U3E0 to U3E2 for the Q02UCPU.

*14: For the Universal model QCPU whose serial number (first five digits) is "12011" or earlier, the

number of points is 8192.

*15: For the Universal model QCPU whose serial number (first five digits) is "12011" or earlier, the

range is Jn\X/Y0 to Jn\1FFF. *16: For the Q50UDEHCPU and Q100UDEHCPU, the number of points is 128k. *17: For the Q50UDEHCPU and Q100UDEHCPU, the number of points is 8192. *18: For the Q50UDEHCPU and Q100UDEHCPU, the range is P0 to P8191. *19: The changeable range differs depending on the CPU module: within 30k words for the

Q03UDVCPU; within 40k words for the Q04UDVCPU and Q06UDVCPU; and within 60k words for

the Q13UDVCPU and Q26UDVCPU. *20: The number of points differs depending on the CPU module: 9216 for the Q03UDVCPU; 15360 for

the Q04UDVCPU and Q06UDVCPU; and 28672 for the Q13UDVCPU and Q26UDVCPU. *21: The range differs depending on the CPU module: M0 to M9215 for the Q03UDVCPU; M0 to

M15359 for the Q04UDVCPU and Q06UDVCPU; and M0 to M28671 for the Q13UDVCPU and

Q26UDVCPU. *22: The number of points differs depending on the CPU module: 13312 for the Q03UDVCPU; 22528

for the Q04UDVCPU and Q06UDVCPU; and 41984 for the Q13UDVCPU and Q26UDVCPU. *23: The range differs depending on the CPU module: D0 to D13311 for the Q03UDVCPU; D0 to

D22527 for the Q04UDVCPU and Q06UDVCPU; and D0 to D41983 for the Q13UDVCPU and

Q26UDVCPU. *24: The setting range differs depending on the CPU module: 0 to 4192k points for the Q03UDVCPU, 0

to 4224k points for the Q04UDVCPU, 0 to 4480k points for Q06UDVCPU, 0 to 4608k points for the

Q13UDVCPU, and 0 to 4736k points for the Q26UDVCPU. *25: For the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU, the number of points is 128.

3 - 15 3 - 15

3 SPECIFICATIONS

3.2.4 Device list of LCPU

Table 3.7 indicates the devices that can be used for the transition conditions and operation outputs of SFC programs.

Classification Type Device name

Input 8192 X0 to X1FFF Hexadecimal

Output 8192 Y0 to Y1FFF Hexadecimal

Internal relay 8192 M0 to M8191 Decimal

Latch relay 8192 L0 to L8191 Decim al

Bit device

Internal user device

• Bit device (contact/coil)

• Word device (current value)

Word device

Bit device

Internal system device

Word device

Module access device Word device Intelligent function module device 65536 Un\G0 to Un\G65535 *2 Decimal N/A

Index register/standard device register

File register Word device File register 0

Extended data register Word device Extended data register 128K D12288 to D143359 *1 Decimal

Extended link register Word device Extended link register 0

Nesting

Pointer

Others

Word device Index register/standard device register 20 Z0 to Z19 Decimal N/A

Bit device SFC block device 320 BL0 to BL319 *4 Decimal

*1: For the L02SCPU, L02SCPU-P, L02CPU, and L02CPU-P, the number of points is 32K (D12288 to

D45055).

*2: The number of points that can be actually used varies depending on the intelligent function module.

Refer to the manual for each intelligent function module. *3: For the L02SCPU, L02SCPU-P, L02CPU, and L02CPU-P, the total number of points is 0 to 64K. *4: For the L02SCPU, L02SCPU-P, L02CPU, and L02CPU-P, the number of points is 128 (BL0 to B127). *5: For the L02SCPU, L02SCPU-P, L02CPU, and L02CPU-P, the range is U0 to U3F. *6: For the LCPU whose serial number (first five digits) is "15101" or earlier, either 0K point or 8K point

can be set for the step relay. For the LCPU whose serial number (first five digits) is "15102" or later,

the step relay points can be set up to the following points.

• L02(S)CPU, L02(S)CPU-P: 8192 points

• Other models: 16384 points

Link relay 8192 B0 to B1FFF Hexadecimal

Annunciator 2048 F0 to F2047 Decimal

Link speci al relay 2048 SB0 to SB7FF Hexadecimal

Edge relay 2048 V0 to V2047 Decimal

Step relay 8192 S0 to S8191 Decimal

Timer 2048 T0 to T2047 Decimal

Retentive timer 0 (ST0 to ST2047) Decimal

Counter 1024 C0 to C1023 Decimal

Data register 12288 D0 to D12287 Decimal

Link register 8192 W 0 to W1FFF Hexadecimal

Link special regis ter 2048 SW0 to SW 7FF Hexadecimal

Function input 16 FX0 to FXF Hexadecimal

Function output 16 FY0 to FYF Hexadecimal

Special relay 2048 SM0 to SM2047 Decimal

Function register 5 FD0 to FD4 Decimal

Special register 2048 SD0 to SD2047 Decimal

Nesting 15 N0 to N14 Decimal N/A

Pointer 4096 P0 to P4095 Decimal

Interrupt pointer 256 I0 to I255 Decimal

I/O No. specification device

Macro instruction argument device 10 VD0 to VD9 Decimal

Table 3.7 Device List

Point Range

Default

U0 to UFF *5 Decimal

Decimal

Hexadecimal

Parameter

setting range

Setting available (Up to 29K words

for the internal

user device)*6

0 to 384K

points in total

*3 (in 1K units)

N/A

3 - 16 3 - 16

3 SPECIFICATIONS

3.2.5 Device list of QnACPU

Table 3.8 indicates the devices that can be used for the transition conditions and operation outputs of SFC programs.

Classification Type Device name

Input *3 8192 X0 to X1FFF Hexadecimal

Output *3 8192 Y0 to Y1FFF Hexadecimal

Internal relay 8192 M0 to M8191 Decimal

Latch relay 8192 L0 to L8191 Decimal

Bit device

Internal user device

Word device

Internal system device

Link direct device

Special function module device

Index register Word device Index register 16 Z0 to Z15 Decimal N/A

File register Word device File register 0

Nesting

Pointer

Bit device

Word device

Bit device

Word device

Word device Buffer register 16384 Un\G0 to Un\G16383 *2 Decimal N/A

Annunciator 2048 F0 to F2047 Decimal

Edge relay 2048 V0 to V2047 Decimal

Step relay *3 8192 S0 to S511/block Decimal

Link relay 8192 B0 to B1FFF Hexadecimal

Link special relay *3 2048 SB0 to SB7FF Hexadecimal

Timer *1 2048 T0 to T2047 Decimal

Retentive timer *1 0 (ST0 to ST2047) Decimal

Counter *1 1024 C0 to C1023 Decimal

Data register 12288 D0 to D12287 Decimal

Link register 8192 W 0 to W 1FFF Hexadecimal

Link special regis ter *3 2048 SW0 to SW 7FF Hexadecimal

Function input 5 FX0 to FX4 Hexadecimal

Function output 5 FY0 to FX4 Hexadecimal

Special relay 2048 SM0 to SM2047 Decimal

Function register 5 FD0 to FD4 Decimal

Special register 2048 SD0 to SD2047 Decimal

Link input 8192 Jn\X0 to Jn\X1FFF Hexadecimal

Link output 8192 Jn\Y0 to Jn\Y1FFF Hexadecimal

Link relay 8192 Jn\B0 to Jn\B1FFF Hexadecimal

Link speci al relay 512 Jn\SB0 to Jn\SB1FF Hexadecimal

Link register 8192 Jn\W 0 to Jn\W1FFF Hexadecimal

Link special regis ter 512 Jn\SW 0 to Jn\SW1FF Hexadecimal

Nesting 15 N0 to N14 Decimal N/A

Pointer 4096 P0 to P4095 Decimal

Interrupt pointer 48 I0 to I47 Decimal

Table 3.8 Device List

Point Range

Default

Parameter

setting range

Can be

changed within

29k words. *3

0 to 1024k

points

(Continued to the next page)

N/A

3 - 17 3 - 17

3 SPECIFICATIONS

Classification Type Device name

Bit device

Others

Constant

SFC block device 320 BL0 to 319 Decimal

SFC transition device 512 TR0 to TR511 Decimal

Network No. specification device 256 J1 to J255 Decimal

I/O No. specification device

Decimal constant K-2147483648 to 2147483647

Hexadecimal constant H0 to HFFFFFFFF

Real constant E 1.17549435-38 to E 3.40282347+38

Character string constant "ABC", "123"

Table 3.8 Device List (continued)

REMARKS

Default

Point Range

U0 to UFF Hexadecimal

setting range

Parameter

N/A

*1: For the timer, retentive timer, and counter, contact/coil values are stored in bit devices, and

current values are stored in word devices.

*2: The number of points that can be actually used varies depending on the special function

module. For the points in the buffer memory, refer to the manual for the special function module used.

*3: The values of the input, output, step relay, link special relay, and link special register are

fixed to the default values, and cannot be changed.

3 - 18 3 - 18

3 SPECIFICATIONS

3.3 Processing Time

3.3.1 Processing time for SFC program

The time required to process the SFC program is discussed below.

(1) Method for calculating the SFC program processing time

Calculate the SFC program processing time with the following expression

SFC program processing time

(A) + (B) + (C)

(a) "(A): Processing time of operation outputs in all blocks"

Indicates the total sum of the processing times of the instructions used for the operation outputs of all steps that are active. For the processing time of the instructions, refer to the Programming Manual (Common Instructions) for the CPU module used.

(b) "(B): Processing time of all transition conditions"

Indicates the total sum of the processing times of the instructions used for the transition conditions associated with all steps that are active. For the processing time of the instructions, refer to the Programming Manual (Common Instructions) for the CPU module used.

(c) "(C)" SFC system processing time"

Calculate the SFC system processing time with the following expression.

SFC system processing time

(a) + (b) + (c) + (d) + (e) + (f) + (g)

Processing Time Calculation of Processing Time (Unit: µs) (a) Active block

processing time

(b) Inactive block

processing time

(c) Nonexistent

block processing time

(d) Active step

processing time

(e) Active

transition processing time

(f) Transition

conditionsatisfied step processing time

(g) SFC end

processing time

(Active block processing time) (active block processing time coefficient) (number of active blocks)

• Active block processing time: System processing time required to execute active blocks

• Number of active blocks: Number of blocks that are active (Inactive block processing time) (inactive block processing time coefficient) (number of inactive blocks)

• Inactive block processing time: System processing time required to execute inactive blocks

• Number of inactive blocks: Number of blocks that are inactive (Nonexistent block processing time) (nonexistent block processing time coefficient) (number of nonexistent blocks)

• Nonexistent block processing time: System processing time required to execute blocks that have not

been created

• Number of nonexistent blocks: Number of blocks where programs have not been created within the

number of blocks set in the parameter

(Active step processing time) (active step processing time coefficient) (number of active steps)

• Active step processing time: Time required to execute active steps

• Number of active steps: Number of steps that are active in all blocks (Active transition processing time) (active transition processing time coefficient) (number of active transitions)

• Active transition processing time: System processing time required to execute active transitions

• Number of active transitions: Number of transition conditions associated with all steps that are active in

all blocks (Transition condition-satisfied step processing time) time coefficient)

• Transition condition-satisfied step processing time: Time required to perform OFF execution of active steps

• Number of transition condition-satisfied steps: Number of steps where operation outputs are turned OFF since transition conditions were satisfied in all blocks

(SFC end processing time) (SFC end processing time)

• SFC end processing time: System processing time required to perform the end processing of SFC program.

(number of transition condition-satisfied steps)

(transition condition-satisfied step processing

3 - 19 3 - 19

3 SPECIFICATIONS

(2) System processing times for different CPU module models

(a) When Basic model QCPU is used

Active block processing time coefficient 41.9µs 35.5µs 27.3µs Inactive block processing time coefficient 10.5µs 8.8µs 6.8µs Nonexistent block processing time coefficient 1.1µs 0.9µs 0.7µs Active step processing time coefficient 31.6µs 26.7µs 20.5µs Active transition processing time coefficient 10.2µs 8.7µs 6.7µs

Transition condition-satisfied step processing time coefficient

SFC end processing time 66.8µs 56.5µs 43.5µs

(b) When High Performance model QCPU, Process CPU or Redundant CPU is used

Active block processing time coefficient 33.7µs 14.5µs 14.5µs 14.5µs Inactive block processing time coefficient 12.0µs 5.2µs 5.2µs 5.2µs Nonexistent block processing time coefficient 4.1µs 1.8µs 1.8µs 1.8µs Active step processing time coefficient 24.5µs 10.6µs 10.6µs 10.6µs Active transition processing time coefficient 10.0µs 4.3µs 4.3µs 4.3µs

Transition condition-satisfied step processing time coefficient

SFC end processing time 108.2µs 46.6µs 46.6µs 46.6µs

Item Q00JCPU Q00CPU Q01CPU

Item

With HOLD step designation Normal step designation

216.0µs 182.8µs 140.6µs

263.5µs 222.9µs 171.5µs

High Performance model

QCPU

QnCPU QnHCPU QnPHCPU QnPRHCPU

130.4µs 56.2µs 56.2µs 56.2µs

119.4µs 51.5µs 51.5µs 51.5µs

Process

CPU

Redundant

CPU

3 - 20 3 - 20

3 SPECIFICATIONS

Active block processing time coefficient Inactive block processing time coefficient Nonexistent block processing time coefficient Active step processing time coefficient Active transition processing time coefficient

Transition condition-satisfied step processing time coefficient

SFC end processing time 67.5µs 38.4µs

(c) When Universal model QCPU is used

Item

Active block processing time coefficient Inactive block processing time coefficient Nonexistent block processing time coefficient Active step processing time coefficient Active transition processing time coefficient

Transition condition-satisfied step processing time coefficient

SFC end processing time

With HOLD step designation

Normal step designation

With HOLD step designation Normal step designation

Universal model QCPU

Q04UDHCPU, Q06UDHCPU Q10UDHCPU, Q13UDHCPU

Q00UJCPU,

Q00UCPU,

Q01UCPU

12.7µs 8.4µs 8.3µs 7.0µs

5.3µs 3.9µs 3.8µs 3.4µs

0.9µs 0.8µs 0.7µs 0.6µs

11.9µs 8.6µs 8.2µs 6.4µs

3.4µs 2.1µs 2.0µs 1.6µs

86.7µs 69.6µs 60.3µs

106.9µs 83.2µs 73.7µs 52.0µs

Q02UCPU

Q03UDVCPU

5.0µs 4.8µs

2.5µs 2.3µs

0.60µs 0.33µs

5.8µs 5.5µs

1.3µs 1.3µs

38µs 34µs

50µs 41µs

25.5µs 25.5µs

Q03UDCPU,

Q03UDECPU

36.6µs 26.9µs

Universal model QCPU

Q20UDHCPU, Q26UDHCPU Q04UDEHCPU, Q06UDEHCPU Q10UDEHCPU, Q13UDEHCPU

Q20UDEHCPU, Q26UDEHCPU,

Q50UDEHCPU, Q100UDEHCPU

42.7µs

Q04UDVCPU, Q06UDVCPU,

Q13UDVCPU, Q26UDVCPU

3 - 21 3 - 21

3 SPECIFICATIONS

(d) When LCPU is used

Active block processing time coefficient 12.7µs 8.5µs 7.0µs

Inactive block processing time coefficient 5.3µs 3.8µs 3.4µs

Nonexistent block processing time coefficient 0.9µs 1.2µs 0.6µs

Active step processing time coefficient 11.9µs 8.7µs 6.4µs

Active transition processing time coefficient 3.4µs 2.0µs 1.6µs

Transition condition-satisfied step processing time coefficient

Item

With HOLD step designation

Normal step designation

L06CPU,

L06CPU-P

L02SCPU,

L02SCPU-P

86.7µs 66.1µs 42.7µs

106.9µs 79.4µs 52.0µs

L02CPU,

L02CPU-P

L26CPU,

L26CPU-P

L26CPU-BT,

L26CPU-PBT

SFC end processing time 67.5µs 44.7µs 26.9µs

The HOLD step includes all of the coil hold steps and operation hold steps (with or without

transition check). The Normal step represents steps other than the above.

(e) When QnACPU is used

Q4ACPU,

Item

Active block processing time coefficient 30.6µs 61.2µs 32.6µs Inactive block processing time coefficient 10.7µs 21.3µs 28.8µs Nonexistent block processing time coefficient 4.6µs 9.2µs 12.5µs Active step processing time coefficient 23.2µs 46.4µs 62.7µs Active transition processing time coefficient 9.4µs 18.7µs 25.2µs

Transition condition-satisfied step processing time coefficient

SFC end processing time 89.7µs 179.3µs 242.1µs

With HOLD step designation Normal step designation

Q4ARCPU,

Q2ASHCPU(S1)

Q3ACPU

137.2µs 274.3µs 370.4µs

122.5µs 245.1µs 330.9µs

Q2ACPU(S1),

Q2ASCPU(S1)

The HOLD step includes all of the coil hold steps and operation hold steps (with or without

transition check). The Normal step represents steps other than the above.

3 - 22 3 - 22

3 SPECIFICATIONS

[SFC system processing time calculation example]

Using the Q25HCPU as an example, the processing time for the SFC system is calculated as shown below, given the following conditions.

• Designated at initial START

• Number of active blocks: 30 (active blocks at SFC program)

• Number of inactive blocks: 70 (inactive blocks at SFC program)

• Number of nonexistent blocks: 50 (number of blocks between 0 and the max. created block No. which have no SFC program)

• Number of active steps: 60 (active steps within active blocks)

• Active step transition conditions: 60

• Steps with satisfied transition conditions: 10 (active steps (no HOLD steps) with satisfied transition conditions)

SFC system process time =(14.5 × 30) + (5.2 × 70) + (1.8 × 50) + (10.6 × 60) + (4.3 × 60) + (56.2 × 10) + 46.6 = 2391.6 µs

In this case, calculation using the equation shown above results in an SFC system processing time of 2.40 ms. With the Q4ACPU, given the same conditions, the processing time would be 5.32 ms. The scan time is the total of the following times; SFC system processing time, main sequence program processing time, SFC active step transition condition ladder processing time, and CPU END processing time. The scan time is the total of the following times: SFC system processing time, main sequence program processing time, processing time of ladder circuit having transition conditions associated with SFC's active steps, and CPU module's END processing time. The number of active steps, the number of transition conditions, and the number of steps with satisfied transition conditions varies according to the conditions shown below.

• When transition condition is unsatisfied

• When transition condition is satisfied (without continuous transition)

• When transition condition is satisfied (with continuous transition)

The method for determining the number of the above items is illustrated in the SFC diagram below.

2.40 ms

Step 1

Transition condition 1

Step 2

Transition condition 2

Step 3

Transition condition 3

Step 4

Transition condition 4

Step 5

Transition condition 8

Step 10

Step 6

Transition condition 5

Step 7

Transition condition 6

Step 8

Transition condition 7

Step 9

3 - 23 3 - 23

3 SPECIFICATIONS

The following table indicates the number of active steps, number of active transitions, and number

Whether Transition

Conditions Are

Satisfied or Not

• Transition conditions not satisfied

• Transition conditions 2, 5 satisfied

• Transition conditions 3, 6 not satisfied

• Transition conditions 2, 3, 5, 6 satisfied

of transition condition-satisfied steps when Step 2 and Step 6 are active.

Presence/Absence

of Continuous

Transition

Absence

Presence

Absence

Presence

Number of Active

Steps

2

(Steps 2, 6)

2

(Steps 2, 6)

4

(Steps 2, 3, 6, 7)

2

(Steps 2, 6)

6

(Steps 2 to 4, 6 to 8)

Number of Active

Transitions

2

(Transition

conditions 2, 5)

2

(Transition

conditions 2, 5)

4

(Transition

conditions 2, 3, 5, 6)

2

(Transition

conditions 2, 5)

6

(Transition

conditions 2 to 7)

Number of

Transition

Condition-

Satisfied Steps

0

2

(Steps 2, 6)

2

(Steps 2, 6)

2

(Steps 2, 6)

4

(Steps 2, 3, 6, 7)

3 - 24 3 - 24

3 SPECIFICATIONS

3.3.2 Processing time for S(P).SFCSCOMR instruction and S(P).SFCTCOMR instruction

Processing time for S(P).SFCSCOMR instruction and S(P).SFCTCOMR instruction is shown below.

[Condition]

• The number of comments to be stored in the comment file: 1000

• Sequence steps in the SFC step in the SFC program: 1000 sequence steps

• The number of active steps: 40

Instruction Condition

S(P).SFCSCOMR

S(P).SFCTCOMR

At instruction execution 280µs 120µs 120µs 120µs

At END processing (read 1 comment) 780µs 350µs 350µs 350µs

At instruction execution 300µs 130µs 120µs 120µs

• Transition condition for serial transition

• Transition condition after

At END processing (read 1 comment)

selection branching

• Transition condition after parallel coupling

Number of parallel couplings: 2

Number of parallel couplings: 32

1: Indicates that the sequence steps in SFC steps consist of 800 sequence

steps.

Instruction Condition

S(P).SFCSCOMR

S(P).SFCTCOMR

At instruction execution

High Performance model

QCPU

QnCPU QnHCPU

2.5ms 1.1ms 1.1ms 1.1ms

4.5ms 2.0ms 2.0ms 2.0ms

60.5ms

1

26.2ms 26.2ms 26.2ms

Universal model QCPU

Q03UD(E)CPU

Min. Max. Min. Max.

190µs 193µs 176µs 177µs

Process

CPU

Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU, Q13UD(E)HCPU, Q20UD(E)HCPU, Q26UD(E)HCPU,

Q50UDEHCPU,

Q100UDEHCPU

Redundant

CPU

3 - 25 3 - 25

3 SPECIFICATIONS

Instruction Condition

S(P).SFCSCOMR

S(P).SFCTCOMR

At END processing (read 1 comment) 3.3ms 4.5ms 2.5ms 4.0ms

• Transition condition for serial transition

• Transition condition after

At END processing (read 1 comment)

selection branching

• Transition condition after parallel coupling

Number of parallel couplings: 2

Number of parallel couplings: 32

Instruction Condition

Min. Max. Min. Max.

S(P).SFCSCOMR

S(P).SFCTCOMR

At instruction execution

54.7μs 60.0μs 51.8μs 56.8μs

55.3μs 60.2μs 52.6μs 57.1μs

Instruction Condition

S(P).SFCSCOMR At END processing (read 1 comment)

• Transition condition for serial transition

• Transition condition after

S(P).SFCTCOMR

At END processing (read 1 comment)

selection branching

• Transition condition after parallel coupling

Number of parallel couplings: 2

Number of parallel couplings: 32

Universal model QCPU

Q03UD(E)CPU

SRAM card Flash card

3.7ms 5.3ms 3.3ms 5.0ms

3.2ms 4.9ms 2.9ms 4.4ms

4.0ms 5.7ms 3.6ms 5.1ms

18.7ms 21.0ms 13.8ms 14.0ms

Universal model QCPU

Q03UDVCPU

Standard RAM Standard RAM

0.26ms 0.25ms

0.66ms 0.44ms

0.66ms 0.35ms

0.87ms 0.55ms

1.28ms 0.75ms

Q04UDVCPU, Q06UDVCPU,

Q13UDVCPU, Q26UDVCPU

Universal model QCPU

Q04UDVCPU, Q06UDVCPU,

Q13UDVCPU, Q26UDVCPU

Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU, Q13UD(E)HCPU, Q20UD(E)HCPU, Q26UD(E)HCPU,

Q50UDEHCPU,

Q100UDEHCPU

SRAM

card

Flash card

3 - 26 3 - 26

3 SPECIFICATIONS

Instruction Condition

S(P).SFCSCOMR

S(P).SFCTCOMR

At instruction execution

Instruction Condition

S(P).SFCSCOMR At END processing (read 1 comment)

• Transition condition for serial transition

• Transition condition after selection branching

• Transition condition after parallel coupling

Number of parallel couplings: 2

Number of parallel couplings: 32

S(P).SFCTCOMR

At END processing (read 1 comment)

1: Processing time for the program shown in the condition (scan time: 15ms).

The processing time varies depending on the number of files in standard ROM and the SFC program (transition conditions and the number of active steps).

LCPU L06CPU, L06CPU-P, L26CPU, L26CPU-P,

L26CPU-BT, L26CPU-PBT

Min. Max.

97.4μs 99.0μs

97.7μs 98.9μs

LCPU L06CPU, L06CPU-P, L26CPU, L26CPU-P,

L26CPU-BT, L26CPU-PBT

Standard ROM

1.5ms

1

3 - 27 3 - 27

3 SPECIFICATIONS

3.4 Calculating the SFC Program Capacity

In order to express the SFC diagram using instructions, the memory capacity shown below is required. The method for calculating the SFC program capacity and the number of steps when the SFC diagram is expressed by SFC dedicated instructions is described in this section.

(1) Method for calculating the SFC program capacity

Number of steps where SFC diagram is expressed by SFC dedicated instructions.

• Step ( 3 sequence steps (+) for step START (STEP

• Transition conditions (+)

1) For serial transition or selective branching coupling

2) For parallel branching

3) For parallel coupling

• Jump ( Calculated as step 0 because it is included in the previous transition condition.

• Operation outputs for each step: The capacity per step is as follows

• Total number of sequence steps for all instructions.

• Transition conditions: The capacity per transition condition is as follows

• Total number of sequence steps for all instructions.

, )

Sn) and END (SEND) instructions.

4 sequence steps for transition START instruction (TRAN destination instruction (TSET Sn).

Total number of steps for the transition START instruction (TRAN transition destination instructions (TSET Sn) for the number of parallel branches in question.

Total number of steps for the transition START instruction (TRAN the transition destination instructions (TSETSn) and coupling check instructions (TAND Sn) for the (number of parallel branchings in question

) , end step ( )

For details regarding the number of sequence steps for each instruction, refer to the Programming Manual (Common Instructions) for the CPU module used.

TRn) and transition

TRn), and

1.

3 - 28 3 - 28

3 SPECIFICATIONS

(2) Number of steps required for expressing the SFC diagram as SFC dedicated instructions

The following table shows the number of steps required for expressing the SFC diagram as SFC dedicated instructions.

Name

SFCP START instruction

SFCP END instruction [SFCPEND] 1

Block START instruction Block END instruction [BEND] 1 Indicates the block END 1 per block

Step START instruction

Transition START instruction

Coupling check instruction

Transition designation instruction

Step END instruction [SEND] 1

Ladder

Expression

[SFCP] 1

[BLOCK BLm] 1 Indicates the block START 1 per block

[STEP

[TRAN

[TAND Si] 2

[TSET Si] 2

Number of

Steps

Si] 2

TRj] 2

Description Required Number of Steps

Indicates the SFC program START Indicates the SFC program END

Indicates the step START (“

” varies according to the step attribute) Indicates the transition START (“ according to the step attribute) “Coupling completed” check occurs at parallel coupling

Designates the transition destination step

Indicates the step / transition END

” varies

1 per program

1 per step

1 per transition condition

“[Number of parallel couplings] - [1]” per parallel coupling For serial transitions and selection transitions, 1 per transition condition; for parallel branching transitions, the number of steps is the same as the number of parallel couplings

1 per step

3 - 29 3 - 29

3 SPECIFICATIONS

MEMO

3 - 30 3 - 30

4 SFC PROGRAM CONFIGURATION

4. SFC PROGRAM CONFIGURATION

This chapter explains the SFC program symbols, SFC control instructions and SFC information devices that comprise an SFC program. When applying the program examples introduced in this manual to an actual system, ensure the applicability and confirm that it will not cause system control problems.

(1) As shown below, an SFC program consists of an initial step, transition conditions, intermediate

steps, and an END step. The data beginning from the initial step and ending at the END step is referred to as a block.

Step 0(S0)

Transition condition 0(t0)

Step 1(S1)

Transition condition 1(t1)

Step 2(S2)

Initial step

Transition condition

Step

Transition condition

Step

Block

4

End step

(2) An SFC program starts at an initial step, executes a step following a transition condition in due

order every time that transition condition is satisfied, and ends a series of operations at an end step.

(a) When the SFC program is started, the initial step is executed first.

While the initial step is being executed, whether the transition condition following the initial step (transition condition 0 (t0) in the figure) has been satisfied or not is checked.

(b) Only the initial step is executed until transition condition 0 (t0) is satisfied.

When transition condition 0 (t0) is satisfied, the execution of the initial step is stopped, and the step following the initial step (step 1 (S1) in the figure) is executed. While step 1 (S1) is being executed, whether the transition condition following step 1 (transition condition 1 (t1) in the figure) has been satisfied or not is checked.

(c) When transition condition 1 (t1) is satisfied, the execution of step 1 (S1) is stopped, and the

next step (step 2 (S2) in the figure) is executed.

(d) Every time the transition condition is satisfied in order, the next step is executed, and the

block ends when the end step is executed.

4 - 1 4 - 1

4 SFC PROGRAM CONFIGURATION

4.1 List of SFC Diagram Symbols

4

Class Name

Step

The symbols used in the SFC program are listed below.

SFC Diagram

Symbol Initial step Dummy initial step 0 Coil HOLD initial step Operation HOLD step (without

transition check) initial step Operation HOLD step (with transition check) initial step Reset initial step Initial step Dummy initial step i Coil HOLD initial step Operation HOLD step (without transition check) initial step Operation HOLD step (with transition check) initial step Reset initial step Step Dummy step i Coil HOLD step Operation HOLD step (without transition check) Operation HOLD step (with transition check) Reset step Block START step (with END check) Block START step (without END check)

End step

When step No. is “0”

When initial step No. is other than “0”

Steps other than “initial” step

0

SC

0

SE

0

ST

0

R

0 Sn i

SC

i

SE

i

ST

R

i Sn i

SC

i

SE

i

ST

i

R

i Sn

i BLm

Remarks

Any of these steps in 1 block *: Initial step at top left (column 1) of

SFC diagram is fixed to No. 0.

n = reset destination step No.

Up to 31 steps in 1 block. i = step No. (1 to 511) n = reset destination step No.

i

Up to 512 steps in 1 block, including initial step (128 steps for Basic model QCPU) i = step No. (1 to 511) n = reset destination step No. m = movement destination block No.

More than one step can be used in 1 block.

4 - 2 4 - 2

j

4 SFC PROGRAM CONFIGURATION

Class Name SFC Diagram Symbol Remarks

Transition

Serial transition

Selection branching

Selection coupling

Selection coupling - parallel branching

Parallel branching

Parallel coupling

Parallel coupling - parallel branching

a

a b n

a b

a

a, b = Transition condition No.

Parallel coupling - selection branching

a b

Selection branching - parallel branching

Parallel coupling - selection coupling

Selection branching - parallel branching

a b

a

a b

b

Parallel coupling - selection coupling

a

b

Jump transition

a

j

a = Transition condition No. j = jump destination step No.

4 - 3 4 - 3

4 SFC PROGRAM CONFIGURATION

Class Name SFC Diagram Symbol Remarks

Transition

End step transition

Selection coupling - Jump

Selection coupling - Selection branching Jump

Selection coupling - Selection coupling Jump

Selection branching - Jump

Selection coupling - Jump

a

j

ab

j

ab

j

ab

j+1 j+2

ab

j

j+1 j+2

j

a, b = Transition condition No. j = jump destination step No.

4 - 4 4 - 4

4 SFC PROGRAM CONFIGURATION

4.2 Steps

Steps are the basic units for comprising a block, and each step consists of operation outputs.

(1) The following table indicates the number of steps that can be used in one block.

CPU module type

Basic model QCPU 128 steps 1024 steps

High Performance model QCPU

Redundant CPU

Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU

Q03UDCPU, Q03UDVCPU, Q03UDECPU, Q04UDHCPU, Q04UDVCPU, Q04UDEHCPU,

Universal model QCPU

LCPU

QnACPU 512 steps 8192 steps

Q06UDHCPU, Q06UDVCPU, Q06UDEHCPU, Q10UDHCPU, Q10UDEHCPU, Q13UDHCPU, Q13UDVCPU, Q13UDEHCPU, Q20UDHCPU, Q20UDEHCPU, Q26UDHCPU, Q26UDVCPU, Q26UDEHCPU, Q50UDEHCPU, Q100UDEHCPU

L02SCPU, L02SCPU-P, L02CPU, L02CPU-P

L06CPU, L06CPU-P, L26CPU, L26CPU-P, L26CPU-BT, L26CPU-PBT

*1: For the Universal model QCPU whose serial number (first five digits) is "12051" or

earlier, the maximum number of steps for all blocks is 8192.

*2: For the modules whose serial number (first five digits) is "15101" or earlier, the

maximum number of steps is 8192 for all blocks.

(2) Serial step numbers are assigned to the steps in creation order at the time of SFC program

creation. The user can specify the step numbers to change them within the range of the maximum number of steps in one block. The step numbers are used for monitoring the executed step and for making a forced start or end with the SFC control instruction.

Maximum number of

steps in one block

512 steps 8192 steps Process CPU

128 steps 1024 steps

512 steps 16384 steps *1

128 steps 1024 steps

512 steps 16384 steps *2

Maximum number of

steps for all blocks

4 - 5 4 - 5

T

4 SFC PROGRAM CONFIGURATION

4.2.1 Step (without step attribute)

During processing of steps without attributes, the next transition condition is constantly monitored, with transition to the next step occurring when the condition is satisfied.

(1) The operation output status of each step (n) varies after a transition to the next step (n + 1),

depending on the instruction used. (a) When the OUT instruction is used (excluding OUT C

When a transition to the next step occurs and the corresponding step becomes inactive, the output turned ON by the OUT instruction turns OFF automatically. The timer also turns OFF its coil and contact and also clears its present value.

Example:

Step “n”

Transition condition “n”

Step “n+1”

X1

Y0

(b) When the SET, basic or application instruction is used

If a transition to the next step occurs and the corresponding step becomes inactive, the device remains ON or the data stored in the device is held. To turn OFF the ON device or clear the data stored in the device, use the RST instruction, etc. at another step.

Example:

Step “n”

Transition condition “n”

Step “n+1”

X2

SET Y0

)

When transition condition “n” becomes satisfied at the step “n” operation output where Y0 is ON (in accordance with the OUT instruction), Y0 is automatically switched OFF.

When transition condition “n” becomes satisfied at the step “n” operation output where Y0 is ON (by SET instruction), the Y0 ON status will be maintained even after the transition to step “n + 1”.

(c) When the OUT C instruction is used:

1) If the execution conditions for the counter at step “n” are already ON when transition

Example:

Step “n-1”

ransition

condition “n”

Step “n”

condition "n" is satisfied, the counter's count will increase by 1 when step “n” becomes active.

If X10 at step n is already ON while step (n-1) is active, counter C0 counts once when execution proceeds to step n after transition condition n is

X10

K10

satisfied.

C0

2) When a transition to the next step occurs before the reset instruction of the counter is executed, the present value of the counter and the ON/OFF status of the contact are held if the corresponding step becomes inactive.

Example:

Step “n”

ransition

condition “n”

Step “n+1”

To reset the counter, use the RST instruction, etc. at another step.

When the counter (C0) is reset at step “n+1” (or subsequent step), the present value will be cleared,

C0

X10

K10

and the contact will be switched OFF.

SM400

RST C0

4 - 6 4 - 6

4 SFC PROGRAM CONFIGURATION

(2) The PLS or

P instruction used for the operation output of any step is executed every time the corresponding step turns from an inactive to an active status if the execution condition contact is always ON.

Execution condition contact

Example:

Step “n+1”

Always ON

PLS Y0Step “n”

The ladder shown above is actually executed as shown below. Because the step conditions contact is ON when the step is active and OFF when the step is inactive, the PLS or

P instruction will be executed when the step becomes active, even though the execution condition contact is always ON.

Step conditions contact

Always ON

PLS Y0

When active: ON

When inactive: OFF

4 - 7 4 - 7

4 SFC PROGRAM CONFIGURATION

4.2.2 Initial step

The initial step represents the beginning of a block. Up to 32 initial steps per block can be designated. When there are more than one initial step, the coupling enabled is only a selective coupling. Execute the initial steps in the same way as executing the steps other than the initial step.

(1) Active steps at block START

When the block that has more than one initial step is started, the active steps change depending on the starting method as described below.

• When the block START step makes a start using ( m)

• When a start is made using the block START instruction

(SET BLm) of the SFC control instructions

• When a forced start is made using the block START/END

bit of the SFC information devices

• When any of the initial steps is specified using the step

control instruction (SET BLm\Sn, SET Sn) of the SFC control instructions

(2) Transition processing performed when multiple initial steps become active

S0

t0

S4

S1

t1

S5

m,

S2

t2

S6

S3

t3

S7

All initial steps become active.

Only the specified step becomes active.

t4

S8

t5

t6

t7

If steps are selectively coupled in the block that has more than one active initial steps, the step immediately after the coupling becomes active if any of the transition conditions immediately before the coupling is satisfied. In the above program example, step 8 (S8) becomes active when any of transition conditions t4 to t7 is satisfied. When, after the step immediately after the coupling (S8 in the above program example) becomes active, another transition condition immediately before the coupling (any of t4 to t7 in the above program example) is satisfied, reactivation processing is performed as a follow-up function. The processing, which will be performed when another transition condition is satisfied with the step immediately after coupling being active, can be selected between STOP, WAIT and TRANSFER in the "Operation mode at transition to active step (double step START)" (refer to Section 4.7.6) in the block parameter setting of the SFC setting dialog box in the Tools menu. For the Basic model QCPU, Universal model QCPU, and LCPU, the operation mode cannot be selected. It operates in the default "TRANSFER" mode.

(3) The operation of the initial steps with step attributes is the same as that of the other steps.

Refer to Section 4.2.4 to Section 4.2.7.

4 - 8 4 - 8

4 SFC PROGRAM CONFIGURATION

4.2.3 Dummy step

A dummy step is a waiting step, etc., which contains no operation output program.

(1) The transition condition following the corresponding step is always checked during execution

of a dummy step, and execution proceeds to the next step when the transition condition is satisfied.

(2) The dummy step changes to a step (without step attribute, indication:

output program is created.

X1

(ON)

Y10

SC

When X1 turns ON, Y10 turns ON.

4.2.4 Coil HOLD step

A coil HOLD step is a step where the coil output status is maintained in the transition to the next step. (The coil output is switched ON by the OUT instruction when the transition condition is satisfied.)

(1) During normal SFC program operation, the coil ON status (switched ON by OUT instruction

when transition condition is satisfied) is automatically switched OFF before proceeding to the next step. By designating an operation output step as a “coil HOLD step”, the coil ON status will remain in effect when proceeding to the next step.

[When designated as a coil HOLD step]

1) When step n is executed

n

SC

n+1

Y10

(ON)

) when an operation

[When not designated as a coil HOLD step]

1) When step n is executed

X1

n

(ON)

Y10

n+1

When X1 turns ON, Y10 turns ON.

Y10

(ON)

2) When a transition to step (n+1) occurs

X1

n

SC

(ON)

Y10

n+1

(ON)

Remains ON if transition to step (n+1) occurs.

Y10

(ON)

• At a designated coil HOLD step, “Y10” (switched ON by OUT instruction) will remain ON even when the transition condition is satisfied.

2) When a transition to step (n+1) occurs

X1

n

(ON)

Y10

n+1

(OFF)

Y10 turns OFF when transition to step (n+1) occurs.

Y10

(OFF)

• At steps not designated as coil HOLD steps, “Y10” (switched ON by OUT instruction) is automatically switched OFF when the transition condition is satisfied.

4 - 9 4 - 9

F

4 SFC PROGRAM CONFIGURATION

(2) No ladder processing occurs following a transition to the next step. Therefore, the coil output

status will remain unchanged even if the input conditions are changed.

SC

n

n+1

X1

(ON)

Y10

(ON)

Y10

(ON)

SC

X1:OFF

n+1

X1

n

(OFF)

Y10

(ON)

Since processing of step n is not performed, Y10 remains ON if X1 turns OF

Y10

(ON)

(3) When a coil ON status (at coil HOLD step) has been maintained to the next step, the coil will

be switched OFF at any of the following times: (a) When the end step of the corresponding block is executed. (Except when SM327 is ON) (b) When an SFC control instruction (RST, BLm) designates a forced END at the block in

question.

(c) When an SFC control instruction (RST, BLm\Sn, RST Sn) designates a reset at the block in

question.

(d) When a reset occurs at the device designated as the SFC information register's block

START/END device. (e) When a reset step for resetting the step in question becomes active. (f) When the SFC START/STOP command (SM321) is switched OFF. (g) When the coil in question is reset by the program. (h) When the STOP instruction is executed with the stop-time output mode OFF. (i) When S999 is designated at the reset step in the corresponding block.

(4) Block STOP processing

Make a block STOP using the STOP/RESTART bit of the SFC information devices or the block STOP instruction of the SFC control instructions. The processing of the active step in the block where a block STOP was made is as described below. (a) When the "block STOP-time operation output flag (SM325)" is OFF (coil output OFF)

• The step becomes inactive when the processing of the corresponding block is performed first after a block STOP request.

• All coil outputs turn OFF. However, the coils turned ON by the SET instruction remain ON.

(b) When the "block STOP-time operation output flag (SM325)" is ON (coil output held)

The coil outputs remain ON during a block STOP and after a block RESTART.

4 - 10 4 - 10

4 SFC PROGRAM CONFIGURATION

(5) Precautions when designating coil HOLD steps

(a) PLS instruction

When the execution condition of the PLS instruction is satisfied and the transition condition is satisfied at the same scan where the PLS instruction was executed, the device turned ON by the PLS instruction remains ON until the OFF condition in above (3) is satisfied.

(b) PLF instruction

When the execution condition of the PLF instruction is satisfied and the transition condition is satisfied at the same scan where the PLF instruction was executed, the device turned ON by the PLF instruction remains ON until the OFF condition in above (3) is satisfied.

(c) Counter

If the count input condition turns ON/OFF after a transition to the next step, the counter does not start counting.

(d) Timer

When a step transition occurs after the transition condition is satisfied with the coil of the timer ON, the timer stops timing and holds the then present value.

4 - 11 4 - 11

4 SFC PROGRAM CONFIGURATION

4.2.5 Operation HOLD step (without transition check)

An operation HOLD step (without transition check) is a step where the operation output processing of the corresponding step continues after a transition to the next step. However, transition processing to the next step is not executed if the transition condition is satisfied again at the corresponding step.

(1) During normal SFC program operation, the coil ON status (switched ON by OUT instruction

when transition condition is satisfied) is automatically switched OFF before proceeding to the next step. When an operation output step is designated as an operation HOLD step (without transition check), the corresponding step will remain active after a transition to the next step, and operation output processing will continue. Therefore, when the input condition changes, the coil status also changes.

[When transition from step n to step (n+1) occurs with Y10 ON]

[When X1 turns OFF after transition to step (n+1)]

SE

Transition

SE

n

n+1

X1

(ON)

Y10

(ON)

Y10

(ON)

Remains ON after transition to step (n+1).

SE

X1:OFF

X1

n

(OFF)

Y10

n+1

(OFF)

When X1 turns OFF, Y10 also turns OFF since processing is being performed after transition to step (n+1).

Y10

(OFF)

(2) The transition conditions have been satisfied, so no transition condition check is performed

after the next step becomes active. Therefore, no step transition (subsequent transition) will occur even if the transition conditions for the relevant step are satisfied again.

SE

No subsequent transition

Step activated by transition condition being satisfied

(3) An operation HOLD step (without transition check) becomes inactive when any of the following

occur: (a) When the END step of the block in question is executed. (b) When an SFC control instruction (RST BLm) designates a forced END at the block in

question.

(c) When the corresponding step is reset by the SFC control instruction (RST BLm\Sn, RST

Sn). (Except when SM327 is ON)

(d) When the device designated as the block START/END device of the SFC information

devices is reset. (e) When a reset step for resetting the step in question becomes active. (f) When "S999" is designated at the reset step in the same block. (g) When the SFC START/STOP command (SM321) is switched OFF.

4 - 12 4 - 12

4 SFC PROGRAM CONFIGURATION

(4) Block STOP processing

The following processing is performed when a block STOP request is issued to the corresponding block using the STOP/RESTART bit of the SFC information devices or the block STOP instruction of the SFC control instructions.

• STOP status timing

A STOP status is established after the block STOP request output occurs, and processing returns to the beginning of the block in question.

• Coil output

A coil output OFF or HOLD status will be established, depending on the output mode setting (see Section 4.7.3) at the time of the block STOP designated in the SFC operation mode. However, an ON status will be maintained for coil outputs which were switched ON by the SET instruction.

POINTS

(1) When the transition condition immediately before the corresponding step is satisfied or

when the step is reactivated by a JUMP transition, a transition will occur again when the transition condition is satisfied.

(2) Double STARTs do not apply to reactivated steps.

4 - 13 4 - 13

4 SFC PROGRAM CONFIGURATION

4.2.6 Operation HOLD step (with transition check)

An operation HOLD step (with transition check) is a step where the operation output processing of the corresponding step continues after a transition to the next step. When the transition condition is satisfied again at the corresponding step, transition processing to the next step (reactivation) is executed.

(1) During normal SFC program operation, the coil ON status (switched ON by OUT instruction

when transition condition is satisfied) is automatically switched OFF before proceeding to the next step. When an operation output step is designated as an operation HOLD step (with transition check), the corresponding step will remain active after a transition to the next step, and operation output processing will continue. Therefore, when the input condition changes, the coil status also changes.

[When transition from step n to step (n+1) occurs with Y10 ON]

ST

[When X1 turns OFF after transition to step (n+1)]

X1

n

Transition

ST

n+1

(ON)

Y10

(ON)

Y10

(ON)

Remains ON after transition to step (n+1).

X1:OFF

ST

X1

n

(OFF)

Y10

n+1

(OFF)

When X1 turns OFF, Y10 also turns OFF since processing is being performed after transition to step (n+1).

Y10

(OFF)

(2) The transition condition will be checked after the transition condition is satisfied and the next

step is activated. Hence, when the transition condition of the corresponding step is satisfied again, a transition to the next step (subsequent transition) occurs to activate it. At this time, the current step remains active.

4 - 14 4 - 14

4 SFC PROGRAM CONFIGURATION

POINTS

(1) Convert the transition conditions into pulses.

If they are not pulsed, transition processing to the next step is performed every scan while the condition is satisfied.

(2) When a double START occurs as the transition condition was satisfied with the transition

destination step being active, the processing changes depending on the parameter setting. The Basic model QCPU does not allow the parameters to be selected. It operates in the default "Transfer" mode. Refer to Section 4.7.6 for the parameter setting and the processing performed for each setting.

(3) The difference between the operation HOLD step (with transition check) and the operation

HOLD step (without transition check) is whether the next step will be activated or not as a follow-up when the transition condition is satisfied again.

(3) An operation HOLD step (with transition check) becomes inactive when any of the following

occur: (a) When the end step of the corresponding block is executed. (b) When an SFC control instruction (RST BLm) designates a forced END at the block in

question. (c) When an SFC control instruction (RST BLm\Sn, RST Sn) designates a reset at the block in

question. (d) When a reset occurs at the device designated as the SFC information register's block

START/END device. (e) When a reset step for resetting the step in question becomes active. (f) When "S999" is designated at the reset step in the same block. (g) When the SFC START/STOP command (SM321) is switched OFF.

(4) Block STOP processing

Make a block STOP using the STOP/RESTART bit of the SFC information devices or the block STOP instruction of the SFC control instructions. The processing of the active step in the block where a block STOP was made is as described below. (a) When the "block STOP-time operation output flag (SM325)" is OFF (coil output OFF)

The step becomes inactive when the processing of the corresponding block is performed

first after a block STOP request.

• All coil outputs turn OFF.

• However, the coils turned ON by the SET instruction remain ON.

(b) When the "block STOP-time operation output flag (SM325)" is ON (coil output held)

The coil outputs remain ON during a block STOP and after a block RESTART.

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4 SFC PROGRAM CONFIGURATION

4.2.7 Reset step R

A reset step is a step which designates a forced deactivation of another specified step (operation output). The reset step deactivates the designated step in the current block before execution of the operation output every scan. Except the deactivation of the specified step, the reset step execute the operation output with the same functions as a normal step (without step attributes).

RnSn

(1) When deactivating only the designated step

Set the step number to be deactivated to the specified step number Sn.

(2) When deactivating all the held steps

Set "999" to the specified step number Sn. When the number of the specified step is "999", all held steps of the coil HOLD steps, operation HOLD steps (without transition check) and operation HOLD steps (with transition check) in the current block are batch-deactivated.

POINT

(1) Only held steps can be deactivated by the reset step.

The following steps are not the targets of the reset step.

• HOLD steps that are active but not held

• Steps that are not specified as the HOLD steps

(2) For the Basic model QCPU, Universal model QCPU, and LCPU, a step of the CPU itself

cannot be specified as a reset step.

When a reset step is activated, a specified step is deactivated (reset).

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4 SFC PROGRAM CONFIGURATION

4.2.8 Block START step (with END check)

A block START step (with END check) is the step where the specified block is started, and when the START destination block is then deactivated, the check of the transition condition to the next step is started.

(1) The operation of the block START step (with END check) is described below.

(a) When activated, the block START step (with END check) starts the specified block. (b) No processing is performed until the START destination block is deactivated after its

execution has ended. (c) When the START destination block is deactivated after its execution has ended, only the

transition condition check is performed. (d) When the transition condition is satisfied, a transition to the next step occurs.

Block m

m

(2) A simultaneous start cannot be made for a single block.

The block that has already started cannot be started, either. If either of the above starts is made, the following processing is performed depending on the setting of the operation mode at block double START. *1 (Refer to Section 4.7.5 for details of the operation at block double START.) (a) When the setting of the operation mode at block double START is "STOP"

A "BLOCK EXE. ERROR" (error code: 4620) occurs and the CPU module stops

processing. (b) When the setting of the operation mode at block double START is the default setting of

"WAIT"

(3) A block START request can start multiple blocks simultaneously by performing a parallel

Processing is not performed and waits until the START destination block ends its execution.

*1: For the following CPU modules, the operation mode at double block START cannot be set.

The operation mode at double block START is limited to the "WAIT" mode.

• Basic model QCPU

• Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU

• Universal model QCPU whose serial number (first five digits) is "12051" or earlier

• L02(S)CPU, L02(S)CPU-P

• LCPU whose serial number (first five digits) is "15101" or earlier

transition (refer to Section 4.3.3). The steps in the simultaneously started blocks are processed in parallel.

4 - 17 4 - 17

4 SFC PROGRAM CONFIGURATION

(4) The following table indicates the number of steps that can be executed simultaneously in all

blocks and the maximum number of active steps in a single block.

CPU module type

Basic mode QCPU 1024 steps 128 steps

High Performance model QCPU

Redundant CPU

Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU

Q03UDCPU, Q03UDVCPU, Q03UDECPU, Q04UDHCPU,

Q04UDVCPU, Q04UDEHCPU, Universal model QCPU

LCPU

QnACPU

Q06UDHCPU, Q06UDVCPU,

Q06UDEHCPU, Q10UDHCPU,

Q10UDEHCPU, Q13UDHCPU,

Q13UDVCPU, Q13UDEHCPU,

Q20UDHCPU, Q20UDEHCPU,

Q26UDHCPU, Q26UDVCPU,

Q26UDEHCPU, Q50UDEHCPU,

Q100UDEHCPU

L02SCPU, L02SCPU-P,

L02CPU, L02CPU-P

L06CPU, L06CPU-P, L26CPU,

L26CPU-P, L26CPU-BT,

L26CPU-PBT

POINTS

(1) The block START step (with END check) cannot be described immediately before the

coupling of a parallel coupling. (The block START step (with END check) cannot be used for a wait.) The block START step (without END check) can be described immediately before the coupling of a parallel coupling.

(2) The execution status of each block can be checked at another block using the block

START/END bit (refer to Section 4.5.1) of the SFC information devices or the block activation check instruction (refer to Section 4.4.3) of the SFC control instructions.

Number of steps that

can be executed

simultaneously in all

blocks

1280 steps 256 steps Process CPU

1024 steps 128 steps

1280 steps 256 steps

1024 steps 128 steps

1280 steps 256 steps

Maximum number of

active steps in one

block

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4 SFC PROGRAM CONFIGURATION

4.2.9 Block START step (without END check)

A block START step (without END check) is the step where the specified block is started, and if the START destination block is active, the check of the transition condition to the next step is performed.

(1) The operation of the block START step (without END check) is described below.

(a) When activated, the block START step (without END check) starts the specified block. (b) After starting the specified block, the step performs only the check of the transition

condition.

(c) When the transition condition is satisfied, execution proceeds to the next step without

waiting for the START destination block to end.

Block m

m

X0

TRAN

(When transition condition is satisfied)

(2) A simultaneous start cannot be made for a single block.

The block that has already started cannot be started, either. If either of the above starts is made, the following processing is performed depending on the setting of the operation mode at block double START. *1 (Refer to Section 4.7.5 for details of the operation at block double START.) (a) When the setting of the operation mode at block double START is "STOP"

A "BLOCK EXE. ERROR" (error code: 4620) occurs and the CPU module stops processing.

(b) When the setting of the operation mode at block double START is the default setting of

"WAIT" Processing is not performed and waits until the START destination block ends its execution.

*1: For the following CPU modules, the operation mode at double block START cannot be set.

The operation mode at double block START is limited to the "WAIT" mode.

• Basic model QCPU

• Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCP

• Universal model QCPU whose serial number (first five digits) is "12051" or earlier

• L02(S)CPU, L02(S)CPU-P

• LCPU whose serial number (first five digits) is "15101" or earlier

(3) A block START request can start multiple blocks simultaneously by performing a parallel

transition (refer to Section 4.3.3). The steps in the simultaneously started blocks are processed in parallel.

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4 SFC PROGRAM CONFIGURATION

(4) The number of steps that can be executed simultaneously is a total of up to 1280 steps*2 for

all blocks. The number of steps that can be executed simultaneously in a single block is a maximum of 256 steps*3 including those of the HOLD steps. *2: Up to 1024 steps for the following CPU modules:

• Basic model QCPU

• Universal model QCPU (Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU)

• LCPU (L02SCPU, L02SCPU-P, L02CPU, L02CPU-P)

*3: Up to 128 steps for the following CPU modules:

• Basic model QCPU

• Universal model QCPU (Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU)

• LCPU (L02SCPU, L02SCPU-P, L02CPU, L02CPU-P)

POINTS

The execution status of each block can be checked at another block using the block START/END bit (refer to Section 4.5.1) or the block activation check instruction (refer to Section 4.4.3) of the SFC control instructions.

4 - 20 4 - 20

W

4 SFC PROGRAM CONFIGURATION

4.2.10 End step

An end step indicates that a series of processings in the corresponding block is all ended.

(1) When the end step is reached, the following processing is performed to end the block.

(a) All steps in the block are deactivated.

(The held step are also deactivated.)

(b) The coil outputs turned ON by the OUT instruction are all turned OFF.

When the special relay for output mode at end step execution (SM327) is ON, however, the

(2) When the special relay for clear processing mode at arrival at end step (SM328) is turned ON,

hen there is normal active step left

coil outputs of the held steps all remain ON.

POINTS

(1) SM327 is valid only when the end step is reached.

When a forced end is made by the block END instruction, etc., the coil outputs of all steps are turned OFF.

(2) SM327 is valid for only the HOLD steps being held.

The outputs of the HOLD steps that are not held as the transition conditions are not satisfied are all turned OFF.

the execution of the active step other than the one held in the block can be continued when the end step is reached. *1 (The block is not ended if the end step is executed.) However, when there is only the held step left in the block at arrival at the end step, the held step is deactivated and the block ends if SM328 is ON.

When there is HOLD step, whose transition condition is not satisfied (which is not held), left

When there is held active step left

Transition

When SM328 is turned ON, processing of active step is continued.

SE

Transition

When SM328 is turned ON, processing of HOLD step is continued.

Block is ended independently of whether SM328 is ON or OFF.

SE

Transition

REMARKS

*1: For the Basic model QCPU, Universal model QCPU, and LCPU, SM328 can be used to

4 - 21 4 - 21

continue execution of active steps other than the one held in the block.

4 SFC PROGRAM CONFIGURATION

POINTS

The following gives the precautions to be taken when SM328 is turned ON (1) When there is only the held step left at arrival at the end step, that held step is deactivated

if SM328 is ON. When the user does not want to turn OFF the coil output of the held step suddenly, it can be prevented by turning ON SM327.

(2) If a block is started at the block START step when SM328 is ON, execution returns to the

source as soon as there are no non-held active steps in the block.

(3) Do not describe an always satisfied transition condition immediately after the operation

HOLD step (with transition check).

Block n

Step n

3)

Step (n+1)

1)

Block m

ST

Step m

Step (m+1)

2)

SM400

M0

Tran n

1) Since the transition condition is always satisfied, step (m+1) remains an active step (non-held active status).

) If M0 turns ON and the transition

condition is satisfied, block m cannot be ended.

) Since block m is not ended, execution

cannot proceed to step (n+1).

(a) When the transition condition immediately after the operation HOLD step (with transition

check) is always satisfied, the next step is kept in a "non-held active status". Therefore, the block cannot be ended when SM328 is ON. Further, if this block has been started at the block START step (with END check), processing cannot be returned to the START source step.

(b) When it is desired to describe an always satisfied transition condition immediately after

the operation HOLD step (with transition check), make provision so that the block can be forcibly ended from outside.

(3) After end step execution, a restart is performed as described below.

Block No. Restarting Method

START condition of block 0 is set to "Auto START ON" in the SFC setting of the PLC

Block 0

All blocks other than block 0

parameter dialog box START condition of block 0 is set to "Auto START OFF" in the SFC setting of the PLC parameter dialog box

• Execution automatically returns to the initial step again, and processing is executed repeatedly.

• A restart is made when any of the following is executed.

1) When another START request is received from another block

(when the block START step is activated)

2) When the block START instruction of the SFC control

instructions is executed

3) When the block START/END bit of the block information

devices is forcibly turned ON

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4 SFC PROGRAM CONFIGURATION

4.2.11 Instructions that cannot be used with operation outputs

Table 4.1 indicates the instructions that cannot be used with operation outputs.

Table 4.1 Unusable Instruction List

Class Instruction Symbol Symbol Function Remarks

Master control

End

Program branch

Program control

Structuring

Debugging troubleshooting

SFC dedicated instruction

*1: The Basic model QCPU, Universal model QCPU, and LCPU do not support the instruction.

MC MC N No.1_D

MCR MCR N

FEND FEND

END END

CJ CJ P

SCJ SCJ P

JMP JMP P

GOEND GOEND

IRET IRET

BREAK BREAK

RET RET

CHKST *1 CHKST

CHK *1 CHK

CHKCIR *1 CHKCIR

CHKEND *1 CHKEND

SFCP SFCP

SFCPEND SFCPEND

BLOCK BLOCK

BEND BEND STEP? STEP?

? = N, D, SC, SE, ST, R, C, G, I, ID, ISC, ISE, IST, IR TRAN? TRAN? ? = L, O, OA, OC, OCA, A, C, CA, CO, COC

TAND TAND

TSET TSET

SEND SEND

S

D

P

S

Master control set

Master control reset

Main routine program end

Sequence program end

Conditional jump

Delayed jump

Unconditional jump

Jump to END

Return from interrupt program

Repetitive forced end

Return from subroutine

CHK instruction start

Specific format error check

Check pattern change start

Check pattern change end

SFC program start

SFC program end

SFC block start

SFC block end

SFC step start

SFC transition start

SFC coupling check

SFC transition destination designation

SFC step end

Label P cannot be used, either.

Label I cannot be used, either.

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4 SFC PROGRAM CONFIGURATION

4.3 Transition

A transition is the basic unit for comprising a block, and is used by specifying a transition condition. A transition condition is a condition for execution to proceed to the next step, and execution proceeds to the next step when the condition is satisfied.

Type Function Outline

Serial transition • When the transition condition is satisfied, execution proceeds from the current step to

Selection transition (branch/coupling)

Parallel transition (branch/coupling)

Jump transition • When the transition condition is satisfied, execution proceeds to the specified step in

Table 4.2 Transition Condition Type List

the subsequent step.

• A single step branches out into multiple transition conditions.

• Among those multiple transition conditions, execution proceeds to only the step in the line where the transition condition is satisfied first.

• Execution simultaneously proceeds to all multiple steps that branch from a single step.

• When all steps immediately before a coupling are activated, execution proceeds to the next step when the common transition condition is satisfied.

the same block.

4 - 24 4 - 24

)

4 SFC PROGRAM CONFIGURATION

4.3.1 Serial transition

“Serial transition” is the transition format in which processing proceeds to the step immediately below the current step when the transition condition is satisfied.

Step “n” (operation output [A])

Transition condition “b”

Step “n+1” (operation output [B]

(1) A maximum of 512*1 serial transition steps (

Therefore, a maximum of 512* serial transitions (+) can be described. However, there is a restriction on the number of lines as indicated below depending on the SFC display column setting. *1: 128 for the Basic model QCPU, Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU,

L02SCPU, L02SCPU-P, L02CPU, and L02CPU-P.

• When transition condition “b” becomes satisfied at step “n” (operation output [A]) execution, operation output [A] will be deactivated, and processing will proceed to step “n+1” (operation output [B]).

, , ) can be described in each block.

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4 SFC PROGRAM CONFIGURATION

(2) Serial transition operation flowchart

Initial step

Operation status

Transition condition “a”

Step 1

Transition condition “b”

Step 2

Transition condition “c”

Step 3

Transition condition “d”

END step

Initial step operation output executed.

Transition condition “a” satisfied?

YES

Initial step operation output

deactivated.

Step 1 operation output executed.

Transition condition “b” satisfied?

YES

Step 1 operation output deactivated.

Step 2 operation output executed.

1

NO

1

NO

Transition condition “c” satisfied?

YES

Step 2 operation output deactivated.

Step 3 operation output executed.

Transition condition “d” satisfied?

YES

Step 3 operation output deactivated.

END step executed, operation

completed.

1 For steps with attribute designations, processing occurs in accordance with the attributes.

NO

1

NO

1

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”

4 SFC PROGRAM CONFIGURATION

4.3.2 Selection transition

A “selection transition” is the transition format in which several steps are coupled in a parallel manner, with processing occurring only at the step where the transition condition is satisfied first.

Step “n” (operation output [A])

Branch

Transition condition “b”

Step “n+1” (operation output [B])

Transition condition “c”

Step “n+2” (operation output [C])

• From step “n”, processing will proceed to either step “n+1” or step “n+2”, depending on which transition condition (“b” or “c”) is satisfied first.

• If both transition conditions are satisfied simultaneously, the condition to the left will take precedence. Step “n” will then be deactivated.

• Subsequent processing will proceed from step to step in the selected column until another parallel coupling selection occurs.

Coupling

Step “n” (operation output [A])

Transition condition “b”

Step “n+2” (operation output [C])

Step “n+1” (operation output [B])

Transition condition “c”

• When the transition condition (“b” or “c”) at the executed branch is satisfied, the executed step ([A] or [B]) will be deactivated, and processing will proceed to step “n+2”.

(1) Up to 32 steps can be available for selection in the selection transition format.

Step “n”

Step “n+1”

Step “n+2”

Step “n+3”

Max. of 32 steps

Step “n+4”

Step “n+32

(2) When two or more selection step transition conditions are satisfied simultaneously, the left-

most condition will take precedence.

Example: If transition conditions “c”

Step “n”

Transition condition “b”

Step “n+1”

Transition condition “c”

Step “n+2”

Transition condition “d”

Step “n+3”

Transition condition “e”

Step “n+4”

and “d” are satisfied simultaneously, the step “n+2” operation output will be executed.

4 - 27 4 - 27

4 SFC PROGRAM CONFIGURATION

(3) In a selection transition, a coupling can be omitted by a jump transition or end transition.

Step n

Transition condition “b”

Step “n+1”

Step “n+2”

Step “n+3”

Transition condition “d”

n

POINTS

In a selective transition, the number of branches and the number of couplings may be different. However, a selection branch and parallel coupling or a parallel branch and selection coupling cannot be combined.

Transition condition “c”

Step “n+4”

Step “n+5”

When transition condition “b” is satisfied at the step “n” operation output, processing will proceed in order through steps “n+1”, “n+2” and “n+3”. When transition condition “d” is satisfied, processing will jump to step “n”. (For details on “jump transitions”, see Section

4.3.4.)

4 - 28 4 - 28

4 SFC PROGRAM CONFIGURATION

(4) Selection transition operation flowchart

Initial step

Transition condit i on “a”

Step 1

Operation status

Operation output of

initial step 0 is executed.

Transition condit ion “b”

Transition condit i on “e”

Transition condit ion “h”

St ep 2 St ep 4 St ep 6

Transition condit i on “c”

Transition condit i on “f”

St ep 3 St ep 5

Transition condit i on “d”

Transition condit i on “g”

Transition condit ion “i”

Step 7

Transition condit i on “j”

Is transition condition

a satisfied?

YES

Operation output of initial

step 0 is deactivated.

Operation output of initial

step 1 is executed.

Is transition condition

b satisfied?

YES

Operation output of initial step 1 is deactivated.

Operation output of initial step 2 is executed.

Is transition condition

c satisfied?

YES

Operation output of initial

step 2 is deactivated.

NO

Is transition condition

e satisfied?

YES

Operation output of initial step 1 is deactivated.

Operation output of initial step 4 is executed.

NO

Is transition condition

YES

Operation output of initial

step 4 is deactivated.

f satisfied?

NO

Is transition condition

Operation output of initial step 1 is deactivated.

Operation output of initial step 6 is executed.

NO

h satisfied?

YES

Operation output of initial

step 3 is executed.

Is transition condition

d satisfied?

Operation output of initial

step 3 is deactivated.

Operation output of initial

step 7 is executed.

Is transition condition

j satisfied?

YES

Operation output of initial

step 7 is deactivated.

Block is ended since end

step is reached.

Operation output of initial

step 5 is executed.

NO

Is transition condition

YESYES

Operation output of initial

step 5 is deactivated.

NO

g satisfied?

NO

Is transition condition

YES

Operation output of initial

step 6 is deactivated.

i satisfied?

4 - 29 4 - 29

NO

”

4 SFC PROGRAM CONFIGURATION

4.3.3 Parallel transition

“Parallel transition” is the transition format in which several steps linked in parallel are processed simultaneously when the relevant transition condition is satisfied.

Step “n” (operation output [A])

Branch

Coupling

Transition condition “b”

• From step “n”, processing will proceed simultaneously to steps “n+1” and “n+3” when

Step “n+1” (operation output [B])

Transition condition “c” Transition condition “d

Step “n+2” (operation output [C])

Step “n+3” (operation output [D])

Step “n+4” (operation output [E])

transition condition “b” is satisfied.

• Processing will proceed to step “n+4” when transition condition “c” is satisfied, and to step “n+4” when transition condition “d” is satisfied.

Step “n” (operation output [A])

Transition condition “b”

Waiting step

Transition condition “d”

Step “n+2” (operation output [C])

Step “n+1” (operation output [B])

Transition condition “c”

Waiting step

• When transition conditions “b” and “c” are satisfied at step “n” and step “n+1” execution, steps “n” and “n+1” will be deactivated, and processing will proceed to the waiting steps.

• Waiting steps are used to synchronize parallel processing operations. Parallel processing steps always proceed to a waiting step. When condition “d” is satisfied at the waiting steps, processing will proceed to step “n+2”.

• Waiting steps are dummy steps which require no operation output ladder.

(1) Up to 32 steps can processed simultaneously with the parallel transition format.

Step “n”

Step “n+1”

Step “n+2”

Step “n+3”

Up to 32 steps

Step “n+4”

Step “n+32

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4 SFC PROGRAM CONFIGURATION

(2) If another block is started by the parallel processing operation, the START source block and

START destination block will be executed simultaneously. (In the example below, processing from step “n+1” will be executed simultaneously with block 1.)

Block 0

Step “n”

Transition condition “b”

Step “n+1”

Transition condition

Block 1 START

Transition condition

(3) The following table indicates the number of steps that can be executed simultaneously in all

blocks and the maximum number of active steps in a single block. If the number of simultaneously processed steps exceeds the value in the following table, an error occurs and the CPU module stops processing.

CPU module type

Basic mode QCPU 1024 steps 128 steps

High Performance model QCPU

Redundant CPU

Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU

Q03UDCPU, Q03UDVCPU, Q03UDECPU, Q04UDHCPU, Q04UDVCPU, Q04UDEHCPU,

Universal model QCPU

LCPU

QnACPU

Q06UDHCPU, Q06UDVCPU, Q06UDEHCPU, Q10UDHCPU, Q10UDEHCPU, Q13UDHCPU, Q13UDVCPU, Q13UDEHCPU, Q20UDHCPU, Q20UDEHCPU, Q26UDHCPU, Q26UDVCPU, Q26UDEHCPU, Q50UDEHCPU, Q100UDEHCPU

L02SCPU, L02SCPU-P, L02CPU, L02CPU-P

L06CPU, L06CPU-P, L26CPU, L26CPU-P, L26CPU-BT, L26CPU-PBT

When condition “b” is satisfied at step “n” execution, processing will proceed to step “n+1” and block 1 will be started. Blocks “0” and “1” will then be processed simultaneously.

Number of steps that

are processed

simultaneously

1280 steps 256 steps Process CPU

1024 steps 128 steps

1280 steps 256 steps

1024 steps 128 steps

1280 steps 256 steps

Maximum number of

active steps in one

block

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4 SFC PROGRAM CONFIGURATION

(4) Couplings must be provided when the parallel transition format is used. Program creation is

impossible without couplings. Example: Program without couplings (Cannot be designated)

END step

Each column ends at the END step.

(5) As a rule, a waiting step must be created prior to the coupling.

However, in cases such as the example below where each of the parallel transition columns consist of only 1 step (program without a transition condition between the parallel transition branch and the coupling), a waiting step is not required.

Jump transition (see Section 4.3.4) occurs without coupling

Jump

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4 SFC PROGRAM CONFIGURATION

(6) Parallel transition operation flowchart

Initial step

Transition condition “a”

Step 1

Transition condition “b”

Step 2 Step 3 Step 4

Transition condition “c”

Waiting step

Transition condition “d”

Waiting step

Transition condition “e”

Waiting step

Initial step operation output

Operation status

executed.

Transition condition

“a” satisfied?

YES

deactivated.

NO

1

Transition condition “f”

Step 5

Transition condition “g”

Parallel processing

Step 1 operation output

executed.

Transition condition

“b” satisfied?

Step 1 operation output

deactivated.

Step 2 operation output

executed.

Transition condition

“c” satisfied?

Step 2 operation output

deactivated.

Waiting step executed.

NO

All waiting steps

executed?

YES

NO

1

Step 3 operation output

executed.

NO

Transition condition

“d” satisfied?

1

Step 3 operation output

Waiting step executed. Waiting step executed.

YES

deactivated.

Step 4 operation output

NO

Transition condition

1

Step 4 operation output

executed.

“e” satisfied?

YES

deactivated.

NO

1

YES

Transition condition

“f” satisfied?

YES

Step 5 operation output

executed.

Transition condition

“g” satisfied?

YES

Step 5 operation output

deactivated.

NO

1

END step executed,

operation completed.

1 For steps with attribute designations, processing occurs in accordance with the attributes.

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4 SFC PROGRAM CONFIGURATION

4.3.4 Jump transition

A “jump transition” is a jump to a specified step within the same block which occurs when the transition condition is satisfied.

Step “n” (operation output [A])

Transition condition “b”

m

Step “m” (operation output [B])

(1) There are no restrictions regarding the number of jump transitions within a single block. (2) In the parallel transition format, only jumps in the vertical direction are possible at each of the

branches. Example 1: Jump transition program in vertical direction from branch to coupling

• When condition “b” is satisfied at step “n” execution, step “n” (operation output [A]) is deactivated, and processing proceeds to step “m”.

n

A program of a jump transition to another vertically branched ladder, a jump transition for exiting from a parallel branch, or a jump transition to a parallel branch from outside a parallel branch cannot be created. Example 2: Program for exiting from parallel branch (cannot be designated)

Parallel transition

Jump transition

No parallel coupling

(3) Do not specify a jump transition to the current step when the transition condition is satisfied as

shown below.

n

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4 SFC PROGRAM CONFIGURATION

4.3.5 Precautions when creating sequence programs for operation outputs (steps) and transition conditions

The points to consider when creating operation output (step) and transition condition sequence programs are described below.

(1) Sequence program for operation outputs (steps)

(a) Step sequence program expression format

A step sequence program using the ladder expression format is shown below.

Condition can be omitted only at the first ladder block

Condition

Output instruction

REMARKS

The lack of a sequence program at a given step will not result in an error. In such cases, no processing will occur until the transition condition immediately following the step in question is satisfied.

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t

4 SFC PROGRAM CONFIGURATION

(2) Sequence program for transition condition

(a) Transition condition sequence program expression format

A transition condition sequence program using the ladder expression format is shown below.

Class

Contacts

Coupling

(b) Instructions used

Instructions which can be used in a transition condition sequence program are listed below.

Instruction

Code

LD AND OR

LDI ANI ORI

LDP ANDP ORP

LDF ANDF ORF

ANB ORB

INV

MEP MEF

EGP EGF

Condition

Symbol Function

Operation START (N/O contact) Serial connection (N/O contact) Parallel connection (N/O contact)

Operation START (N/C contact) Serial connection (N/C contact) Parallel connection (N/C contact)

Leading edge pulse operation START Leading edge pulse serial connection Leading edge pulse parallel connection

Trailing edge pulse operation START Trailing edge pulse serial connection Trailing edge pulse parallel connection

V V

Ladder block serial connection Ladder block parallel connection

Operation result inversion

Operation results converted to leading edge pulse (step memory) Operation results converted to trailing edge pulse (step memory)

Operation results converted to leading edge pulse (memory) Operation results converted to trailing edge pulse (memory)

TRAN

[TRAN] is a dummy outpu

Basic model

QCPU

CPU Module Type

High

Performance

Model QCPU,

Process CPU,

Redundant CPU,

QnACPU

Universal

model QCPU,

LCPU

: Usable, : Unusable

4 - 36 4 - 36

4 SFC PROGRAM CONFIGURATION

Class

Comparison operation

Instruction

Code

LD AND OR

LDD ANDD ORD

LDE ANDE ORE

LD$ AND$ OR$

LD AND OR

LDD ANDD ORD

LDE ANDE ORE

LD$ AND$ OR$

Symbol Function

S1 S2

(=, <>, >, >=, <, <=)

S1 S2

(=, <>, >, >=, <, <=)

S1 S2

(=, <>, >, >=, <, <=)

S1 S2

(=, <>, >, >=, <, <=)

BIN16 bit data comparison

BIN32 bit data comparison

Floating decimal point data comparison

Character string data comparison

POINT

• When using the leading edge pulse instructions mentioned below for the execution condition (<a> on the right) of "Tran" instruction on the transition condition, the "Tran" instruction becomes conductive only when the condition of the leading edge pulse instruction turns from OFF to ON after the step ( on the right) that is associated with the transition condition becomes active. As described in the time chart on the right, "Tran" instruction is executed and the active step moves to the next step.

Leading edge pulse instruction: LDP, ANDP, ORP, MEP, and EGP

• When the execution condition (<a> on the right) of "Tran" instruction on the transition condition has been turned ON before the step ( on the right) becomes active, the "Tran" instruction does not become conductive and the active step does not move to the next step.

• When using the leading edge pulse instruction mentioned above for the execution condition (<a> on the right) of "Tran" instruction, specify a device whose condition turns from OFF to ON after the step ( on the right) becomes active.

CPU Module Type

High Performance

Basic model

QCPU

Model QCPU, Process CPU,

Redundant CPU,

QnACPU

: Usable, : Unusable

Step

Transition condition

Step

<a>

Condition

Tran

Active

Inactive

ON

OFF

Execution

Nonexecution

Condition

<a>

Universal

model

QCPU,

LCPU

TRAN

Transition to the next step

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4 SFC PROGRAM CONFIGURATION

4.4 Controlling SFC Programs by Instructions (SFC Control Instructions)

SFC control instructions can be used to check a block or step operation status (active/inactive), or to execute a forced START or END, etc. An normal SFC program can be controlled by SFC control instructions in a sequence program and SFC program. (A program execution management SFC program cannot be controlled by using SFC control instructions.)

Name Ladder Expression Function

Step operation status check instruction 0

Forced transition check instruction

Block operation status check instruction

Active steps batch readout instruction

Block START instruction

Block END instruction Block STOP instruction

Block restart instruction

The types and functions of the SFC control instructions will be explained.

Basic

model

QCPU

LD, AND, OR, LDI, ANI, ORI LD, AND, OR, LDI, ANI, ORI LD, AND, OR, LDI, ANI, ORI

LD, AND, OR,

LDI, ANI, ORI

LD, AND, OR, LDI, ANI, ORI

MOV(P) K4Sn

MOV(P) BLm\K4Sn D

DMOV(P) K8Sn D 1

DMOV(P) BLm\K8Sn D

BMOV(P) K4Sn D Kn 1

BMOV(P) BLm\K4Sn D Kn

SET BLm

RST BLm

PAUSE BLm • A specified block is temporarily stopped.

RSTART BLm

Sn

BLm/Sn

TRn

BLn\TRn

BLm

D

1

• Checks a specified step in a specified block to determine if the step is active or inactive.

• Checks a specified step in a specified block to determine if the transition condition (by transition control instruction) for that step was satisfied forcibly or not.

• Checks a specified block to determine if it is active or inactive.

• Active steps in a specified block are read to a specified device as bit information.

• A specified block is forcibly started (activated) independently and is executed from an initial step.

• A specified block is forcibly ended (deactivated).

• The temporary stop status at a specified block is canceled, with operation resuming from the STOP step.

CPU Module Type

High

Performance Model QCPU, Process CPU,

Redundant

CPU,

QnACPU

: Usable, : Unusable

Universal

model

QCPU,

LCPU

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4 SFC PROGRAM CONFIGURATION

Name Ladder Expression Function

• A specified block is forcibly started

Step START instruction

Step END instruction

Transition control instruction

Block switching instruction

SET Sn

SET BLm\Sn

RST Sn

RST BLm/Sn

SCHG

SET TRn

SET BLm\TRn

RST TRn 1

RST BLm\TRn

BRSET

D

S

1

(activated) independently and is executed from a specified step.

1

• A specified step in a specified block is forcibly ended (deactivated).

• The instruction execution step is

2

deactivated, and a specified step is activated.

1

• A specified transition condition at a specified block is forcibly satisfied.

• The forced transition at a specified transition condition in a specified block is canceled.

• Blocks subject to the “*1” SFC control instruction are designated.

1: In a sequence program, block 0 is the instruction execution target block.

In an SFC program, the current block is the instruction execution target block. The instruction execution target block can be changed with the block switching instruction (BRSET). Note, however, that the following CPU modules cannot use the BRSET instruction.

• Basic model QCPU

• Universal model QCPU whose serial number (first five digits) is "13101" or earlier

• LCPU

2: Can be used at the step of an SFC program.

An error occurs if it is executed in a sequence program other than an SFC program.

3: The Universal model QCPU whose serial number (first five digits) is "13102" or later can

execute this instruction.

CPU Module Type

High

Performance

Basic

model

QCPU

Model QCPU, Process CPU,

Redundant

CPU,

QnACPU

: Usable, : Unusable

Universal

model

QCPU,

LCPU

3

4 - 39 4 - 39

4 SFC PROGRAM CONFIGURATION

POINTS

(1) Either of the following errors occurs if the SFC control instruction is executed from the

sequence program when the special relay for SFC program start/stop (SM321) is OFF.

• Instruction that specifies a block: BLOCK EXE. ERROR (error No.: 4621)

• Instruction that specifies a step: STEP EXE. ERROR (error No.: 4631)

(2) The SFC block (BL) and step relay (S) in the Basic model QCPU, High Performance model

QCPU, Process CPU, Redundant CPU, and Universal model QCPU (except for Highspeed Universal model QCPU) cannot be index-modified.

(3) The SFC block (BL) and step relay (S) in the High-speed Universal model QCPU can be

index-modified within the following range.

• BL0 to BL319 for the SFC block (BL)

• Range that is set in the Device tab of the PLC parameter dialog box for the step relay (S) Note that the range will be S0 to S511 when the step relay (S) in SFC blocks is indexmodified.

(4) Do not use the SFC control instructions in interrupt programs or fixed scan execution type

programs. If used, operation of the SFC program cannot be guaranteed.

(5) The step relay (S) can be used only in the following instructions.

• Step activation check instruction

• Active step batch read instruction

• Step START instruction

• Step END instruction

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4 SFC PROGRAM CONFIGURATION

POINT

Beginning from Section 4.4.1 of this manual, the following table is used in the explanations of the various instructions. The table contents are explained below.

Usable Devices Internal Device (System, User)

Bit Word Bit Word Step

S

D

Register

File

R

Link Direct

J

\

Intelligent

Function

Module

U

\G

Index

Z

Constant

K, H

Expansion

SFC

BLm\Sn

Other

Programs Using Instructions Execution Site

Data

Sequence

Type

Program

BIN16/

BIN32

BIN16/

BIN32

SFC Program

Transition

Condition

Block Step

Transition Condition

4)2) 5)1) 3)

1) Ladder symbols are indicated in this area.

MOV DS

Destination Source Instruction code

Destination ................................... Data destination following the operation.

Source .......................................... Where data is stored prior to the operation.

2) Usable devices are indicated at this area.

• Devices indicated by a circle mark (O) can be used with the instruction in question. The device application classifications are shown below.

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4 SFC PROGRAM CONFIGURATION

Device

Class

Usable

devices

Internal

(System, User)

Bit Word Bit Word

FX, FY, S, SM, X, Y,M, L, F, V,B, T, C, SB

A, VD, SD, T, C, D, W, SW, FD, ST

File

Register

R

R, ZR J

Link Direct

J \

\X J \Y J \B

\SB

J

• When a device name is indicated in the “constant”, “expansion SFC”, or the “other” column, only that device may be used. Example: If “K, H” is indicated in the “constant” column, only a decimal (K) or hexadecimal (H) constant may be used. Real number constants (E) and character string constants ($) may not be used.

3) The data type for the designated device is indicated here.

• Bit .................................. Indicates a bit data operation.

• BIN16 ............................ Indicates 16-bit binary value processing. 1 word used.

• BIN32 ............................ Indicates 16-bit binary value processing. 2 words used.

• Character string ............ Indicates character Variable

string processing. number of words.

• Device Indicates ............ device name and Variable

first device processing. number of words.

4) The type of program which can be used with the instruction in question is indicated here.

5) The request destination for the instruction in question is indicated here.

J

\W

J \SW

Intelligent

Function

Module

\G

U

U \G Z BLm\Sn

Index Z Expansion

SFC

BLm\Trm

Constant Other

Decimal hexadecimal real number constant character string constant

P, I, J, U, DX, DY, N, BL, TR, BL\S

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Mitsubishi MELSEC-Q, MELSEC-L, MELSEC-QnA Programming Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

 SAFETY PRECAUTIONS 

 CONDITIONS OF USE FOR THE PRODUCT 

REVISIONS

INTRODUCTION

CONTENTS

ABOUT MANUALS

GENERIC TERMS

1. GENERAL DESCRIPTION

1.1 Description of SFC Program

1.2 SFC (MELSAP3) Features

2. SYSTEM CONFIGURATION

3. SPECIFICATIONS

3.1 Performance Specifications Related to SFC Programs

3.1.1 When the Basic model QCPU is used

3.1.2 When the High Performance model QCPU, Process CPU, Redundant CPU, Universal model CPU, or LCPU is used

3.1.3 Performance specifications of QnACPU

3.2 Device List

3.2.1 Device list of Basic model QCPU

3.2.2 Device list of High Performance model QCPU, Process CPU, and Redundant CPU

3.2.3 Device list of Universal model QCPU

3.2.4 Device list of LCPU

3.2.5 Device list of QnACPU

3.3 Processing Time

3.3.1 Processing time for SFC program

3.3.2 Processing time for S(P).SFCSCOMR instruction and S(P).SFCTCOMR instruction

3.4 Calculating the SFC Program Capacity

4. SFC PROGRAM CONFIGURATION

4.1 List of SFC Diagram Symbols

4.2 Steps

4.2.10 End step

4.2.11 Instructions that cannot be used with operation outputs

4.3 Transition

4.3.1 Serial transition

4.3.2 Selection transition

4.3.3 Parallel transition

4.3.4 Jump transition

4.3.5 Precautions when creating sequence programs for operation outputs (steps) and transition conditions

4.4 Controlling SFC Programs by Instructions (SFC Control Instructions)