Mitsubishi M5M5W816WG-85HI Datasheet

2001.6.11 Ver. 3.1

8388608

-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM

of distribution, and is not 100% tested.

1

(TOP VIEW)

*Don't connect E3 ball to voltage level more than 0V

MITSUBISHI LSIs

M5M5W816WG - 70HI, 85HI

DESCRIPTION

The M5M5W816 is a family of low voltage 8-Mbit static RAMs
organized as 524288-words by 16-bit, fabricated by Mitsubishi's
high-performance 0.18µm CMOS technology.
The M5M5W816 is suitable for memory applications where a
simple interfacing , battery operating and battery backup are the
important design objectives.
M5M5W816WG is packaged in a CSP (chip scale package),
with the outline of 7.5mm x 8.5mm, ball matrix of 6 x 8 (48ball)
and ball pitch of 0.75mm. It gives the best solution for a
compaction of mounting area as well as flexibility of wiring pattern
of printed circuit boards.
Those are summarized in the part name table below.

Version,

Operating

temperature

I-version

-40 ~ +85°C

Part name

M5M5W816WG -70HI

M5M5W816WG -85HI

Power

Supply

2.7 ~ 3.0V

Access time

max.

70ns
85ns

PRELIMINARY

Notice: This is not a final specification.
Some parametric limits are subject to change

FEATURES

- Single 2.7~3.0V power supply

- Small stand-by current: 0.1µA (2V, typ.)

- No clocks, No refresh

- Data retention supply voltage =2.0V

- All inputs and outputs are TTL compatible.

- Easy memory expansion by S1#, S2, BC1#
and BC2#

- Common Data I/O

- Three-state outputs: OR-tie capability

- OE prevents data contention in the I/O bus

- Process technology: 0.18µm CMOS

- Package: 48ball 7.5mm x 8.5mm CSP

Stand-by current

* Typical

1.0

0.5

* Typical parameter indicates the value for the center

(µA @ Vcc=3.0V)

Ratings (max.)

40°C25°C 40°C

4

2

70°C 85°C25°C

40

20

Active

current

Icc1

* ( typ.)

40mA

(10MHz)

10mA

(1MHz)

PIN CONFIGURATION

A

B

C

D

E

F

G

H

Outline : 48F7Q
NC : No Connection

1 2 3 4 5 6

BC1#

DQ16

DQ14

GND

VCC

DQ11

DQ9

A18

OE#

BC2#

DQ15

DQ13

DQ12

DQ10

N.C.

A8

A0

A3

A5

A17

NC or
GND

A14

A12

A9

A1

A4

A6

A7

A16

A15

A13

A10

A2

S1#

DQ2

DQ4

DQ5

DQ7

W#

A11

S2

DQ1

DQ3

VCC

GND

DQ6

DQ8

N.C.

Pin Function

A0 ~ A18

DQ1 ~ DQ16

S1#

S2
W#

OE#
BC1#
BC2#

Vcc

GND

Address input
Data input / output
Chip select input 1
Chip select input 2
Write control input
Output enable input

Lower Byte (DQ1 ~ 8)

Upper Byte (DQ9 ~ 16)

Power supply
Ground supply

MITSUBISHI ELECTRIC

2001.6.11 Ver. 3.1

8388608

-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM

CLOCK

GENERATOR

S2

BC1#BC2#W#OE#

-

S1

#

S2

S1

#

Non selection

Non selection

MITSUBISHI LSIs

M5M5W816WG - 70HI, 85HI

FUNCTION

The M5M5W816WG is organized as 524288-words by 16-bit.
These devices operate on a single +2.7~3.0V power supply,
and are directly TTL compatible to both input and output. Its
fully static circuit needs no clocks and no refresh, and
makes it useful.
The operation mode are determined by a combination of
the device control inputs BC1# , BC2# , S1#, S2 , W# and
OE#. Each mode is summarized in the function table.
A write operation is executed whenever the low level W#
overlaps with the low level BC1# and/or BC2# and the low
level S1# and the high level S2. The address(A0~A18) must
be set up before the write cycle and must be stable during
the entire cycle.
A read operation is executed by setting W# at a high level
and OE# at a low level while BC1# and/or BC2# and S1# and
S2 are in an active state(S1#=L,S2=H).
When setting BC1# at the high level and other pins are in
an active stage , upper-byte are in a selectable mode in
which both reading and writing are enabled, and lower-byte
are in a non-selectable mode. And when setting BC2# at a
high level and other pins are in an active stage, lower-byte
are in a selectable mode and upper-byte are in a non­selectable mode.

BLOCK DIAGRAM

When setting BC1# and BC2# at a high level or S1# at a high
level or S2 at a low level, the chips are in a non-selectable
mode in which both reading and writing are disabled. In this
mode, the output stage is in a high-impedance state, allowing
OR-tie with other chips and memory expansion by BC1#,
BC2# and S1#, S2.
The power supply current is reduced as low as 0.1µA(25°C,
typical), and the memory data can be held at +2.0V power
supply, enabling battery back-up operation during power
failure or power-down operation in the non-selected mode.

FUNCTION TABLE

BC1#BC2#

L X X

H

L X X

L

H X X

H

X H H X X

X

H XLL H Din

L

H HL H

L

H HL Active

L

H H L L Write Din ActiveX

L

H L H

L

H H L Active

L

H L DinLL X

L

H L DoutHL L

L

H L

L

PRELIMINARY

Notice: This is not a final specification.
Some parametric limits are subject to change

OE#

W#

X X
X X
X X

Mode

Non selection
Non selection

Write
Read

DQ1~8

High-Z
High-Z
High-Z

DQ9~16

High-Z
High-Z
High-Z

High-Z High-Z

High-Z
High-ZDout ActiveL

H H High-Z High-Z

High-Z

Read

H

H High-Z

Write
Read

H High-Z

High-Z

Din Active
Dout Active

High-Z ActiveHL

Icc
Standby
Standby

Standby
Standby

Active

ActiveL DoutH High-Z

A0

A1

A17

A18

MEMORY ARRAY

524288 WORDS

x 16 BITS

DQ

1

DQ

8

DQ

9

DQ

16

Vcc

GND

MITSUBISHI ELECTRIC

2

2001.6.11 Ver. 3.1

8388608

-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM

3

10

f= 10MHz

0 ~ Vcc

f= 10MHz

Other inputs= 0 ~ Vcc

Typ

<=<=>

<

=

10

(1)

>=other inputs = 0 ~ Vcc

(2)

other inputs = 0 ~ Vcc

<=>

=

(3)

>=other inputs = 0 ~ Vcc

>

=<=

MITSUBISHI LSIs

M5M5W816WG - 70HI, 85HI

PRELIMINARY

Notice: This is not a final specification.
Some parametric limits are subject to change

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Units

V

cc

VI
VO
Pd

Ta

Tstg

Supply voltage

Input voltage

Output voltage

Power dissipation

Operating
temperature

Storage temperature

Conditions
With respect to GND
With respect to GND
With respect to GND

25°C

Ta=

Ratings

-0.3* ~ +4.6

-0.3* ~ Vcc + 0.3 (max. 4.6V)

700

- 40 ~ +85

- 65 ~ +150

* -3.0V in case of AC (Pulse width 30ns)

DC ELECTRICAL CHARACTERISTICS

Symbol

VIH
VIL
VOH IOH= -0.5mA
VOL IOL=2mA

II
IO

Icc1

Icc2

Icc3

Icc4

Parameter

High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Input leakage current
Output leakage current

Active supply current
( AC,MOS level )

Active supply current
( AC,TTL level )

Stand by supply current
( AC,MOS level )

Stand by supply current
( AC,TTL level )

VI =0 ~ Vcc

BC1# and BC2# =VIH or S1# =VIH or S2=VIL or OE# =VIH, VI/O=0 ~ Vcc
BC1# and BC2# 0.2V, S1# 0.2V, S2 Vcc-0.2V

other inputs 0.2V or Vcc-0.2V
Output - open (duty 100%)

BC1# and BC2#=VIL , S1#=VIL ,S2=VIH
other pins =V IH or VIL
Output - open (duty 100%)

S1# Vcc - 0.2V,

S2 Vcc - 0.2V,

S2 0.2V,

BC1# and BC2# Vcc - 0.2V

S1# 0.2V, S2 Vcc - 0.2V

BC1# and BC2# =VIH or S1# =VIH or S2=VIL

Conditions

=

2.2

-0.2 *

2.4

f= 1MHz

f= 1MHz

~ +25°C

~ +40°C

~ +70°C

~ +85°C

Limits

MaxTypMin

Vcc+0.2V

0.6

0.4
±1
±1

-

-

5

-

-

0.5

-

-

1.0

-

-

-

-

-

-

4030
10
4030

105

2

4
20
40

2

V

mW

°C
°C

<
=

Units

V

µA

mA

µA

mA

Note 1: Direction for current flowing into IC is indicated as positive (no mark)
Note 2: Typical parameter indicates the value for the center of distribution, and is not 100% tested.

CAPACITANCE

Symbol

CI
CO

Parameter

Input capacitance

Output capacitance

VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz

* -3.0V in case of AC (Pulse width 30ns)

Conditions

MITSUBISHI ELECTRIC

Min

Limits

Max

<
=

Units

pF