Mitsubishi M38503M2H-XXXSP, M38503M2H-XXXFP, M38503M4H-XXXSP, M38503M4H-XXXFP Datasheet
MITSUBISHI MICROCOMPUTERS
K
D
D
3
S
T
T
N
T
S
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 3850 group (spec. H) is the 8-bit microcomputer based on the
740 family core technology.
The 3850 group (spec. H) is designed for the household products
and office automation equipment and includes serial I/O functions,
8-bit timer, and A-D converter.
FEATURES
●Basic machine-language instructions ...................................... 71
●Minimum instruction execution time .................................. 0.5 µs
(at 8 MHz oscillation frequency)
●Memory size
ROM ................................................................... 8K to 32K bytes
RAM................................................................. 512 to 1024 bytes
●Programmable input/output ports ............................................ 34
●Interrupts ................................................. 14 sources, 14 vectors
●Timers............................................................................. 8-bit ✕ 4
●Serial I/O1 .................... 8-bit ✕ 1(UART or Clock-synchronized)
●Serial I/O2 ................................... 8-bit ✕ 1(Clock-synchronized)
●PWM ............................................................................... 8-bit ✕ 1
●A-D converter ............................................... 10-bit ✕ 5 channels
●Watchdog timer ............................................................ 16-bit ✕ 1
●Clock generating circuit..................................... Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
●Power source voltage
In high-speed mode .................................................. 4.0 to 5.5 V
(at 8 MHz oscillation frequency)
In middle-speed mode............................................... 2.7 to 5.5 V
(at 8 MHz oscillation frequency)
In low-speed mode .................................................... 2.7 to 5.5 V
(at 32 kHz oscillation frequency)
●Power dissipation
In high-speed mode ..........................................................34 mW
(at 8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode ............................................................ 60 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
●Operating temperature range ....................................–20 to 85°C
APPLICATION
Office automation equipment, FA equipment, Household products,
Consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
VC
C
R E F
V
S
S
V
A
P 44/ I N T3/ P W M
M P
P 43/ I N T2/ SC
P 42/ I N T1
P 41/ I N T0
P 40/ C N T R1
C N T
D Y
7/
P 2
R0/ SR
L
P 26/ SC
P 25/ T x
P 24/ R x
I
P 21/ XC
O U
P 20/ XC
Package type : FP ........................... 42P2R-A/E (42-pin plastic-molded SSOP)
Package type : SP ........................... 42P4B (42-pin plastic-molded SDIP)
P 2
P 22
C N VS
R E S E
XI
U
XO
VS
2
1
N
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
1
2
3
4
5
6
7
8
9
M
P
M
P
3 8 5 0 3 M 4 H - X X X F
3 8 5 0 3 M 4 H - X X X S
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
P 30/ A N0
P 31/ A N1
P 32/ A N2
P 33/ A N3
P 34/ A N4
N
P 00/ SI
U T
P 01/ SO
L K
P 02/ SC
D Y
P 03/ SR
2
2
P 04
P 05
P 06
P 07
P 10/ ( L E D0)
P 11/ ( L E D1)
P 12/ ( L E D2)
P 13/ ( L E D3)
P 14/ ( L E D4)
P 15/ ( L E D5)
P 16/ ( L E D6)
P 17/ ( L E D7)
2
2
Fig. 1 M38503M4H-XXXFP/SP pin configuration
FUNCTIONAL BLOCK
INT
0
–
V
REF
AV
SS
R A M
R O M
C P U
A
X
Y
S
PC
H
PC
L
PS
VSS
21
RESET
18
VCC
1 15
CNV
SS
23
X
IN
19
20
SI/O1(8)
Reset input
Clock generating circuit
Main-clock
input
Main-clock
output
A-D
converter
(10)
CNTR
0
CNTR
1
Timer Y( 8 )
Timer X( 8 )
Prescaler 12(8)
Prescaler X(8)
Prescaler Y(8)
Timer 1( 8 )
Timer 2( 8 )
Sub-clock
input
X
OUT
XCIN
XCOUT
Sub-clock
output
Watchdog
timer
Reset
P2(8)
P3(5)
I/O port P2
I/O port P3
P4(5)
I/O port P4
INT
3
4
6
8
5
7
39
4138 40
42
9
11
13
17
10
12
14
16
P1(8)
I/O port P1
22 24 26 2823
25
27 29
P0(8)
I/O port P0
30 31
32 333435 36
37
PWM
(8)
X
CIN
X
COUT
SI/O2(8)
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL BLOCK DIAGRAM
Fig. 2 Functional block diagram
2
PIN DESCRIPTION
Table 1 Pin description
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
VCC, VSS
RESET
XIN
XOUT
P00/SIN2
P01/SOUT2
P02/SCLK2
P03/SRDY2
P04–P07
P20/XCOUT
P21/XCIN
P22
P23
P24/RxD
P25/TxD
P26/SCLK
P27/CNTR0/
SRDY1
P30/AN0–
P34/AN4
P40/CNTR1
P41/INT0
P42/INT1
P43/INT2/SCMP2
P44/INT3/PWM
NamePin
Power source
CNVSS inputCNVSS
Reset input
Clock input
Clock output
I/O port P0
I/O port P1P10–P17
I/O port P2
I/O port P3
I/O port P4
Functions
•Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss.
•This pin controls the operation mode of the chip.
•Normally connected to VSS.
•Reset input pin for active “L.”
•Input and output pins for the clock generating circuit.
•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT
pin open.
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•CMOS compatible input level.
•CMOS 3-state output structure.
•P10 to P17 (8 bits) are enabled to output large current for LED drive.
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•CMOS compatible input level.
•P20, P21, P24 to P27: CMOS3-state output structure.
•P22, P23: N-channel open-drain structure.
•8-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
•CMOS 3-state output structure.
•8-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
•CMOS 3-state output structure.
Function except a port function
• Serial I/O2 function pin
• Sub-clock generating circuit I/O
pins (connect a resonator)
• Serial I/O1 function pin
• Serial I/O1 function pin/
Timer X function pin
• A-D converter input pin
• Timer Y function pin
• Interrupt input pins
• Interrupt input pin
• SCMP2 output pin
• Interrupt input pin
• PWM output pin
3
PART NUMBERING
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
P r o d u c t n a m e
M 3 8 5 0 3 M 4 H– X X XS P
P a c k a g e t y p e
S P : 4 2 P 4 B
F P : 4 2 P 2 R - A / E
S S : 4 2 S 1 B - A
R O M n u m b e r
O m i t t e d i n O n e T i m e P R O M v e r s i o n s h i p p e d i n b l a n k ,
E P R O M v e r s i o n , a n d f l a s h m e m o r y v e r s i o n .
– : s t a n d a r d
O m i t t e d i n O n e T i m e P R O M v e r s i o n s h i p p e d i n b l a n k , E P R O M
v e r s i o n , a n d f l a s h m e m o r y v e r s i o n .
H – : P a r t i a l s p e c i f i c a t i o n c h a n g e d v e r s i o n
R O M / P R O M / F l a s h m e m o r y s i z e
: 3 6 8 6 4 b y t e s
: 4 0 9 6 b y t e s
1
: 8 1 9 2 b y t e s
2
: 1 2 2 8 8 b y t e s
3
: 1 6 3 8 4 b y t e s
4
: 2 0 4 8 0 b y t e s
5
: 2 4 5 7 6 b y t e s
6
: 2 8 6 7 2 b y t e s
7
: 3 2 7 6 8 b y t e s
8
T h e f i r s t 1 2 8 b y t e s a n d t h e l a s t 2 b y t e s o f R O M a r e r e s e r v e d a r e a s ; t h e y
c a n n o t b e u s e d a s a u s e r ’ s R O M a r e a .
H o w e v e r , t h e y c a n b e p r o g r a m m e d o r e r a s e d i n t h e f l a s h m e m o r y v e r s i o n ,
s o t h a t t h e u s e r s c a n u s e t h e m .
9
: 4 0 9 6 0 b y t e s
A
: 4 5 0 5 6 b y t e s
B
: 4 9 1 5 2 b y t e s
C
: 5 3 2 4 8 b y t e s
D
: 5 7 3 4 4 b y t e s
E
: 6 1 4 4 0 b y t e s
F
Fig. 3 Part numbering
M e m o r y t y p e
M: M a s k R O M v e r s i o n
E : E P R O M o r O n e T i m e P R O M v e r s i o n
F: F l a s h m e m o r y v e r s i o n
R A M s i z e
5
0
: 1 9 2 b y t e s
1
: 2 5 6 b y t e s
2
: 3 8 4 b y t e s
3
: 5 1 2 b y t e s
4
: 6 4 0 b y t e s
: 7 6 8 b y t e s
6
: 8 9 6 b y t e s
7
: 1 0 2 4 b y t e s
8
: 1 5 3 6 b y t e s
9
: 2 0 4 8 b y t e s
4
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Mitsubishi plans to expand the 3850 group (spec. H) as follows.
Memory Type
Support for mask ROM, One Time PROM, and flash memory versions.
Memory Size
Flash memory size .........................................................32 K bytes
One Time PROM size.....................................................24 K bytes
Mask ROM size ................................................... 8 K to 32 K bytes
RAM size ...............................................................512 to 1 K bytes
Memory Expansion Plan
R O M s i z e ( b y t e s )
R O M
e x t e r a n a l
3 2 K
2 8 K
M a s s p r o d u c t i o n
U n d e r d e v e l o p m e n t
Packages
42P4B ......................................... 42-pin shrink plastic-molded DIP
42P2R-A/E........................................... 42-pin plastic-molded SOP
42S1B-A .................. 42-pin shrink ceramic DIP (EPROM version)
A s o f F e b . 2 0 0 0
M 3 8 5 0 7 M 8 / F 8
2 4 K
2 0 K
M a s s p r o d u c t i o n
1 6 K
1 2 K
M a s s p r o d u c t i o n
8 K
3 8 45 1 26 4 07 6 88 9 61 0 2 4
P r o d u c t s u n d e r d e v e l o p m e n t o r p l a n n i n g : t h e d e v e l o p m e n t s c h e d u l e a n d s p e c i f i c a t i o n m a y b e r e v i s e d w i t h o u t n o t i c e .
T h e d e v e l o p m e n t o f pl a n n i n g p r o d u c t s m a y b e s t o p p e d .
Fig. 4 Memory expansion plan
M 3 8 5 0 4 M 6 / E 6
M 3 8 5 0 3 M 4 H
M 3 8 5 0 3 M 2 H
1 1 5 21 2 8 01 4 0 81 5 3 62 0 4 8
R A M s i z e ( b y t e s )
5
Currently planning products are listed below.
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 2 Support products
Product name
M38503M2H-XXXSP
M38503M2H-XXXFP
M38503M4H-XXXSP
M38503M4H-XXXFP
M38504M6-XXXSP
M38504E6-XXXSP
M388504E6SP
M388504E6SS
M38504M6-XXXFP
M38504E6-XXXFP
M38504E6FP
Table 3 3850 group (standard) and 3850 group (spec. H)
corresponding products
3850 group (standard)
M38503M2-XXXFP/SP
M38503M4-XXXFP/SP
M38503E4-XXXFP/SP
M38503E4FP/SP
M38503E4SS
ROM size (bytes)
ROM size for User in ( )
8192
(8062)
16384
(16254)
24576
(24446)
3850 group (spec. H)
M38503M2H-XXXFP/SP
M38503M4H-XXXFP/SP
M38504M6-XXXFP/SP
M38504E6-XXXFP/SP
M38504E6FP/SP
M38504E6SS
M38507M8-XXXFP/SP
M38507F8FP/SP
RAM size (bytes)
512
512
640
Package
42P4B
42P2R-A/E
424P4B
42P2R-A/E
424P4B
42S1B-A
42P2R-A/E
As of Feb. 2000
Remarks
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
One Time PROM version
One Time PROM version (blank)
EPROM version
Mask ROM version
One Time PROM version
One Time PROM version (blank)
Table 4 Differences between 3850 group (standard) and 3850 group (spec. H)
3850 group (spec. H)
Serial I/O
A-D converter
Large current port
3850 group (standard)
1: Serial I/O (UART or Clock-synchronized)
Unserviceable in low-speed mode
5: P13–P17
2: Serial I/O1 (UART or Clock-synchronized)
Serial I/O2 (Clock-synchronized)
Serviceable in low-speed mode
8: P10–P17
Notes on differences between 3850 group (standard) and 3850 group (spec. H)
(1) The absolute maximum ratings of 3850 group (spec. H) is smaller than that of 3850 group (standard).
•Power source voltage Vcc = –0.3 to 6.5 V
•CNVss input voltage VI = –0.3 to Vcc +0.3 V
(2) The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT may be some differences between 3850 group (standard) and 3850 group
(spec. H).
(3) Do not write any data to the reserved area and the reserved bit. (Do not change the contents after rest.)
(4) Fix bit 3 of the CPU mode register to “1”.
(5) Be sure to perform the termination of unused pins.
6
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The 3850 group (spec. H) uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and
machine instructions or the 740 Family Software Manual for details on the instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“0116”.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 6.
Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine
calls.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
b7
b0
A Accumulator
b7
b0
X Index register X
b7
b0
Y Index register Y
b7 b0
S Stack pointer
b7b15 b0
H
PC
L
Program counterPC
b7 b0
N V T B D I Z C Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 5 740 Family CPU register structure
7
e
O n - g o i n g R o u t i n
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
P u s h r e t u r n a d d r e s s
o n s t a c k
P O P re t u r n
a d d r e s s f r o m s t a c k
I n t e r r u p t r e q u e s t
M ( S )( P CH)
( S )
M ( S )( P CL)
( S )
S u b r o u t i n e
E x e c u t e R T S
( S )
( P CL)M ( S )
( S )
( P CH)M ( S )
( S ) – 1
( S ) + 1
( S ) + 1
( N o t e )
( S ) – 1
E x e c u t e J S R
M ( S )( P CH)
( S )
( S ) – 1
M ( S )( P CL)
( S )
( S ) – 1
M ( S )( P S )
( S )
( S ) – 1
I n t e r r u p t
S e r v i c e R o u t i n e
E x e c u t e R T I
( S )
( S ) + 1
( P S )M ( S )
( S )
( S ) + 1
( P CL)M ( S )
( S )
( S ) + 1
P u s h r e t u r n a d d r e s s
o n s t a c k
P u s h c o n t e n t s o f p r o c e s s o r
s t a t u s r e g i s t e r o n s t a c k
I F l a g i s s e t f r o m “ 0 ” t o “ 1 ”
F e t c h t h e j u m p v e c t o r
P O P c o n t e n t s o f
p r o c e s s o r s t a t u s
r e g i s t e r f r o m s t a c k
P O P r e t u r n
a d d r e s s
f r o m s t a c k
N o t e: C o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t I n t e r r u p t e n a b l e f l a g i s “ 1 ”
Fig. 6 Register push and pop at interrupt generation and subroutine call
Table 5 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Accumulator
Processor status register
PHA
PHP
I n t e r r u p t d i s a b l e f l a g i s “ 0 ”
( P CH)M ( S )
Pop instruction from stack
PLA
PLP
8
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
•Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 6 Set and clear instructions of each bit of processor status register
C flag Z flag I flag D flag B flag T flag V flag N flag
Set instruction
Clear instruction
SEC
CLC
_
_
SEI
CLI
SED
CLD
_
_
SET
CLT CLV
_
_
_
9
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, etc.
The CPU mode register is allocated at address 003B16.
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
CPU mode register
(
CPUM : address
003B16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 : Not available
1 1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Fix this bit to “1”.
C switch bit
Port X
0 : I/O port function (stop oscillating)
CIN–XCOUT oscillating function
1 : X
Main clock (X
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
0 0 : φ = f(X
0 1 : φ = f(X
1 0 : φ = f(X
1 1 : Not available
IN–XOUT) stop bit
IN)/2 (high-speed mode)
IN)/8 (middle-speed mode)
CIN)/2 (low-speed mode)
Fig. 7 Structure of CPU mode register
10
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains
control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM size
(bytes)
192
256
384
512
640
768
896
1024
1536
2048
ROM area
ROM size
(bytes)
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
Address
XXXX
00FF
013F
01BF
023F
02BF
033F
03BF
043F
063F
083F
Address
YYYY
F000
E000
D000
C000
B000
A000
9000
8000
7000
6000
5000
4000
3000
2000
1000
16
16
16
16
16
16
16
16
16
16
16
Address
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
ZZZZ
F080
E080
D080
C080
B080
A080
9080
8080
7080
6080
5080
4080
3080
2080
1080
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Zero Page
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
Special Page
Access to this area with only 2 bytes is possible in the special
page addressing mode.
0000
16
0040
16
0100
16
XXXX
0FF0
0FFF
YYYY
ZZZZ
16
16
16
16
16
RAM
ROM
FF00
16
FFDC
16
FFFE
16
FFFF
16
Note: Flash memory version only
SFR area
Not used
SFR area (Note)
Not used
Reserved ROM area
(128 bytes)
Interrupt vector area
Reserved ROM area
Zero page
Special page
Fig. 8 Memory map diagram
11
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
0 0 0 0
0 0 0 1
0 0 0 2
0 0 0 3
0 0 0 4
0 0 0 5
0 0 0 6
0 0 0 7
0 0 0 8
0 0 0 9
0 0 0 A
0 0 0 B
0 0 0 C
0 0 0 D
0 0 0 E
0 0 0 F
0 0 1 0
0 0 1 1
0 0 1 2
0 0 1 3
0 0 1 4
0 0 1 5
0 0 1 6
0 0 1 7
0 0 1 8
0 0 1 9
0 0 1 A
0 0 1 B
0 0 1 C
0 0 1 D
0 0 1 E
0 0 1 F
P o r t P 0 ( P 0 )
1 6
P o r t P 0 d i r e c t i o n r e g i s t e r ( P 0 D )
1 6
P o r t P 1 ( P 1 )
1 6
P o r t P 1 d i r e c t i o n r e g i s t e r ( P 1 D )
1 6
P o r t P 2 ( P 2 )
1 6
P o r t P 2 d i r e c t i o n r e g i s t e r ( P 2 D )
1 6
P o r t P 3 ( P 3 )
1 6
P o r t P 3 d i r e c t i o n r e g i s t e r ( P 3 D )
1 6
P o r t P 4 ( P 4 )
1 6
P o r t P 4 d i r e c t i o n r e g i s t e r ( P 4 D )
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
R e s e r v e d ✽
1 6
R e s e r v e d ✽
1 6
R e s e r v e d ✽
S e r i a l I / O 2 c o n t r o l r e g i s t e r 1 ( S I O 2 C O N 1 )
1 6
S e r i a l I / O 2 c o n t r o l r e g i s t e r 2 ( S I O 2 C O N 2 )
1 6
S e r i a l I / O 2 r e g i s t e r ( S I O 2 )
1 6
T r a n s m i t / R e c e i v e b u f f e r r e g i s t e r ( T B / R B )
1 6
S e r i a l I / O 1 s t a t u s r e g i s t e r ( S I O S T S )
1 6
S e r i a l I / O 1 c o n t r o l r e g i s t e r ( S I O C O N )
1 6
U A R T c o n t r o l r e g i s t e r ( U A R T C O N )
1 6
B a u d r a t e g e n e r a t o r ( B R G )
1 6
P W M c o n t r o l r e g i s t e r ( P W M C O N )
1 6
P W M p r e s c a l e r ( P R E P W M )
1 6
P W M r e g i s t e r ( P W M )
1 6
0 0 2 0
0 0 2 1
0 0 2 2
0 0 2 3
0 0 2 4
0 0 2 5
0 0 2 6
0 0 2 7
0 0 2 8
0 0 2 9
0 0 2 A
0 0 2 B
0 0 2 C
0 0 2 D
0 0 2 E
0 0 2 F
0 0 3 0
0 0 3 1
0 0 3 2
0 0 3 3
0 0 3 4
0 0 3 5
0 0 3 6
0 0 3 7
0 0 3 8
0 0 3 9
0 0 3 A
0 0 3 B
0 0 3 C
0 0 3 D
0 0 3 E
0 0 3 F
P r e s c a l e r 1 2 ( P R E 1 2 )
1 6
T i m e r 1 ( T 1 )
1 6
T i m e r 2 ( T 2 )
1 6
T i m e r X Y m o d e r e g i s t e r ( T M )
1 6
P r e s c a l e r X ( P R E X )
1 6
T i m e r X ( T X )
1 6
P r e s c a l e r Y ( P R E Y )
1 6
T i m e r Y ( T Y )
1 6
T i m e r c o u n t s o u r c e s e l e c t i o n r e g i s t e r ( T C S S )
1 6
1 6
1 6
1 6
R e s e r v e d ✽
R e s e r v e d ✽
1 6
1 6
R e s e r v e d ✽
1 6
R e s e r v e d ✽
1 6
R e s e r v e d ✽
1 6
R e s e r v e d ✽
1 6
R e s e r v e d ✽
1 6
1 6
A - D c o n t r o l r e g i s t e r ( A D C O N )
1 6
A - D c o n v e r s i o n l o w - o r d e r r e g i s t e r ( A D L )
1 6
A - D c o n v e r s i o n h i g h - o r d e r r e g i s t e r ( A D H )
1 6
1 6
R e s e r v e d ✽
M I S R G
1 6
W a t c h d o g t i m e r c o n t r o l r e g i s t e r ( W D T C O N )
1 6
I n t e r r u p t e d g e s e l e c t i o n r e g i s t e r ( I N T E D G E )
1 6
C P U m o d e r e g i s t e r ( C P U M )
1 6
I n t e r r u p t r e q u e s t r e g i s t e r 1 ( I R E Q 1 )
1 6
I n t e r r u p t r e q u e s t r e g i s t e r 2 ( I R E Q 2 )
1 6
I n t e r r u p t c o n t r o l r e g i s t e r 1 ( I C O N 1 )
1 6
I n t e r r u p t c o n t r o l r e g i s t e r 2 ( I C O N 2 )
1 6
✽ R e s e r v e d : D o n o t w r i t e a n y d a t a t o t h i s a d d r e s s e s , b e c a u s e t h e s e a r e a s a r e r e s e r v e d .
Fig. 9 Memory map of special function register (SFR)
12
I/O PORTS
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction
register corresponds to one pin, and each pin can be set to be
input port or output port.
When “0” is written to the bit corresponding to a pin, that pin
becomes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
Table 5 I/O port function
Pin
P00/SIN2
P01/SOUT2
P02/SCLK2
P03/SRDY2
P04–P07
P10–P17
P20/XCOUT
P21/XCIN
P22
P23
P24/RxD
P25/TxD
Name
Port P0
Port P1
Port P2
Input/Output
Input/output,
individual
bits
I/O Structure Non-Port Function
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
N-channel open-drain
output
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Related SFRs
Serial I/O2 function I/O
Sub-clock generating
circuit
Serial I/O1 function I/O
Serial I/O2 control
register
CPU mode register
Serial I/O1 control
register
Ref.No.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
P26/SCLK
P27/CNTR0/SRDY1
P30/AN0–
P34/AN4
P40/CNTR1
P41/INT0
P42/INT1
P43/INT2/SCMP2
P44/INT3/PWM
Port P3
Port P4
CMOS compatible
input level
CMOS 3-state output
Serial I/O1 function I/O
Serial I/O1 function I/O
Timer X function I/O
A-D conversion input
Timer Y function I/O
External interrupt input
External interrupt input
SCMP2 output
External interrupt input
PWM output
Serial I/O1 control
register
Serial I/O1 control
register
Timer XY mode register
A-D control register
Timer XY mode register
Interrupt edge selection
register
Interrupt edge selection
register
Serial I/O2 control register
Interrupt edge selection
register
PWM control register
(11)
(12)
(13)
(14)
(15)
(16)
(17)
13
MITSUBISHI MICROCOMPUTERS
r
t
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
( 1 ) P o r t P 0
( 3 ) P o r t P 0
0
D a t a b u s
2
P 02/ S
C L K 2
S e r i a l I / O 2 s y n c h r o n o u s
S e r i a l I / O 2 p o r t s e l e c t i o n b i t
D a t a b u s
S e r i a l I / O 2 c l o c k o u t p u t
D i r e c t i o n
r e g i s t e r
P o r t l a t c h
S e r i a l I / O 2 i n p u t
P - c h a n n e l o u t p u t d i s a b l e b i t
c l o c k s e l e c t i o n b i t
D i r e c t i o n
r e g i s t e r
P o r t l a t c h
S e r i a l I / O 2 e x t e r n a l c l o c k i n p u t
( 2 ) P o r t P 0
P 01/ S
S e r i a l I / O 2 T r a n s m i t c o m p l e t i o n s i g n a l
D a t a b u s
( 4 ) P o r t P 0
1
O U T 2
P - c h a n n e l o u t p u t d i s a b l e b i t
S e r i a l I / O 2 p o r t s e l e c t i o n b i t
D i r e c t i o n
r e g i s t e r
P o r t l a t c h
S e r i a l I / O 2 o u t p u t
3
R D Y 2
o u t p u t e n a b l e b i t
S
D i r e c t i o n
r e g i s t e r
D a t a b u s
P o r t l a t c h
S e r i a l I / O 2 r e a d y o u t p u t
( 5 ) P o r t s P 04- P 0
( 7 ) P o r t P 2
D a t a b u s
D a t a b u s
1
7 ,
P o r t X
P 1
C
D i r e c t i o n
r e g i s t e r
P o r t l a t c h
Fig. 10 Port block diagram (1)
D i r e c t i o n
r e g i s t e r
P o r t l a t c h
s w i t c h b i t
S u b - c l o c k g e n e r a t i n g c i r c u i t i n p u
( 6 ) P o r t P 2
D a t a b u s
( 8 ) P o r t s P 2
D a t a b u s
0
C
s w i t c h b i t
P o r t X
D i r e c t i o n
r e g i s t e r
P o r t l a t c h
O s c i l l a t o
P o r t P 2
1
P o r t XC s w i t c h b i t
2 ,
P 2
3
D i r e c t i o n
r e g i s t e r
P o r t l a t c h
14
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(9) Port P24
Serial I/O1 enable bit
Receive enable bit
Data bus
(11) Port P26
Serial I/O1 synchronous
clock selection bit
Serial I/O1 enable bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Data bus
Serial I/O1 clock output
Direction
register
Port latch
Direction
register
Port latch
Serial I/O1 input
External clock input
(10) Port P25
P-channel output disable bit
Serial I/O1 enable bit
Transmit enable bit
Direction
register
Data bus
Port latch
Serial I/O1 output
(12) Port P27
Serial I/O1 mode selection bit
S
Pulse output mode
Serial I/O1 enable bit
RDY1 output enable bit
Data bus
Serial ready output
Timer output
Direction
register
Port latch
Pulse output mode
CNTR
0 interrupt
input
(13) Ports P30-P34
Data bus
(15) Ports P41,P42
Data bus
Direction
register
Port latch
Direction
register
Port latch
Interrupt input
A-D converter input
Analog input pin selection bit
(14) Port P40
Data bus
Pulse output mode
(16) Port P43
comparison signal control bit
Data bus
comparison signal output
Direction
register
Port latch
Timer output
Serial I/O2 I/O
Direction
register
Port latch
Serial I/O2 I/O
CNTR
1 interrupt
Interrupt input
input
Fig. 11 Port block diagram (2)
15
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(17) Port P4
Data bus
4
PWM output enable bit
Direction
register
Port latch
PWM output
Fig. 12 Port block diagram (3)
Interrupt input
16
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