Mitsubishi M38027M8DXXXSP, M38027M8DXXXFP, M38027E8DXXXSP, M38027E8DXXXFP, M38027E8DSP Datasheet
...
ADVANCED AND EVER ADVANCING
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 38000 SERIES
MITSUBISHI ELECTRIC
3802
Group
User’s Manual
MITSUBISHI
ELECTRIC
keep safety first in your circuit designs !
● Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble
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of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention
against any malfunction or mishap.
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Preface
This user’s manual describes Mitsubishi’s CMOS 8bit microcomputers 3802 Group.
After reading this manual, the user should have a
through knowledge of the functions and features of
the 3802 Group, and should be able to fully utilize
the product. The manual starts with specifications
and ends with application examples.
For details of software, refer to the “SERIES MELPS
740 <SOFTWARE> USER’S MANUAL.”
For details of development support tools, refer to the
“DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTERS” data book.
BEFORE USING THIS USER’S MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such
as hardware design or software development. Chapter 3 also includes necessary information for systems development.
Be sure to refer to this chapter.
1. Organization
● CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
● CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on setting examples
of related registers.
● CHAPTER 3 APPENDIX
This chapter includes necessary information for systems development using the microcomputer, electric
characteristics, a list of registers, the masking confirmation (mask ROM version), and mark specifications which
are to be submitted when ordering.
2. Structure of register
The figure of each register structure describes its functions, contents at reset, and attributes as follows :
(Note 1)
(Note 2)
At reset
0
0
0
0
0
1
✻
✻
RWB
✕
✕
Bits
b0b1b2b3b4b5b6b7
0
CPU mode register (CPUM) [Address : 3B16]
0
Processor mode bits
1
2
Stack page selection bit
3
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
4
5
Fix this bit to “0.”
6
Main clock (X
7
Internal system clock selection bit
: Bit in which nothing is arranged
Note 1. Contents immediately after reset release
0••••••“0” at reset release
1••••••“1” at reset release
Undefined••••••Undefined or reset release
••••••Contents determined by option at reset release
✻
Contents immediately after reset release
Name Function
IN-XOUT
) stop bit
: Bit that is not used for control of the corresponding function
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 :
1 1 :
0 : 0 page
1 : 1 page
0 : Operating
1 : Stopped
0 : X
1 : X
Not available
IN-XOUT
selected
CIN-XCOUT
Bit attributes
selected
Note 2. Bit attributes••••••The attributes of control register bits are classified into 3 bytes : read-only, write-only
and read and write. In the figure, these attributes are represented as follows :
R••••••Read
••••••Read enabled
✕••••••Read disabled
W••••••Write
••••••Write enabled
✕ ••••••Write disabled
LIST OF GROUPS HAVING THE SIMILAR FUNCTIONS
3802 group, one of the CMOS 8-bit microcomputer 38000 series presented in this user’s manual is provided with
standard functions.
The basic functions of the 3800, 3802, 3806 and 3807 groups having the same functions are shown below. For the
detailed functions of each group, refer to the related data book and user’s manual.
List of groups having the same functions
Group
Function
Pin
(Package type)
Clock generating circuit
Timer
Serial I/O
A-D converter
D-A converter
3800 group
64 pin
• 64P4B
• 64P6N-A
• 64P6D-A
1 circuit
<8-bit>
Prescaler : 3
Timer : 4
UART or
Clock synchronous ✕ 1
<8-bit>
UART or
Clock synchronous ✕ 1
Clock synchronous ✕ 1
8-bit ✕ 8-channel
8-bit ✕ 2-channel
3802 group
64 pin
• 64P4B
• 64P6N-A
1 circuit
Prescaler : 3
Timer : 4
As of September 1995
3806 group 3807 group
80 pin
• 80P6N-A
• 80P6S-A
• 80P6D-A
1 circuit
<8-bit>
<8-bit>
Prescaler : 3
Timer : 4
UART or
Clock synchronous ✕ 1
Clock synchronous ✕ 1
8-bit ✕ 8-channel
8-bit ✕ 2-channel
<16-bit>
UART or
Clock synchronous ✕ 1
Clock synchronous ✕ 1
8-bit ✕ 13-channel
8-bit ✕ 4-channel
80 pin
• 80P6N-A
2 circuit
Timer : 3
Timer X/Y : 2
Timer A/B : 2
Memory
Mask
ROM
One Time
PROM
8K
(Note 1)
8K
16K
(Note 1)
16K
(Note 1)
24K
32K
(Note 1)
32K
8K
(Note 1)
16K
(Note 1)
24K
✽
type
EPROM
RAM
16K 32K
384 384 640
512 384
384 384 640
PWM output
Remarks
Notes 1: Extended operating temperature version available
2: High-speed version available
3: Extended operating temperature version and High-speed version available
✽. ROM expansion
32K
(Note 1)
32K
(Note 1)
32K
1024
12K
(Note 1)
16K
(Note 1)
24K
(Note 3)
24K
(Note 2)
24K
32K
48K
(Note 3)
(Note 3)
48K
(Note 3)
48K
(Note 2)
1024512384 384 1024
16K
16K
16K
512
Real time port output
Analog comparator
Watchdog timer
CHAPTER 1. HARDWARE
DESCRIPTION ................................................................................................................................ 1-2
FEATURES ...................................................................................................................................... 1-2
APPLICATIONS .............................................................................................................................. 1 -2
PIN CONFIGURATION ................................................................................................................... 1 -2
FUNCTIONAL BLOCK ................................................................................................................... 1 -4
PIN DESCRIPTION ......................................................................................................................... 1 -5
PART NUMBERING .......................................................................................................................1-6
GROUP EXPANSION ..................................................................................................................... 1- 7
Table of contents
Table of contents
GROUP EXPANSION (EXTENDED OPERATING TEMPERATURE VERSION) .................... 1 -8
FUNCTIONAL DESCRIPTION ....................................................................................................... 1 -9
Central Processing Unit (CPU) ...............................................................................................1-9
Memory .................................................................................................................................... 1-13
I/O Ports .................................................................................................................................. 1-15
Interrupts .................................................................................................................................. 1-18
Timers ...................................................................................................................................... 1-20
Serial I/O.................................................................................................................................. 1-22
Pulse Width Modulation (PWM) ............................................................................................ 1-28
A-D Converter ......................................................................................................................... 1-30
D-A Converter ......................................................................................................................... 1-31
Reset Circuit ............................................................................................................................ 1- 32
Clock Generating Circuit ........................................................................................................ 1-34
Processor Modes .................................................................................................................... 1-35
NOTES ON PROGRAMMING ..................................................................................................... 1-37
Processor Status Register .....................................................................................................1-37
Interrupts .................................................................................................................................. 1-37
Decimal Calculations ..............................................................................................................1-37
Timers ...................................................................................................................................... 1-37
Multiplication and Division Instructions ................................................................................ 1-37
Ports ......................................................................................................................................... 1-37
Serial I/O.................................................................................................................................. 1-37
A-D Converter ......................................................................................................................... 1-37
D-A Converter ......................................................................................................................... 1-37
Instruction Execution Time .................................................................................................... 1-37
Memory Expansion Mode.......................................................................................................1-37
Memory Expansion Mode and Microprocessor Mode ....................................................... 1-37
DATA REQUIRED FOR MASK ORDERS .................................................................................1-38
3802 GROUP USER'S MANUAL
i
Table of contents
ROM PROGRAMMING METHOD ............................................................................................... 1-38
FUNCTIONAL DESCRIPTION SUPPLEMENT .......................................................................... 1-39
Interrupt ....................................................................................................................................1-39
Timing After Interrupt ............................................................................................................. 1-40
A-D Converter ......................................................................................................................... 1-41
CHAPTER 2. APPLICATION
2.1 I/O port ..................................................................................................................................... 2-2
2.1.1 Memory map of I/O port................................................................................................ 2 -2
2.1.2 Related registers ............................................................................................................. 2 -3
2.1.3 Handling of unused pins ................................................................................................ 2 -4
2.2 Timer ......................................................................................................................................... 2-5
2.2.1 Memory map of timer ..................................................................................................... 2 -5
2.2.2 Related registers ............................................................................................................. 2 -6
2.2.3 Timer application examples ......................................................................................... 2-11
2.3 Serial I/O ................................................................................................................................ 2-23
2.3.1 Memory map of serial I/O ........................................................................................... 2-23
2.3.2 Related registers ........................................................................................................... 2-24
2.3.3 Serial I/O connection examples .................................................................................. 2-30
2.3.4 Setting of serial I/O transfer data format ................................................................. 2-32
2.3.5 Serial I/O application examples .................................................................................. 2-33
2.4 PWM ........................................................................................................................................ 2-53
2.4.1 Memory map of PWM .................................................................................................. 2-53
2.4.2 Related registers ........................................................................................................... 2-54
2.4.3 PWM output circuit application example ................................................................... 2-56
2.5 A-D converter ........................................................................................................................ 2-59
2.5.1 Memory map of A-D conversion................................................................................. 2-59
2.5.2 Related registers ........................................................................................................... 2-60
2.5.3 A-D conversion application example .......................................................................... 2-62
2.6 Processor mode ................................................................................................................... 2-64
2.6.1 Memory map of processor mode ................................................................................ 2-64
2.6.2 Related register ............................................................................................................. 2-64
2.6.3 Processor mode application examples ...................................................................... 2-65
2.7 Reset ....................................................................................................................................... 2-69
2.7.1 Connection example of reset IC ................................................................................. 2-69
CHAPTER 3. APPENDIX
3.1 Electrical characteristics ...................................................................................................... 3- 2
3.1.1 Absolute maximum ratings ............................................................................................ 3 -2
3.1.2 Recommended operating conditions............................................................................. 3-2
3.1.3 Electrical characteristics................................................................................................. 3- 3
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3802 GROUP USER'S MANUAL
Table of contents
3.1.4 A-D converter characteristics ........................................................................................3-3
3.1.5 D-A converter characteristics ........................................................................................3-4
3.1.6 Timing requirements and Switching characteristics .................................................. 3-5
3.1.7 Absolute maximum ratings (Extended operating temperature version) .................. 3 -9
3.1.8 Recommended operating conditions(Extended operating temperature version) .... 3-9
3.1.9 Electrical characteristics (Extended operating temperature version) .................... 3-10
3.1.10 A-D converter characteristics (Extended operating temperature version) ........ 3-10
3.1.11 D-A converter characteristics (Extended operating temperature version) ........ 3-11
3.1.12 Timing requirements and Switching characteristics
(Extended operating temperature version) ......................................................... 3-12
3.1.13 Timing diagram ........................................................................................................... 3-14
3.2 Standard characteristics ..................................................................................................... 3-17
3.2.1 Power source current characteristic examples ........................................................ 3-17
3.2.2 Port standard characteristic examples ...................................................................... 3-18
3.2.3 A-D conversion standard characteristics .................................................................. 3-20
3.2.4 D-A conversion standard characteristics .................................................................. 3-21
3.3 Notes on use......................................................................................................................... 3-22
3.3.1 Notes on interrupts ....................................................................................................... 3-22
3.3.2 Notes on the serial I/O1 .............................................................................................. 3-22
3.3.3 Notes on the A-D converter ........................................................................................3-23
3.3.4 Notes on the RESET pin ............................................................................................. 3-24
3.3.5 Notes on input and output pins.................................................................................. 3-24
3.3.6 Notes on memory expansion mode and microprocessor mode ............................ 3-25
3.3.7 Notes on built-in PROM ............................................................................................... 3-26
3.4 Countermeasures against noise ....................................................................................... 3-28
3.4.1 Shortest wiring length .................................................................................................. 3-28
3.4.2 Connection of a bypass capacitor across the Vss line and the Vcc line ............ 3-29
3.4.3 Wiring to analog input pins ......................................................................................... 3-30
3.4.4 Consideration for oscillator .......................................................................................... 3-30
3.4.5 Setup for I/O ports ....................................................................................................... 3-31
3.4.6 Providing of watchdog timer function by software .................................................. 3-31
3.5 List of registers .................................................................................................................... 3-33
3.6 Mask ROM ordering method .............................................................................................. 3-47
3.7 Mark specification form ...................................................................................................... 3-61
3.8 Package outline .................................................................................................................... 3-63
3.9 List of instruction codes .................................................................................................... 3-65
3.10 Machine Instructions ......................................................................................................... 3-66
3.11 SFR memory map .............................................................................................................. 3-76
3.12 Pin configuration................................................................................................................ 3-77
3802 GROUP USER'S MANUAL
iii
CHAPTER 1 HARDWARE
Fig. 1 Pin configuration of M38022M4-XXXFP ..........................................................................1 -2
Fig. 2 Pin configuration of M38022M4-XXXSP .......................................................................... 1-3
Fig. 3 Functional block diagram ................................................................................................... 1- 4
Fig. 4 Part numbering .................................................................................................................... 1 -6
Fig. 5 Memory expansion plan ..................................................................................................... 1 -7
Fig. 6 Memory expansion plan (Extended operating temperature version) .......................... 1-8
Fig. 7 740 Family CPU register structure................................................................................... 1- 9
Fig. 8 Register push and pop at interrupt generation and subroutine call ........................ 1-10
Fig. 9 Structure of CPU mode register ..................................................................................... 1-11
Fig. 10 Memory map diagram .................................................................................................... 1-12
Fig. 11 Memory map of special function register (SFR) ....................................................... 1-13
Fig. 12 Port block diagram (single-chip mode) (1) ................................................................ 1-16
Fig. 13 Port block diagram (single-chip mode) (2) ................................................................ 1-17
Fig. 14 Interrupt control...............................................................................................................1-18
Fig. 15 Structure of interrupt-related registers ........................................................................ 1-18
Fig. 16 Structure of timer XY register .......................................................................................1-19
Fig. 17 Block diagram of timer X, timer Y, timer 1, and timer 2 ........................................ 1-21
Fig. 18 Block diagram of clock synchronous serial I/O1....................................................... 1-22
Fig. 19 Operation of clock synchronous serial I/O1 function ............................................... 1-22
Fig. 20 Block diagram of UART serial I/O .............................................................................. 1-23
Fig. 21 Operation of UART serial I/O function ....................................................................... 1-24
Fig. 22 Structure of serial I/O control registers ...................................................................... 1-25
Fig. 23 Structure of serial I/O2 control register...................................................................... 1-26
Fig. 24 Block diagram of serial I/O2 function ......................................................................... 1-26
Fig. 25 Timing of serial I/O2 function ....................................................................................... 1-27
Fig. 26 Timing of PWM cycle .....................................................................................................1-28
Fig. 27 Block diagram of PWM function ................................................................................... 1-28
Fig. 28 Structure of PWM control register............................................................................... 1-29
Fig. 29 PWM output timing when PWM register or PWM prescaler is changed ............... 1-29
Fig. 30 Structure of AD/DA control register ............................................................................ 1-30
Fig. 31 Block diagram of A-D converter ................................................................................... 1-30
Fig. 32 Block diagram of D-A converter ................................................................................... 1-31
Fig. 33 Equivalent connection circuit of D-A converter ......................................................... 1-31
Fig. 34 Example of reset circuit ................................................................................................. 1-32
Fig. 35 Internal status of microcomputer after reset ............................................................. 1-32
Fig. 36 Timing of reset ................................................................................................................ 1-33
Fig. 37 Ceramic resonator circuit...............................................................................................1-34
Fig. 38 External clock input circuit ............................................................................................ 1-34
Fig. 39 Block diagram of clock generating circuit .................................................................................. 1-34
Fig. 40 Memory maps in various processor modes............................................................... 1-35
Fig. 41 Structure of CPU mode register ................................................................................... 1-35
Fig. 42 ONW function timing ......................................................................................................1-36
Fig. 43 Programming and testing of One Time PROM version ........................................... 1-38
Fig. 44 Timing chart after an interrupt occurs ........................................................................ 1-40
Fig. 45 Time up to execution of the interrupt processing routine ....................................... 1-40
Fig. 46 A-D conversion equivalent circuit ................................................................................. 1-42
Fig. 47 A-D conversion timing chart .......................................................................................... 1-42
List of figures
List of figures
3802 GROUP USER’S MANUAL
i
List of figures
CHAPTER 2 APPLICATION
Fig. 2.1.1 Memory map of I/O port related registers ............................................................... 2 -2
Fig. 2.1.2 Structure of Port Pi (i=0, 1, 2, 3, 4, 5, 6)............................................................... 2- 3
Fig. 2.1.3 Structure of Port Pi direction register (i=0, 1, 2, 3, 4, 5, 6) ................................ 2 -3
Fig. 2.2.1 Memory map of timer related registers ......................................................................2 -5
Fig. 2.2.2 Structure of Prescaler 12, Prescaler X, Prescaler Y.............................................. 2 -6
Fig. 2.2.3 Structure of Timer 1.....................................................................................................2-6
Fig. 2.2.4 Structure of Timer 2, Timer X, Timer Y ....................................................................2 -7
Fig. 2.2.5 Structure of Timer XY mode register......................................................................... 2-8
Fig. 2.2.6 Structure of Interrupt request register 1.................................................................... 2-9
Fig. 2.2.7 Structure of Interrupt request register 2.................................................................... 2-9
Fig. 2.2.8 Structure of Interrupt control register 1 .................................................................. 2-10
Fig. 2.2.9 Structure of Interrupt control register 2 .................................................................. 2-10
Fig. 2.2.10 Connection of timers and setting of division ratios [Clock function] ................ 2-12
Fig. 2.2.11 Setting of related registers [Clock function] ......................................................... 2-13
Fig. 2.2.12 Control procedure [Clock function] ........................................................................ 2-14
Fig. 2.2.13 Example of a peripheral circuit ............................................................................... 2-15
Fig. 2.2.14
Fig. 2.2.15 Setting of related registers [Piezoelectric buzzer output] ................................... 2-16
Fig. 2.2.16 Control procedure [Piezoelectric buzzer output] .................................................. 2-16
Fig. 2.2.17 A method for judging if input pulse exists ........................................................... 2-17
Fig. 2.2.18 Setting of related registers [Measurement of frequency] ................................... 2-18
Fig. 2.2.19 Control procedure [Measurement of frequency] ................................................... 2-19
Fig. 2.2.20
Fig. 2.2.21 Setting of related registers [Measurement of pulse width] ................................ 2-21
Fig. 2.2.22 Control procedure [Measurement of pulse width] ................................................ 2-22
Connection of the timer and setting of the division ratio [Piezoelectric buzzer output]
Connection of the timer and setting of the division ratio [Measurement of pulse width] ...........
........... 2-15
2-20
Fig. 2.3.1 Memory map of serial I/O related registers ........................................................... 2-23
Fig. 2.3.2 Structure of Transmit/Receive buffer register ........................................................ 2-24
Fig. 2.3.3 Structure of Serial I/O1 status register ................................................................... 2-24
Fig. 2.3.4 Structure of Serial I/O1 control register .................................................................. 2-25
Fig. 2.3.5 Structure of UART control register ........................................................................... 2-25
Fig. 2.3.6 Structure of Baud rate generator .............................................................................. 2-26
Fig. 2.3.7 Structure of Serial I/O2 control register .................................................................. 2-26
Fig. 2.3.8 Structure of Serial I/O2 register................................................................................2-27
Fig. 2.3.9 Structure of Interrupt edge selection register ........................................................ 2-27
Fig. 2.3.10 Structure of Interrupt request register 1 ............................................................... 2-28
Fig. 2.3.11 Structure of Interrupt request register 2 ............................................................... 2-28
Fig. 2.3.12 Structure of Interrupt control register 1 ................................................................ 2-29
Fig. 2.3.13 Structure of Interrupt control register 2 ................................................................ 2-29
Fig. 2.3.14 Serial I/O connection examples (1) ....................................................................... 2-30
Fig. 2.3.15 Serial I/O connection examples (2) ....................................................................... 2-31
Fig. 2.3.16 Setting of Serial I/O transfer data format ............................................................. 2-32
Fig. 2.3.17 Connection diagram [Communication using a clock synchronous serial I/O] .. 2-33
Fig. 2.3.18 Timing chart [Communication using a clock synchronous serial I/O] ............... 2-33
Fig. 2.3.19 Setting of related registers at a transmitting side
[Communication using a clock synchronous serial I/O] ................................ 2-34
Fig. 2.3.20 Setting of related registers at a receiving side
[Communication using a clock synchronous serial I/O] ................................ 2-35
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3802 GROUP USER’S MANUAL
List of figures
Fig. 2.3.21 Control procedure at a transmitting side
[Communication using a clock synchronous serial I/O] .................................. 2-36
Fig. 2.3.22
Fig. 2.3.23 Connection diagram [Output of serial data] ......................................................... 2-38
Fig. 2.3.24 Timing chart [Output of serial data] ...................................................................... 2-38
Fig. 2.3.25 Setting of serial I/O1 related registers [Output of serial data] .......................... 2-39
Fig. 2.3.26 Setting of serial I/O1 transmission data [Output of serial data]........................ 2-39
Fig. 2.3.27 Control procedure of serial I/O1 [Output of serial data] .................................... 2-40
Fig. 2.3.28 Setting of serial I/O2 related registers [Output of serial data] .......................... 2-41
Fig. 2.3.29 Setting of serial I/O2 transmission data [Output of serial data]........................ 2-41
Fig. 2.3.30 Control procedure of serial I/O2 [Output of serial data] .................................... 2-42
Fig. 2.3.31 Connection diagram
[Cyclic transmission or reception of block data between microcomputers]..2-43
Fig. 2.3.32
Fig. 2.3.33 Setting of related registers
[Cyclic transmission or reception of block data between microcomputers]..2-44
Fig. 2.3.34 Control in the master unit ....................................................................................... 2-45
Fig. 2.3.35 Control in the slave unit .......................................................................................... 2-46
Fig. 2.3.36 Connection diagram [Communication using UART] ............................................ 2-47
Fig. 2.3.37 Timing chart [Communication using UART] ......................................................... 2-47
Fig. 2.3.38
Fig. 2.3.39
Fig. 2.3.40 Control procedure at a transmitting side [Communication using UART] .......... 2-51
Fig. 2.3.41 Control procedure at a receiving side [Communication using UART] ............. 2-52
Control procedure at a receiving side[Communication using a clock synchronous serial I/O]
Timing chart [Cyclic transmission or reception of block data between microcomputers] ..........
Setting of related registers at a transmitting side [Communication using UART] ........................
Setting of related registers at a receiving side [Communication using UART] ............................
..2-37
2-44
2-49
2-50
Fig. 2.4.1 Memory map of PWM related registers .................................................................. 2-53
Fig. 2.4.2 Structure of PWM control register ............................................................................2-54
Fig. 2.4.3 Structure of PWM prescaler...................................................................................... 2-54
Fig. 2.4.4 Structure of PWM register......................................................................................... 2-55
Fig. 2.4.5 Connection diagram .................................................................................................... 2-56
Fig. 2.4.6 PWM output timing.....................................................................................................2-56
Fig. 2.4.7 Setting of related registers ........................................................................................2-57
Fig. 2.4.8 PWM output .................................................................................................................2-57
Fig. 2.4.9 Control procedure .......................................................................................................2-58
Fig. 2.5.1 Memory map of A-D conversion related registers ................................................ 2-59
Fig. 2.5.2 Structure of AD/DA control register ........................................................................ 2-60
Fig. 2.5.3 Structure of A-D conversion register ...................................................................... 2-60
Fig. 2.5.4 Structure of Interrupt request register 2 ................................................................ 2-61
Fig. 2.5.5 Structure of Interrupt control register 2 ................................................................. 2-61
Fig. 2.5.6 Connection diagram [Conversion of Analog input voltage] ................................. 2-62
Fig. 2.5.7 Setting of related registers [Conversion of Analog input voltage] ..................... 2-62
Fig. 2.5.8 Control procedure [Conversion of Analog input voltage]..................................... 2-63
Fig. 2.6.1 Memory map of processor mode related register ................................................ 2-64
Fig. 2.6.2 Structure of CPU mode register .............................................................................. 2-64
Fig. 2.6.3 Expansion example of ROM and RAM .................................................................. 2-65
Fig. 2.6.4 Read-cycle (OE access, SRAM) ............................................................................. 2-66
Fig. 2.6.5 Read-cycle (OE access, EPROM) .......................................................................... 2-66
Fig. 2.6.6 Write-cycle (W control, SRAM).................................................................................2-67
Fig. 2.6.7 Application example of the ONW function ............................................................. 2-68
3802 GROUP USER’S MANUAL
iii
List of figures
Fig. 2.7.1 Example of Poweron reset circuit ........................................................................... 2-69
Fig. 2.7.2 RAM back-up system ................................................................................................. 2-69
CHAPTER 3 APPENDIX
Fig. 3.1.1 Circuit for measuring output switching characteristics ......................................... 3-13
Fig. 3.1.2 Timing diagram (in single-chip mode) ..................................................................... 3-14
Fig. 3.1.3 Timing diagram (in memory expansion mode and microprocessor mode) (1) .. 3-15
Fig. 3.1.4 Timing diagram (in memory expansion mode and microprocessor mode) (2) .. 3-16
Fig. 3.2.1 Power source current characteristic example ....................................................... 3-17
Fig. 3.2.2 Power source current characteristic example (in wait mode) ............................. 3-17
Fig. 3.2.3 Standard characteristic example of CMOS output port at P-channel drive(1) . 3-18
Fig. 3.2.4 Standard characteristic example of CMOS output port at P-channel drive(2) . 3-18
Fig. 3.2.5 Standard characteristic example of CMOS output port at N-channel drive(1) . 3-19
Fig. 3.2.6 Standard characteristic example of CMOS output port at N-channel drive(2) . 3-19
Fig. 3.2.7 A-D conversion standard characteristics ................................................................ 3-20
Fig. 3.2.8 D-A conversion standard characteristics ................................................................ 3-21
Fig. 3.3.1 Structure of interrupt control register 2 ................................................................. 3-22
Fig. 3.4.1 Wiring for the RESET pin ......................................................................................... 3-28
Fig. 3.4.2 Wiring for clock I/O pins ........................................................................................... 3-29
Fig. 3.4.3 Wiring for the VPP pin of the One Time PROM and the EPROM version ....... 3-29
Fig. 3.4.4 Bypass capacitor across the VSS line and the VCC line..................................... 3-29
Fig. 3.4.5 Analog signal line and a resistor and a capacitor ............................................... 3-30
Fig. 3.4.6 Wiring for a large current signal line ..................................................................... 3-30
Fig. 3.4.7 Wiring to a signal line where potential levels change frequently ...................... 3-30
Fig. 3.4.8 Stepup for I/O ports ................................................................................................... 3-31
Fig. 3.4.9 Watchdog timer by software ..................................................................................... 3-31
Fig. 3.5.1 Structure of Port Pi (i=0, 1, 2, 3, 4, 5, 6)............................................................. 3-33
Fig. 3.5.2 Structure of Port Pi direction register (i=0, 1, 2, 3, 4, 5, 6) .............................. 3-33
Fig. 3.5.3 Structure of Transmit/Receive buffer register ....................................................... 3-34
Fig. 3.5.4 Structure of Serial I/O1 status register .................................................................. 3-34
Fig. 3.5.5 Structure of Serial I/O1 control register ................................................................. 3-35
Fig. 3.5.6 Structure of UART control register ......................................................................... 3-35
Fig. 3.5.7 Structure of Baud rate generator ............................................................................ 3-36
Fig. 3.5.8 Structure of Serial I/O2 control register ................................................................. 3-36
Fig. 3.5.9 Structure of Serial I/O2 register .............................................................................. 3-37
Fig. 3.5.10 Structure of Prescaler 12, Prescaler X, Prescaler Y ......................................... 3-37
Fig. 3.5.11 Structure of Timer 1 ................................................................................................ 3-38
Fig. 3.5.12 Structure of Timer 2, Timer X, Timer Y .............................................................. 3-38
Fig. 3.5.13 Structure of Timer XY mode register ................................................................... 3-39
Fig. 3.5.14 Structure of PWM control register ........................................................................ 3-40
Fig. 3.5.15 Structure of PWM prescaler ................................................................................... 3-40
Fig. 3.5.16 Structure of PWM register ....................................................................................... 3-41
Fig. 3.5.17 Structure of AD/DA control register ...................................................................... 3-42
Fig. 3.5.18 Structure of A-D conversion register ..................................................................... 3-42
Fig. 3.5.19 Structure of D-A 1 conversion, D-A 2 conversion register ................................ 3-43
Fig. 3.5.20 Structure of Interrupt edge selection register ...................................................... 3-43
Fig. 3.5.21 Structure of CPU mode register ............................................................................. 3-44
iv
3802 GROUP USER’S MANUAL
List of figures
Fig. 3.5.22 Structure of Interrupt request register 1 ............................................................... 3-45
Fig. 3.5.23 Structure of Interrupt request register 2 ............................................................... 3-45
Fig. 3.5.24 Structure of Interrupt control register 1 ................................................................ 3-46
Fig. 3.5.25 Structure of Interrupt control register 2 ................................................................ 3-46
3802 GROUP USER’S MANUAL
v
CHAPTER 1 HARDWARE
Table 1 Pin description.................................................................................................................. 1- 5
Table 2 List of supported products.............................................................................................. 1- 7
Table 3 List of supported products (Extended operating temperature version)................... 1- 8
Table 4 Push and pop instructions of accumulator or processor status register .............. 1-10
Table 5 Set and clear instructions of each bit of processor status register ...................... 1-11
Table 6 List of I/O port functions .............................................................................................. 1-15
Table 7 Interrupt vector addresses and priority ..................................................................... 1-18
Table 8 Functions of ports in memory expansion mode and microprocessor mode ........ 1-35
Table 9 Programming adapter ....................................................................................................1-38
Table 10 Interrupt sources, vector addresses and interrupt priority.................................... 1-39
Table 11 Change of A-D conversion register during A-D conversion ................................. 1-41
CHAPTER 2 APPLICATION
Table 2.1.1 Handling of unused pins (in single-chip mode) .................................................... 2 -4
Table 2.1.2 Handling of unused pins (
List of tables
in memory expansion mode and microprocessor mode
List of tables
)......... 2 -4
Table 2.2.1 Function of CNTR0/CNTR1 edge switch bit .......................................................... 2 -8
Table 2.3.1
Setting examples of Baud rate generator values and transfer bit rate values
CHAPTER 3 APPENDIX
Table 3.1.1 Absolute maximum ratings .......................................................................................3-2
Table 3.1.2 Recommended operating conditions ....................................................................... 3-2
Table 3.1.3 Electrical characteristics ........................................................................................... 3- 3
Table 3.1.4 A-D converter characteristics................................................................................... 3 -3
Table 3.1.5 D-A converter characteristics................................................................................... 3 -4
Table 3.1.6 Timing requirements ................................................................................................. 3- 5
Table 3.1.7 Timing requirements (2) ........................................................................................... 3 -5
Table 3.1.8 Switching characteristics (1) .................................................................................... 3- 6
Table 3.1.9 Switching characteristics (2) .................................................................................... 3- 6
Table 3.1.10
Table 3.1.11
Table 3.1.12
Table 3.1.13
Table 3.1.14 Absolute maximum ratings (Extended operating temperature version) .......... 3 -9
Table 3.1.15 Recommended operating conditions (
Table 3.1.16 Electrical characteristics (Extended operating temperature version) ............ 3-10
Table 3.1.17 A-D converter characteristics (Extended operating temperature version) ....3-10
Table 3.1.18 D-A converter characteristics (Extended operating temperature version) ....3-11
Table 3.1.19 Timing requirements (Extended operating temperature version) ................... 3-12
Table 3.1.20 Switching characteristics (Extended operating temperature version) ........... 3-12
Timing requirements in memory expansion mode and microprocessor mode (1) .....................
Switching characteristics in memory expansion mode and microprocessor mode (1) ............
Timing requirements in memory expansion mode and microprocessor mode (2) .....................
Switching characteristics in memory expansion mode and microprocessor mode (2) ............
...................... 2-48
3-7
3-7
3-8
3-8
Extended operating temperature version
) ...... 3 -9
3802 GROUP USER’S MANUAL
i
List of tables
Table 3.1.21 Timing requirements in memory expansion mode and microprocessor mode
(Extended operating temperature version) .................................................. 3-13
Table 3.1.22 Switching characteristics in memory expansion mode and microprocessor mode
(Extended operating temperature version) .................................................. 3-13
Table 3.3.1 Programming adapter ..............................................................................................3-26
Table 3.3.2 Setting of programming adapter switch .............................................................. 3-26
Table 3.3.3 Setting of PROM programmer address ............................................................... 3-27
Table 3.5.1 Function of CNTR0/CNTR1 edge switch bit ....................................................... 3-39
ii
3802 GROUP USER’S MANUAL
CHAPTER 1CHAPTER 1
HARDWARE
DESCRIPTION
FEATURES
APPLICATIONS
PIN CONFIGURATION
FUNCTIONAL BLOCK
PIN DESCRIPTION
PART NUMBERING
GROUP EXPANSION
FUNCTIONAL DESCRIPTION
NOTES ON PROGRAMMING
DATA REQUIRED FOR
MASK ORDERS
ROM PROGRAMMING METHOD
FUNCTIONAL DESCRIPTION
SUPPLEMENT
HARDWARE
DESCRIPTION/FEATURES/APPLICATIONS/PIN CONFIGURATION
DESCRIPTION
The 3802 group is the 8-bit microcomputer based on the 740 family core technology.
The 3802 group is designed for controlling systems that require
analog signal processing and include two serial I/O functions, A-D
converters, and D-A converters.
The various microcomputers in the 3802 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
For details on availability of microcomputers in the 3802 group, refer to the section on group expansion.
FEATURES
Basic machine-language instructions....................................... 71
•
The minimum instruction execution time ............................ 0.5 µs
•
(at 8 MHz oscillation frequency)
Memory size
•
ROM .................................................................. 8 K to 32 K bytes
RAM ................................................................. 384 to 1024 bytes
PIN CONFIGURATION (TOP VIEW)
2
/AD3
P01/AD1
P03
P00/AD0
P02/AD
Programmable input/output ports ............................................. 56
•
Interrupts .................................................. 16 sources, 16 vectors
•
Timers ............................................................................. 8 bit ✕ 4
•
Serial I/O1 .................... 8-bit ✕ 1 (UART or Clock-synchronized)
•
Serial I/O2 ....................................8-bit ✕ 1 (Clock-synchronized)
•
PWM................................................................................ 8-bit ✕ 1
•
A-D converter .................................................. 8-bit ✕ 8 channels
•
D-A converter.................................................. 8-bit ✕ 2 channels
•
Clock generating circuit ....................... Internal feedback resistor
•
(connect to external ceramic resonator or quartz-crystal oscillator)
Power source voltage..................................................3.0 to 5.5 V
•
(Extended operating temperature version : 4.0 to 5.5 V)
Power dissipation............................................................... 32 mW
•
Memory expansion possible
•
Operating temperature range .................................... –20 to 85°C
•
(Extended operating temperature version : –40 to 85°C)
APPLICATIONS
Office automation, VCRs, tuners, musical instruments, cameras,
air conditioners, etc.
7
P04/AD4
/AD8
P06/AD6
P10
P05/AD5
P07/AD
/AD13
P12/AD10
P14/AD12
P16/AD14
P13/AD11
P15
P11/AD9
P17/AD15
P37/RD
P36/WR
P35/SYNC
P34/φ
P33/RESETOUT
P32/ONW
P31/DA2
P30/DA1
VCC
VREF
SS
AV
7
/AN
7
P6
6
/AN
6
P6
P65/AN5
P64/AN4
P63 /AN3
Fig. 1 Pin configuration of M38022M4-XXXFP
38
39
45
46
48
47
49
50
51
52
53
54
55
56
M38022M4-XXXFP
57
58
59
60
61
62
63
64
123
4
/AN2
/AN1
/INT3
P60/AN0
P62
P61
P57
41
44
43
42
56789
0
/PWM
/SRDY2
/CNTR1
5
P56
P53
P54/CNTR
P5
40
P52/SCLK2
10
P51/SOUT2
37
35
36
34
11
12
131415
D
/SIN2
P50
/SRDY1
P47
P46/SCLK1
4/RXD
P45/TX
P4
Package type : 64P6N-A
64-pin plastic-molded QFP
33
32
P20/DB0
31
P21/DB1
30
P22/DB2
29
P23/DB3
28
P24/DB4
27
P25/DB5
26
P26/DB6
25
P27/DB7
24
VSS
23
XOUT
22
XIN
21
P40/INT4
20
P41/INT0
19
18
17
16
/INT2
3
P4
RESET
CNVSS
P42/INT1
1-2
3802 GROUP USER’S MANUAL
PIN CONFIGURATION (TOP VIEW)
HARDWARE
PIN CONFIGURATION
V
V
AV
P67/AN
P66/AN
P65/AN
P64/AN
P63/AN
2
/AN
P6
1
/AN
P6
P60/AN
P57/INT
P56/PWM
P5
5
/CNTR
P54/CNTR
/S
RDY2
P5
3
2/SCLK2
P5
P51/S
OUT2
P50/S
P47/S
RDY1
P46/S
CLK1
5/TX
P4
P44/R
3
/INT
P4
P42/INT
CNV
RESET
P41/INT
P40/INT
X
V
REF
IN2
X
X
OUT
CC
1
2
SS
7
6
5
4
3
2
1
0
3
3
4
5
6
7
8
9
10
11
12
M38022M4-XXXSP
13
14
1
15
0
16
17
18
19
20
21
D
D
SS
22
23
24
2
25
1
26
27
28
0
29
4
IN
30
31
SS
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P3
0
/DA
1
P31/DA
2
P32/ONW
P33/RESET
P34/φ
P3
5
/SYNC
/WR
6
P3
/RD
7
P3
P00/AD
0
P01/AD
1
P02/AD
2
3
P03/AD
P04/AD
4
P05/AD
5
P06/AD
6
7
P07/AD
0
/AD
8
P1
P11/AD
9
P12/AD
10
P13/AD
11
P14/AD
12
P15/AD
13
14
P16/AD
15
P17/AD
P20/DB
0
P21/DB
1
P22/DB
2
P23/DB
3
P24/DB
4
P25/DB
5
P26/DB
6
P27/DB
7
OUT
64-pin shrink plastic-molded DIP
Fig.2 Pin configuration of M38022M4-XXXSP
Package type : 64P4B
3802 GROUP USER'S MANUAL
1-3
HARDWARE
CNTR1
CNTR
0
VREF AVSS
RAM
ROM
CPU
A
X
Y
S
PC
H
PCL
PS
VSS
32
RESET
27
VCC
1
26
CNVSS
P0(8)
49 50 51
52 53
54
55
56
P1(8)
41
43 45
47
42 44
46
48
P2(8)
33 35 37 39
36
38 40
P3(8)
57 59
61 63
58 60
62 64
P4(8)
20 22
24 28
21 23
25
29
P5(8)
12 14
16 18
13
15
17
19
P6(8)
46
10
59
11
3
34
2
XIN
30
XOUT
31
D-A
(8)
D-A
(8)
A-D
(8)
Reset input
Clock generating circuit
Clock input Clock output
Prescaler 12 (8)
Timer 1 (8)
Timer 2 (8)
I/O port P4 I/O port P0I/O port P1I/O port P2I/O port P3
I/O port P5
I/O port P6
7 8
SI/O1 (8)
INT0INT2
INT4
Prescaler X (8)
Timer X (8)
Prescaler Y (8)
Timer Y (8)
converter 2
converter 1
~
SI/O2 (8)
PWM (8)
INT3
converter
FUNCTIONAL BLOCK
FUNCTIONAL BLOCK
FUNCTIONAL BLOCK DIAGRAM (Package : 64P4B)
Fig. 3 Functional block diagram
1-4
3802 GROUP USER’S MANUAL
PIN DESCRIPTION
Table 1. Pin description
HARDWARE
PIN DESCRIPTION
Pin
VCC, VSS
CNVSS
VREF
AVSS
RESET
XIN
XOUT
P00–P07
P10–P17
P20–P27
P30/DA1,
P31/DA2
Name
Power source
CNVSS
Analog reference
voltage
Analog power
source
Reset input
Clock input
Clock output
I/O port P0
I/O port P1
I/O port P2
I/O port P3
Function
Function except a port function
• Apply voltage of 3.0 V–5.5 V to VCC, and 0 V to VSS.
(Extended operating temperature version : 4.0 V to 5.5 V)
• This pin controls the operation mode of the chip.
• Normally connected to VSS.
• If this pin is connected to VCC, the internal ROM is inhibited and external memory is accessed.
• Reference voltage input pin for A-D and D-A converters
• GND input pin for A-D and D-A converters
• Connect to VSS.
• Reset input pin for active “L”
• Input and output signals for the clock generating circuit.
• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the
oscillation frequency.
• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• The clock is used as the oscillating source of system clock.
• 8 bit CMOS I/O port
• I/O direction register allows each pin to be individually programmed as either input or output.
• At reset this port is set to input mode.
• In modes other than single-chip, these pins are used as address, data, and control bus I/O pins.
• CMOS compatible input level
• CMOS 3-state output structure
• D–A conversion output pins
P32–P37
P40/INT4,
P41/INT0,
P42/INT1,
P43/INT2
P44/RXD,
P45/TXD,
P46/SCLK1,
P47/SRDY1
P50/SIN2,
P51/SOUT2,
P52/SCLK2,
P53/SRDY2
P54/CNTR0,
P55/CNTR1
P56/PWM
P57/INT3
P60/AN0–
P67/AN7
I/O port P4
I/O port P5
I/O port P6
• 8-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
• CMOS 3-state output structure
• 8-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
• CMOS 3-state output structure
• 8-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
• CMOS 3-state output structure
• External interrupt input pin
• Serial I/O1 I/O pins
• Serial I/O2 I/O pins
• Timer X and Timer Y I/O pins
• PWM output pin
• External interrupt input pin
• A-D conversion input pins
3802 GROUP USER'S MANUAL
1-5
HARDWARE
PART NUMBERING
PART NUMBERING
Product
M3802 2 M 4 - XXX SP
Package type
SP : 64P4B package
FP : 64P6N-A package
SS : 64S1B-E package
FS : 64D0 package
ROM number
Omitted in some types.
Normally, using hyphen.
When electrical characteristic, or division of quality
identification code using alphanumeric character
– : standard
D : Extended operating temperature version
ROM/PROM size
: 4096 bytes
1
: 8192 bytes
2
: 12288 bytes
3
: 16384 bytes
4
: 20480 bytes
5
: 24576 bytes
6
: 28672 bytes
7
: 32768 bytes
8
Fig.4 Part numbering
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used.
Memory type
M
: Mask ROM version
E
: EPROM or One Time PROM version
RAM size
: 192 bytes
0
: 256 bytes
1
: 384 bytes
2
: 512 bytes
3
: 640 bytes
4
: 768 bytes
5
: 896 bytes
6
: 1024 bytes
7
1-6
3802 GROUP USER’S MANUAL
HARDWARE
GROUP EXPANSION
GROUP EXPANSION
Mitsubishi plans to expand the 3802 group as follows:
(1) Support for mask ROM, One Time PROM, and EPROM
versions
ROM/PROM capacity................................... 8 K to 32 K bytes
RAM capacity .............................................. 384 to 1024 bytes
Memory Expansion Plan
ROM size (bytes)
32K
28K
Mass product
24K
20K
Mass product
16K
12K
Mass product
8K
M38022M4
M38022M2
(2) Packages
64P4B ............................................ Shrink plastic molded DIP
64P6N-A................................................... Plastic molded QFP
64S1B-E.................................................... Shrink ceramic DIP
64D0................................................................... Ceramic LCC
Mass product
M38027M8/E8
M38024M6
4K
192
256 384 512 640 768 896 1024
Fig. 5 Memory expansion plan
Currently supported products are listed below
Table 2. List of supported products
Product
M38022M2-XXXSP
M38022M2-XXXFP
M38022M4-XXXSP
M38022M4-XXXFP
M38024M6-XXXSP
M38024M6-XXXFP
M38027M8-XXXSP
M38027E8-XXXSP
M38027E8SP
M38027M8-XXXFP
M38027E8-XXXFP
M38027E8FP
M38027E8SS
M38027E8FS
(P) ROM size (bytes)
ROM size for User in ( )
8192
(8062)
16384
(16254)
24576
(24446)
32768
(32638)
RAM size (bytes)
RAM size (bytes)
384
384
640
1024
Package
64P4B
64P6N-A
64P4B
64P6N-A
64P4B
64P6N-A
64P4B
64P6N-A
64S1B-E
64D0
As of May 1996
Remarks
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
One Time PROM version
One Time PROM version (blank)
Mask ROM version
One Time PROM version
One Time PROM version (blank)
EPROM version
EPROM version
3802 GROUP USER'S MANUAL
1-7
HARDWARE
GROUP EXPANSION
GROUP EXPANSION (Extended operating temperature version)
Mitsubishi plans to expand the 3802 group (extended operating
temperature version) as follows:
(1) Support for mask ROM One Time PROM, and EPROM ver-
sions
ROM/PROM capacity................................... 8 K to 32 K bytes
RAM capacity .............................................. 384 to 1024 bytes
(2) Packages
64P4B ............................................ Shrink plastic molded DIP
64P6N-A................................................... Plastic molded QFP
Memory Expansion Plan (Extended operating temperature version)
ROM size (bytes)
32K
28K
24K
20K
Mass product
16K
12K
Mass product
8K
M38022M4D
M38022M2D
Mass product
M38027M8D/E8D
4K
192
256 384 512 640 768 896 1024
RAM size (bytes)
Fig. 6 Memory expansion plan (Extended operating temperature version)
Currently supported products are listed below.
Table 3. List of supported products (Extended operating temperature version)
Product
M38022M2DXXXSP
M38022M2DXXXFP
M38022M4DXXXSP
M38022M4DXXXFP
M38027M8DXXXSP
M38027E8DXXXSP
M38027E8DSP
M38027M8DXXXFP
M38027E8DXXXFP
M38027E8DFP
(P) ROM size (bytes)
8192
(8062)
16384
(16254)
32768
(32638)
RAM size (bytes)
384
384
1024
Package
64P4B
64P6N-A
64P4B
64P6N-A
64P4B
64P6N-A
As of May 1996
Remarks
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
One Time PROM version
One Time PROM version (blank)
Mask ROM version
One Time PROM version
One Time PROM version (blank)
1-8
3802 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The 3802 group uses the standard 740 family instruction set. Refer
to the table of 740 family addressing modes and machine instructions or the SERIES 740 <Software> User´s Manual for details on
the instruction set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instructions cannot be used.
The MUL, DIV, WIT and STP instruction can be used.
The central processing unit (CPU) has the six registers.
Accumulator (A)
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
Index register X (X), Index register Y (Y)
Both index register X and index register Y are 8-bit registers. In the
index addressing modes, the value of the OPERAND is added to the
contents of register X or register Y and specifies the real address.
When the T flag in the processor status register is set to “1”, the
value contained in index register X becomes the address for the second OPERAND.
Stack pointer (S)
The stack pointer is an 8-bit register used during sub-routine calls
and interrupts. The stack is used to store the current address data
and processor status when branching to subroutines or interrupt routines.
The lower eight bits of the stack address are determined by the contents of the stack pointer. The upper eight bits of the stack address
are determined by the Stack Page Selection Bit. If the Stack Page
Selection Bit is “0”, then the RAM in the zero page is used as the
stack area. If the Stack Page Selection Bit is “1”, then RAM in page
1 is used as the stack area.
The Stack Page Selection Bit is located in the SFR area in the zero
page. Note that the initial value of the Stack Page Selection Bit varies with each microcomputer type. Also some microcomputer types
have no Stack Page Selection Bit and the upper eight bits of the
stack address are fixed. The operations of pushing register contents
onto the stack and popping them from the stack are shown in Fig.7.
Program counter (PC)
The program counter is a 16-bit counter consisting of two 8-bit registers
PC
H and PCL. It is used to indicate the address of the next instruction to
be executed.
b15
PC
b7
A
b7
X
b7
Y
b7
S
b7
H
b7
PC
b0
Accumulator
b0
Index Register X
b0
Index Register Y
b0
Stack Pointer
b0
L
Program Counter
b0
Processor Status Register (PS)
CZIDBTVN
Carry Flag
Zero Flag
Interrupt Disable Flag
Decimal Mode Flag
Break Flag
Index X Mode Flag
Fig. 7. 740 Family CPU register structure
Overflow Flag
Negative Flag
3802 GROUP USER’S MANUAL
1-9
HARDWARE
FUNCTIONAL DESCRIPTION
On-going Routine
Store Return Address
on Stack (Note 2)
Restore Return
Address
Interrupt request
M (S) (PCH)
(S)
M (S) (PCL)
(S)
Subroutine
Execute RTS
(S)
(PCL) M (S)
(S)
(PCH) M (S)
(S – 1)
(S – 1)
(S + 1)
(S + 1)
(Note 1)
Execute JSR
M (S) (PCH)
(S)
(S – 1)
M (S) (PCL)
(S)
(S – 1)
M (S) (PS)
(S)
(S – 1)
Interrupt
Service Routine
Execute RTI
(S)
(S + 1)
(PS) M (S)
(S)
(S + 1)
(PCL) M (S)
(S)
(S + 1)
Store Return Address
on Stack (Note 2)
Store Contents of Processor
Status Register on Stack
I Flag “0” to “1”
Fetch the Jump Vector
Restore Contents of
Processor Status Register
Restore Return
Address
Note 1 : The condition to enable the interrupt Interrupt enable bit is “1”
2 : When an interrupt occurs, the address of the next instruction to be executed is stored in
the stack area. When a subroutine is called, the address one before the next instruction
to be executed is stored in the stack area.
Fig. 8. Register push and pop at interrupt generation and subroutine call
Table. 4. Push and pop instructions of accumulator or processor status register
Push instruction to stack
Accumulator
Processor status register
PHA
PHP
Interrupt disable flag is “0”
(PCH) M (S)
Pop instruction from stack
PLA
PLP
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3802 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
Processor status register (PS)
The processor status register is an 8-bit register consisting of flags
which indicate the status of the processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C)
flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid.
After reset, the Interrupt disable (I) flag is set to “1”, but all other flags
are undefined. Since the Index X mode (T) and Decimal mode (D)
flags directly affect arithmetic operations, they should be initialized in
the beginning of a program.
(1) Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
(2) Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
(3) Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
When an interrupt occurs, this flag is automatically set to “1” to
prevent other interrupts from interfering until the current interrupt
is serviced.
(4) Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
(5) Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”. The saved processor
status is the only place where the break flag is ever set.
(6) Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory, e.g. the results of an
operation between two memory locations is stored in the
accumulator. When the T flag is “1”, direct arithmetic operations
and direct data transfers are enabled between memory locations,
i.e. between memory and memory, memory and I/O, and I/O and
I/O. In this case, the result of an arithmetic operation performed
on data in memory location 1 and memory location 2 is stored in
memory location 1. The address of memory location 1 is
specified by index register X, and the address of memory
location 2 is specified by normal addressing modes.
(7) Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
(8) Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table. 5. Set and clear instructions of each bit of processor status register
C flag Z flag I flag D flag B flag T flag V flag N flag
Set instruction
Clear instruction
SEC
CLC
_
_
SEI
CLI
SED
CLD
_
_
SET
CLT CLV
_
_
_
3802 GROUP USER’S MANUAL
1-11
HARDWARE
FUNCTIONAL DESCRIPTION
CPU Mode Register
The CPU mode register is allocated at address 003B16. The CPU mode
register contains the stack page selection bit.
b7
Fig. 9. Structure of CPU mode register
b0
CPU mode register
(
CPUM : address
003B16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Not available
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (return “0” when read)
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3802 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
Memory
Special function register (SFR) area
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM capacity
(bytes)
192
256
384
512
640
768
896
1024
Address
XXXX
00FF
013F
01BF
023F
02BF
033F
03BF
043F
16
16
16
16
16
16
16
16
16
Zero page
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function registers (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
Special page
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page
addressing mode.
0000
RAM
0040
0100
XXXX
16
16
16
16
SFR area
Zero page
Reserved area
ROM area
ROM capacity
(bytes)
4096
8192
12288
16384
20480
24576
28672
32768
Fig. 10 Memory map diagram
Address
YYYY
F000
E000
D000
C000
B000
A000
9000
8000
0440
16
Not used
16
16
16
16
16
16
16
16
16
Address
ZZZZ
F080
E080
D080
C080
B080
A080
9080
8080
16
16
16
16
16
16
16
16
16
ROM
YYYY
ZZZZ
FF00
FFDC
FFFE
FFFF
16
Reserved ROM area
(128 bytes)
16
16
16
Interrupt vector area
16
Reserved ROM area
16
Special page
3802 GROUP USER’S MANUAL
1-13
HARDWARE
FUNCTIONAL DESCRIPTION
Port P0 (P0)
0000
16
Port P0 direction register (P0D)
0001
16
Port P1 (P1)
0002
16
Port P1 direction register (P1D)
0003
16
Port P2 (P2)
0004
16
Port P2 direction register (P2D)
0005
16
Port P3 (P3)
0006
16
Port P3 direction register (P3D)
0007
16
Port P4 (P4)
0008
16
Port P4 direction register (P4D)
0009
16
Port P5 (P5)
000A
16
Port P5 direction register (P5D)
000B
16
Port P6 (P6)
000C
16
Port P6 direction register (P6D)
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
Transmit/Receive buffer register (TB/RB)
0018
16
Serial I/O1 status register (SIO1STS)
0019
16
Serial I/O1 control register (SIO1CON)
001A
16
UART control register (UARTCON)
001B
16
Baud rate generator (BRG)
001C
16
Serial I/O2 control register (SIO2CON)
001D
16
001E
16
Serial I/O2 register (SIO2)
001F
16
Prescaler 12 (PRE12)
0020
16
Timer 1 (T1)
0021
16
Timer 2 (T2)
0022
16
Timer XY mode register (TM)
0023
16
Prescaler X (PREX)
0024
16
Timer X (TX)
0025
16
Prescaler Y (PREY)
0026
16
Timer Y (TY)
0027
16
0028
16
0029
16
002A
16
PWM control register (PWMCON)
002B
16
PMW prescaler (PREPWM)
002C
16
002D
16
PWM register (PWM)
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
AD/DA control register (ADCON)
0034
16
A-D conversion register (AD)
0035
16
D-A1 conversion register (DA1)
0036
16
D-A2 conversion register (DA2)
0037
16
0038
16
0039
16
Interrupt edge selection register
003A
16
CPU mode register (CPUM)
003B
16
Interrupt request register 1(IREQ1)
003C
16
Interrupt request register 2(IREQ2)
003D
16
Interrupt control register 1(ICON1)
003E
16
Interrupt control register 2(ICON2)
003F
16
(INTEDGE)
Fig. 11 Memory map of special function register (SFR)
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3802 GROUP USER’S MANUAL
HARDWARE
FUNCTIONAL DESCRIPTION
I/O Ports
Direction registers
The 3802 group has 56 programmable I/O pins arranged in seven
I/O ports (ports P0 to P6). The I/O ports have direction registers
which determine the input/output direction of each individual pin.
Each bit in a direction register corresponds to one pin, each pin
can be set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin becomes an input pin. When “1” is written to that bit, that pin becomes an output pin.
Table 6. list of I/O port functions
Pin
P00–P07
P10–P17
P20–P27
P30/DA1
P31/DA2
P32–P37
P40/INT4,
P41/INT0,
P43/INT2
P44/RXD,
P45/TXD,
P46/SCLK1,
P47/SRDY1
P50/SIN2,
P51/SOUT2,
P52/SCLK2,
P53/SRDY2
P54/CNTR0,
P55/CNTR1
P56/PWM
P57/INT3
P60/AN0–
P67/AN7
Note 1: For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as func-
tion I/O ports, refer to the applicable sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
Name
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Input/Output
Input/output,
individual bits
Input/output,
individual bits
Input/output,
individual bits
Input/output,
individual bits
Input/output,
individual bits
Input/output,
individual bits
Input/output,
individual bits
I/O Format
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
Non-Port Function
Address low-order byte
output
Address high-order
byte output
Data bus I/O
D-A conversion output
Control signal I/O
External interrupt input
Serial I/O1 function I/O
Serial I/O2 function I/O
Timer X and Timer Y
function I/O
PWM output
External interrupt input
A-D conversion input
Related SFRs
CPU mode register
CPU mode register
CPU mode register
AD/DA control register
CPU mode register
CPU mode register
Interrupt edge selection
register
Serial I/O1 control
register
UART control register
Serial I/O2 control
register
Timer XY mode register
PWM control register
Interrupt edge selection register
Ref.No.
(1)
(2)
(1)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(3)
(14)
3802 GROUP USER’S MANUAL
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