Mitsubishi M37702S1BFP, M37702S1AFP, M37702M2BXXXFP, M37702M2AXXXFP Datasheet
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702M2-XXXFP and
M37702S1FP are respectively
unified into M37702M2AXXXFP
and M37702S1AFP.
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DESCRIPTION
The M37702M2AXXXFP is a single-chip microcomputers
designed with high-performance CMOS silicon gate technology.
This is housed in a 80-pin plastic molded QFP. This single-chip
microcomputer has a large 16 M bytes address space, three instruction queue buffers, and two data buffers for high-speed
instruction execution. The CPU is a 16-bit parallel processor that
can also be switched to perform 8-bit parallel processing. This
microcomputer is suitable for office, business, and industrial
equipment controller that require high-speed processing of large
data.
The differences between M37702M2AXXXFP, M37702M2BXXXFP,
M37702S1AFP and M37702S1BFP are the ROM size and the external clock input frequency as shown below. Therefore, the
following descriptions will be for the M37702M2AXXXFP unless
otherwise noted.
Type name
M37702M2AXXXFP
M37702M2BXXXFP
M37702S1AFP
M37702S1BFP
ROM size
16 K bytes
16 K bytes
External
External
External clock input frequency
16 MHz
25 MHz
16 MHz
25 MHz
FEATURES
• Number of basic instructions ..................................................103
• Memory size ROM ................................................ 16 K bytes
RAM ................................................. 512 bytes
• Instruction execution time
M37702M2AXXXFP, M37702S1AFP
(The fastest instruction at 16 MHz frequency) .................. 250 ns
M37702M2BXXXFP, M37702S1BFP
(The fastest instruction at 25 MHz frequency) .................. 160 ns
• Single power supply..................................................... 5 V ± 10%
• Low power dissipation (at 16 MHz frequency)
......................................... 60 mW ( Typ.)
• Interrupts............................................................19 types 7 levels
• Multiple function 16-bit timer ................................................ 5 + 3
• UART (may also be synchronous).............................................. 2
• 8-bit A-D converter ............................................. 8-channel inputs
• 12-bit watchdog timer.
• Programmable input/output
(ports P0, P1, P2, P3, P4, P5, P6, P7, P8) .............................. 68
APPLICATION
Control devices for office equipment such as copiers, printers,
typewriters, facsimiles, word processors, and personal computers
Control devices for industrial equipment such as ME, NC, communication and measuring instruments.
NOTE
Refer to “Chapter 5 PRECAUTIONS” when using this microcomputer.
The M37702M2AXXXFP and M37702S1AFP satisfy the timing
requirements and the switching characteristics of the former
M37702M2-XXXFP and M37702S1FP.
PIN CONFIGURATION (TOP VIEW)
P83/TXD
0
P82/RXD
0
P81/CLK
0
/CTS0/RTS
P76/AN
P75/AN
P74/AN
P73/AN
P72/AN
P71/AN
0
0
V
CC
AV
CC
V
REF
AV
SS
V
SS
TRG
6
5
4
3
2
1
P8
P77/AN7/AD
1
RTS
/
1
CTS
/
4
P8
64
65
66
67
6
8
69
70
71
72
73
74
75
76
77
78
79
80
1
0
/AN
0
P7
1
1
1
D
D
/CLK
5
P8
63
2
IN
/TB2
7
P6
X
/R
6
P8
62
3
IN
/TB1
6
P6
X
/T
7
P8
61
4
IN
/TB0
5
P6
0
1
A
A
/
/
0
1
P0
P0
59
60
6
5
2
1
NT
NT
/I
/I
4
3
P6
P6
6
2
A
/
2
P0
58
M37702M2AXXXFP
M37702M2BXXXFP
7
0
NT
/I
2
P6
7
3
4
5
A
A
A
/
/
/
/A
/A
3
4
5
6
7
P0
P0
P0
P0
P0
56
54
55
53
57
or
or
M37702S1AFP
or
M37702S1BFP
8
10
12
9
11
IN
IN
IN
OUT
OUT
/TA4
/TA3
/TA2
1
7
5
/TA4
/TA3
0
6
P6
P5
P5
P6
P5
Outline 80P6N-A
✽ : Used in the evaluation chip mode only
8
/D
8
/A
0
P1
52
13
OUT
/TA2
4
P5
9
/D
9
/A
1
P1
51
14
IN
/TA1
3
P5
10
/D
10
/A
2
P1
50
15
OUT
/TA1
2
P5
11
/D
11
/A
3
P1
49
16
IN
/TA0
1
P5
12
/D
12
/A
4
P1
48
17
OUT
/TA0
0
P5
13
/D
13
/A
5
P1
47
18
✽
/DBC
7
P4
14
/D
14
/A
6
P1
46
19
✽
/VPA
6
P4
15
/D
15
/A
7
P1
45
20
✽
/VDA
5
P4
0
/D
16
/A
0
P2
44
21
✽
/QCL
4
P4
43
22
✽
1
/D
17
/A
1
P2
/MX
3
P4
2
3
/D
/D
18
19
/A
/A
2
3
P2
P2
41
42
40
P24/A20/D
P25/A21/D
P26/A22/D
P27/A23/D
P30/
R/W
P31/
BHE
P32/
ALE
P33/
HLDA
V
ss
E
X
OUT
IN
X
RESET
CNV
SS
BYTE
P40/
HOLD
4
5
6
7
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
/ φ
RDY
2
/
1
P4
P4
X
IN
X
OUT
E
RESET
Reset input
V
REF
P8(8) P7(8) P5(8)P6(8) P4(8) P3(4)
P2(8)
P1(8)
CNVss
BYTE
P0(8)
UART1(9)
UART0(9)
AV
SS
(0V)
AV
CC
(0V)
V
SS
V
CC
A-D Converter(8)
Clock input Clock output
Enable output
Reference
voltage input
Bus width
selection input
Clock Generating Circuit
Instruction Register(8)
Arithmetic Logic
Unit(16)
Accumulator A(16)
Accumulator B(16)
Index Register X(16)
Index Register Y(16)
Stack Pointer S(16)
Direct Page Register DPR(16)
Processor Status Register PS(11)
Input Buffer Register IB(16)
Data Bank Register DT(8)
Program Bank Register PG(8)
Program Counter PC(16)
Incrementer/Decrementer(24)
Data Address Register DA(24)
Program Address Register PA(24)
Incrementer(24)
Instruction Queue Buffer Q
2
(8)
Instruction Queue Buffer Q
1
(8)
Instruction Queue Buffer Q
0
(8)
Data Buffer DB
L
(8)
Data Buffer DB
H
(8)
ROM
16K Bytes
RAM
512 Bytes
Timer TA3(16)
Timer TA4(16)
Timer TA2(16)
Timer TA1(16)
Timer TA0(16)
Watchdog Timer
Timer TB2(16)
Timer TB1(16)
Timer TB0(16)
Address Bus
Data Bus(Odd)
Data Bus(Even)
Input/Output
port P8
Input/Output
port P7
Input/Output
port P6
Input/Output
port P5
Input/Output
port P4
Input/Output
port P3
Input/Output
port P2
Input/Output
port P1
Input/Output
port P0
29 30 31 28
69
32 73 27
(5V) (0V)
72 70
(5V)
71 26
60595857565554535251504948474645444342414039383725242322212019181716151413121110987654321807978777675746867666564636261 36353433
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M37702M2AXXXFP BLOCK DIAGRAM
2
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
FUNCTIONS OF M37702M2AXXXFP
Number of basic instructions
Instruction execution time
Memory size
Input/Output ports
Multi-function timers
Serial I/O
A-D converter
Watchdog timer
Interrupts
Clock generating circuit
Supply voltage
Power dissipation
Input/Output characteristic
Memory expansion
Operating temperature range
Device structure
Package
Parameter
M37702M2AXXXFP, M37702S1AFP
M37702M2BXXXFP, M37702S1BFP
ROM
RAM
P0 – P2, P4 – P8
P3
TA0, TA1, TA2, TA3, TA4
TB0, TB1, TB2
Input/Output voltage
Output current
103
250 ns (the fastest instruction at external clock 16 MHz frequency)
160 ns (the fastest instruction at external clock 25 MHz frequency)
16 K bytes
512 bytes
8-bit ✕ 8
4-bit ✕ 1
16-bit ✕ 5
16-bit ✕ 3
(UART or clock synchronous serial I/O) ✕ 2
8-bit ✕ 1 (8 channels)
12-bit ✕ 1
3 external types, 16 internal types
(Each interrupt can be set the priority levels to 0 – 7.)
Built-in (externally connected to a ceramic resonator or quartz
crystal resonator)
5 V ± 10%
60 mW (at external clock 16 MHz frequency)
5 V
5 mA
Maximum 16 M bytes
–20 – 85°C
CMOS high-performance silicon gate process
80-pin plastic molded QFP
Functions
3
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Pin
VCC, VSS
CNVSS
______
RESET
X
IN
XOUT
_
E
BYTE
CC,
AV
AV
SS
VREF
P00 – P07
P10 – P17
P20 – P27
P30 – P37
P40 – P47
P50 – P57
P60 – P67
P70 – P77
P80 – P87
Name
Power supply
CNVSS input
Reset input
Clock input
Clock output
Enable output
Bus width selection
input
Analog supply input
Reference voltage
input
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
I/O port P5
I/O port P6
I/O port P7
I/O port P8
Input/Output
Input
Input
Input
Output
Output
Input
Input
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Functions
Supply 5 V ± 10% to VCC and 0V to VSS.
This pin controls the processor mode. Connect to VSS for single-chip mode, and
CC for external ROM types.
to V
To enter the reset state, this pin must be kept at a “L” condition which should be
maintained for the required time.
These are I/O pins of internal clock generating circuit. Connect a ceramic or quartz
IN
and X
OUT
crystal resonator between X
source should be connected to the X
. When an external clock is used, the clock
IN
pin and the X
OUT
pin should be left open.
Data or instruction read and data write are performed when output from this pin
is “L”.
In memory expansion mode or microprocessor mode, this pin determines
whether the external data bus is 8-bit width or 16-bit width. The width is 16 bits
when “L” signal inputs and 8 bits when “H” signal inputs.
Power supply for the A-D converter. Connect AV
CC to VCC and AVSS to VSS
externally.
This is reference voltage input pin for the A-D converter.
In single-chip mode, port P0 becomes an 8-bit I/O port. An I/O direction register
is available so that each pin can be programmed for input or output. These ports
are in input mode when reset.
Address (A7 – A0) is output in memory expansion mode or microprocessor mode.
In single-chip mode, these pins have the same functions as port P0. When the
BYTE pin is set to “L” in memory expansion mode or microprocessor mode and
external data bus is 16-bit width, high-order data (D15 – D8) is input or output
__
when E output is “L” and an address (A15 – A8) is output when E output is “H”.
If the BYTE pin is “H” that is an external data bus is 8-bit width, only address
(A15 – A8) is output.
In single-chip mode, these pins have the same functions as port P0. In memory
expansion mode or microprocessor mode low-order data (D
output when E output is “L” and an address (A23 – A16) is output when E output
__
7 – D0) is input or
is “H”.
In single-chip mode, these pins have the same functions as port P0. In memory
expansion mode or microprocessor mode, R/W, BHE, ALE and HLDA signals
__ ____
_____
are output.
In single-chip mode, these pins have the same functions as port P0. In memory
expansion mode or microprocessor mode, P40 and P41 become HOLD and RDY
_____
____
input pin respectively. Functions of other pins are the same as in single-chip
mode. In single-chip mode or memory expansion mode, port P42 can be programmed for φ
mode. P4
1 output pin divided the clock to XIN pin by 2. In microprocessor
2 always has the function as φ1 output pin.
In addition to having the same functions as port P0 in single-chip mode, these
pins also function as I/O pins for timer A0, timer A1, timer A2 and timer A3.
In addition to having the same functions as port P0 in single-chip mode, these
pins also function as I/O pins for timer A4, external interrupt input INT0, INT1 and
____
INT2 pins, and input pins for timer B0, timer B1 and timer B2.
____ ____
In addition to having the same functions as port P0 in single-chip mode, these
pins also function as analog input AN
0 – AN7 input pins. P77 also has an A-D
conversion trigger input function.
In addition to having the same functions as port P0 in single-chip mode, these
pins also function as RXD, TXD, CLK, CTS/RTS pins for UART 0 and UART 1.
____ ____
4
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
BASIC FUNCTION BLOCKS
The M37702M2AXXXFP contains the following devices on a
single chip: ROM and RAM for storing instructions and data, CPU
for processing, bus interface unit (which controls instruction
prefetch and data read/write between CPU and memory), timers,
UART, A-D converter, and other peripheral devices such as I/O
ports. Each of these devices are described below.
MEMORY
The memory map is shown in Figure 1. The address space is 16
M bytes from addresses 0
divided into 64 K bytes units called banks. The banks are numbered from 0
16 to FF16.
Built-in ROM, RAM and control registers for built-in peripheral devices are assigned to bank 0
Bank 0
16
Bank 1
16
• • • • • • • • • •
Bank FE
16
Bank FF
16
16 to FFFFFF16. The address space is
16.
000000
16
00FFFF
16
010000
16
01FFFF
16
FE0000
16
FEFFFF
16
FF0000
16
FFFFFF
16
000000
00007F
000080
00027F
00C000
00FFD6
00FFFF
The 16 K bytes area from addresses C000
built-in ROM. Addresses FFD6
16 to FFFF16 are the RESET and
16 to FFFF16 is the
interrupt vector addresses and contain the interrupt vectors. Refer
to the section on interrupts for details.
The 512 bytes area from addresses 80
16 to 27F16 contains the
built-in RAM. In addition to storing data, the RAM is used as stack
during a subroutine call, or interrupts.
Assigned to addresses 0
16 to 7F16 are peripheral devices such as
I/O ports, A-D converter, UART, timer, and interrupt control registers.
A 256 bytes direct page area can be allocated anywhere in bank
0
16 using the direct page register DPR. In direct page addressing
mode, the memory in the direct page area can be accessed with
two words thus reducing program steps.
16
16
16
16
Internal RAM
512 bytes
000000
00007F
16
Peripheral devices
control registers
see Fig. 2 for
further information
16
Interrupt vector table
00FFD6
16
A-D conversion
UART1 transmission
UART1 receive
UART0 transmission
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
16
16
16
Internal ROM
16K bytes
00FFFE
16
Timer A1
Timer A0
INT
2
INT
1
INT
0
Watchdog timer
DBC
BRK instruction
Zero divide
RESET
Fig. 1 Memory map
5
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address (Hexadecimal notation)
000000
000001
000002
000003
000004
000005
000006
000007
000008
000009
00000A
00000B
00000C
00000D
00000E
00000F
000010
000011
000012
Port P0
Port P1
Port P0 data direction register
Port P1 data direction register
Port P2
Port P3
Port P2 data direction register
Port P3 data direction register
Port P4
Port P5
Port P4 data direction register
Port P5 data direction register
Port P6
Port P7
Port P6 data direction register
Port P7 data direction register
Port P8
000013
000014
Port P8 data direction register
000015
000016
000017
000018
000019
00001A
00001B
00001C
00001D
00001E
00001F
000020
A-D control register
A-D sweep pin selection register
A-D register 0
000021
000022
A-D register 1
000023
000024
A-D register 2
000025
000026
A-D register 3
000027
000028
A-D register 4
000029
00002A
A-D register 5
00002B
00002C
A-D register 6
00002D
00002E
A-D register 7
00002F
000030
000031
000032
000033
000034
000035
000036
000037
000038
000039
00003A
00003B
00003C
00003D
00003E
00003F
UART 0 transmit/receive mode register
UART 0 bit rate generator
UART 0 transmission buffer register
UART 0 transmit/receive control register 0
UART 0 transmit/receive control register 1
UART 0 receive buffer register
UART 1 transmit/receive mode register
UART 1 bit rate generator
UART 1 transmission buffer register
UART 1 transmit/receive control register 0
UART 1 transmit/receive control register 1
UART 1 receive buffer register
Address (Hexadecimal notation)
000040
Count start flag
000041
000042
One-shot start flag
000043
000044
Up-down flag
000045
000046
000047
000048
000049
00004A
00004B
00004C
00004D
00004E
00004F
000050
000051
000052
000053
000054
000055
000056
000057
000058
000059
00005A
00005B
00005C
00005D
00005E
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Processor mode register
00005F
000060
000061
Watchdog timer
Watchdog timer frequency selection flag
000062
000063
000064
000065
000066
000067
000068
000069
00006A
00006B
00006C
00006D
00006E
00006F
000070
000071
000072
000073
000074
000075
000076
000077
000078
000079
00007A
00007B
00007C
00007D
00007E
00007F
A-D conversion interrupt control register
UART 0 transmission interrupt control register
UART 0 receive interrupt control register
UART 1 transmission interrupt control register
UART 1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT
0
interrupt control register
INT
1
interrupt control register
INT
2
interrupt control register
Fig. 2 Location of peripheral devices and interrupt control registers
6
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CENTRAL PROCESSING UNIT (CPU)
The CPU has ten registers and is shown in Figure 3. Each of
these registers is described below.
ACCUMULATOR A (A)
Accumulator A is the main register of the microcomputer. It consists of 16 bits and the lower 8 bits can be used separately. The
data length flag m determines whether the register is used as 16bit register or as 8-bit register. It is used as a 16-bit register when
flag m is “0” and as an 8-bit register when flag m is “1”. Flag m is
a part of the processor status register (PS) which is described
later.
Data operations such as calculations, data transfer, input/output,
etc., is executed mainly through the accumulator.
ACCUMULATOR B (B)
Accumulator B has the same functions as accumulator A, but the
use of accumulator B requires more instruction bytes and execution cycles than accumulator A.
INDEX REGISTER X (X)
Index register X consists of 16 bits and the lower 8 bits can be
used separately. The index register length flag x determines
whether the register is used as 16-bit register or as 8-bit register.
It is used as a 16-bit register when flag x is “0” and as an 8-bit reg-
ister when flag x is “1”. Flag x is a part of the processor status register (PS) which is described later.
In index addressing mode, register X is used as the index register
and the contents of this address is added to obtain the real address.
Also, when executing a block transfer instruction MVP or MVN, the
contents of index register X indicate the low-order 16 bits of the
source data address. The third byte of the MVP and MVN is the
high-order 8 bits of the source data address.
INDEX REGISTER Y (Y)
Index register Y consists of 16 bits and the lower 8 bits can be
used separately. The index register length flag x determines
whether the register is used as 16-bit register or as 8-bit register.
It is used as a 16-bit register when flag x is “0” and as an 8-bit register when flag x is “1”. Flag x is a part of the processor status
register (PS) which is described later.
In index addressing mode, register Y is used as the index register
and the contents of this address is added to obtain the real address.
Also, when executing a block transfer instruction MVP or MVN, the
contents of index register Y indicate the low-order 16 bits of the
destination address. The second byte of the MVP and MVN is the
high-order 8 bits of the destination data address.
70
PG
70
DT
Program bank register PG
Data bank register DT
Fig. 3 Register structure
15 07
15 07
15 07
15 07
15 0
A
H
B
H
X
H
Y
H
A
L
B
L
X
L
Y
L
S
15 0
PC
15 0
DPR
715 0
IPL
N
0
1
IPL2IPL
Accumulator A
Accumulator B
Index register X
Index register Y
Stack pointer S
Program counter PC
Direct page register DPR
Processor status register PS0
CZIDxmV0000
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Index register length flag
Data length flag
Overflow flag
Negative flag
Processor interrupt priority level IPL
7
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
STACK POINTER (S)
Stack pointer (S) is a 16-bit register. It is used during a subroutine
call or interrupts. It is also used during stack, stack pointer relative, or stack pointer relative indirect indexed Y addressing mode.
PROGRAM COUNTER (PC)
Program counter (PC) is a 16-bit counter that indicates the low-order 16-bits of the next program memory address to be executed.
There is a bus interface unit between the program memory and
the CPU, so that the program memory is accessed through bus interface unit. This is described later.
PROGRAM BANK REGISTER (PG)
Program bank register is an 8-bit register that indicates the highorder 8 bits of the next program memory address to be executed.
When a carry occurs by incrementing the contents of the program
counter, the contents of the program bank register (PG) is
incremented by 1. Also, when a carry or borrow occurs after adding or subtracting the offset value to or from the contents of the
program counter (PC) using branch instruction, the contents of the
program bank register (PG) is incremented or decremented by 1
so that programs can be written without worrying about bank
boundaries.
DATA BANK REGISTER (DT)
Data bank register (DT) is an 8-bit register. With some addressing
modes, a part of the data bank register (DT) is used to specify a
memory address. The contents of data bank register (DT) is used
as the high-order 8 bits of a 24-bit address. Addressing modes
that use the data bank register (DT) are direct indirect, direct indexed X indirect, direct indirect indexed Y, absolute, absolute bit,
absolute indexed X, absolute indexed Y, absolute bit relative, and
stack pointer relative indirect indexed Y.
DIRECT PAGE REGISTER (DPR)
Direct page register (DPR) is a 16-bit register. Its contents is used
as the base address of a 256-byte direct page area. The direct
page area is allocated in bank 0, but when the contents of DPR is
FF01
16 or greater, the direct page area spans across bank 016 and
bank 1
16. All direct addressing modes use the contents of the di-
rect page register (DPR) to generate the data address. If the
low-order 8 bits of the direct page register (DPR) is “00
number of cycles required to generate an address is minimized.
Normally the low-order 8 bits of the direct page register (DPR) is
set to “00
16”.
16”, the
PROCESSOR STATUS REGISTER (PS)
Processor status register (PS) is an 11-bit register. It consists of a
flag to indicate the result of operation and CPU interrupt levels.
Branch operations can be performed by testing the flags C, Z, V,
and N.
The details of each processor status register bit are described
below.
1. Carry flag (C)
The carry flag contains the carry or borrow generated by the ALU
after an arithmetic operation. This flag is also affected by shift and
rotate instructions. This flag can be set and reset directly with the
SEC and CLC instructions or with the SEP and CLP instructions.
2. Zero flag (Z)
This zero flag is set if the result of an arithmetic operation or data
transfer is zero and reset if it is not. This flag can be set and reset directly with the SEP and CLP instructions.
3. Interrupt disable flag (I)
When the interrupt disable flag is set to “1”, all interrupts except
watchdog timer, DBC, and software interrupt are disabled. This
flag is set to “1” automatically when there is an interrupt. It can be
set and reset directly with the SEI and CLI instructions or SEP and
CLP instructions.
____
4. Decimal mode flag (D)
The decimal mode flag determines whether addition and subtraction are performed as binary or decimal. Binary arithmetic is
performed when this flag is “0”. If it is “1”, decimal arithmetic is
performed with each word treated as two or four digit decimal.
Arithmetic operation is performed using four digits when the data
length flag m is “0” and with two digits when it is “1”. (Decimal operation is possible only with the ADC and SBC instructions.) This
flag can be set and reset with the SEP and CLP instructions.
8
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5. Index register length flag (x)
The index register length flag determines whether index register X
and index register Y are used as 16-bit registers or as 8-bit registers. The registers are used as 16-bit registers when flag x is “0”
and as 8-bit registers when it is “1”. This flag can be set and reset
with the SEP and CLP instructions.
6. Data length flag (m)
The data length flag determines whether the data length is 16-bit
or 8-bit. The data length is 16-bit when flag m is “0” and 8-bit when
it is “1”. This flag can be set and reset with the SEM and CLM instructions or with the SEP and CLP instructions.
7. Overflow flag (V)
The overflow flag has meaning when addition or subtraction is
performed a word as signed binary number. When the data length
flag m is “0”, the overflow flag is set when the result of addition or
subtraction is outside the range between –32768 and +32767.
When the data length flag m is “1”, the overflow flag is set when
the result of addition or subtraction is outside the range between
–128 and +127. It is reset in all other cases. The overflow flag can
also be set and reset directly with the SEP, and CLV or CLP instructions.
8. Negative flag (N)
The negative flag is set when the result of arithmetic operation or
data transfer is negative (If data length flag m is “0”, when data bit
15 is “1”. If data length flag m is “1”, when data bit 7 is “1”.) It is reset in all other cases. It can also be set and reset with the SEP
and CLP instructions.
9. Processor interrupt priority level (IPL)
The processor interrupt priority level (IPL) consists of 3 bits and
determines the priority of processor interrupts from level 0 to level
7. Interrupt is enabled when the interrupt priority of the device requesting interrupt (set using the interrupt control register) is higher
than the processor interrupt priority. When interrupt is enabled, the
current processor interrupt priority level is saved in a stack and the
processor interrupt priority level is replaced by the interrupt priority level of the device requesting the interrupt. Refer to the section
on interrupts for more details.
BUS INTERFACE UNIT
The CPU operates on an internal clock frequency which is obtained by dividing the external clock frequency f(X
frequency is twice the bus cycle frequency. In order to speed-up
processing, a bus interface unit is used to pre-fetch instructions
when the data bus is idle. The bus interface unit synchronizes the
CPU and the bus and pre-fetches instructions. Figure 4 shows the
relationship between the CPU and the bus interface unit. The bus
interface unit has a program address register, a 3-byte instruction
queue buffer, a data address register, and a 2-byte data buffer.
The bus interface unit obtains an instruction code from memory
and stores it in the instruction queue buffer, obtains data from
memory and stores it in the data buffer, or writes the data from the
data buffer to the memory.
IN) by two. This
D'
15 to D'8
D'7 to D'
0
A'
23
to A'
0
CPU
Control signal
Fig. 4 Relationship between the CPU and the bus interface unit
Bus interface
unit
D
15
to D
D7 to D
A
23
to A
BHE
R/
W
E
ALE
BYTE
HOLD
8
0
0
9
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The bus interface unit operates using one of the waveforms (1) to
(6) shown in Figure 5. The standard waveforms are (1) and (2).
The ALE signal is used to latch only the address signal from the
multiplexed signal containing data and address.
_
The E signal becomes “L” when the bus interface unit reads an instruction code or data from memory or when it writes data to
memory. Whether to perform read or write is controlled by the R/W
signal. Read is performed when the R/W signal is “H” state and
__
__
write is performed when it is “L” state.
Waveform (1) in Figure 5 is used to access a single byte or two
bytes simultaneously. To read or wr ite two bytes simultaneously,
the first address accessed must be even. Furthermore, when accessing an external memory area in memory expansion mode or
microprocessor mode, set the bus width selection input pin BYTE
to “L”. (external data bus width to 16 bits) The internal memory
area is always treated as 16-bit bus width regardless of BYTE.
When performing 16-bit data read or write, if the conditions for simultaneously accessing two bytes are not satisfied, waveform (2)
is used to access each byte one by one.
However, when prefetching the instruction code, if the address of
the instruction code is odd, waveform (1) is used, and only one
byte is read in the instruction queue buffer.
The signals A0 and BHE in Figure 5 are used to control these
____
cases: 1-byte read from even address, 1-byte read from odd address, 2-byte simultaneous read from even and odd addresses,
1-byte write to even address, 1-byte write to odd address, or 2byte simultaneous write to even and odd addresses. The A
that is the address bit 0 is “L” when an even number address is
accessed. The BHE signal becomes “L” when an odd number ad-
____
0 signal
dress is accessed.
The bit 2 of processor mode register (address 5E
When this bit is set to “0”, the “L” width of E signal is 2 times as
16) is the wait bit.
_
long when accessing an external memory area in memory expansion mode or microprocessor mode. However, the “L” width of E
signal is not extended when an internal memory area is accessed.
When the wait bit is “1”, the “L” width of E signal is not extended
_
for any access. Waveform (3) is an expansion of the “L” width of E
signal in waveform (1). Waveform (4), (5), and (6) are expansion
of each “L” width of E signal in waveform (2), first half of waveform
_
(2), and the last half of waveform (2) respectively.
Instruction code read, data read, and data write are described below.
_
_
Internal clock φ
(1)
Port P2
E
AD
ALE
A + 1
AD D
(2)
Port P2
E
ALE
AD
(3)
Port P2
E
ALE
A + 1
DD
(4)
Port P2
A
E
ALE
A + 1
DD
(5)
Port P2
A
E
ALE
A + 1
AD D
(6)
Port P2
E
ALE
A : Address
D : Data
These waveforms are at the memory expansion mode and
the microprocessor mode.
10
Access
Access 2-byte
method
A
BHE
0
____
simultaneously
“L” “L” “H”
“L” “H” “L”
Signal
Fig. 5 Relationship between access method and signals A0
and BHE
Access even
address 1-byte
Access odd
address 1-byte
MITSUBISHI MICROCOMPUTERS
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Instruction code read will be described first.
The CPU obtains instruction codes from the instruction queue
buffer and executes them. The CPU notifies the bus interface unit
that it is requesting an instruction code during an instruction code
request cycle. If the requested instruction code is not yet stored in
the instruction queue buffer, the bus interface unit halts the CPU
until it can store more instructions than requested in the instruction
queue buffer.
Even if there is no instruction code request from the CPU, the bus
interface unit reads instruction codes from memory and stores
them in the instruction queue buffer when the instruction queue
buffer is empty or when only one instruction code is stored and the
bus is idle on the next cycle.
This is referred to as instruction pre-fetching.
Normally, when reading an instruction code from memory, if the
accessed address is even the next odd address is read together
with the instruction code and stored in the instruction queue buffer.
However, in memory expansion mode or microprocessor mode, if
the bus width switching pin BYTE is “H”, external data bus width is
8 bits and the address to be read is in external memory area is
odd, only one byte is read and stored in the instruction queue
buffer. Therefore, waveform (1) or (3) in Figure 5 is used for instruction code read.
Data read and write are described below.
The CPU notifies the bus interface unit when performing data read
or write. At this time, the bus interface unit halts the CPU if the bus
interface unit is already using the bus or if there is a request with
higher priority. When data read or write is enabled, the bus interface unit uses one of the waveforms from (1) to (6) in Figure 5 to
perform the operation.
During data read, the CPU waits until the entire data is stored in
the data buffer. The bus interface unit sends the address received
from the CPU to the address bus. Then it reads the memory when
_
the E signal is “L” and stores the result in the data buffer.
During data write, the CPU writes the data in the data buffer and
the bus interface unit writes it to memory. Therefore, the CPU can
proceed to the next step without waiting for write to complete. The
bus interface unit sends the address received from the CPU to the
address bus. Then when the E signal is “L”, the bus interface unit
sends the data in the data buffer to the data bus and writes it to
memory.
_
11
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INTERRUPTS
Table 1 shows the interrupt types and the corresponding interrupt
vector addresses. Reset is also treated as a type of interrupt and
is discussed in this section, too. DBC is an interrupt used during
debugging.
Interrupts other than reset, DBC, watchdog timer, zero divide, and
BRK instruction all have interrupt control registers. Table 2 shows
the addresses of the interrupt control registers and Figure 6 shows
the bit configuration of the interrupt control register.
Use the SEB and CLB instructions when setting each interrupt
control register.
The interrupt request bit is automatically cleared by the hardware
during reset or when processing an interrupt.
Also, interrupt request bits other than DBC and watchdog timer
can be cleared by software.
____ ____
INT2 to INT0 are external interrupts and whether to cause an interrupt at the input level (level sense) or at the edge (edge sense)
can be selected with the level sense/edge sense selection bit. Furthermore, the polarity of the interrupt input can be selected with
polarity selection bit.
Timer and UART interrupts are described in the respective section. The priority of interrupts when multiple interrupts are caused
simultaneously is partially fixed by hardware, but, it can also be
adjusted by software as shown in Figure 7. The hardware priority
is fixed the following:
____
reset > DBC > watchdog timer > other interrupts
____
____
____
Table 1. Interrupt types and the interrupt vector addresses
Interrupts
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
____
INT2 external interrupt
____
INT1 external interrupt
____
INT0 external interrupt
Watchdog timer
____
DBC (unusable)
Break instruction
Zero divide
Reset
Vector addresses
00FFD616 00FFD716
00FFD816 00FFD916
00FFDA16 00FFDB16
00FFDC16 00FFDD16
00FFDE16 00FFDF16
00FFE016 00FFE116
00FFE216 00FFE316
00FFE416 00FFE516
00FFE616 00FFE716
00FFE816 00FFE916
00FFEA16 00FFEB16
00FFEC16 00FFED16
00FFEE16 00FFEF16
00FFF016 00FFF116
00FFF216 00FFF316
00FFF416 00FFF516
00FFF616 00FFF716
00FFF816 00FFF916
00FFFA16 00FFFB16
00FFFC16 00FFFD16
00FFFE16 00FFFF16
7
6543210
Interrupt control register configuration for A-D converter, UART0, UART1, timer A0 to timer A4, and
timer B0 to timer B2
7
6543210
Interrupt control register configuration for
Fig. 6 Interrupt control register configuration
Interrupt priority
Interrupt request bit
0 : No interrupt
1 : Interrupt
Interrupt priority
Interrupt request bit
0 : No interrupt
1 : Interrupt
Polarity selection bit
0 : Set interrupt request bit at “H” level for level sense and when changing
from “H” to “L” level for edge sense.
1 : Set interrupt request bit at “L” level for level sense and when changing
from “L” to “H” level for edge sense.
Level sense/edge sense selection bit
0 : Edge sense
1 : Level sense
INT
2
to
INT
0.
12
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Table 2. Addresses of interrupt control registers
Interrupt control registers
A-D conversion interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
____
INT0 interrupt control register
____
INT1 interrupt control register
____
INT2 interrupt control register
Addresses
00007016
00007116
00007216
00007316
00007416
00007516
00007616
00007716
00007816
00007916
00007A16
00007B16
00007C16
00007D16
00007E16
00007F16
Interrupts caused by a BRK instruction and when dividing by zero
are software interrupts and are not included in this list.
Other interrupts previously mentioned are A-D converter, UART,
Timer, INT interrupts. The priority of these interrupts can be
changed by changing the priority level in the corresponding interrupt control register by software.
Figure 8 shows a diagram of the interrupt priority resolution circuit.
When an interrupt is caused, the each interrupt device compares
its own priority with the priority from above and if its own priority is
higher, then it sends the priority below and requests the interrupt.
If the priorities are the same, the one above has priority.
This comparison is repeated to select the interrupt with the highest
priority among the interrupts that are being requested. Finally the
selected interrupt is compared with the processor interrupt priority
level (IPL) contained in the processor status register (PS) and the
request is accepted if it is higher than IPL and the interrupt disable
flag I is “0”. The request is not accepted if flag I is “1”. The reset,
____
DBC, and watchdog timer interrupts are not affected by the interrupt disable flag I.
When an interrupt is accepted, the contents of the processor status register (PS) is saved to the stack and the interrupt disable
flag I is set to “1”.
Furthermore, the interrupt request bit of the accepted interrupt is
cleared to “0” and the processor interrupt priority level (IPL) in the
processor status register (PS) is replaced by the priority level of
the accepted interrupt.
Therefore, multi-level priority interrupts are possible by resetting
the interrupt disable flag I to “0” and enable further interrupts.
For reset, DBC, watchdog timer, zero divide, and BRK instruction
____
interrupts, which do not have an interrupt control register, the processor interrupt level (IPL) is set as shown in Table 3.
Priority resolution is performed by latching the interrupt request bit
and interrupt priority level so that they do not change. They are
sampled at the first half and latched at the last half of the operation code fetch cycle.
Because priority resolution takes some time, no sampling pulse is
generated for a certain interval even if it is the next operation code
fetch cycle.
Priority is determined by hardware
3
4
➂➃
Watchdog
timer
DBC
12
Reset
A-D converter, UART, Timer, INT interrupts
Priority can be changed with software inside
4
Fig. 7 Interrupt priority
Level 0
A-D conversion
Interrupt request
Reset
DBC
Watchdog
timer
Interrupt disable flag I
IPL
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT
2
INT
1
INT
0
Fig. 8 Interrupt priority resolution
13
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As shown in Figure 9, there are three different interrupt priority
resolution time from which one is selected by software. After the
selected time has elapsed, the highest priority is determined and
is processed after the currently executing instruction has been
completed.
The time is selected with bits 4 and 5 of the processor mode register (address 5E
16) shown in Figure 10. Table 4 shows the
relationship between these bits and the number of cycles. After a
reset, the processor mode register is initialized to “00
16” and
therefore, the longest time is selected.
However, the shortest time should be selected by software.
Internal clock
Operation code fetch cycle
Sampling pulse
Priority resolution time
φ
0
Table 3. Value set in processor interrupt level (IPL) during an
interrupt
Interrupt types
Reset
____
DBC
Watchdog timer
Zero divide
BRK instruction
Setting value
0
7
7
Not change value of IPL.
Not change value of IPL.
Table 4. Relationship between priority level resolution time
selection bit and number of cycles
Priority level resolution time selection bit
Bit 5
0
0
1
Bit 4
0
1
0
Number of cycles
7 cycles of φ
4 cycles of φ
2 cycles of φ
φ : internal clock
Select from 0 to 2 with bits
4 and 5 of the processor
mode register
Fig. 9 Interrupt priority resolution time
7
6 5 4 3 2 1 0
0
Fig. 10 Processor mode register configuration
1
2
Processor mode register (5E16)
Processor mode bits
0 0 : Single-chip mode
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Evaluation chip mode
Wait bit
0 : Wait
1 : No wait
Software reset bit
The processor is reset when this bit is set to “1”.
Priority resolution time selection bits
0 0 : Select 0 in Figure 9
0 1 : Select 1 in Figure 9
1 0 : Select 2 in Figure 9
Test mode bit
Must be “0”
Clock
φ
1
output selection bit
φ
1
φ
1
output
output
0 : No
1 :
14
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TIMER
There are eight 16-bit timers. They are divided by type into timer A
(5) and timer B (3).
The timer I/O pins are shared with I/O pins for port P5 and P6. To
use these pins as timer input pins, the data direction register bit
corresponding to the pin must be cleared to “0” to specify input
mode.
TIMER A
Figure 11 shows a block diagram of timer A.
Timer A has four modes; timer mode, event counter mode, oneshot pulse mode, and pulse width modulation mode. The mode is
selected with bits 0 and 1 of the timer Ai mode register (i = 0 to 4).
Each of these modes is described below.
f
f(X
IN
)
Clock source selection
f
2
f
16
f
64
f
512
TAi
(i = 0 – 4)
2
1/2 1/8 1/2 1/2 1/8
Polarity
selection
IN
f
16
• Timer
• One-shot
• Pulse width modulation
Timer (gate function)
Event counter
External trigger
f
32
(1) Timer mode [00]
Figure 12 shows the bit configuration of the timer Ai mode register
during timer mode. Bits 0, 1, and 5 of the timer Ai mode register
must always be “0” in timer mode.
Bit 3 is ignored if bit 4 is “0”.
Bits 6 and 7 are used to select the timer counter source.
The counting of the selected clock starts when the count start flag
is “1” and stops when it is “0”.
Figure 13 shows the bit configuration of the count start flag. The
counter is decremented, an interrupt is caused and the interrupt
request bit in the timer Ai interrupt control register is set when the
contents becomes 0000
reload register is transferred to the counter and count is continued.
f
64
f
Data bus (odd)
Data bus (even)
Reload register(16)
Count start flag
(4016)
Down count
16. At the same time, the contents of the
512
(Lower 8 bits)
(Higher 8 bits)
Counter(16)
Up/Down
Always decremented
except in event count mode
Addresses
Timer A0 4716 46
Timer A1 4916 48
Timer A2 4B16 4A
Timer A3 4D16 4C
Timer A4 4F16 4E
16
16
16
16
16
Pulse output
TAi
OUT
(i = 0 – 4)
Fig. 11 Block diagram of timer A
Up-down flag
(4416)
Toggle flip-flop
15
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When bit 2 of the timer Ai mode register is “1”, the output is generated from TAi
of the counter reaches to 0000
start flag is “0”, “L” is output from TAi
When bit 2 is “0”, TAi
bit 4 is “0”, TAi
OUT pin. The output is toggled each time the contents
16. When the contents of the count
OUT pin.
OUT can be used as a normal port pin. When
IN can be used as a normal port pin. When bit 4 is
“1”, counting is performed only while the input signal from the
TAi
IN pin is “H” or “L” as shown in Figure 14. Therefore, this can
be used to measure the pulse width of the TAi
IN input signal.
Whether to count while the input signal is “H” or while it is “L” is
determined by bit 3. If bit 3 is “1”, counting is performed while the
TAi
IN pin input signal is “H” and if bit 3 is “0”, counting is performed
Timer A0 mode register 56
Timer A1 mode register 57
Timer A2 mode register 58
623451
70
0
Timer A3 mode register 59
Timer A4 mode register 5A
00
0
0 : Always “00” in timer mode
0 : No pulse output (TAi
1 : Pulse output
while it is “L”.
Note that the duration of “H” or “L” on the TAi
IN pin must be two or
more cycles of the timer count source.
When data is written to timer Ai register with timer Ai halted, the
same data is also written to the reload register and the counter.
When data is written to timer Ai which is busy, the data is written to
the reload register, but not to the counter. The counter is reloaded
with new data from the reload register at the next reload timer. The
contents of the counter can be read at any time.
When the value set in the timer Ai register is n, the timer frequency
dividing ratio is 1/(n + 1).
Addresses
16
16
16
16
16
OUT
is normal port pin)
0 ✕ : No gate function (TAi
1
0 : Count only while TAiIN input is “L”
1 : Count only while TAi
1
0 : Always “0” in timer mode
Clock source selection bit
0 0 : Select f
0 1 : Select f
1 0 : Select f
1 1 : Select f
Fig. 12 Timer Ai mode register bit configuration during timer mode
2
16
64
512
IN
is normal port pin)
IN
input is “H”
16
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70654321
Fig. 13 Count start flag bit configuration
Selected clock source f
TAi
i
N
Count start flag
(Stop at “0”, Start at “1”)
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
Address
40
16
Timer mode register
Bit 4 Bit 3
10
Timer mode register
Bit 4 Bit 3
11
11
Fig. 14 Count waveform when gate function is available
17
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(2) Event counter mode [01]
Figure 15 shows the bit configuration of the timer Ai mode register
during event counter mode. In event counter mode, the bit 0 of the
timer Ai mode register must be “1” and bit 1 and 5 must be “0”.
The input signal from the TAi
IN pin is counted when the count start
flag shown in Figure 13 is “1“ and counting is stopped when it
is “0”.
Count is performed at the fall of the input signal when bit 3 is “0”
and at the rise of the signal when it is “1”.
In event counter mode, whether to increment or decrement the
count can be selected with the up-down flag or the input signal
from the TAi
OUT pin.
When bit 4 of the timer Ai mode register is “0”, the up-down flag is
used to determine whether to increment or decrement the count
(decrement when the flag is “0” and increment when it is “1”). Figure 16 shows the bit configuration of the up-down flag.
When bit 4 of the timer Ai mode register is “1”, the input signal
from the TAi
OUT pin is used to determine whether to increment or
decrement the count. However, note that bit 2 must be “0” if bit 4
is “1” because if bit 2 is “1”, TAi
OUT pin becomes an output pin with
pulse output.
The count is decremented when the input signal from the TAi
OUT
pin is “L” and incremented when it is “H”. Determine the level of
the input signal from the TAi
the TAi
IN pin.
OUT pin before valid edge is input to
An interrupt request signal is generated and the interrupt request
bit in the timer Ai interrupt control register is set when the counter
reaches 0000
16 (decrement count) or FFFF16 (increment count).
At the same time, the contents of the reload register is transferred
to the counter and the count is continued.
When bit 2 is “1” and the counter reaches 0000
count) or FFFF
ity is output from TAi
If bit 2 is “0”, TAi
ever, if bit 4 is “1“ and the TAi
16 (increment count), the waveform reversing polar-
OUT pin.
OUT pin can be used as a normal port pin. How-
OUT pin is used as an output pin, the
16 (decrement
output from the pin changes the count direction. Therefore, bit 4
should be “0” unless the output from the TAi
OUT pin is to be used
to select the count direction.
Timer A0 mode register 56
Timer A1 mode register 57
Timer A2 mode register 58
7 6543210
001
✕✕
Timer A3 mode register 59
Timer A4 mode register 5A
0 1 : Always “01” in event counter
mode
0 : No pulse output
1 : Pulse output
0 : Count at the falling edge of input
signal
1 : Count at the rising edge of input
signal
0 : Increment or decrement according
to up-down flag
1 : Increment or decrement according
to TAi
0 : Always “0” in event counter mode
✕ ✕
OUT
: Not used in event counter mode
Fig. 15 Timer Ai mode register bit configuration during event
counter mode
7 6543210
Up-down flag
Timer A0 up-down flag
Timer A1 up-down flag
Timer A2 up-down flag
Timer A3 up-down flag
Timer A4 up-down flag
Timer A2 two-phase pulse signal processing
selection bit
0 : Two-phase pulse signal processing disabled
1 : Two-phase pulse signal processing mode
Timer A3 two-phase pulse signal processing
selection bit
0 : Two-phase pulse signal processing disabled
1 : Two-phase pulse signal processing mode
Timer A4 two-phase pulse signal processing
selection bit
0 : Two-phase pulse signal processing disabled
1 : Two-phase pulse signal processing mode
Addresses
16
16
16
16
16
pin input signal level
Address
44
16
18
Fig. 16 Up-down flag bit configuration
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