Mitsubishi M37540M4-XXXSP, M37540M4-XXXGP, M37540M4-XXXFP, M37540E8SP, M37540E8GP Datasheet
...
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 7540 Group is the 8-bit microcomputer based on the 740 family
core technology.
The 7540 Group has a serial I/O, 8-bit timers, a 16-bit timer, and an
A-D converter, and is useful for control of home electric appliances
and office automation equipment.
FEATURES
Basic machine-language instructions....................................... 71
•
The minimum instruction execution time .......................... 0.50 µs
•
(at 8 MHz oscillation frequency for the shortest instruction)
Memory size ROM ............................................16K to 32K bytes
•
Programmable I/O ports ........................................................... 29
•
Interrupts .................................................. 15 sources, 15 vectors
•
Timers ............................................................................ 8-bit ✕ 4
•
Serial I/O1 ...................................................................... 8-bit ✕ 1
•
Serial I/O2 ...................................................................... 8-bit ✕ 1
•
A-D converter ................................................ 10-bit ✕ 8 channels
•
Clock generating circuit ............................................. Built-in type
•
RAM ..............................................512 to 768 bytes
(25 in 32-pin version)
(14 sources, 14 vectors for 32-pin version)
16-bit ✕ 1
(UART or Clock-synchronized)
(Clock-synchronized)
(6 channels for 32-pin version)
(low-power dissipation by a ring oscillator enabled)
(connect to external ceramic resonator or quartz-crystal oscillator
permitting RC oscillation)
Watchdog timer ............................................................ 16-bit ✕ 1
•
Power source voltage
•
XIN oscillation frequency at ceramic oscillation, in high-speed mode
At 8 MHz ....................................................................4.0 to 5.5 V
At 4 MHz ....................................................................2.4 to 5.5 V
At 2 MHz ....................................................................2.2 to 5.5 V
XIN oscillation frequency at RC oscillation
At 4 MHz ....................................................................4.0 to 5.5 V
At 2 MHz ....................................................................2.4 to 5.5 V
At 1 MHz ....................................................................2.2 to 5.5 V
Power dissipation ............................................ 25 mW (standard)
•
Operating temperature range ................................... –20 to 85 °C
•
(–40 to 85 °C for extended operating temperature version)
APPLICATION
Office automation equipment, factory automation equipment, home
electric appliances, consumer electronics, car, etc.
Note: Serial I/O2 can be used in the following cases;
(1) Serial I/O1 is not used,
(2) Serial I/O1 is used as UART and BRG output divided by 16 is
selected as the synchronized clock.
PIN CONFIGURATION (TOP VIEW)
P0
7
P12/S
P13/S
P10/RXD
P11/TXD
CLK1/SCLK2
RDY1/SDATA2
P14/CNTR
P20/
P21/
AN
AN
1
1
0
0
1
OUT
/TX
5
P0
23
2
3
/AN
3
P2
4
P0
22
3
4
/AN
4
P2
3
P0
21
4
5
/AN
5
P2
6
P0
24
25
26
27
M37540M4-XXXGP
28
29
30
31
32
M37540E8GP
1
2
/AN
2
P2
OUT
OUT
/TY
/TZ
1
2
P0
P0
201718
19
7
6
5
REF
V
RESET
1
0
/INT
/CNTR
7
0
P3
P0
8
SS
CC
V
CNV
16
15
14
13
12
11
10
9
P34(LED4)
3
(LED3)
P3
2
(LED2)
P3
P3
1
(LED1)
0
(LED0)
P3
SS
V
X
OUT
X
IN
Package type: 32P6B-A
Fig. 1 M37540M4-XXXGP, M37540E8GP pin configuration
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
P12/S
P13/S
CLK1/SCLK2
RDY1/SDATA2
P14/CNTR
P20/AN
P21/AN
P22/AN
P23/AN
P24/AN
P25/AN
P26/AN
P27/AN
V
REF
RESET
CNV
SS
Vcc
X
IN
X
OUT
V
SS
1
2
10
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
M37540M4-XXXFP
M37540E8FP
0
0
1
2
3
4
5
6
7
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
P11/TXD
P10/RXD
P0
P0
P0
P0
P03/TX
P02/TZ
P01/TY
1
1
7
6
5
4
OUT
OUT
OUT
P00/CNTR
P37/INT
P3
0
6
(LED6)/INT
P35(LED5)
P3
4
(LED4)
P3
3
(LED3)
P3
2
(LED2)
P31(LED1)
P30(LED0)
1
1
Package type: 36P2R-A
Fig. 2 M37540M4-XXXFP, M37540E8FP pin configuration
P12/S
CLK1/SCLK2
P13/S
RDY1/SDATA2
P14/CNTR
P20/AN
P21/AN
P22/AN
P23/AN
P24/AN
P25/AN
V
REF
RESET
CNV
SS
V
CC
X
X
OUT
V
SS
0
0
1
2
3
4
5
10
11
12
13
14
IN
14
15
15
16
16
Package type: 32P4B
1
2
3
4
5
6
7
8
9
M37540M4-XXXSP
M37540E8SP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P11/TXD
1
P10/RXD
P0
7
P0
6
P0
5
P0
4
P03/TX
P02/TZ
P01/TY
P0
P37/INT
0
/CNTR
OUT
OUT
OUT
0
P34(LED4)
P33(LED3)
P3
2
(LED2)
P3
1
(LED1)
P30(LED0)
1
1
Fig. 3 M37540M4-XXXSP, M37540E8SP pin configuration
2
PRELIMINARY
X
IN OUT
X
SI/O1(8)
RAM
ROM
CPU
A
X
Y
S
PC
H
PCLPS
V
SS
11
RESET
6
V
CC
8
7
CNV
SS
P1(5)
30 28 2629 27
32
31
P2(6)
P3(6)
1215 13
5
Reset input
I/O port P2
I/O port P1I/O port P3
Clock generating circuit
Clock input
Clock output
9
10
4
2
3
1
A-D
converter
(10)
V
REF
Watchdog timer
Reset
0
14
INT
0
1617
SI/O2(8)
CNTR
0
I/O port P0
Prescaler Y (8)
Prescaler Z (8)
Timer X (8)
Timer Z (8)
Timer Y (8)
Key-on wakeup
TY
OUT
TZ
OUT
Prescaler X (8)
CNTR
1
Timer A (16)
P0(8)
25
23 21
19
24 22
20 18
INT
0
Timer 1 (8)
Prescaler 1 (8)
TX
OUT
Notice: This is not a final specification.
Some parametric limits are subject to change.
FUNCTIONAL BLOCK
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL BLOCK DIAGRAM (Package: 32P6B)
Fig. 4 Functional block diagram (32P6B package)
3
PRELIMINARY
A-D
converter
(10)
X
IN OUT
X
CPU
V
SS
18
RESET
13
V
CC
15
14
CNV
SS
P0(8)
34
32 30 28
33
31 29 27
P1(5)
31
35
2
36
7
56
4
P2(8)
P3(8)
2023 21 19
12
I/O port P2
I/O port P0I/O port P1I/O port P3
16 17
11
9
10
8
0
22
26 2425
SI/O1(8)
RAM
ROM
A
X
Y
S
PC
H
PCL
PS
Reset input
Clock generating circuit
Clock input Clock output
V
REF
Watchdog timer
Reset
INT
0
SI/O2(8)
CNTR
0
Prescaler Y (8)
Prescaler Z (8)
Timer X (8)
Timer Z (8)
Timer Y (8)
Key-on wakeup
TY
OUT
TZ
OUT
Prescaler X (8)
CNTR
1
Timer A (16)
INT
0
Timer 1 (8)
Prescaler 1 (8)
TX
OUT
INT
1
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL BLOCK DIAGRAM (Package: 36P2R)
Fig. 5 Functional block diagram (36P2R package)
4
PRELIMINARY
16
11
13
12
P1(5)
31
31
2
32
5
4
P2(6)
P3(6)
1720 18
10
14
15
9
7
8
6
0
19
2122
P0(8)
30
28 26 24
29
27 25 23
A-D
converter
(10)
X
IN OUT
X
CPU
V
SS
RESET
V
CC
CNV
SS
I/O port P2
I/O port P0I/O port P1
I/O port P3
SI/O1(8)
RAM
ROM
A
X
Y
S
PC
H
PC
L
PS
Reset input
Clock generating circuit
Clock input
Clock output
V
REF
Watchdog timer
Reset
INT
0
SI/O2(8)
CNTR
0
Prescaler Y (8)
Prescaler Z (8)
Timer X (8)
Timer Z (8)
Timer Y (8)
Key-on wakeup
TY
OUT
TZ
OUT
Prescaler X (8)
CNTR
1
Timer A (16)
INT
0
Timer 1 (8)
Prescaler 1 (8)
TX
OUT
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL BLOCK DIAGRAM (Package: 32P4B)
Fig. 6 Functional block diagram (32P4B package)
5
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PIN DESCRIPTION
Table 1 Pin description
Pin
Vcc, Vss
VREF
CNVss
RESET
XIN
XOUT
P00/CNTR1
P01/TYOUT
P02/TZOUT
P03/TXOUT
P04–P07
P10/RxD1
P11/TxD1
P12/SCLK1/SCLK2
P13/SRDY1/SDATA2
P14/CNTR0
P20/AN0–
P27/AN7
P30–P35
P36/INT1
P37/INT0
Name
Power source
Analog reference
voltage
CNVss
Reset input
Clock input
Clock output
I/O port P0
I/O port P1
I/O port P2
I/O port P3
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Function
•Apply voltage of 2.2–5.5 V to Vcc, and 0 V to Vss.
•Reference voltage input pin for A-D converter
•Chip operating mode control pin, which is always connected to Vss.
•Reset input pin for active “L”
•Input and output pins for main clock generating circuit
•Connect a ceramic resonator or quartz crystal oscillator between the XIN and XOUT pins.
•For using RC oscillator, short between the XIN and XOUT pins, and connect the capacitor and resistor.
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
•8-bit I/O port.
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level
•CMOS 3-state output structure
•Whether a built-in pull-up resistor is to be used or not can be
determined by program.
•5-bit I/O port
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level
•CMOS 3-state output structure
•CMOS/TTL level can be switched for P10, P12 and P13
•8-bit I/O port having almost the same function as P0
•CMOS compatible input level
•CMOS 3-state output structure
•8-bit I/O port
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level (CMOS/TTL level can be switched for P36 and P37).
•CMOS 3-state output structure
•P30 to P36 can output a large current for driving LED.
•Whether a built-in pull-up resistor is to be used or not can be
determined by program.
Function expect a port function
• Key-input (key-on wake up
interrupt input) pins
• Timer Y, timer Z, timer X and
timer A function pin
•Serial I/O1 function pin
•Serial I/O1 function pin
•Serial I/O2 function pin
•Timer X function pin
•Input pins for A-D converter
•Interrupt input pins
6
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Mitsubishi plans to expand the 7540 group as follow:
Memory type
Support for Mask ROM version, One Time PROM version, and Emulator MCU .
ROM size
(bytes)
32K
Under development
16K
Under development
Memory size
ROM/PROM size ................................................ 16 K to 32 K bytes
RAM size................................................................512 to 768 bytes
Package
32P4B ...........................................32-pin shrink plastic molded DIP
32P6B-A...................................... 0.8 mm-pitch plastic molded QFP
36P2R-A ..................................... 0.8 mm-pitch plastic molded SOP
42S1M.....................................42-pin shrink ceramic PIGGY BACK
Under development
M37540E8
M37540M4T
M37540M4
0
384
Note: Products under development•••the development schedule and
specification may be revised without notice.
Fig. 7 Memory expansion plan
Currently supported products are listed below.
Table 2 List of supported products
Product
M37540M4-XXXSP
M37540M4-XXXFP
M37540M4T-XXXFP
M37540M4-XXXGP
M37540M4T-XXXGP
M37540E8SP
M37540E8FP
M37540E8GP
M37540RSS
(P) ROM size (bytes)
ROM size for User ()
16384
(16254)
32768
(32638)
RAM size
(bytes)
512
768
768
Package
32P4B
36P2R-A
32P6B-A
32P4B
36P2R-A
32P6B-A
42S1M
512 768
Remarks
Mask ROM version
Mask ROM version
Mask ROM version (extended operating temperature version)
Mask ROM version
Mask ROM version (extended operating temperature version)
One Time PROM version (blank)
One Time PROM version (blank)
One Time PROM version (blank)
Emulator MCU
RAM size
(bytes)
7
PRELIMINARY
Oscillation mode selection bit (Note 1)
0 : Ceramic oscillation
1 : RC oscillation
CPU mode register
(CPUM: address 003B
16
)
Stack page selection bit
0 : 0 page
1 : 1 page
Clock division ratio selection bits
b7 b6
0 0 : f(φ) = f(X
IN
)/2 (High-speed mode)
0 1 : f(φ) = f(X
IN
)/8 (Middle-speed mode)
1 0 : applied from ring oscillator
1 1 : f(φ) = f(X
IN
) (Double-speed mode)(Note 2)
Ring oscillator oscillation control bit
0 : Ring oscillator oscillation enabled
1 : Ring oscillator oscillation stop
X
IN
oscillation control bit
0 : Ceramic or RC oscillation enabled
1 : Ceramic or RC oscillation stop
Processor mode bits (Note 1)
b1 b0
0 0 Single-chip mode
0 1
1 0
1 1
Not available
b7 b0
2: These bits are used only when a ceramic oscillation is selected.
Note 1: The bit can be rewritten only once after releasing reset. After rewriting
it is disable to write any data to the bit. However, by reset the bit is
initialized and can be rewritten, again.
(It is not disable to write any data to the bit for emulator MCU
“M37540RSS”.)
Do not use these when an RC oscillation is selected.
Notice: This is not a final specification.
Some parametric limits are subject to change.
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The 7540 Group uses the standard 740 family instruction set. Refer
to the table of 740 family addressing modes and machine-language
instructions or the 740 Family Software MANUAL for details on each
instruction set.
Machine-resident 740 family instructions are as follows:
1. The FST and SLW instructions cannot be used.
2. The MUL and DIV instructions can be used.
3. The WIT instruction can be used.
4. The STP instruction can be used.
(This instruction cannot be used while CPU operates by a ring oscillator.)
[CPU mode register] CPUM
The CPU mode register contains the stack page selection bit.
This register is allocated at address 003B16.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Switching method of CPU mode register
Switch the CPU mode register (CPUM) at the head of program after
releasing Reset in the following method.
After releasing reset
Switch the oscillation mode
selection bit (bit 5 of CPUM)
Fig. 9 Switching method of CPU mode register
8
Wait by ring oscillator operation until
establishment of oscillator clock
Switch the clock division ratio
selection bits (bits 6 and 7 of CPUM)
Main routine
Fig. 8 Structure of CPU mode register
Start with a built-in ring oscillator
An initial value is set as a ceramic
oscillation mode. When it is switched to an
RC oscillation, its oscillation starts.
When using a ceramic oscillation, wait until
establlishment of oscillation from oscillation starts.
When using an RC oscillation, wait time is not
required basically (time to execute the instruction to
switch from a ring oscillator meets the requirement).
Switch to other mode except a ring oscillator.
At the same time, select the double-speed,
high-speed, or middle-speed mode.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Memory
Special function register (SFR) area
The SFR area in the zero page contains control registers such as I/O
ports and timers.
RAM
RAM is used for data storage and for a stack area of subroutine calls
and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is a user area for storing programs.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM capacity
(bytes)
512
768
address
XXXX16
023F16
033F16
Zero page
The 256 bytes from addresses 000016 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
Special page
The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
000016
SFR area
Zero page
RAM
004016
010016
XXXX
16
Reserved area
044016
Not used
ROM area
ROM capacity
(bytes)
16384
32768
Fig. 10 Memory map diagram
address
YYYY16
C00016
800016
address
ZZZZ16
C08016
808016
ROM
YYYY16
ZZZZ16
FF0016
FFDC16
FFFE16
FFFF16
Reserved ROM area
(128 bytes)
Interrupt vector area
Reserved ROM area
Special page
9
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port P0 (P0)
000016
Port P0 direction register (P0D)
000116
Port P1 (P1)
000216
Port P1 direction register (P1D)
000316
Port P2 (P2)
000416
Port P2 direction register (P2D)
000516
Port P3 (P3)
000616
Port P3 direction register (P3D)
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
Pull-up control register (PULL)
001616
Port P1P3 control register (P1P3C)
001716
Transmit/Receive buffer register (TB/RB)
001816
Serial I/O1 status register (SIO1STS)
001916
Serial I/O1 control register (SIO1CON)
001A16
UART control register (UARTCON)
001B16
Baud rate generator (BRG)
001C16
Timer A mode register (TAM)
001D16
001E16
Timer A (low-order) (TAL)
001F16
Timer A (high-order) (TAH)
Timer Y, Z mode register (TYZM)
002016
Prescaler Y (PREY)
002116
Timer Y secondary (TYS)
002216
Timer Y primary (TYP)
002316
Timer Y, Z waveform output control register (PUM)
002416
Prescaler Z (PREZ)
002516
Timer Z secondary (TZS)
002616
Timer Z primary (TZP)
002716
Prescaler 1 (PRE1)
002816
Timer 1 (T1)
002916
One-shot start register (ONS)
002A16
Timer X mode register (TXM)
002B16
Prescaler X (PREX)
002C16
Timer X (TX)
002D16
Timer count source set register (TCSS)
002E16
002F16
Serial I/O2 control register (SIO2CON)
003016
Serial I/O2 register (SIO2)
003116
003216
003316
A-D control register (ADCON)
003416
A-D conversion register (low-order) (ADL)
003516
A-D conversion register (high-order) (ADH)
003616
003716
MISRG
003816
Watchdog timer control register (WDTCON)
003916
Interrupt edge selection register (INTEDGE)
003A16
CPU mode register (CPUM)
003B16
Interrupt request register 1 (IREQ1)
003C16
Interrupt request register 2 (IREQ2)
003D16
Interrupt control register 1 (ICON1)
003E16
Interrupt control register 2 (ICON2)
003F16
Note : Do not access to the SFR area including nothing.
Fig. 11 Memory map of special function register (SFR)
10
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O Ports
[Direction registers] PiD
The I/O ports have direction registers which determine the input/output direction of each pin. Each bit in a direction register corresponds
to one pin, and each pin can be set to be input or output.
When “1” is set to the bit corresponding to a pin, this pin becomes an
output port. When “0” is set to the bit, the pin becomes an input port.
When data is read from a pin set to output, not the value of the pin
itself but the value of port latch is read. Pins set to input are floating,
and permit reading pin values.
If a pin set to input is written to, only the port latch is written to and the
pin remains floating.
b7 b0
Pull-up control register
(PULL: address 0016
[Pull-up control register] PULL
By setting the pull-up control register (address 001616), ports P0 and
P3 can exert pull-up control by program. However, pins set to output
are disconnected from this control and cannot exert pull-up control.
[Port P1P3 control register] P1P3C
By setting the port P1P3 control register (address 001716), a CMOS
input level or a TTL input level can be selected for ports P10, P12,
P13, P36, and P37 by program.
16
, initial value: 0016)
P00 pull-up control bit
P0
1
pull-up control bit
P0
2
, P03 pull-up control bit
P0
4
– P07 pull-up control bit
P3
0
– P33 pull-up control bit
Note 1: Pins set to output ports are disconnected from pull-up control.
5
2: Set the P3
Fig. 12 Structure of pull-up control register
, P36 pull-up control bit to “1” (initial value: “0”) for 32-pin version.
b7 b0
Note: Keep setting the P36/INT1 input level selection bit
to “0” (initial value) for 32-pin version.
P3
4
pull-up control bit
P3
5
, P36 pull-up control bit
P3
7
pull-up control bit
Port P1P3 control register
(P1P3C: address 0017
P37/INT0 input level selection bit
0 : CMOS level
1 : TTL level
6
/INT1 input level selection bit
P3
0 : CMOS level
1 : TTL level
P1
0
,P12,P13 input level selection bit
0 : CMOS level
1 : TTL level
Not used
16
, initial value: 0016)
0 : Pull-up Off
1 : Pull-up On
Fig. 13 Structure of port P1P3 control register
11
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 3 I/O port function table
Pin
P00/CNTR1
P01/TYOUT
P02/TZOUT
P03/TXOUT
P04–P07
P10/RxD1
P11/TxD1
P12/SCLK1/SCLK2
P13/SRDY1/SDATA2
P14/CNTR0
P20/AN0–P27/AN7
P30–P35
P36/INT1
P37/INT0
Note: Ports P10, P12, P13, P36, and P37 are CMOS/TTL level.
Name
I/O port P0
I/O port P1
I/O port P2
I/O port P3
Input/output
I/O individual
bits
I/O format
•CMOS compatible input
level
•CMOS 3-state output
(Note)
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Non-port function
Key input interrupt
Serial I/O1 function
input/output
Serial I/O2 function
input/output
Timer X function
input/output
A-D conversion
input
External interrupt
input
Related SFRs Diagram No.
Pull-up control register
Timer Y mode register
Timer Z mode register
Timer X mode register
Timer Y,Z waveform output control register
Timer A mode register
Serial I/O1 control register
Serial I/O1 control register
Serial I/O2 control register
Timer X mode register
A-D control register
Interrupt edge selection
register
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
12
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1)Port P00
Data bus
(3)Port P03
Data bus
Pull-up control
Direction
register
Port latch
Direction
register
Port latch
Timer output
CNTR1 interrupt input
To key input interrupt
generating circuit
Pull-up control
P0
3
/TX
output valid
To key input interrupt
generating circuit
OUT
(2)Ports P01, P02
Pull-up control
Direction
register
Data bus Port latch
Pulse output mode
Timer output
To key input interrupt
generating circuit
(4)Ports P04–P07
Pull-up control
Direction
register
Data bus
Port latch
To key input interrupt
generating circuit
(5)Port P10
Serial I/O1 enable bit
Receive enable bit
Data bus
Direction
register
Port latch
Serial I/O1 input
(7)Port P12
CLK2
pin
S
Serial I/O1 synchronous
clock selection bit
Serial I/O1 enable bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Data bus
Serial I/O1, serial I/O2 clock output
selection bit
Direction
register
Port latch
Serial I/O1, serial I/O2 clock input
P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register.
*
Fig. 14 Block diagram of ports (1)
P1
0
, P12, P13
input level
selection bit
*
P1
0
, P12, P13
input level
selection bit
(6)Port P11
1/TxD1
P-channel output disable bit
P1
Serial I/O1 enable bit
Transmit enable bit
Direction
register
Data bus
Port latch
Serial I/O1 output
*
13
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(8) Port P1
DATA2
S
Serial I/O mode selection bit
Data bus
3
output in operation signal
DATA2
pin selection bit
S
Serial I/O1 enable bit
S
RDY1
output enable bit
Serial I/O1 ready output
Serial I/O2 output
(10) Ports P20–P2
Data bus
Direction
register
Port latch
7
Direction
register
Port latch
Serial I/O2 input
P10, P12, P13
input level
selection bit
*
(9) Port P1
Data bus
4
Pulse output mode
(11) Ports P30–P3
Data bus
Direction
register
Port latch
Timer output
5
Pull-up control
Direction
register
Port latch
CNTR0 interrupt input
A-D converter input
(12) Ports P36, P3
Data bus
P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register.
*
7
Pull-up control
Direction
register
Port latch
INT interrupt input
Fig. 15 Block diagram of ports (2)
Analog input pin
selection bit
P3 input level
selection bit
*
14
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupts
Interrupts occur by 15 different sources : 5 external sources, 9 internal sources and 1 software source.
Interrupt control
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit, and they are controlled by the
interrupt disable flag. When the interrupt enable bit and the interrupt
request bit are set to “1” and the interrupt disable flag is set to “0”, an
interrupt is accepted.
The interrupt request bit can be cleared by program but not be set.
The interrupt enable bit can be set and cleared by program.
The reset and BRK instruction interrupt can never be disabled with
any flag or bit. All interrupts except these are disabled when the interrupt disable flag is set.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Table 4 Interrupt vector address and priority
Vector addresses (Note 1)
Interrupt source
Reset (Note 2)
Serial I/O1 receive
Serial I/O1 transmit
INT0
INT1 (Note 3)
Key-on wake-up
CNTR0
CNTR1
Timer X
Timer Y
Timer Z
Timer A
Serial I/O2
A-D conversion
Timer 1
Reserved area
BRK instruction
Note 1: Vector addressed contain internal jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3: It is an interrupt which can use only for 36 pin version.
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
High-order
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
Low-order
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
Interrupt request generating conditions
At reset input
At completion of serial I/O1 data receive
At completion of serial I/O1 transmit shift or
when transmit buffer is empty
At detection of either rising or falling edge of
INT0 input
At detection of either rising or falling edge of
INT1 input
At falling of conjunction of input logical level for
port P0 (at input)
At detection of either rising or falling edge of
CNTR0 input
At detection of either rising or falling edge of
CNTR1 input
At timer X underflow
At timer Y underflow
At timer Z underflow
At timer A underflow
At completion of transmit/receive shift
At completion of A-D conversion
At timer 1 underflow
Not available
At BRK instruction execution
Interrupt operation
Upon acceptance of an interrupt the following operations are automatically performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status register are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. Concurrently with the push operation, the interrupt destination
address is read from the vector table into the program counter.
Notes on use
When the active edge of an external interrupt (INT0, INT1,CNTR0) is
set, the interrupt request bit may be set.
Therefore, please take following sequence:
1. Disable the external interrupt which is selected.
2. Change the active edge in interrupt edge selection register. (in
case of CNTR0: Timer X mode register, in case of CNTR1: Timer
A mode register)
3. Clear the set interrupt request bit to “0”.
4. Enable the external interrupt which is selected.
Remarks
Non-maskable
Valid only when serial I/O1 is selected
Valid only when serial I/O1 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (valid at falling)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
STP release timer underflow
Non-maskable software interrupt
15
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 16 Interrupt control
b7 b0
b7 b0
b7 b0
BRK instruction
Reset
Interrupt edge selection register
(INTEDGE : address 003A
INT0 interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
INT
1
interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
Not used (returns “0” when read)
P0
0
key-on wakeup enable bit
0 : Key-on wakeup enabled
1 : Key-on wakeup disabled
Interrupt request register 1
(IREQ1 : address 003C
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
INT0 interrupt request bit
INT
1
interrupt request bit
Key-on wake up interrupt request bit
CNTR
0
interrupt request bit
CNTR
1
interrupt request bit
Timer X interrupt request bit
Interrupt request register 2
(IREQ2 : address 003D
Timer Y interrupt request bit
Timer Z interrupt request bit
Timer A interrupt request bit
Serial I/O2 interrupt request bit
A-D conversion interrupt request bit
Timer 1 interrupt request bit
Not used (returns “0” when read)
16
)
16
)
16
)
Interrupt request
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
b7 b0
b7 b0
Interrupt control register 1
(ICON1 : address 003E
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
INT
0
interrupt enable bit
INT
1
interrupt enable bit
Key-on wake up interrupt enable bit
CNTR
0
CNTR
1
Timer X interrupt enable bit
Interrupt control register 2
(ICON2 : address 003F
Timer Y interrupt enable bit
Timer Z interrupt enable bit
Timer A interrupt enable bit
Serial I/O2 interrupt enable bit
A-D conversion interrupt enable bit
Timer 1 interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
Fig. 17 Structure of Interrupt-related registers
16
16
)
interrupt enable bit
interrupt enable bit
16
)
0 : Interrupts disabled
1 : Interrupts enabled
0 : Interrupts disabled
1 : Interrupts enabled
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Key Input Interrupt (Key-On Wake-Up)
A key-on wake-up interrupt request is generated by applying “L” level
to any pin of port P0 that has been set to input mode.
In other words, it is generated when the AND of input level goes from
“1” to “0”. An example of using a key input interrupt is shown in Figure 18, where an interrupt request is generated by pressing one of
the keys provided as an active-low key matrix which uses ports P00
to P03 as input ports.
Port PXx
“L” level output
PULL register
bit 3 = “0”
***
Port P0
P07 output
latch
7
Port P0
Direction register = “1”
7
Falling edge
detection
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Key input interrupt request
P0
P0
P0
P0
P0
P0
P0
6
output
5
output
4
output
3
2
1
0
input
input
input
input
PULL register
bit 3 = “0”
***
PULL register
bit 3 = “0”
***
PULL register
bit 3 = “0”
***
PULL register
bit 2 = “1”
***
PULL register
bit 2 = “1”
***
PULL register
bit 1 = “1”
***
PULL register
bit 0 = “1”
***
Port P0
Direction register = “1”
Port P0
6
latch
Port P0
Direction register = “1”
Port P0
5
latch
Port P0
Direction register = “1”
Port P0
4
latch
Port P0
Direction register = “0”
Port P0
3
latch
Port P0
Direction register = “0”
Port P0
2
latch
Port P0
Direction register = “0”
Port P0
1
latch
Port P0
Direction register = “0”
Port P0
0
latch
6
5
4
3
2
1
0
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Port P0
Input read circuit
* P-channel transistor for pull-up
** CMOS output buffer
Fig. 18 Connection example when using key input interrupt and port P0 block diagram
17
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timers
The 7540 Group has 5 timers: timer 1, timer A, timer X, timer Y and
timer Z.
The division ratio of every timer and prescaler is 1/(n+1) provided
that the value of the timer latch or prescaler is n.
All the timers are down count timers. When a timer reaches “0”, an
underflow occurs at the next count pulse, and the corresponding timer
latch is reloaded into the timer. When a timer underflows, the interrupt request bit corresponding to each timer is set to “1”.
●Timer 1
Prescaler 1 always counts f(XIN)/16. Timer 1 always counts the
prescaler 1 output and periodically sets the interrupt request bit.
●Timer A
Timer A is a 16-bit timer that can be selected in one of four modes.
• Timer Mode
The timer counts f(XIN)/16.
• Period Measurement Mode
CNTR1 interrupt request is generated at rising/falling edge of
CNTR1 pin input signal. Simultaneously, the value in timer A latch
is reloaded in timer A and timer A continues counting down. Except for the above-mentioned, the operation in period measurement mode is the same as in timer mode.
The timer value just before the reloading at rising/falling of CNTR1
pin input signal is retained until the timer A is read once after the
reload.
The rising/falling timing of CNTR1 pin input signal is found by CNTR1
interrupt.
b7 b0
Timer A mode register
(TAM : address 001D
Not used (return “0” when read)
Timer A operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Period measurement mode
1 0 : Event counter mode
1 1 : Pulse width HL continuously
measurement mode
CNTR
1
active edge switch bit
0 : Count at rising edge in event counter mode
Measure the falling edge period in period
measurement mode
Falling edge active for CNTR
1 : Count at falling edge in event counter mode
Measure the rising edge period in period
measurement mode
Rising edge active for CNTR
Timer A stop control bit
0 : Count start
1 : Count stop
Fig. 19 Structure of timer A mode register
16
)
1
interrupt
1
interrupt
• Event Counter Mode
The timer counts signals input through the CNTR1 pin.
Except for this, the operation in event counter mode is the same
as in timer mode.
• Pulse Width HL Continuously Measure-ment Mode
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode.
■ Note
● CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit. However, in pulse width HL continuously measurement
mode, CNTR1 interrupt request is generated at both rising and
falling edges of CNTR1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
18
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
●Timer X
Timer X can be selected in one of 4 operating modes by setting the
timer X mode register.
• Timer Mode
The timer counts the signal selected by the timer X count source
selection bits.
• Pulse Output Mode
The timer counts the signal selected by the timer X count source
selection bits, and outputs a signal whose polarity is inverted each
time the timer value reaches “0”, from the CNTR0 pin.
When the CNTR0 active edge switch bit is “0”, the output of the
CNTR0 pin is started with an “H” output. At “1”, this output is started
with an “L” output. When using a timer in this mode, set the port
P14 direction register to output mode. Also, in the pulse output
mode, the inverted waveform of pulse output from CNTR0 pin can
be output from TXOUT pin by setting the P03/TXOUT output valid
bit to “1” . When using a timer in this mode, set the port P03 direction register to output mode.
• Event Counter Mode
The operation in the event counter mode is the same as that in
the timer mode except that the timer counts the input signal from
the CNTR0 pin.
When the CNTR0 active edge switch bit is “0”, the timer counts
the rising edge of the CNTR0 pin. When this bit is “1”, the timer
counts the falling edge of the CNTR0 pin.
• Pulse Width Measurement Mode
When the CNTR0 active edge switch bit is “0”, the timer counts
the signal selected by the timer X count source selection bit while
the CNTR0 pin is “H”. When this bit is “1”, the timer counts the
signal while the CNTR0 pin is “L”.
In any mode, the timer count can be stopped by setting the timer
X count stop bit to “1”. Each time the timer overflows, the interrupt
request bit is set.
b7 b0
Timer X mode register
(TXM : address 002B
Timer X operating mode bits
b1 b0
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNTR
0
active edge switch bit
0 : Interrupt at falling edge
Count at rising edge
(in event counter mode)
1 : Interrupt at rising edge
Count at falling edge
(in event counter mode)
Timer X count stop bit
0 : Count start
1 : Count stop
P03/TX
OUT
0 : Output invalid (I/O port)
1 : Output valid (Inverted CNTR
Not used (return “0” when read)
output valid bit
Fig. 20 Structure of timer X mode register
b7 b0
Timer count source set register
(TCSS : address 002E
Timer X count source selection bits
b1 b0
0 0 : f(X
0 1 : f(X
1 0 : f(X
1 1 : Not available
Timer Y count source selection bits
b3 b2
0 0 : f(X
0 1 : f(X
1 0 : Ring oscillator output (Note)
1 1 : Not available
Timer Z count source selection bits
b5 b4
0 0 : f(X
0 1 : f(X
1 0 : Timer Y underflow
1 1 : Not available
Fix this bit to “0”.
Not used (return “0” when read)
IN)/16
IN)/2
IN)
IN)/16
IN)/2
IN)/16
IN)/2
16
16)
)
0
output)
Note : System operates using a ring oscillator as a count source by setting
the ring oscillator to oscillation enabled by bit 3 of CPUM.
Fig. 21 Timer count source set register
19
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
●Timer Y
Timer Y is an 8-bit timer and can be selected in one of 2 operating
modes by setting the timer Y, Z mode register (TYZM).
• Timer mode
• Programmable waveform generation mode
The division ratio of timer Y and prescaler Y is 1/(n+1) provided that
the value of the timer latch or prescaler Y latch is n.
(1)Timer mode
• Mode select
Timer mode is selected by setting timer Y operation mode bit (b0)
of TYZM to “0”.
• Count source select
The count source is f(XIN)/2 or f(XIN)/16.
• Interrupt
When an underflow occurs, timer Y interrupt request bit (b0) of
IREQ2 is set to “1”.
• Operation description
After reset release, timer Y is operating because the timer Y count
stop bit (b3) of TYZM is “0”. Timer operation is stopped by setting
b3 of TYZM to “1”. In the timer mode, the timer count value is set
by timer Y primary latch (TYP). When a value is set to TYP while
timer is stopped, the setting value is written to latch and timer simultaneously.
When timer Y reaches “00”, an underflow occurs at the next count
pulse, and the timer Y latch is reloaded into the timer and count
continues. When timer value is changed during the count operation, either “writing to latch and timer simultaneously” or “writing to
only latch” can be selected by setting the timer Y write control bit
(b2) of TYZM. When selecting “writing to only latch”, the timer count
value is changed after the next underflow.
(2)Programmable waveform generation mode
• Mode select
Timer mode is selected by setting timer Y operation mode bit (b0)
of TYZM to “1”.
When this mode is selected, set timer Y write control bit (b2) of
TYZM to “1” (“writing to only latch” selected).
• Count source select
The count source is f(XIN)/2 or f(XIN)/16.
• Interrupt
When an underflow occurs, timer Y interrupt request bit (b0) of
IREQ is set to “1”.
• Operation description
After reset release, timer Y is operating because the timer Y count
stop bit (b3) of TYZM is “0”. MCU operates in the programmable
waveform generation mode when timer Y operation mode bit (b0)
of TYZM is set to “1” and b3 to “0” after timer Y operation is stopped
by setting b3 of TYZM to “1”.
In the programmable waveform generation mode, timer counts the
setting value of timer Y primary latch (TYP) and the setting value
of timer Y secondary latch (TYS) alternately, the waveform inverted
each time TYP and TYS underflow is output from TYOUT pin. The
active edge of output waveform is set by the timer Y output level
latch (b4) of the timer Y, Z waveform output control register (PUM).
When “0” is set to b4 of PUM, the initial state of timer at stop is “L”,
and “H” interval by the setting value of TYP or “L” interval by the
setting value of TYS is output alternately. When “1” is set to b4 of
PUM, the initial state of timer at stop is “H”, and “L” interval by the
setting value of TYP or “H” interval by the setting value of TYS is
output alternately.
Also, in this mode, the primary interval and the secondary interval
of the output waveform can be extended respectively for 0.5 cycle
of timer count source clock by setting the timer Y primary waveform extension control bit (b0) and the timer Y secondary waveform extension control bit (b1) of PUM to “1”. As a result, the waveforms of more accurate resolution can be output.
When b0 and b1 of PUM are used, the frequency and duty of the
output waveform are as follows;
Waveform frequency:
FTYOUT = (2 ✕ TMCL)/(2 ✕ (TYP+1) + 2 ✕ (TYS) + (EXPYP + EXPYS))
Duty:
DTYOUT = (2 ✕ (TYP + 1)) + EXPYP)/(2 ✕ (TYS + 1) + EXPYS))
TMCL: Timer Y count clock f(XIN)/2 or f(XIN)/16
TYP: Timer Y primary latch (8 bits)
TYS: Timer Y secondary latch (8 bits)
EXPYP: Timer Y primary waveform extension control bit (1 bit)
EXPYS: Timer Y secondary waveform extension control bit (1 bit)
When using the programmable waveform generation mode, note
the following;
Notes on using the programmable waveform generation mode
• When setting and changing TYP, TYS, EXPYP and EXPYS, write
to TYP at last because the setting to them is executed all at once
by writing to TYP. Even when TYP is not changed, write the same
value. The value is reloaded to timer at the beginning of the next
primary interval.
• Set by software in order not to execute the writing to timer Y primary and the timing of timer underflow simultaneously. When reading the timer Y secondary, the undefined value is read out. However, while timer counts the setting value of the timer Y secondary,
the count values at the secondary interval can be identified by
reading the timer Y primary.
• In this mode, set port P01 which is also used as TYOUT pin to output.
• B0 and b1 of PUM can be used only when “0016” is set to prescaler
Y.
20
Loading...