Mitsubishi M37540M4-XXXGP, M37540M4-XXXFP, M37540E8GP, M37540E8FP, M37540RSS Datasheet

...
PRELIMINARY
Notice: This is not a final specification.
e parametric limits are subject to change.
Som
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

DESCRIPTION

The 7540 Group is the 8-bit microcomputer based on the 740 fam­ily core technology. The 7540 Group has a serial I/O, 8-bit timers, a 16-bit timer, and an A-D converter, and is useful for control of home electric appli­ances and office automation equipment.

FEATURES

The minimum instruction execution time ......................... 0.34 µs
(at 6 MHz oscillation frequency, double-speed mode for the shortest instruction)
Memory size ROM.......................................... 16 K to 32 K bytes
RAM ............................................. 512 to 768 bytes
Programmable I/O ports....................... 29 (25 in 32-pin version)
Interrupts ................................................. 15 sources, 15 vectors
................................. (14 sources, 14 vectors for 32-pin version)
Timers............................................................................. 8-bit 4
...................................................................................... 16-bit 1
Serial I/O1 ................... 8-bit 1 (UART or Clock-synchronized)
Serial I/O2 ...................................8-bit 1 (Clock-synchronized)
A-D converter ............................................... 10-bit ✕ 8 channels
.................................................... (6 channels for 32-pin version)
Clock generating circuit............................................. Built-in type
(low-power dissipation by a ring oscillator enabled) (connect to external ceramic resonator or quartz-crystal oscilla­tor permitting RC oscillation)
Watchdog timer ............................................................ 16-bit 1
Power source voltage
XIN oscillation frequency at ceramic oscillation, in double-speed mode
At 6 MHz.................................................................... 4.5 to 5.5 V
XIN oscillation frequency at ceramic oscillation, in high-speed mode
At 8 MHz.................................................................... 4.0 to 5.5 V
At 4 MHz.................................................................... 2.4 to 5.5 V
At 2 MHz.................................................................... 2.2 to 5.5 V
XIN oscillation frequency at RC oscillation
At 4 MHz.................................................................... 4.0 to 5.5 V
At 2 MHz.................................................................... 2.4 to 5.5 V
At 1 MHz.................................................................... 2.2 to 5.5 V
Power dissipation
Mask ROM version.......................................22.5 mW (standard)
One Time PROM version ................................30 mW (standard)
Operating temperature range...................................–20 to 85 °C
(–40 to 85 °C for extended operating temperature version)

APPLICATION

Office automation equipment, factory automation equipment, home electric appliances, consumer electronics, car, etc.
Note: Serial I/O2 can be used in the following cases; (1) Serial I/O1 is not used, (2) Serial I/O1 is used as UART and BRG output divided by 16 is selected
as the synchronized clock.

PIN CONFIGURATION (TOP VIEW)

P0
7
P12/S
P13/S
P10/RXD
P11/TXD
CLK1/SCLK2
RDY1/SDATA2
P14/CNTR
P20/ P21/
AN AN
1 1
0 0
1
OUT
/TX
5
P0
23
2
3
/AN
3
P2
4
P0
22
3
4
/AN
4
P2
3
P0
201718
21
4
5
5
/AN
5
P2
6
P0
24
25 26 27
M37540M4-XXXGP
28
M37540M4T-XXXGP
29 30 31 32
M37540E8GP
1
2
/AN
2
P2
OUT
OUT
/TY
/TZ
1
2
P0
P0
19
6
REF
V
RESET
1
0
/INT
/CNTR
7
0
P3
P0
8
7
SS
CC
V
CNV
16 15 14 13 12 11 10
9
P34(LED4) P3
3
(LED3)
P3
2
(LED2)
1
(LED1)
P3 P3
0
(LED0)
V
SS
X
OUT
X
IN
Package type: 32P6U-A
Fig. 1 M37540M4-XXXGP, M37540E8GP, M37540M4T-XXXGP pin configuration
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
P12/S
P13/S
CLK1/SCLK2
RDY1/SDATA2
P14/CNTR
P20/AN P21/AN P22/AN P23/AN P24/AN P25/AN
P26/AN P27/AN
REF
V
RESET
CNV
SS
Vcc
X
IN
X
OUT
V
SS
1 2
10
3 4 5 6 7 8 9
11 12 13 14 15 16 17 18
M37540M4-XXXFP
M37540M4T-XXXFP
M37540E8FP
0 0 1 2 3 4 5
6 7
36 35 34 33 32 31 30 29 28 27
26 25 24 23 22 21
20 19
P11/TXD P10/RXD P0 P0 P0 P0 P03/TX P02/TZ P01/TY
1
1 7 6 5 4
OUT
OUT
OUT
P00/CNTR P37/INT P3
0
6
(LED6)/INT
P35(LED5)
4
(LED4)
P3 P3
3
(LED3)
2
(LED2)
P3 P31(LED1) P30(LED0)
1
1
Package type: 36P2R-A
Fig. 2 M37540M4-XXXFP, M37540M4T-XXXFP, M37540E8FP pin configuration
P12/S
P13/S
CLK1/SCLK2
RDY1/SDATA2
P14/CNTR
P20/AN P21/AN P22/AN P23/AN P24/AN P25/AN
V
REF
RESET
CNV
SS
V
CC
X
X
OUT
V
SS
1
2 0 0 1 2 3 4 5
IN
3
4
5
6
7
8
9
10 11 12 13 14
14 15
15 16
16
M37540E8SP
32 31 30 29 28
M37540M4-XXXSP
27 26 25 24
23 22 21 20 19 18 17
Package type: 32P4B
P11/TXD P10/RXD
P0
7
P0
6
P0
5
P0
4
P03/TX
OUT
P02/TZ
OUT
P01/TY
OUT
P0
0
/CNTR
P37/INT
0
P34(LED4) P33(LED3) P3
2
(LED2)
1
(LED1)
P3 P30(LED0)
1
1
1
Fig. 3 M37540M4-XXXSP, M37540E8SP pin configuration
2
PRELIMINARY
Notice: This is not a final specification.
e parametric limits are subject to change.
Som
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
P14/CNTR
NC
NC
P20/AN
1
/AN
P2
NC
2
/AN
P2 P23/AN P24/AN
P25/AN P26/AN P27/AN
NC
NC
REF
V
RESET
CNV
Vcc
X
X
OUT
V
SS
IN
SS
42 41 40 39
38 37 36 35 34 33
32 31 30 29 28 27
26 25 24 23 22
P13/S
RDY1/SDATA2
P12/S
CLK1/SCLK2
P11/TXD P1 P0 P0 P0 P0 P03/TX P02/TZ P01/TY
1 0/RXD1 7 6 5 4
OUT
OUT
OUT
P00/CNTR NC
P37/INT P3
0
6
(LED6)/INT
P35(LED5)
4
(LED4)
P3 P3
3
(LED3)
P3
2
(LED2) P31(LED1) P30(LED0)
1
1
10
1 2 3 4 5 6 7 8 9
11 12 13 14 15 16 17 18 19 20 21
M37540RSS
0
0 1
2 3 4
5 6 7
Fig. 4 M37540RSS pin configuration
Outline 42S1M
3
PRELIMINARY
X
IN OUT
X
SI/O1(8)
RAM
ROM
CPU
A
X
Y
S
PC
H
PC
L
PS
V
SS
11
RESET
6
V
CC
8
7
CNV
SS
P1(5)
30 28 2629 27
32
31
P2(6)
P3(6)
1215 13
5
Reset input
I/O port P2
I/O port P1I/O port P3
Clock generating circuit
Clock input
Clock output
9
10
4
2 3
1
A-D
converter
(10)
V
REF
Watchdog timer
Reset
0
14
INT
0
1617
SI/O2(8)
CNTR
0
I/O port P0
Prescaler Y (8)
Prescaler Z (8)
Timer X (8)
Timer Z (8)
Timer Y (8)
Key-on wakeup
TY
OUT
TZ
OUT
Prescaler X (8)
CNTR
1
Timer A (16)
P0(8)
25
23 21
19
24 22
20 18
INT
0
Timer 1 (8)
Prescaler 1 (8)
TX
OUT
Notice: This is not a final specification.
Some parametric limits are subject to change.

FUNCTIONAL BLOCK

MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL BLOCK DIAGRAM (Package: 32P6U)
Fig. 5 Functional block diagram (32P6U package)
4
PRELIMINARY
A-D
converter
(10)
X
IN OUT
X
CPU
V
SS
18
RESET
13
V
CC
15
14
CNV
SS
P0(8)
34
32 30 28 33
31 29 27
P1(5)
31
35
2
36
7
56
4
P2(8)
P3(8)
2023 21 19
12
I/O port P2
I/O port P0I/O port P1I/O port P3
16 17
11
9 10
8
0
22
26 2425
SI/O1(8)
RAM
ROM
A
X
Y
S
PC
H
PC
L
PS
Reset input
Clock generating circuit
Clock input Clock output
V
REF
Watchdog timer
Reset
INT
0
SI/O2(8)
CNTR
0
Prescaler Y (8)
Prescaler Z (8)
Timer X (8)
Timer Z (8)
Timer Y (8)
Key-on wakeup
TY
OUT
TZ
OUT
Prescaler X (8)
CNTR
1
Timer A (16)
INT
0
Timer 1 (8)
Prescaler 1 (8)
TX
OUT
INT
1
Notice: This is not a final specification.
e parametric limits are subject to change.
Som
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL BLOCK DIAGRAM (Package: 36P2R)
Fig. 6 Functional block diagram (36P2R package)
5
PRELIMINARY
16
11
13
12
P1(5)
31
31
2
32
5
4
P2(6)
P3(6)
1720 18
10
14
15
9
7 8
6
0
19
2122
P0(8)
30
28 26 24 29
27 25 23
A-D
converter
(10)
X
IN OUT
X
CPU
V
SS
RESET
V
CC
CNV
SS
I/O port P2
I/O port P0I/O port P1
I/O port P3
SI/O1(8)
RAM
ROM
A
X
Y
S
PC
H
PC
L
PS
Reset input
Clock generating circuit
Clock input
Clock output
V
REF
Watchdog timer
Reset
INT
0
SI/O2(8)
CNTR
0
Prescaler Y (8)
Prescaler Z (8)
Timer X (8)
Timer Z (8)
Timer Y (8)
Key-on wakeup
TY
OUT
TZ
OUT
Prescaler X (8)
CNTR
1
Timer A (16)
INT
0
Timer 1 (8)
Prescaler 1 (8)
TX
OUT
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL BLOCK DIAGRAM (Package: 32P4B)
Fig. 7 Functional block diagram (32P4B package)
6
PRELIMINARY
Notice: This is not a final specification.
e parametric limits are subject to change.
Som

PIN DESCRIPTION

Table 1 Pin description
Pin
Vcc, Vss
VREF
CNVss RESET XIN
XOUT
P00/CNTR1 P01/TYOUT P02/TZOUT P03/TXOUT P04–P07
P10/RxD1 P11/TxD1
P12/SCLK1/SCLK2 P13/S
RDY1/SDATA2
P14/CNTR0
P20/AN0–P27/AN
P30–P35
P36/INT1 P37/INT0
Notes 1: VCC = 2.4 to 5.5 V for the extended operating temperature version.
2: P2
6/AN6 and P27/AN7 do not exist for the 32-pin version, so that Port P2 is a 6-bit I/O port.
3: P3
5 and P36/INT1 do not exist for the 32-pin version, so that Port P3 is a 6-bit I/O port.
Name
Power source (Note 1)
Analog reference voltage
CNVss Reset input Clock input
Clock output
I/O port P0
I/O port P1
7
I/O port P2 (Note 2)
I/O port P3 (Note 3)
Apply voltage of 2.2 to 5.5 V to Vcc, and 0 V to Vss.
Reference voltage input pin for A-D converter
Chip operating mode control pin, which is always connected to Vss.
Reset input pin for active L
Input and output pins for main clock generating circuit
Connect a ceramic resonator or quartz crystal oscillator between the XIN and XOUT pins.
For using RC oscillator, short between the XIN and XOUT pins, and connect the capacitor and resistor.
If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
8-bit I/O port.
I/O direction register allows each pin to be individually pro-
grammed as either input or output.
CMOS compatible input level
CMOS 3-state output structure
Whether a built-in pull-up resistor is to be used or not can be de-
termined by program.
5-bit I/O port
I/O direction register allows each pin to be individually pro-
grammed as either input or output.
CMOS compatible input level
CMOS 3-state output structure
CMOS/TTL level can be switched for P10, P12 and P13
8-bit I/O port having almost the same function as P0
CMOS compatible input level
CMOS 3-state output structure
8-bit I/O port
I/O direction register allows each pin to be individually programmed as either input or output.
CMOS compatible input level (CMOS/TTL level can be switched for P36 and P37).
CMOS 3-state output structure
P30 to P36 can output a large current for driving LED.
Whether a built-in pull-up resistor is to be used or not can be de-
termined by program.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Function
Function expect a port function
Key-input (key-on wake up interrupt input) pins
Timer Y, timer Z, timer X and timer A function pin
Serial I/O1 function pin
Serial I/O1 function pin
Serial I/O2 function pin
Timer X function pin
Input pins for A-D converter
Interrupt input pins
7
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

GROUP EXPANSION

Mitsubishi plans to expand the 7540 group as follow:

Memory type

Support for Mask ROM version, One Time PROM version, and Emulator MCU.
ROM size
(bytes)
32K
Under development
16K
Under development

Memory size

ROM/PROM size ............................................... 16 K to 32 K bytes
RAM size ..............................................................512 to 768 bytes

Package

32P4B ......................................... 32-pin shrink plastic molded DIP
32P6U-A ..................................0.8 mm-pitch plastic molded LQFP
36P2R-A ................................. 0.8 mm-pitch plastic molded SSOP
42S1M....................................42-pin shrink ceramic PIGGY BACK
Under development
M37540E8
M37540M4T
M37540M4
0
384
Note: Products under development•••the development schedule and
specification may be revised without notice.
Fig. 8 Memory expansion plan
Currently supported products are listed below.
Table 2 List of supported products
Product
M37540M4-XXXSP M37540M4-XXXFP M37540M4T-XXXFP M37540M4-XXXGP M37540M4T-XXXGP M37540E8SP M37540E8FP M37540E8GP M37540RSS
(P) ROM size (bytes) ROM size for User ()
16384
(16254)
32768
(32638)
RAM size
(bytes)
512
768
768
Package
32P4B
36P2R-A
32P6U-A
32P4B 36P2R-A 32P6U-A
42S1M
512 768
Remarks
Mask ROM version Mask ROM version Mask ROM version (extended operating temperature version) Mask ROM version Mask ROM version (extended operating temperature version) One Time PROM version (blank) One Time PROM version (blank) One Time PROM version (blank) Emulator MCU
RAM size
(bytes)
8
PRELIMINARY
Notice: This is not a final specification.
e parametric limits are subject to change.
Som
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION Central Processing Unit (CPU)
The MCU uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine-language instructions or the SERIES 740 <SOFTWARE> USERS MANUAL for details on each instruction set. Machine-resident 740 family instructions are as follows:
1. The FST and SLW instructions cannot be used.
2. The MUL and DIV instructions can be used.
3. The WIT instruction can be used.
4. The STP instruction can be used. This instruction cannot be used while CPU operates by a ring os­cillator.
Accumulator (A)
The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator.
Index register X (X), Index register Y (Y)
Both index register X and index register Y are 8-bit registers. In the index addressing modes, the value of the OPERAND is added to the contents of register X or register Y and specifies the real address. When the T flag in the processor status register is set to “1”, the value contained in index register X becomes the address for the second OPERAND.
Stack pointer (S)
The stack pointer is an 8-bit register used during subroutine calls and interrupts. The stack is used to store the current address data and processor status when branching to subroutines or interrupt routines. The lower eight bits of the stack address are determined by the contents of the stack pointer. The upper eight bits of the stack ad­dress are determined by the Stack Page Selection Bit. If the Stack Page Selection Bit is “0”, then the RAM in the zero page is used as the stack area. If the Stack Page Selection Bit is “1”, then RAM in page 1 is used as the stack area. The Stack Page Selection Bit is located in the SFR area in the zero page. Note that the initial value of the Stack Page Selection Bit varies with each microcomputer type. Also some microcom­puter types have no Stack Page Selection Bit and the upper eight bits of the stack address are fixed. The operations of pushing reg­ister contents onto the stack and popping them from the stack are shown in Fig. 9.
Program counter (PC)
The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed.
b15
PC
b7
A
b7
X
b7
Y
b7
S
b7
H
PC
b7
b0
Accumulator
b0
Index Register X
b0
Index Register Y
b0
Stack Pointer
b0
L
Program Counter
b0
Processor Status Register (PS)
CZIDBTVN
Carry Flag Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag
Fig. 9 740 Family CPU register structure
9
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
On-going Routine
Store Return Address on Stack
Restore Return Address
Interrupt request
M (S) (PCH)
(S) (S – 1)
M (S) (PCL)
(S) (S – 1)
Subroutine
Execute RTS
(S) (S + 1)
(PCL) M (S)
(S) (S + 1)
(PCH) M (S)
(Note)
Execute JSR
M (S) (PCH)
(S) (S – 1)
M (S) (PCL)
(S) (S – 1)
M (S) (PS)
(S) (S – 1)
Interrupt
Service Routine
Execute RTI
(S) (S + 1)
(PS) M (S)
(S) (S + 1)
(PCL) M (S)
(S) (S + 1)
Store Return Address on Stack
Store Contents of Processor Status Register on Stack
I Flag 0 to 1 Fetch the Jump Vector
Restore Contents of Processor Status Register
Restore Return Address
Note : The condition to enable the interrupt Interrupt enable bit is 1
Fig. 10 Register push and pop at interrupt generation and subroutine call
Table 3 Push and pop instructions of accumulator or processor status register
Push instruction to stack Accumulator Processor status register
PHA PHP
Interrupt disable flag is 0
(PCH) M (S)
Pop instruction from stack
PLA PLP
10
PRELIMINARY
Notice: This is not a final specification.
e parametric limits are subject to change.
Som
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Processor status register (PS)
The processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. After reset, the Interrupt disable (I) flag is set to “1”, but all other flags are undefined. Since the Index X mode (T) and Decimal mode (D) flags directly affect arithmetic operations, they should be initialized in the beginning of a program.
(1) Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction.
(2) Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”.
(3) Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is 1. When an interrupt occurs, this flag is automatically set to “1” to prevent other interrupts from interfering until the current interrupt is serviced.
(4) Decimal mode flag (D)
The D flag determines whether additions and subtractions are ex­ecuted in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic.
(5) Break flag (B)
The B flag is used to indicate that the current interrupt was gener­ated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to gener­ate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”. The saved processor status is the only place where the break flag is ever set.
(6) Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed be­tween accumulator and memory, e.g. the results of an operation between two memory locations is stored in the accumulator. When the T flag is “1”, direct arithmetic operations and direct data trans­fers are enabled between memory locations, i.e. between memory and memory, memory and I/O, and I/O and I/O. In this case, the result of an arithmetic operation performed on data in memory lo­cation 1 and memory location 2 is stored in memory location 1. The address of memory location 1 is specified by index register X, and the address of memory location 2 is specified by normal ad­dressing modes.
(7) Overflow flag (V)
The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location oper­ated on by the BIT instruction is stored in the overflow flag.
(8) Negative flag (N)
The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag.
Table 4 Set and clear instructions of each bit of processor status register
Set instruction Clear instruction
C flag
SEC CLC
Z flag
– –
I flag
SEI CLI
D flag
SED
CLD
B flag
– –
T flag
SET CLT
V flag
CLV
N flag
– –
11
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[CPU mode register] CPUM
The CPU mode register contains the stack page selection bit. This register is allocated at address 003B16.
Switching method of CPU mode register
Switch the CPU mode register (CPUM) at the head of program af­ter releasing Reset in the following method.
b7 b0
CPU mode register (CPUM: address 003B
Processor mode bits (Note 1) b1 b0 0 0 Single-chip mode 0 1 1 0 1 1
Stack page selection bit 0 : 0 page 1 : 1 page
Ring oscillator oscillation control bit 0 : Ring oscillator oscillation enabled 1 : Ring oscillator oscillation stop
IN
oscillation control bit
X 0 : Ceramic or RC oscillation enabled 1 : Ceramic or RC oscillation stop
Oscillation mode selection bit (Note 1) 0 : Ceramic oscillation 1 : RC oscillation
Clock division ratio selection bits b7 b6 0 0 : f(φ) = f(X 0 1 : f(φ) = f(X 1 0 : applied from ring oscillator 1 1 : f(φ) = f(X
Note 1: The bit can be rewritten only once after releasing reset. After rewriting
it is disable to write any data to the bit. However, by reset the bit is initialized and can be rewritten, again. (It is not disable to write any data to the bit for emulator MCU M37540RSS.)
2: These bits are used only when a ceramic oscillation is selected.
Do not use these when an RC oscillation is selected.
16
, initial value: 8016)
Not available
IN
)/2 (High-speed mode)
IN
)/8 (Middle-speed mode)
IN
) (Double-speed mode)(Note 2)
After releasing reset
Switch the oscillation mode
selection bit (bit 5 of CPUM)
Wait by ring oscillator operation until establishment of oscillator clock
Switch the clock division ratio
selection bits (bits 6 and 7 of CPUM)
Fig. 11 Structure of CPU mode register
Start with a built-in ring oscillator
An initial value is set as a ceramic oscillation mode. When it is switched to an RC oscillation, its oscillation starts.
When using a ceramic oscillation, wait until establlishment of oscillation from oscillation starts. When using an RC oscillation, wait time is not required basically (time to execute the instruction to switch from a ring oscillator meets the requirement).
Select 1/1, 1/2, 1/8 or ring oscillator.
Main routine
Fig. 12 Switching method of CPU mode register
12
PRELIMINARY
Notice: This is not a final specification.
e parametric limits are subject to change.
Som
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Memory

Special function register (SFR) area
The SFR area in the zero page contains control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for a stack area of subroutine calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is a user area for storing programs.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
RAM
RAM area
RAM capacity
(bytes)
512 768
address
XXXX
023F 033F
16 16
16
Zero page
The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function regis­ters (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.
Special page
The 256 bytes from addresses FF00
16 to FFFF16 are called the
special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Ac­cess to this area with only 2 bytes is possible in the special page addressing mode.
0000
16
SFR area
0040
0100
XXXX
16
16
16
Zero page
Reserved area
0440
16
Not used
ROM area
ROM capacity
(bytes)
16384 32768
address YYYY
C000 8000
Fig. 13 Memory map diagram
YYYY
16
Reserved ROM area
(128 bytes)
ZZZZ
16
ROM
FF00
16
address
16
16
16
ZZZZ
C080 8080
16 16
16
FFDC
FFFE
FFFF
16
Interrupt vector area
16
Reserved ROM area
16
Special page
13
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port P0 (P0)
0000
16
Port P0 direction register (P0D)
0001
16
Port P1 (P1)
0002
16
Port P1 direction register (P1D)
0003
16
Port P2 (P2)
0004
16
Port P2 direction register (P2D)
0005
16
Port P3 (P3)
0006
16
Port P3 direction register (P3D)
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
Pull-up control register (PULL)
0016
16
Port P1P3 control register (P1P3C)
0017
16
Transmit/Receive buffer register (TB/RB)
0018
16
Serial I/O1 status register (SIO1STS)
0019
16
Serial I/O1 control register (SIO1CON)
001A
16
UART control register (UARTCON)
001B
16
Baud rate generator (BRG)
001C
16
Timer A mode register (TAM)
001D
16
001E
16
Timer A (low-order) (TAL)
001F
16
Timer A (high-order) (TAH)
Timer Y, Z mode register (TYZM)
0020
16
Prescaler Y (PREY)
0021
16
Timer Y secondary (TYS)
0022
16
Timer Y primary (TYP)
0023
16
Timer Y, Z waveform output control register (PUM)
0024
16
Prescaler Z (PREZ)
0025
16
Timer Z secondary (TZS)
0026
16
Timer Z primary (TZP)
0027
16
Prescaler 1 (PRE1)
0028
16
Timer 1 (T1)
0029
16
One-shot start register (ONS)
002A
16
Timer X mode register (TXM)
002B
16
Prescaler X (PREX)
002C
16
Timer X (TX)
002D
16
Timer count source set register (TCSS)
002E
16
002F
16
Serial I/O2 control register (SIO2CON)
0030
16
Serial I/O2 register (SIO2)
0031
16
0032
16
0033
16
A-D control register (ADCON)
0034
16
A-D conversion register (low-order) (ADL)
0035
16
A-D conversion register (high-order) (ADH)
0036
16
0037
16
MISRG
0038
16
Watchdog timer control register (WDTCON)
0039
16
Interrupt edge selection register (INTEDGE)
003A
16
CPU mode register (CPUM)
003B
16
Interrupt request register 1 (IREQ1)
003C
16
Interrupt request register 2 (IREQ2)
003D
16
Interrupt control register 1 (ICON1)
003E
16
Interrupt control register 2 (ICON2)
003F
16
Note : Do not access to the SFR area including nothing.
Fig. 14 Memory map of special function register (SFR)
14
PRELIMINARY
Notice: This is not a final specification.
e parametric limits are subject to change.
Som
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

I/O Ports

[Direction registers] PiD
The I/O ports have direction registers which determine the input/ output direction of each pin. Each bit in a direction register corre­sponds to one pin, and each pin can be set to be input or output. When “1” is set to the bit corresponding to a pin, this pin becomes an output port. When “0” is set to the bit, the pin becomes an in­put port. When data is read from a pin set to output, not the value of the pin itself but the value of port latch is read. Pins set to input are float­ing, and permit reading pin values. If a pin set to input is written to, only the port latch is written to and the pin remains floating.
b7 b0
Pull-up control register (PULL: address 0016
[Pull-up control register] PULL
By setting the pull-up control register (address 001616), ports P0 and P3 can exert pull-up control by program. However, pins set to output are disconnected from this control and cannot exert pull-up control.
[Port P1P3 control register] P1P3C
By setting the port P1P3 control register (address 0017 CMOS input level or a TTL input level can be selected for ports P10, P12, P13, P36, and P37 by program.
16
, initial value: 0016)
16), a
P00 pull-up control bit P0
1
pull-up control bit
P0
2
, P03 pull-up control bit
P0
4
– P07 pull-up control bit
P3
0
– P33 pull-up control bit
Note 1: Pins set to output ports are disconnected from pull-up control.
2: Set the P3
Fig. 15 Structure of pull-up control register
5
, P36 pull-up control bit to 1 (initial value: 0) for 32-pin version.
b7 b0
Note: Keep setting the P36/INT1 input level selection bit
to 0 (initial value) for 32-pin version.
P3
4
pull-up control bit
P3
5
, P36 pull-up control bit
P3
7
pull-up control bit
Port P1P3 control register (P1P3C: address 0017
P37/INT0 input level selection bit 0 : CMOS level 1 : TTL level
6
/INT1 input level selection bit
P3 0 : CMOS level 1 : TTL level
0
,P12,P13 input level selection bit
P1 0 : CMOS level 1 : TTL level
Not used
16
, initial value: 0016)
0 : Pull-up Off 1 : Pull-up On
Fig. 16 Structure of port P1P3 control register
15
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 5 I/O port function table
Pin
P00/CNTR1 P01/TYOUT P02/TZOUT P03/TXOUT P04–P07
P10/RxD1 P11/TxD1
P12/SCLK1/SCLK2 P13/SRDY1/SDATA2
P14/CNTR0 P20/AN0–
P27/AN7 P30–P35 P36/INT1
P37/INT0
Notes 1: Ports P10, P12, P13, P36, and P37 are CMOS/TTL level.
2: P2
6/AN6 and P27/AN7 do not exist for the 32-pin version.
3: P3
5 and P36/INT1 do not exist for the 32-pin version.
Name
I/O port P0
I/O port P1
I/O port P2 (Note 2)
I/O port P3 (Note 3)
Input/output
I/O individual bits
I/O format
CMOS compatible input level
CMOS 3-state output (Note 1)
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Non-port function
Key input interrupt Timer X function output Timer Y function output Timer Z function output Timer A function input
Serial I/O1 function input/output
Serial I/O2 function input/output
Timer X function input/output A-D conversion input
External interrupt input
7540 Group
Related SFRs
Pull-up control register Timer Y mode register Timer Z mode register Timer X mode register Timer Y,Z waveform output control register Timer A mode register
Serial I/O1 control register
Serial I/O1 control register Serial I/O2 control register
Timer X mode register A-D control register
Interrupt edge selection register
Diagram No.
(1) (2) (3) (4)
(5) (6)
(7) (8)
(9)
(10)
(11) (12)
16
PRELIMINARY
Notice: This is not a final specification.
e parametric limits are subject to change.
Som
(1)Port P0
0
Pull-up control
Direction register
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2)Ports P0
1, P02
Pull-up control
Direction register
Data bus
(3)Port P0
3
Data bus
(5)Port P1
0
Serial I/O1 enable bit
Receive enable bit
Data bus
Port latch
Direction register
Port latch
Timer output
Direction register
Port latch
CNTR1 interrupt input
To key input interrupt generating circuit
Pull-up control
P0 output valid
To key input interrupt generating circuit
Data bus Port latch
Pulse output mode
P00 key-on wakeup selection bit
(4)Ports P04–P0
Data bus
3
/TX
OUT
(6)Port P1
0
, P12, P13
P1 input level selection bit
Data bus
Timer output
7
Direction register
Port latch
1
P1
1/TxD1
P-channel output disable bit
Serial I/O1 enable bit
Transmit enable bit
Port latch
To key input interrupt generating circuit
Pull-up control
To key input interrupt generating circuit
Direction register
Serial I/O1 input
(7)Port P1
2
S
CLK2
pin
Serial I/O1 synchronous
clock selection bit
Serial I/O1 enable bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Data bus
Serial I/O1, serial I/O2 clock output
selection bit
Direction register
Port latch
Serial I/O1, serial I/O2 clock input
P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register.
*
When the TTL level is selected, there is no hysteresis characteristics.
Fig. 17 Block diagram of ports (1)
*
0
, P12, P13
P1 input level selection bit
Serial I/O1 output
*
17
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(8) Port P1
DATA2
S
Serial I/O mode selection bit
Data bus
3
output in operation signal
S
DATA2
pin selection bit
Serial I/O1 enable bit
S
RDY1
output enable bit
Serial I/O1 ready output Serial I/O2 output
(10) Ports P20–P2
Data bus
Direction register
Port latch
7
Direction register
Port latch
Serial I/O2 input
P10, P12, P13 input level selection bit
*
(9) Port P1
4
Data bus
Pulse output mode
(11) Ports P30–P3
Data bus
Direction register
Port latch
Timer output
5
Pull-up control
Direction register
Port latch
CNTR0 interrupt input
A-D converter input
(12) Ports P36, P3
Data bus
P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register.
*
When the TTL level is selected, there is no hysteresis characteristics.
7
Pull-up control
Direction register
Port latch
INT interrupt input
Fig. 18 Block diagram of ports (2)
Analog input pin selection bit
P3 input level selection bit
*
18
PRELIMINARY
Notice: This is not a final specification.
e parametric limits are subject to change.
Som
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Interrupts

Interrupts occur by 15 different sources : 5 external sources, 9 in­ternal sources and 1 software source.
Interrupt control
All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit, and they are controlled by the interrupt disable flag. When the interrupt enable bit and the in­terrupt request bit are set to “1” and the interrupt disable flag is set to “0”, an interrupt is accepted. The interrupt request bit can be cleared by program but not be set. The interrupt enable bit can be set and cleared by program. The reset and BRK instruction interrupt can never be disabled with any flag or bit. All interrupts except these are disabled when the interrupt disable flag is set. When several interrupts occur at the same time, the interrupts are received according to priority.
Table 6 Interrupt vector address and priority
Vector addresses (Note 1)
Priority
Reset (Note 2) Serial I/O1 receive Serial I/O1 transmit
INT0
INT1 (Note 3)
Key-on wake-up
CNTR0
CNTR1
Timer X Timer Y Timer Z Timer A Serial I/O2 A-D conversion Timer 1 Reserved area BRK instruction
Note 1: Vector addressed contain internal jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority. 3: It is an interrupt which can use only for 36 pin version.
1 2 3
4
5
6
7
8
9 10 11 12 13 14 15 16 17
High-order
FFFD16 FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16 FFEB16
FFE916 FFE716 FFE516 FFE316
FFE116 FFDF16 FFDD16
Low-order
FFFC16
FFFA16 FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16 FFEA16
FFE816 FFE616 FFE416 FFE216
FFE016 FFDE16 FFDC16
Interrupt request generating conditions RemarksInterrupt source
At reset input At completion of serial I/O1 data receive At completion of serial I/O1 transmit shift or
when transmit buffer is empty At detection of either rising or falling edge of
INT0 input At detection of either rising or falling edge of
INT1 input At falling of conjunction of input logical level
for port P0 (at input) At detection of either rising or falling edge of
CNTR0 input At detection of either rising or falling edge of
CNTR1 input At timer X underflow At timer Y underflow At timer Z underflow At timer A underflow At completion of transmit/receive shift At completion of A-D conversion At timer 1 underflow Not available At BRK instruction execution
Interrupt operation
Upon acceptance of an interrupt the following operations are auto­matically performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status reg­ister are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt request bit is cleared.
4. Concurrently with the push operation, the interrupt destination address is read from the vector table into the program counter.
Notes on use
When the active edge of an external interrupt (INT0, INT1,CNTR0,CNTR1) is set, the interrupt request bit may be set to “1”. Related register: Interrupt edge selection register (address 003A16) When not requiring the interrupt occurrence synchronized with this setting, take following sequence:
1. Clear the interrupt enable bit to “0” (disabled).
2. Set the interrupt edge selection bit to “1”.
3. Clear the interrupt request bit to “0” after 1 or more instructions have been executed.
4. Set the interrupt enable bit to “1” (enabled).
Non-maskable Valid only when serial I/O1 is selected Valid only when serial I/O1 is
selected External interrupt
(active edge selectable) External interrupt
(active edge selectable) External interrupt (valid at falling)
External interrupt (active edge selectable)
External interrupt (active edge selectable)
STP release timer underflow
Non-maskable software interrupt
19
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 19 Interrupt control
b7 b0
b7 b0
b7 b0
BRK instruction
Reset
Interrupt edge selection register
(INTEDGE : address 003A
INT0 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active INT
1
interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active Not used (returns 0 when read) P0
0
key-on wakeup enable bit 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled
Interrupt request register 1 (IREQ1 : address 003C
Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit INT
0
interrupt request bit
INT
1
interrupt request bit Key-on wake up interrupt request bit CNTR
0
interrupt request bit
CNTR
1
interrupt request bit
Timer X interrupt request bit
Interrupt request register 2 (IREQ2 : address 003D
Timer Y interrupt request bit Timer Z interrupt request bit Timer A interrupt request bit Serial I/O2 interrupt request bit A-D conversion interrupt request bit Timer 1 interrupt request bit Not used (returns 0 when read)
16
, initial value : 0016)
16
, initial value : 0016)
16
, initial value : 0016)
Interrupt request
0 : No interrupt request issued 1 : Interrupt request issued
0 : No interrupt request issued 1 : Interrupt request issued
b7 b0
b7 b0
Interrupt control register 1 (ICON1 : address 003E
Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit
0
INT INT
1
Key-on wake up interrupt enable bit CNTR CNTR Timer X interrupt enable bit
Interrupt control register 2 (ICON2 : address 003F
Timer Y interrupt enable bit Timer Z interrupt enable bit Timer A interrupt enable bit Serial I/O2 interrupt enable bit A-D conversion interrupt enable bit Timer 1 interrupt enable bit Not used (returns 0 when read) (Do not write 1 to this bit)
Fig. 20 Structure of Interrupt-related registers
20
16
, initial value : 0016)
interrupt enable bit
interrupt enable bit (Do not write 1 to this bit for 32-pin version)
0
interrupt enable bit
1
interrupt enable bit
16
, initial value : 0016)
0 : Interrupts disabled 1 : Interrupts enabled
0 : Interrupts disabled 1 : Interrupts enabled
PRELIMINARY
Notice: This is not a final specification.
e parametric limits are subject to change.
Som
Key Input Interrupt (Key-On Wake-Up)
A key-on wake-up interrupt request is generated by applying “L” level to any pin of port P0 that has been set to input mode. In other words, it is generated when the AND of input level goes from “1” to “0”. An example of using a key input interrupt is shown in Figure 21, where an interrupt request is generated by pressing one of the keys provided as an active-low key matrix which uses ports P00 to P03 as input ports.
Port PXx L level output
PULL register bit 3 = “0”
***
Port P0
P07 output
latch
7
Port P0 Direction register = 1
7
Falling edge detection
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Key input interrupt request
P0
P0
P0
P0
P0
P0
P0
6
output
5
output
4
output
3
2
1
0
input
input
input
input
Port P00 key-on wakeup selection bit
PULL register bit 3 = “0”
***
PULL register bit 3 = “0”
***
PULL register bit 3 = “0”
***
PULL register bit 2 = “1”
***
PULL register bit 2 = “1”
***
PULL register bit 1 = “1”
***
PULL register bit 0 = “1”
***
Port P0 Direction register = 1
6
Port P0 latch
Port P0 Direction register = 1
Port P0
5
latch
Port P0 Direction register = 1
4
Port P0 latch
Port P0 Direction register = 0
Port P0
3
latch
Port P0 Direction register = 0
2
Port P0 latch
Port P0 Direction register = 0
Port P0
1
latch
Port P0 Direction register = 0
Port P0
0
latch
6
5
4
3
2
1
0
Falling edge detection
Falling edge detection
Falling edge detection
Falling edge detection
Falling edge detection
Falling edge detection
Falling edge detection
* P-channel transistor for pull-up ** CMOS output buffer
Port P0 Input read circuit
Fig. 21 Connection example when using key input interrupt and port P0 block diagram
21
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Timers

The 7540 Group has 5 timers: timer 1, timer A, timer X, timer Y and timer Z. The division ratio of every timer and prescaler is 1/(n+1) provided that the value of the timer latch or prescaler is n. All the timers are down count timers. When a timer reaches “0”, an underflow occurs at the next count pulse, and the corresponding timer latch is reloaded into the timer. When a timer underflows, the interrupt request bit corresponding to each timer is set to “1”.

Timer 1

Timer 1 is an 8-bit timer and counts the prescaler output. When Timer 1 underflows, the timer 1 interrupt request bit is set to 1. Prescaler 1 is an 8-bit prescaler and counts the signal which is the oscillation frequency divided by 16. Prescaler 1 and Timer 1 have the prescaler 1 latch and the timer 1 latch to retain the reload value, respectively. The value of prescaler 1 latch is set to Prescaler 1 when Prescaler 1 underflows.The value of timer 1 latch is set to Timer 1 when Timer 1 underflows. When writing to Prescaler 1 (PRE1) is executed, the value is writ­ten to both the prescaler 1 latch and Prescaler 1. When writing to Timer 1 (T1) is executed, the value is written to both the timer 1 latch and Timer 1. When reading from Prescaler 1 (PRE1) and Timer 1 (T1) is ex­ecuted, each count value is read out. Timer 1 always operates in the timer mode. Prescaler 1 counts the selected count source. Each time the count clock is input, the contents of Prescaler 1 is decremented by 1. When the contents of Prescaler 1 reach 00 curs at the next count clock, and the prescaler 1 latch is reloaded into Prescaler 1 and count continues. The division ratio of Prescaler 1 is 1/(n+1) provided that the value of Prescaler 1 is n. The contents of Timer 1 is decremented by 1 each time the under­flow signal of Prescaler 1 is input. When the contents of Timer 1 reach 0016, an underflow occurs at the next count clock, and the timer 1 latch is reloaded into Timer 1 and count continues. The di­vision ratio of Timer 1 is 1/(m+1) provided that the value of Timer 1 is m. Accordingly, the division ratio of Prescaler 1 and Timer 1 is 1/((n+1)(m+1)) provided that the value of Prescaler 1 is n and the value of Timer 1 is m. Timer 1 cannot stop counting by software.
16”, an underflow oc-
22
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