Mitsubishi M37536RSS, M37536M4-XXXSP Datasheet

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

DESCRIPTION

The 7536 Group is the 8-bit microcomputer based on the 740 family core technology. The 7536 Group has a USB, 8-bit timers, and an A-D converter, and is useful for an input device for personal computer peripherals.

FEATURES

Basic machine-language instructions....................................... 69

•

The minimum instruction execution time.......................... 0.34 µs

•

•

•

•

•

(at 6 MHz oscillation frequency for the shortest instruction)

Memory size

ROM..................................................................... 8K to 16K bytes

RAM ....................................................................256 to 384 bytes

Programmable I/O ports........................................................... 33

Interrupts ....................................................14 sources, 8 vectors

Timers ............................................................................ 8-bit ✕ 3

PIN CONFIGURATION (TOP VIEW)

P14/CNTR0

P15

P16 P20/AN0 P21/AN1

NC P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7

P4 P41

REF

V

RESET

CNVSS

Vcc

XIN

XOUT

VSS

0

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21

Serial I/O1 ................................ used only for Low Speed in USB

•

Serial I/O2 ...................................................................... 8-bit ✕ 1

•

A-D converter ................................................ 10-bit ✕ 8 channels

•

Clock generating circuit ............................................. Built-in type

•

(connect to external ceramic resonator or quartz-crystal oscillator )

Watchdog timer ............................................................ 16-bit ✕ 1

•

Power source voltage

•

At 6 MHz X

...................................................................................4.1 to 5.5 V

Power dissipation ............................................ 30 mW (standard)

•

Operating temperature range ................................... –20 to 85 °C

•

IN oscillation frequency at ceramic resonator

APPLICATION

Input device for personal computer peripherals

42 41 40

M37536M4-XXXSP

M37536E8SP

39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22

P13/SDATA

2/SCLK

P1 P1

1/TXD/D+

P10/RXD/DP07 P06 P0

5

P04 P03 P02 P01 P00 USBVREFOUT P3

7/INT0

P3

6(LED6)/INT1

P35(LED5)

4(LED4)

P3 P3

3(LED3) 2(LED2)

P3 P31(LED1) P30(LED0)

(USB/UART)

(Clock-synchronized)

Package type:42P4B

Fig. 1 Pin configuration of M37536M4-XXXSP,M37536E8SP

PIN CONFIGURATION (TOP VIEW)

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

P14/CNTR0

P15

P16

P20/AN0

1/AN1

P2

NC P22/AN2 P23/AN3 P24/AN4

P25/AN5 P26/AN6 P27/AN7

P40

P41

V

REF

RESET

CNVSS

Vcc

XIN

XOUT

VSS

1 2 3 4 5 6 7 8 9

10

11 12 13 14 15 16 17 18 19 20 21

42 41 40 39

38 37 36

M37536RSS

35 34 33

32 31 30 29 28 27

26 25 24 23

22

P13/SDATA P12/SCLK

1/TXD/D+

P1 P10/RXD/DP07 P06 P05 P04 P03 P02 P01 P00 USBV

REFOUT

P37/INT0

6(LED6)/INT1

P3 P35(LED5)

4(LED4)

P3 P3

3(LED3)

P3

2(LED2)

P31(LED1) P30(LED0)

Fig. 2 Pin configuration of M37536RSS

2

Outline 42S1M

FUNCTIONAL BLOCK

Timer 1 (8)

Timer 2 (8)

Timer X (8)

Prescaler 12 (8)

Prescaler X (8)

X

IN OUT

X

R A M

R O M

C P U

A

X

Y

S

PC

H

PC

L

PS

V

SS

21

RESET

16

V

CC

18

17

CNV

SS

CNTR

0

P1(7)

P2(8)

P3(8)

19 20

V

REF

0

INT

0

USBV

REFOUT

INT

1

P4(2)

SI/O1(8)

USB(LS)

SI/O2(8)

Clock generating circuit

Watchdog timer

Reset

A-D

converter

(10)

I/O port P3 I/O port P2 I/O port P1 I/O port P0

I/O port P4

Key-on wakeup

Clock input

Clock output

Reset input

13 14 15

2427 25 23262829 22

857412 1011 9

30

3141242 3940

P0(8)

38 36 34 3237 35 33 31

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

FUNCTIONAL BLOCK DIAGRAM (Package: 42P4B)

Fig. 3 Functional block diagram

3

PIN DESCRIPTION

Table 1 Pin description

Pin Vcc, Vss VREF

USBVREFOUT

CNVss RESET XIN

XOUT P00–P07

P10/RxD/DP11/TxD/D+ P12/SCLK P13/SDATA P14/CNTR0

P15, P16 P20/AN0–

P27/AN7

P30–P35

P36/INT1 P37/INT0

P40, P41

Name Power source Analog reference

voltage USB reference

voltage output CNVss Reset input Clock input

Clock output I/O port P0

I/O port P1

I/O port P2

I/O port P3

I/O port P4

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Function

•Apply voltage of 4.1 to 5.5 V to Vcc, and 0 V to Vss.

•Reference voltage input pin for A-D converter

•Output pin for pulling up a D- line with 1.5 kΩ external resistor

•Chip operating mode control pin, which is always connected to Vss.

•Reset input pin for active “L”

•Input and output pins for main clock generating circuit

•Connect a ceramic resonator or quartz crystal oscillator between the XIN and XOUT pins.

•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.

•8-bit I/O port.

•I/O direction register allows each pin to be individually programmed as either input or output.

•CMOS compatible input level

•CMOS 3-state output structure

•Whether a built-in pull-up resistor is to be used or not can be determined by program.

•7-bit I/O port

•I/O direction register allows each pin to be individually programmed as either input or output.

•CMOS compatible input level

•CMOS 3-state output structure

•CMOS/TTL level can be switched for P10, P12, P13.

•When using the USB function, input level of ports P10 and P11 becomes USB input level, and output level of them becomes USB output level.

•8-bit I/O port having almost the same function as P0

•CMOS compatible input level

•CMOS 3-state output structure

•8-bit I/O port

•I/O direction register allows each pin to be individually programmed as either input or output.

•CMOS compatible input level (CMOS/TTL level can be switched for P36, P37).

•CMOS 3-state output structure

•P30 to P36 can output a large current for driving LED.

•Whether a built-in pull-up resistor is to be used or not can be determined by program.

•2-bit I/O port

•I/O direction register allows each pin to be individually programmed as either input or output.

Function expect a port function

•Key-input (key-on wake up interrupt input) pins

•Serial I/O1 function pin

•Serial I/O2 function pin

•Timer X function pin

•Input pins for A-D converter

•Interrupt input pins

4

GROUP EXPANSION

Mitsubishi plans to expand the 7536 group as follow:

Memory type

Support for Mask ROM version, One Time PROM version, and Emulator MCU .

Memory size

ROM/PROM size ..................................................8 K to 16 K bytes

RAM size................................................................256 to 384 bytes

Package

42P4B ................................................... 42-pin plastic molded SDIP

42SIM...................................... 42-pin shrink ceramic PIGGY BACK

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

ROM size (Byte)

16K

8K

M37536E8

M37536M4

0

128

256 384

RAM size (Byte)

Note. Products under development: the development schedule and specification

may be revised without notice.

Fig. 4 Memory expansion plan

Currently supported products are listed below.

Table 2 List of supported products

Product

M37536M4-XXXSP M37536E8SP M37536RSS

(P) ROM size (bytes) ROM size for User ()

8192 (8062)

16384 (16254)

RAM size

(bytes)

256 384 384

Package

42P4B 42P4B

42S1M

Remarks

Mask ROM version One Time PROM version (blank) Emulator MCU

5

FUNCTIONAL DESCRIPTION Central Processing Unit (CPU)

The 7536 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instructions cannot be used. The MUL and DIV instructions cannot be used. The WIT and STP instructions can be used. The central processing unit (CPU) has the six registers.

Switching method of CPU mode register

Switch the CPU mode register (CPUM) at the head of program after releasing Reset in the following method.

[CPU Mode Register] CPUM

The CPU mode register contains the stack page selection bit. This register is allocated at address 003B16.

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Fig. 5 Structure of CPU mode register

b7 b0

CPU mode register (CPUM: address 003B

After releasing reset

Wait until ceramic oscillator clock is stabilized.

16

)

Processor mode bits b1 b0 0 0 Single-chip mode 0 1 1 0

Not available

1 1

Stack page selection bit 0 : 0 page 1 : 1 page

Not used (returns “0” when read) (Do not write “1” to these bits )

Main clock division ratio selection bits b7 b6 0 0 : f(φ) = f(X 0 1 : f(φ) = f(X 1 0 : applied from ring oscillator 1 1 : f(φ) = f(X

IN

)/2 (High-speed mode)

IN

)/8 (Middle-speed mode)

IN

) (Double-speed mode)

Start with a built-in ring oscillator ( Note)

Switch the clock division ratio selection bits (bits 6 and 7 of CPUM)

Note. After releasing reset the operation starts by starting a ring oscillator automatically. Do not use a ring oscillator at ordinary operation.

Fig. 6 Switching method of CPU mode register

6

Switch to other mode except a ring oscillator (Select one of 1/1, 1/2, and 1/8)

Main routine

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Memory

Special function register (SFR) area

The SFR area in the zero page contains control registers such as I/O ports and timers.

RAM

RAM is used for data storage and for a stack area of subroutine calls and interrupts.

ROM

The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is a user area for storing programs.

Interrupt vector area

The interrupt vector area contains reset and interrupt vectors.

RAM area

RAM capacity

(bytes)

256 384

address XXXX

013F16 01BF16

16

Zero page

The 256 bytes from addresses 0000

16 to 00FF16 are called the zero

page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.

Special page

The 256 bytes from addresses FF00

16 to FFFF16 are called the spe-

cial page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.

RAM

000016

004016

010016

XXXX

044016

YYYY16

ZZZZ16

SFR area

16

Reserved area

Not used

Reserved ROM area

(128 bytes)

Zero page

ROM area

ROM capacity

(bytes)

8192

16384

Fig. 7 Memory map diagram

address

YYYY

E00016 C00016

ROM

FF0016

address

16

ZZZZ

E08016 C08016

16

FFEC16

FFFE16 FFFF16

Interrupt vector area

Reserved ROM area

Special page

7

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 001A 001B 001C 001D 001E 001F

Port P0 (P0)

16

Port P0 direction register (P0D)

16

Port P1 (P1)

16

Port P1 direction register (P1D)

16

Port P2 (P2)

16

Port P2 direction register (P2D)

16

Port P3 (P3)

16

Port P3 direction register (P3D)

16

Port P4 (P4)

16

Port P4 direction register (P4D)

16

16 16 16 16

16 16 16 16 16 16 16 16

Pull-up control register (PULL)

16

Port P1P3 control register (P1P3C)

16

Transmit/Receive buffer register (TB/RB)

16

USB status register (USBSTS)/UART status register (UARTSTS)

16

Serial I/O1 control register (SIO1CON)

16

UART control register (UARTCON)

16

Baud rate generator (BRG)

16

USB data toggle synchronization register ( TRSYNC)

16

USB interrupt source discrimination register 1 (USBIR1)

16

USB interrupt source discrimination register 2 (USBIR2)

16

0020 0021 0022 0023 0024 0025 0026 0027 0028 0029 002A 002B 002C 002D 002E 002F 0030 0031 0032 0033 0034 0035 0036 0037 0038 0039 003A 003B 003C 003D 003E 003F

USB interrupt control register (USBICON)

16

USB transmit data byte number set register 0 (EP0BYTE)

16

USB transmit data byte number set register 1 (EP1BYTE)

16

USBPID control register 0 (EP0PID)

16

USBPID control register 1 (EP1PID)

16

USB address register (USBA)

16

USB sequence bit initialization register (INISQ1)

16 16

USB control register (USBCON) Prescaler 12 (PRE12)

16

Timer 1 (T1)

16

Timer 2 (T2)

16

Timer X mode register

16

(TX)

(PREX)

Prescaler X

16

Timer X

16

Timer count source set register (TCSS)

16

16

Serial I/O2 control register (SIO2CON)

16

Serial I/O2 register (SIO2)

16 16 16

A-D control register (ADCON)

16

A-D conversion register (low-order) (ADL)

16

A-D conversion register (high-order) (ADH)

16 16

MISRG

16

Watchdog timer control register (WDTCON)

16

Interrupt edge selection register

16

CPU mode register (CPUM)

16

Interrupt request register 1 (IREQ1)

16 16

Interrupt control register 1 (ICON1)

16

16

(TM)

(INTEDGE)

Fig. 8 Memory map of special function register (SFR)

8

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

I/O Ports

[Direction registers] PiD

The I/O ports have direction registers which determine the input/output direction of each pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input or output. When “1” is set to the bit corresponding to a pin, this pin becomes an output port. When “0” is set to the bit, the pin becomes an input port. When data is read from a pin set to output, not the value of the pin itself but the value of port latch is read. Pins set to input are floating, and permit reading pin values. If a pin set to input is written to, only the port latch is written to and the pin remains floating.

b7 b0

[Pull-up control] PULL

By setting the pull-up control register (address 001616), ports P0 and P3 can exert pull-up control by program. However, pins set to output are disconnected from this control and cannot exert pull-up control.

[Port P1P3 control] P1P3C

By setting the port P1P3 control register (address 001716), a CMOS input level or a TTL input level can be selected for ports P10, P12, P13, P35, P36 and P37 by program.

Pull-up control register

16

(PULL: address 0016

P00 pull-up control bit P0

1

pull-up control bit

P0

2

, P03 pull-up control bit

P0

4

– P07 pull-up control bit

P3

0

– P33 pull-up control bit

P3

4

pull-up control bit

P3

5

, P36 pull-up control bit

P3

7

pull-up control bit

)

Note : Pins set to output ports are disconnected from pull-up control.

Fig. 9 Structure of pull-up control register

b7 b0

Fig. 10 Structure of port P1P3 control register

0: Pull-up off 1: Pull-up on Initial value: FF

Port P1P3 control register (P1P3C: address 0017

P37/INT0 input level selection bit 0 : CMOS level 1 : TTL level

6/INT1 input level selection bit

P3 0 : CMOS level 1 : TTL level

P1

0,P12,P13 input level selection bit

0 : CMOS level 1 : TTL level

Not used

16

16)

9

Table 3 I/O port function table

Pin

P00–P07

P10/RxD/DP11/TxD/D+ P12/SCLK P13/SDATA P14/CNTR0 P15, P16 P20/AN0–

P27/AN7 P30–P35 P36/INT1 P37/INT0 P40, P41

Note: Port P10, P12, P13, P36, P37 is CMOS/TTL level.

Name

I/O port P0

I/O port P1

I/O port P2

I/O port P3

I/O port P4

I/O individual bits

•CMOS compatible input level

•CMOS 3-state output

•USB input/output level when selecting USB function

•CMOS compatible input level

•CMOS 3-state output (Note)

I/O format

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Non-port function

Key input interrupt

Serial I/O1 function input/output

Serial I/O2 function input/output

Timer X function input/output

A-D conversion input

External interrupt input

Related SFRs

Pull-up control register

Serial I/O1 control register

Serial I/O2 control register

Timer X mode register

A-D control register

Interrupt edge selection register

Diagram No.Input/output

(1) (2)

(3) (4) (5)

(6)

(10)

(7)

(8)

(9)

(10)

10

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(1) Port P0

Pull-up control

Direction register

Data bus

Port latch

To key input interrupt

(3) Port P11

P-channel output disable bit

Serial I/O1 mode selection bit (b7) Serial I/O1 mode selection bit (b6)

Serial I/O1 mode selection bit (b7) Serial I/O1 mode selection bit (b6)

Data bus

Transmit enable bit

Direction register

Port latch

generating circuit

(2) Port P10

Serial I/O1 mode selection bit (b7) Serial I/O1 mode selection bit (b6)

Serial I/O1 mode selection bit (b7) Serial I/O1 mode selection bit (b6)

Data bus

Receive enable bit

Direction register

Port latch

-

+

Serial I/O1 input

D- input

D- output

USB output enable

(internal signal)

USB differential input

0

,P12,P13 input

P1 level selection bit

*

Serial I/O1 output

D+ output

USB output enable

(internal signal)

(4) Port P12

S

CLK

pin selection bit

Direction register

Data bus

0

, P12, P13, P36, P37 input levels are switched to the CMOS/TTL level by the port P1P3 control register.

P1

When the TTL level is selected, there is no hysteresis characteristics.

Port latch

Serial I/O2 clock output

Serial I/O2 clock input

Fig. 11 Block diagram of ports (1)

D+ input

0

,P12,P13 input

P1 level selection bit

*

(5) Port P13

Signals during the S

S

DATA

Data bus

DATA

output action

pin selection bit

Direction register

Port latch

Serial I/O2 clock output

Serial I/O2 clock input

S

DATA

pin

selection bit

P1

0

,P12,P13 input

level selection bit

*

11

MITSUBISHI MICROCOMPUTERS

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(6) Port P1

4

Data bus

Pulse output mode

(8) Ports P30 – P3

Data bus

(10) Ports P1

5, P16

Direction register

Port latch

Timer output

5

Pull-up

Direction register

Port latch

, P4

0, P41

CNTR

0

interrupt input

control

(7) Ports P20 – P2

Data bus

(9) Port P36, P3

Data bus

7

7

INT

Direction register

Port latch

Direction register

Port latch

A-D conversion input

Pull-up

control

interrupt input

Analog input pin selection bit

P3

7

/INT0 input

level selection bit

*

Direction register

Data bus

Port latch

Fig. 12 Block diagram of ports (2)

P1

0

, P12, P13, P36, P37 input levels are switched to the CMOS/TTL level by the port P1P3 control register.

*

When the TTL level is selected, there is no hysteresis characteristics.

12

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Interrupts

Interrupts occur by 14 different sources : 4 external sources, 9 internal sources and 1 software source.

Interrupt control

All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit, and they are controlled by the interrupt disable flag. When the interrupt enable bit and the interrupt request bit are set to “1” and the interrupt disable flag is set to “0”, an interrupt is accepted. The interrupt request bit can be cleared by program but not be set. The interrupt enable bit can be set and cleared by program. It becomes usable by switching CNTR0 and A-D interrupt sources with bit 7 of the interrupt edge selection register, timer 2 and serial I/ O2 interrupt sources with bit 6, timer X and key-on wake-up interrupt sources with bit 5, and serial I/O transmit and INT1 interrupt sources with bit 4. The reset and BRK instruction interrupt can never be disabled with any flag or bit. All interrupts except these are disabled when the interrupt disable flag is set. When several interrupts occur at the same time, the interrupts are received according to priority.

Table 4 Interrupt vector address and priority

Interrupt source

Reset (Note 2) UART receive USB IN token UART transmit

USB SETUP/OUT token Reset/Suspend/Resume

INT1

INT0

Timer X Key-on wake-up

Timer 1 Timer 2 Serial I/O2 CNTR0

A-D conversion BRK instruction

Note 1: Vector addressed contain internal jump destination addresses.

2: Reset function in the same way as an interrupt with the highest priority.

Priority

Vector addresses (Note 1)

High-order

FFFD16

1

FFFB16

2

FFF916

3

FFF716

4

FFF516

5

FFF316

6

FFF116

7

FFEF16

8

FFED16

9

Low-order

FFFC16 FFFA16

FFF816

FFF616

FFF416

FFF216 FFF016

FFEE16

FFEC16

Interrupt request generating conditions

At reset input At completion of UART data receive At detection of IN token At completion of UART transmit shift or

when transmit buffer is empty At detection of SETUP/OUT token or

At detection of Reset/ Suspend/ Resume At detection of either rising or falling edge

of INT1 input At detection of either rising or falling edge

of INT0 input At timer X underflow At falling of conjunction of input logical

level for port P0 (at input) At timer 1 underflow At timer 2 underflow At completion of transmit/receive shift At detection of either rising or falling edge

of CNTR0 input At completion of A-D conversion At BRK instruction execution

Interrupt operation

Upon acceptance of an interrupt the following operations are automatically performed:

1. The processing being executed is stopped.

2. The contents of the program counter and processor status register are automatically pushed onto the stack.

3. The interrupt disable flag is set and the corresponding interrupt request bit is cleared.

4. Concurrently with the push operation, the interrupt destination address is read from the vector table into the program counter.

Notes on use

When the active edge of an external interrupt (INT0, INT1, CNTR0) is set, the interrupt request bit may be set. Therefore, please take following sequence:

1. Disable the external interrupt which is selected.

2. Change the active edge in interrupt edge selection register. (in case of CNTR0: Timer X mode register)

3. Clear the set interrupt request bit to “0”.

4. Enable the external interrupt which is selected.

Remarks

Non-maskable Valid in UART mode Valid in USB mode Valid in UART mode

Valid in USB mode

External interrupt (active edge selectable)

External interrupt (active edge selectable)

External interrupt (valid at falling)

STP release timer underflow

External interrupt (active edge selectable)

Non-maskable software interrupt

13

Interrupt request bit

Interrupt enable bit

Interrupt disable flag I

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Fig. 13 Interrupt control

b7 b0

BRK instruction

Reset

Interrupt edge selection register (INTEDGE : address 003A

INT0 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active INT

1

interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active Not used (returns “0” when read)

Serial I/O1 or INT1 interrupt selection bit 0 : Serial I/O1 1 : INT Timer X or key-on wake up interrupt selection bit 0 : Timer X 1 : Key-on wake up Timer 2 or serial I/O2 interrupt selection bit 0 : Timer 2 1 : Serial I/O2 CNTR 0 : CNTR 1 : AD converter

1

0

or AD converter interrupt selection bit

16

)

0

Interrupt request

b7 b0

b7 b0

Interrupt request register 1 (IREQ1 : address 003C

UART receive/USB IN token interrupt request bit UART transmit/USB SETUP/OUT token/ Reset/Suspend/Resume/INT interrupt request bit INT

0

Timer X or key-on wake up interrupt request bit Timer 1 interrupt request bit Timer 2 or serial I/O2 interrupt request bit CNTR Not used (returns “0” when read)

Interrupt control register 1 (ICON1 : address 003E16)

UART receive/USB IN token interrupt enable bit UART transmit/USB SETUP/OUT token/ Reset/Suspend/Resume/INT interrupt enable bit INT

0

Timer X or key-on wake up interrupt enable bit Timer 1 interrupt enable bit Timer 2 or serial I/O2 interrupt enable bit CNTR Not used (returns “0” when read) (Do not write “1” to this bit)

Fig. 14 Structure of interrupt-related registers

14

16

)

interrupt request bit

0

or AD converter interrupt request bit

interrupt enable bit

0

or AD converter interrupt enable bit

1

0 : No interrupt request issued 1 : Interrupt request issued

1

0 : Interrupts disabled 1 : Interrupts enabled

Key Input Interrupt (Key-On Wake-Up)

A key-on wake-up interrupt request is generated by applying “L” level to any pin of port P0 that has been set to input mode. In other words, it is generated when the AND of input level goes from “1” to “0”. An example of using a key input interrupt is shown in Figure 15, where an interrupt request is generated by pressing one of the keys provided as an active-low key matrix which uses ports P00 to P03 as input ports.

Port PXx “L” level output

PULL register bit 3 = “0”

***

P07 output

Port P0 Direction register = “1”

7

Port P0 latch

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

7

Key input interrupt request

Falling edge detection

6

output

P0

5

output

P0

P04 output

P0

3

input

P0

2

input

1

input

P0

0

input

P0

PULL register bit 3 = “0”

***

PULL register bit 3 = “0”

***

PULL register bit 3 = “0”

***

PULL register bit 2 = “1”

***

PULL register bit 2 = “1”

***

PULL register bit 1 = “1”

***

PULL register bit 0 = “1”

***

Port P0 Direction register = “1”

6

Port P0 latch

Port P0 Direction register = “1”

Port P0

5

latch

Port P0 Direction register = “1”

4

Port P0 latch

Port P0 Direction register = “0”

Port P0

3

latch

Port P0 Direction register = “0”

Port P0

2

latch

Port P0 Direction register = “0”

Port P0

1

latch

Port P0 Direction register = “0”

Port P0

0

latch

6

5

4

3

2

1

0

Falling edge detection

Falling edge detection

Falling edge detection

Falling edge detection

Falling edge detection

Falling edge detection

Falling edge detection

Port P0 Input read circuit

Fig. 15 Connection example when using key input interrupt and port P0 block diagram

* P-channel transistor for pull-up ** CMOS output buffer

15

Timers

Timer X mode register (TM : Address 002B

16

)

CNTR

0

active edge switch bit 0 : Interrupt at falling edge Count at rising edge (in event counter mode) 1 : Interrupt at rising edge Count at falling edge (in event counter mode)

Timer X operating mode bits b1 b0 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode

Not used (return “0” when read)

Timer X count stop bit 0 : Count start 1 : Count stop

b7 b0

Timer count source set register (TCSS : Address 002E

16

)

b7 b0

Timer X count source selection bit (Note) 0 : f(X

IN

)/16

1 : f(X

IN

)/2

Not used (return “0” when read)

Note : To switch the timer X count source selection bit , stop the timer X count operation.

The 7536 Group has 3 timers: timer X, timer 1 and timer 2. The division ratio of every timer and prescaler is 1/(n+1) provided that the value of the timer latch or prescaler is n. All the timers are down count timers. When a timer reaches “0”, an underflow occurs at the next count pulse, and the corresponding timer latch is reloaded into the timer. When a timer underflows, the interrupt request bit corresponding to each timer is set to “1”.

●Timer 1, Timer 2

Prescaler 12 always counts f(XIN)/16. Timer 1 and timer 2 always count the prescaler output and periodically sets the interrupt request bit.

●Timer X

Timer X can be selected in one of 4 operating modes by setting the timer X mode register.

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

• Timer Mode

The timer counts the signal selected by the timer X count source selection bit.

• Pulse Output Mode

The timer counts the signal selected by the timer X count source selection bit, and outputs a signal whose polarity is inverted each time the timer value reaches “0”, from the CNTR0 pin. When the CNTR0 active edge switch bit is “0”, the output of the CNTR0 pin is started with an “H” output. At “1”, this output is started with an “L” output. When using a timer in this mode, set the port P14 direction register to output mode.

• Event Counter Mode

The operation in the event counter mode is the same as that in the timer mode except that the timer counts the input signal from the CNTR0 pin. When the CNTR0 active edge switch bit is “0”, the timer counts the rising edge of the CNTR0 pin. When this bit is “1”, the timer counts the falling edge of the CNTR0 pin.

• Pulse Width Measurement Mode

When the CNTR0 active edge switch bit is “0”, the timer counts the signal selected by the timer X count source selection bit while the CNTR0 pin is “H”. When this bit is “1”, the timer counts the signal while the CNTR0 pin is “L”. In any mode, the timer count can be stopped by setting the timer X count stop bit to “1”. Each time the timer overflows, the interrupt request bit is set.

Fig. 16 Structure of timer X mode register

Fig. 17 Timer count source set register

16

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Data bus

P14/CNTR0

Port P14 direction register

f(XIN)/16

Pulse output mode

f(XIN)/16

f(XIN)/2

Timer X count source selection bit

CNTR0 active edge switch bit

Port P14 latch

Pulse width measurement mode

“0”

“1”

Prescaler 12 (8)

Event counter mode

CNTR0 active edge switch bit

Prescaler X latch (8)

Timer mode pulse output mode

Timer X count stop bit

“1”

“0”

Timer 1 (8) Timer 2 (8)

Prescaler X (8)

Q

Toggle flip-flop

Q

R

Data bus

Timer X latch (8)

To timer X

To timer 2 interrupt request bit

To timer 1 interrupt request bit

interrupt request bit

To CNTR0 interrupt request bit

Timer X (8)

T

Timer X latch write Pulse output mode

Timer 2 latch (8)Timer 1 latch (8)Prescaler 12 latch (8)

Fig. 18 Block diagram of timer X, timer 1 and timer 2

17

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Serial I/O

●Serial I/O1

• Asynchronous serial I/O (UART) mode

Serial I/O1 can be used as an asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation when serial I/O1 is in operation. Eight serial data transfer formats can be selected, and the transfer formats to be used by a transmitter and a receiver must be identical. Each of the transmit and receive shift registers has a buffer register

Data bus

Address (0018

Receive Buffer Register

OE

Character length selection bit

0/RX

D

P1

P11/TXD

ST Detector

BRG count source selection bit

X

IN

1/4

7-bit

8-bit

Character length selection bit

Continuous transmit valid bit

Receive Shift Register

PE FE

SP Detector

Division ratio 1/(n+1)

Baud Rate Generator

ST/SP/PA Generator

Transmit Shift Register

Transmit Buffer Register

Data bus

Serial I/O1 control register

16

)

Address (001C

Address (0018

(the same address on memory). Since the shift register cannot be written to or read from directly, transmit data is written to the trans mit buffer, and receive data is read from the respective buffer regis ters. These buffer registers can also hold the next data to be trans mitted and receive 2-byte receive data in succession. By selecting "1" for continuous transmit valid bit (bit 2 of SIO1CON), continuous transmission of the same data is made possible. This can be used as a simplified PWM.

Receive buffer full flag (RBF) Receive interrupt request (RI)

Clock Control Circuit

16

)

1/16

Transmit interrupt source selection bit

16

)

Address (001A

1/16

Serial I/O1 status register

16

)

UART Control Register

Address (001B

Transmit shift register shift completion flag (TSC)

Transmit interrupt request (TI)

Transmit buffer empty flag (TBE)

Address (0019

16

)

16

)

Fig. 19 Block diagram of UART serial I/O

Transmit/Receive Clock

Transmit Buffer Register Write Signal

TBE=0

TSC=0 TBE=1

Serial Output T

Receive Buffer Register Read Signal

Serial Input R

X

D

X

D

Notes

1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit

interrupt source selection bit (TIC) of the serial I/O1 control register.

3 : The receive interrupt (RI) is set when the RBF flag becomes “1”. 4 : After data is written to the transmit buffer when TSC = 1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC = 0.

ST SP

0

ST

0

Fig. 20 Operation of UART serial I/O function

TBE=0

D

1

1 Start Bit 7 or 8 Data Bit 1 or 0 Parity Bit 1 or 2 Stop Bit

D

1

TBE=1

STD

SP

RBF=1

STD

SP D

TSC=1*

D

0

D

1

* Generated at second bit in 2-stop -bit mode

0

RBF=0

D

1

RBF=1

SP

18

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

[Serial I/O1 control register] SIO1CON

The serial I/O1 control register consists of eight control bits for the serial I/O1 function.

[UART control register] UARTCON

The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of a data transfer. One bit in this register (bit 4) is always valid and sets the input/output structure of the P11/TxD pin.

[UART status register] UARTSTS

The read-only UART status register consists of seven flags (bits 0 to

6) which indicate the operating status of the UART function and various errors. This register functions as the UART status register (UARTSTS) when selecting the UART. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O1 mode selection bits MOD1 and MOD0 (bit 7 and 6 of the Serial I/O1 control register ) also clears all the status flags, including the error flags. All bits of the serial I/O1 status register are initialized to "8116" at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to "1", the continuous transmit valid bit (bit 2) becomes "1".

[Baud Rate Generator] BRG

The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator.

[Transmit/Receive buffer register] TB/RB

The transmit buffer and the receive buffer are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7-bit, the MSB of data stored in the receive buffer is "0".

Transmit/Receive Clock

Transmit Buffer Register Write Signal

TBE=0

TSC=0 TBE=1

ST SP

0

D

Serial Output T

Notes

X

D

1 : When the serial I/O1 mode selection bit (b7, b6) is “10”, the transmit enable bit is “1”, and continuous transmit valid bit is “1”, writing on the transmit buffer initiates continuous transmission of the same data. 2 : Select 0 for continuous transmit valid bit to stop continuous transmission.

X

D pin will stop at high level after completing transmission of 1 byte.

The T 3 : If the transmit buffer contents are rewritten during a continuous transmission, transmission of the rewritten data will be started after completing transmission of 1 byte.

1

1 Start Bit 7 or 8 Data Bit 1 or 0 Parity Bit 1 or 2 Stop Bit

STD

D

0

D

SP

1

ST

Fig. 21 Continuous transmission operation of UART serial I/O

19

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

• Universal serial bus (USB) mode

By setting bits 7 and 6 of the serial I/O1 control register (address 001A16) to “11”, the USB mode is selected. This mode conforms to “Low Speed device” of USB Specification

1.0. In this mode serial I/O1 interrupt have 6 sources; USB in and out token receive, USB reset, suspend, and resume. The USB/UART

1.5 MHz

Bus state detection

NRZI, bit stuffing encoder

EOP generating unit

X

P10/D-

1

P1

IN

USB

transceiver

/D+

6 MHz

Digital PLL

Differential input and Single end input

Output data and I/O control

USB transmit unit

status register (address 001916) functions as the USB status register (USBSTS).There is the USBVREFOUT pin for the USB reference voltage output, and a D-line with 1.5 kΩ external resistor can be pull up. USB mode block and USB transceiver block show in figures 22 and

23.

Data bus

NRZI, bit stuffing decoder

BSTFE

EOP

Reset interrupt request

Suspend interrupt request

Resume interrupt request

CRC encoder

Data bus

Address 0018

Receive buffer register

Receive shift register

Transmit shift register

Transmit buffer register

Address 0018

16

16

SYNC decoder

PID decoder

PIDE

Address

comparative unit

Endpointer decoder

CRC check

CRCE

RxRDY

TxRDY EP0BYTE

EP1BYTE

RxPID OPID

USBA

RxEP

SYNC, PID generating unit

Token interrupt request

EP0PID EP1PID

Fig. 22 USB mode block diagram

Serial I/O1 control register

MOD0 MOD1

USB reference power source voltage

Fig. 23 USB transceiver block diagram

USB control register

USBV

REFOUT

output valid flag

(initial value “0”)

Output enable signal

Voltage input

Voltage input

Internal D- output signal

Internal D+ output signal

Suspend

(internal signal)

OE

Differential input

Single end input

Single end input

Output amplifier USBV

D+/D-

output amplifier

Signal for function stop

Output enable signal

-

+

REFOUT

D-

D+

20

b7 b0

b7 b0

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Transmit buffer register (TB: address 0018

After setting data to address 0018

16

)

16

, a content of the transmit buffer register transfers to the transmit shift register automatically.

CPU read: Disabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used

Receive buffer register (RB: address 0018

By reading data from address 0018

16

)

16

, a content of the

receive buffer register can be read out.

CPU read: Enabled CPU write: Disabled Hardware read: Not used Hardware write: Set/Clear

7536 Group

b7 b0

USB status register (USBSTS: address 0019

Transmit buffer empty flag 0: Buffer full 1: Buffer empty

EOP detection flag 0: Not detected 1: Detect

False EOP error flag 0: No error 1: False EOP error

CRC error flag 0: No error 1: CRC error

PID error flag 0: No error 1: PID error

Bit stuffing error flag 0: No error 1: Bit stuffing error

Summing error flag 0: No error 1: Summing error

16

)

CPU read: Enabled CPU write: Disabled Hardware read: Not used Hardware write: Set/Clear

CPU read: Enabled CPU write: Clear Hardware read: Not used Hardware write: Set

Receive buffer full flag 0: Buffer empty 1: Buffer full

Fig. 24 Structure of serial I/O1-related registers (1)

CPU read: Enabled CPU write: Disabled Hardware read: Not used Hardware write: Set/Clear

21

b7 b0

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

USB data toggle synchronization register (TRSYNC: address 001D

Not used (return “1” when read)

16

)

7536 Group

b7 b0

b7 b0

Sequence bit toggle flag 0: No toggle 1: Sequence toggle

CPU read: Enabled CPU write: Clear Hardware read: Not used Hardware write: Set

USB interrupt source discrimination register 1 (USBIR1: address 001E

16

)

Not used (return “1” when read) Endpoint determination flag

0: Endpoint 0 interrupt 1: Endpoint 1 interrupt

CPU read: Enabled CPU write: Disabled Hardware read: Not used Hardware write: Set/Clear

USB interrupt source discrimination register 2

16

(USBIR2: address 001F

)

Not used (return “1” when read) Suspend request flag

0: No request 1: Suspend request

USB reset request flag 0: No request 1: Reset request

CPU read: Enabled CPU write: Clear Hardware read: Not used Hardware write: Set

CPU read: Enabled CPU write: Disabled Hardware read: Not used Hardware write: Set/Clear

Not used (return “1” when read) Token PID determination flag

0: SETUP interrupt 1: OUT interrupt

Token interrupt flag 0: No request

CPU read: Enabled CPU write: Disabled Hardware read: Not used Hardware write: Set/Clear

1: Token request

b7 b0

Fig. 25 Structure of serial I/O1-related registers (2)

USB interrupt control register

16

(USBICON: address 0020

)

Not used (return “1” when read) Endpoint 1 enable

0: Endpoint 1 invalid 1: Endpoint 1 valid

USB reset interrupt enable 0: USB reset invalid 1: USB reset valid

Resume interrupt enable 0: Resume invalid 1: Resume valid

Token interrupt enable 0: Token invalid 1: Token valid

USB enable flag 0: USB invalid 1: USB valid

CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used

22

b7 b0

b7 b0

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

USB transmit data byte number set register 0 (EP0BYTE: address 0021

Set a number of data byte for transmitting with endpoint 0.

CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used

Not used (return “0” when read)

USB transmit data byte number set register 1 (EP1BYTE: address 0022

Set a number of data byte for transmitting with endpoint 1.

CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used

Not used (return “0” when read)

16

)

16

)

7536 Group

b7 b0

b7 b0

USB PID control register 0

16

(EP0PID: address 0023

)

Not used (return “1” when read) Endpoint 0 enable flag

0: Endpoint 0 invalid 1: Endpoint 0 valid

Endpoint 0 PID selection flag 1xxx: IN token interrupt of DATA0/1 is valid

01xx: STALL handshake is valid for IN token

00xx: NAK handshake is valid for IN token

xxx1: STALL handshake is valid for OUT token

xx10: ACK handshake is valid for OUT token

xx00: NAK handshake is valid for OUT token

x: any data

USB PID control register 1

16

(EP1PID: address 0024

)

Not used (return “1” when read) Endpoint 1 PID selection flag

1x: IN token interrupt of DATA0/1 is valid

01: STALL handshake is valid for IN token

00: NAK handshake is valid for IN token

x: any data

CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used

b4, b5, b6 CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used

b7 CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Clear

b6 CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used

b7 CPU read: Enabled CPU write: Set/Clear Hardware read: Used Hardware write: Clear

b7 b0

USB address register (USBA: address 0025

Set an address allocated by the USB host.

CPU read: Disabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used

Not used (returns “1” when read)

Fig. 26 Structure of serial I/O1-related registers (3)

16

)

23

b7 b0

b7 b0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

USB sequence bit initialization register (INISQ1: address 0026

A sequence bit of endpoint 1 is initialized.

CPU read: Disabled CPU write: Dummy Hardware read: Not used Hardware write: Not used

USB control register (USBCON: address 0027

Not used (return “1” when read) USBV

REFOUT

output valid flag 0: Output off 1: Output on

Remote wake up request flag 0: No request 1: Remote wake up request

16

)

16

)

CPU read: Disabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used

CPU read: Disabled CPU write: Set Hardware read: Used Hardware write: Clear

MITSUBISHI MICROCOMPUTERS

7536 Group

b7 b0

UART status register (UARTSTS: address 0019

16

)

Transmit buffer empty flag 0: Buffer full 1: Buffer empty

Receive buffer full flag 0: Buffer empty 1: Buffer full

Transmit shift register shift completion flag 0: Transmit shift in progress 1: Transmit shift completed

Overrun error flag 0: No error 1: Overrun error

Parity error flag 0: No error 1: Parity error

Framing error flag 0: No error 1: Framing error

Summing error flag 0: No error 1: Summing error

Not used (returns “1” when read)

CPU read: Enabled CPU write: Disabled Hardware read: Not used Hardware write: Set/Clear

CPU read: Enabled CPU write: Clear Hardware read: Not used Hardware write: Set

b7 b0

Baud rate generator (BRG: address 001C

This register is valid only when selecting the UART mode. A baud rate value is set.

CPU read: Disabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used

Fig. 27 Structure of serial I/O1-related registers (4)

24

16

)

b7 b0

UART control register (UARTCON: address 001B

Character length selection bit 0: 8 bits 1: 7 bits

Parity enable bit 0: Parity checking disabled 1: Parity checking enabled

Parity selection bit 0: Even parity 1: Odd parity

Stop bit length selection bit 0: 1 stop bit 1: 2 stop bits

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7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

16

)

CPU read: Disabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used

b7 b0

P-channel output disable bit 0: CMOS output 1: N-channel open-drain output

Not used (returns “1” when read)

Serial I/O1 control register

16

(SIO1CON: address 001A

)

BRG count source selection bit

IN

)

0: f(X

IN

)/4

1: f(X Not used (returns “1” when read) Continuous transmit valid bit

0: Continuous transmit invalid 1: Continuous transmit valid

Transmit interrupt source selection bit 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed

Transmit enable bit 0: Transmit disabled 1: Transmit enabled

CPU read: Disabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used

CPU read: Disabled CPU write: Set/Clear Hardware read: Used Hardware write: Not used

Fig. 28 Structure of serial I/O1-related registers (5)

Receive enable bit 0: Receive disabled 1: Receive enabled

Serial I/O1 mode selection bits 00: I/O port 01: Not available 10: UART mode 11: USB mode

25

Note on using USB mode Handling of SE0 signal in program (at receiving)

7536 group has the border line to detect as USB RESET or EOP (End of Packet) on the width of SE0 (Single Ended 0). A response apposite to a state of the device is expected. The name of the following short words which is used in table 7 shows as follow.

•TKNE: Token interrupt enable (bit 6 of address 2016)

•RSME: Resume interrupt enable (bit 5 of address 2016)

•RSTE: USB reset interrupt enable (bit 4 of address 2016)

•Spec: A response of the device requested by USB Specification 1.0

•SIE: Hardware operation in 7536 group

•F/W: Recommendation process in the program

•FEOPE: False EOP error flag (bit 2 of address 1916)

•RxPID: Token interrupt flag (bit 7 of address 1F16)

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Table 5 Relation of the width of SE0 and the state of the device

Width of SE0

0 µ sec.

0.5 µ sec.

0.5 µ sec.

2.5 µ sec.

2.5 µ sec.

2.67 µ sec.

2.67 µ sec.

Spec

Ignore Keep counting suspend

timer

SIE

F/W

Not acknowledge

Spec

Keep alive Initialize suspend timer

SIE

count value Not acknowledge

F/W

Spec

Keep alive or Reset may determine as keep

SIE

alive and Reset interrupt Keep alive in case of no

interrupt request

F/W

Reset processing in case of interrupt request

Spec

Reset Reset interrupt request

SIE

Reset processing

F/W

Idle state TKNE = X RSME = 0

RSTE =1

End of Token in transaction

TKNE = 1

RSME = 0

RSTE =1

Ignore Not detected as EOP(in

case of no detection EOP, SIE returns idle state as time out. FEOPE flag is set.)

Not acknowledge EOP Token interrupt request

Token interrupt processing execute

EOP or Reset may determine as EOP

and Reset interrupt RxPID = 1> Token

interrupt processing RxPID = 0> Reset

interrupt processing

Reset Reset interrupt request Reset processing

State of device

End of data or handshake in transaction

Ignore Not detected as EOP(in

case of no detection EOP, SIE returns idle state as timeup. FEOPE flag is set.)

Wait for the next EOP flag EOP Set EOP flag

After checking the set of EOP flag, go to the next processing

EOP or Reset may determine as EOP

and Reset interrupt Continue the processing

in case of no interrupt request

Reset processing in case of interrupt request

Reset Reset interrupt request Reset processing

TKNE = 0

RSME = 0

RSTE = 0 or 1

Suspend state

Spec

SIE

F/W

TKNE = 0

RSME = 1

RSTE = 0

Reset or resume

Reset interrupt request

Reset interrupt processing

Resume interrupt processing

26

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

●Serial I/O2

The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2 the transmitter and the receiver must use the same clock. When the internal clock is used, transfer is started by a write signal to the serial I/O2 register.

[Serial I/O2 control register] SIO2CON

The serial I/O2 control register contains 8 bits which control various serial I/O functions.

• For receiving, set “0” to bit 3.

• When receiving, bit 7 is cleared by writing dummy data to serial I/ O2 register after shift is completed.

• Bit 7 is set earlier a half cycle of shift clock than completion of shift operation. Accordingly, when checking shift completion by using this bit, the setting is as follows: (1) check that this bit is set to “1”, (2) wait a half cycle of shift clock, (3) read/write to serial I/O2 register.

XIN

SCLK pin

selection bit

SCLK

b7 b0

Serial I/O2 control register (SIO2CON: address 0030

Internal synchronous clock selection bits 000 : f(X 001 : f(X 010 : f(X 011 : f(X 110 : f(X 111 : f(X

S 0 : I/O port/S 1 : S

Not used (returns "0" when read)

Transfer direction selection bit 0 : LSB first 1 : MSB first

S 0 : External clock (S 1 : Internal clock (S

Transmit / receive shift completion flag 0 : shift in progress 1 : shift completed

Note : When using it as a S

direction register to “0”.

IN

)/8

IN

)/16

IN

)/32

IN

)/64

IN

)/128

IN

DATA

CLK

)/256

pin selection bit (Note)

DATA

DATA

output

pin selection bit

DATA

input, set the port P13

input

CLK

Fig. 29 Structure of serial I/O2 control registers

Data bus

1/8 1/16 1/32 1/64

Divider

1/128 1/256

“1”

Internal synchronous clock selection bits

“0”

16

)

CLK

is an input)

is an output)

SCLK pin selection bit

P12/SCLK

SDATA pin selection bit

P13/SDATA

S

DATA pin selection bit

Fig. 30 Block diagram of serial I/O2

“0”

P12 latch

“1”

“0”

P13 latch

“1”

Serial I/O counter 2 (3)

Serial I/O shift register 2 (8)

Serial I/O2 interrupt request

27

Serial I/O2 operation

By writing to the serial I/O2 register(address 0031

16) the serial I/O2

counter is set to “7”. After writing, the S

DATA pin outputs data every time the transfer clock

shifts from a high to a low level. And, as the transfer clock shifts from a low to a high, the S

DATA pin reads data, and at the same time the

contents of the serial I/O2 register are shifted by 1 bit. When the internal clock is selected as the transfer clock source, the following operations execute as the transfer clock counts up to 8.

• Serial I/O2 counter is cleared to “0”.

• Transfer clock stops at an “H” level.

• Interrupt request bit is set.

• Shift completion flag is set.

Also, the S

DATA pin is in a high impedance state after the data trans-

fer is complete (refer to figure 31). When the external clock is selected as the transfer clock source, the interrupt request bit is set as the transfer clock counts up to 8, but external control of the clock is required since it does not stop. Notice that the S

DATA pin is not in a high impedance state on the completion

of data transfer.

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Synchronous clock

Transfer clock

Serial I/O2 register

write signal

DATA

at serial I/O2

S output transmit

S

DATA

at serial I/O2

input receive

Note : When the internal clock is selected as the transfer and the direction register of P13/S

the S

DATA

pin is in a high impedance state after the data transfer is completed.

Fig. 31 Serial I/O2 timing (LSB first)

D

0

D1D2D3D4D5D6D

DATA

(Note)

7

Serial I/O2 interrupt request bit set

pin is set to the input mode,

28

MITSUBISHI MICROCOMPUTERS

Read 8-bit (Read only address 003516)

b7 b0

b9 b8 b7 b6 b5 b4 b3 b2

(Address 003516)

Read 10-bit (read in order address 0036

16

, 003516)

b7

b0

b9 b8

(Address 0036

16

)

b7

b0

b7 b6 b5 b4 b3 b2 b1 b0

(Address 0035

16

)

High-order 6-bit of address 0036

16

returns “0” when read.

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

A-D Converter

The functional blocks of the A-D converter are described below.

[A-D conversion register] AD

The A-D conversion register is a read-only register that stores the result of A-D conversion. Do not read this register during an A-D conversion.

[A-D control register] ADCON

The A-D control register controls the A-D converter. Bit 2 to 0 are analog input pin selection bits. Bit 4 is the AD conversion completion bit. The value of this bit remains at “0” during A-D conversion, and changes to “1” at completion of A-D conversion. A-D conversion is started by setting this bit to “0”.

[Comparison voltage generator]

The comparison voltage generator divides the voltage between VSS and VREF by 1024 by a resistor ladder, and outputs the divided voltages. Since the generator is disconnected from VREF pin and VSS pin, current is not flowing into the resistor ladder.

[Channel Selector]

The channel selector selects one of ports P27/AN7 to P20/AN0, and inputs the voltage to the comparator.

[Comparator and control circuit]

The comparator and control circuit compares an analog input voltage with the comparison voltage and stores its result into the A-D conversion register. When A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to “1”. Because the comparator is constructed linked to a capacitor, set f(XIN) to 500 kHz or more during A-D conversion.

b7 b0

A-D control register (ADCON : address 0034

Analog input pin selection bits 000 : P2 001 : P21/AN1 010 : P22/AN2 011 : P23/AN3 100 : P24/AN4 101 : P25/AN5 110 : P26/AN6 111 : P27/AN7

Not used (returns “0” when read) AD conversion completion bit

0 : Conversion in progress 1 : Conversion completed Not used (returns “0” when read)

0/AN0

Fig. 32 Structure of A-D control register

Fig. 33 Structure of A-D conversion register

16)

Data bus

P20/AN P21/AN P22/AN P23/AN P24/AN P25/AN P26/AN P27/AN

Fig. 34 Block diagram of A-D converter

A-D control register

(Address 0034

0 1 2 3 4 5 6 7

16

Channel selector

b7 b0

)

3

A-D control circuit

Comparator

A-D conversion register (high-order)

A-D conversion register (low-order)

Resistor ladder

V

REF

A-D interrupt request

(Address 003616)

(Address 0035

16

)

10

V

SS

29

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Watchdog Timer

The watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. The watchdog timer consists of an 8-bit watchdog timer H and an 8bit watchdog timer L, being a 16-bit counter.

Standard operation of watchdog timer

The watchdog timer stops when the watchdog timer control register (address 003916) is not set after reset. Writing an optional value to the watchdog timer control register (address 003916) causes the watchdog timer to start to count down. When the watchdog timer H underflows, an internal reset occurs. Accordingly, it is programmed that the watchdog timer control register (address 003916) can be set before an underflow occurs. When the watchdog timer control register (address 003916) is read, the values of the high-order 6-bit of the watchdog timer H, STP instruction disable bit and watchdog timer H count source selection bit are read.

Initial value of watchdog timer

By a reset or writing to the watchdog timer control register (address

003916), the watchdog timer H is set to “FF16” and the watchdog

timer L is set to “FF16”.

Operation of watchdog timer H count source selection bit

A watchdog timer H count source can be selected by bit 7 of the watchdog timer control register (address 003916). When this bit is “0”, the count source becomes a watchdog timer L underflow signal. The detection time is 174.763 ms at f(XIN)=6 MHz. When this bit is “1”, the count source becomes f(XIN)/16. In this case, the detection time is 683 µs at f(XIN)=6 MHz. This bit is cleared to “0” after reset.

Operation of STP instruction disable bit

When the watchdog timer is in operation, the STP instruction can be disabled by bit 6 of the watchdog timer control register (address

003916). When this bit is “0”, the STP instruction is enabled. When this bit is “1”, the STP instruction is disabled, and an internal reset occurs if the STP instruction is executed. Once this bit is set to “1”, it cannot be changed to “0” by program. This bit is cleared to “0” after reset.

Write "FF

16" to the

watchdog timer control register

XIN

STP Instruction Disable Bit

RESET

Fig. 35 Block diagram of watchdog timer

1/16

STP Instruction

b7 b0

Data bus

Write "FF16" to the

Watchdog timer L (8)

“0”

“1”

Watchdog timer H count source selection bit

Watchdog timer H (8)

Reset circuit

watchdog timer control register

Internal reset

Watchdog timer control register(address 003916) WDTCON

Watchdog timer H (read only for high-order 6-bit) STP instruction disable bit

0 : STP instruction enabled 1 : STP instruction disabled

Watchdog timer H count source selection bit 0 : Watchdog timer L underflow 1 : f(X

Fig. 36 Structure of watchdog timer control register

30

IN

)/16

Reset Circuit

The microcomputer is put into a reset status by holding the RESET pin at the “L” level for 15 µs or more when the power source voltage is 4.1 to 5.5 V and X After that, this reset status is released by returning the RESET pin to the “H” level. The program starts from the address having the contents of address FFFD address FFFC Note that the reset input voltage should be 0.82 V or less when the power source voltage passes 4.1 V.

IN is in stable oscillation.

16 as high-order address and the contents of

16 as low-order address.

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Poweron

Power source voltage

VCCRESET

0 V

Reset input voltage

0 V

Note : Reset release voltage Vcc = 4.1 V

(Note)

0.2 V

CC

Clock from built-in ring oscillator

φ

RESET

OUT

RESET

SYNC

Address

Data

? ? FFFC FFFD

8-13 clock cycles

???

??

Notes

RESET

VCC

Power source voltage detection circuit

Fig. 37 Example of reset circuit

ADH,AD

L

L

AD

???

1 : A built-in ring oscillator applies about 250 kHz frequency clock as f at average of Vcc = 5 V. 2 : The mark “?” means that the address is changeable depending on the previous state. 3 : These are all internal signals except RESET

AD

H

Reset address from the vector table

Fig. 38 Timing diagram at reset

31

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

(1)

Port P0 direction register

(2)

Port P1 direction register

(3)

Port P2 direction register

(4)

Port P3 direction register

(5)

Port P4 direction register

(6)

Pull-up control register

(7)

USB/UART status register

(8)

Serial I/O1 control register

(9)

UART control register

(10)

USB data toggle synchronization register

(11)

USB interrupt source discrimination register 1

(12)

USB interrupt source discrimination register 2

(13)

USB interrupt control register

(14)

USB transmit data byte number set register 0

(15)

USB transmit data byte number set register 1

(16)

USBPID control register 0

(17)

USBPID control register 1

(18)

USB address register

(19)

USB sequence bit initialization register

(20)

USB control register

(21)

Prescaler 12

(22)

Timer 1

(23)

Timer 2

(24)

Timer X mode register

(25)

Prescaler X

(26)

Timer X

(27)

Timer count source set register

(28)

Serial I/O2 control register

(29)

A-D control register

(30)

MISRG

(31)

Watchdog timer control register

(32)

Interrupt edge selection register

(33)

CPU mode register

(34)

Interrupt request register 1

(35)

Interrupt control register 1

(36)

Processor status register

(37)

Program counter

Address

0001

16

0003

16

0005

16

0007

16

0009

16

0016

16

0019

16

16

001A 001B

16

001D

16

001E

16

001F

16

0020

16

0021

16

0022

16

0023

16

0024

16

0025

16

0026

16

0027

16

0028

16

0029

16

002A

16

002B

16

002C

16

002D

16

002E

16

16

0030 0034

16

0038

16

0039

16

003A

16

003B

16

003C

16

003E

16

(PS)

(PCH)

L

)

(PC

Register contents

00

16

X00000

00

00

16

00

16

XXX 00XXX

FF

16

10000001

02

16

11100000

01111111 01111111

01110011

00000111

00

16

00

16

00000111 00111111 10000000

11111111

00111111

FF

16

01

16

00

16

00

16

FF

16

FF

16

00

16

00

16

10

16

00

16

00111111

00

16

10000000

00

16

00

16

XXXXX1XX

Contents of address FFFD Contents of address FFFC

Note X : Undefined

16

16

Fig. 39 Internal status of microcomputer at reset

32

Clock Generating Circuit

XIN XOUT

External oscillation circuit

V

CC

VSS

Open

An oscillation circuit can be formed by connecting a resonator between XIN and XOUT. Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip.

●Oscillation control

For the details of the state and release of stop mode and wait mode, refer to “Stop mode” and “Wait mode” of “FUNCTIONAL DESCRIPTION SUPPLEMENT”.

• Stop mode

When the STP instruction is executed, the internal clock φ stops at an “H” level and the XIN oscillator stops. At this time, timer 1 is set to “0116” and prescaler 12 is set to “FF16” when the oscillation stabilization time set bit after release of the STP instruction is “0”. On the other hand, timer 1 and prescaler 12 are not set when the above bit is “1”. Accordingly, set the wait time fit for the oscillation stabilization time of the oscillator to be used. f(XIN)/16 is forcibly connected to the input of prescaler 12. When an external interrupt is accepted, oscillation is restarted but the internal clock φ remains at “H” until timer 1 underflows. As soon as timer 1 underflows, the internal clock φ is supplied. This is because when a ceramic oscillator is used, some time is required until a start of oscillation. In case oscillation is restarted by reset, no wait time is generated. So apply an “L” level to the RESET pin while oscillation becomes stable.

______

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

XIN

CIN

Fig. 40 External circuit of ceramic resonator

XOUT

COUT

• Wait mode

If the WIT instruction is executed, the internal clock φ stops at an “H” level, but the oscillator does not stop. The internal clock φ re starts if a reset occurs or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that interrupts will be received to release the STP or WIT state, interrupt enable bits must be set to “1” before the STP or WIT instruction is executed. When the STP status is released, prescaler 12 and timer 1 will start counting with the f(XIN)/16, so set the timer 1 interrupt enable bit to “0” before the STP instruction is executed.

Note

For use with the oscillation stabilization time set bit after release of the STP instruction set to “1”, set values in timer 1 and prescaler 12 after fully appreciating the oscillation stabilization time of the oscillator to be used.

• Clock mode

Operation is started by a built-in ring oscillator after releasing reset. A division ratio (1/1,1/2,1/8) is selected by setting bits 7 and 6 of the CPU mode register after releasing it.

Fig. 41 External clock input circuit

b7 b0

MISRG(Address 003816)

Oscillation stabilization time set bit after release of the STP instruction 0: Set "01 in prescaler 12 automatically 1: Not set automatically

Reserved bits (return “0” when read) (Do not write “1” to these bits)

Not used (return “0” when read)

Fig. 42 Structure of MISRG

16

" in timer1, and "FF16"

33

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

X

X

IN

Rf

OUT

Rd

Main clock division ratio selection bit Middle-speed, High-speed, double -speed mode

Ring oscillator

mode

1/2

1/4

High-speed mode

1/2

Main clock division ratio selection bit

Middle-speed mode

Prescaler 12

Timer 1

Timing φ (Internal clock)

Double-speed mode

Ring oscillator

(Note)

SRQ

STP instruction

1/8

Ring oscillator mode

instruction

WIT

Q

S

R

Reset

Interrupt disable flag l

Interrupt request

Fig. 43 Block diagram of system clock generating circuit (for ceramic resonator)

Note: Ring oscillator is used only for starting.

S

Q

R

STP instruction

34

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

NOTES ON PROGRAMMING Processor Status Register

The contents of the processor status register (PS) after reset are undefined except for the interrupt disable flag I which is “1”. After reset, initialize flags which affect program execution. In particular, it is essential to initialize the T flag and the D flag because of their effect on calculations.

Interrupts

The contents of the interrupt request bit do not change even if the BBC or BBS instruction is executed immediately after they are changed by program because this instruction is executed for the previous contents. For executing the instruction for the changed contents, execute one instruction before executing the BBC or BBS instruction.

Decimal Calculations

• For calculations in decimal notation, set the decimal mode flag D to “1”, then execute the ADC instruction or SBC instruction. In this case, execute SEC instruction, CLC instruction or CLD instruction after executing one instruction following the ADC instruction or SBC instruction.

• In the decimal mode, the values of the N (negative), V (overflow) and Z (zero) flags are invalid.

NOTES ON USE Handling of Power Source Pin

In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of to

0.1 µF is recommended.

Handling of USBVREFOUT Pin

In order to prevent the instability of the USBVREFOUT output due to external noise, connect a capacitor as bypass capacitor between USBVREFOUT pin and GND pin (VSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor, a ceramic or electrolytic capacitor of 0.1 µF is recommended.

One Time PROM Version

The CNVss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (VPP pin) as well. To improve the noise reduction, connect a track between CNVss pin and Vss pin with 1 to 10 kΩ resistance. The mask ROM version track of CNVss pin has no operational interference even if it is connected via a resistor.

Timers

• When n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1).

• When a count source of timer X is switched, stop a count of timer X.

Ports

• The values of the port direction registers cannot be read. That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is “1”, addressing mode using direction register values as qualifiers, and bit test instructions such as BBC and BBS. It is also impossible to use bit operation instructions such as CLB and SEB and read/modify/write instructions of direction registers for calculations such as ROR. For setting direction registers, use the LDM instruction, STA instruction, etc.

• Set "1" to each bit 6 of the port P3 direction register and the port P3 register (for only 7532 Group).

A-D Converter

The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(XIN) is 500kHz or more during A-D conversion. Do not execute the STP instruction during A-D conversion.

Instruction Execution Timing

The instruction execution time can be obtained by multiplying the frequency of the internal clock φ by the number of cycles mentioned in the machine-language instruction table. The frequency of the internal clock φ is the same as that of the XIN in double-speed mode, twice the XIN cycle in high-speed mode and 8 times the XIN cycle in middle-speed mode.

35

MITSUBISHI MICROCOMPUTERS

Programming with PROM programmer

Screening (Caution)

(150 °C for 40 hours)

Verification with PROM

programmer

Functional check in

target device

The screening temperature is far higher than the storage temperature. Never expose to 150 °C exceeding 100 hours.

Caution:

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

DATA REQUIRED FOR MASK ORDERS

The following are necessary when ordering a mask ROM production:

(1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form

(three identical copies)

ROM PROGRAMMING METHOD

The built-in PROM of the blank One Time PROM version can be read or programmed with a general-purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area.

Table 6 Special programming adapter

Package

42P4B

The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 44 is recommended to verify programming.

Name of Programming Adapter

PCA7435SP

36

Fig. 44 Programming and testing of One Time PROM version

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

ELECTRICAL CHARACTERISTICS

Table 7 Absolute maximum ratings

Symbol VCC VI

VI VI VO

Pd Topr Tstg

Note: It is a rating only for the One Time PROM version. Connect to VSS for mask ROM version.

Power source voltage Input voltage P00–P07, P10–P16, P20–P27, P30–

Input voltage Input voltage CNVSS (Note)

Output voltage P00–P07, P10–P16, P20–P27, P30–

Power dissipation Operating temperature Storage temperature

Parameter

P37, VREF, P40, P41

____________

RESET, XIN

P37, XOUT, USBVREFOUT, P40, P41

Conditions

All voltages are based on VSS. Output transistors are cut off.

Ta = 25°C

MITSUBISHI MICROCOMPUTERS

7536 Group

Ratings

–0.3 to 7.0

–0.3 to VCC + 0.3

–0.3 to VCC + 0.3

–0.3 to 13

–0.3 to VCC + 0.3

1000

–20 to 85

–40 to 125

Unit

V V

V V V

mW

°C °C

37

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Table 8 Recommended operating conditions (VCC = 4.1 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)

Symbol Parameter Unit

VCC VSS VREF VIH

VIH VIH VIH

VIL

VIL VIL VIL VIL

∑IOH(peak)

∑IOL(peak)

∑IOL(peak) ∑IOH(avg)

∑IOL(avg)

∑IOL(avg)

IOH(peak)

IOL(peak)

IOL(peak) IOH(avg)

IOL(avg)

IOL(avg) f(XIN)

Note 1:The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average

2: The peak output current is the peak current flowing in each port. 3: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms. 4: When the oscillation frequency has a duty cycle of 50 %.

Power source voltage Power source voltage

Analog reference voltage “H” input voltage P00–P07, P10–P16, P20–P27,

“H” input voltage (TTL input level selected) P10, P12, P13, P36, P37 “H” input voltage “H” input voltage D+, D“L” input voltage P00–P07, P10–P16, P20–P27,

“L” input voltage (TTL input level selected) P10, P12, P13, P36, P37 “L” input voltage “L” input voltage D+, D“L” input voltage XIN “H” total peak output current (Note 1) P00–P07, P10–P16, P20–P27,

“L” total peak output current (Note 1) P00–P07, P10–P16, P20–P27,

“L” total peak output current (Note 1) P30–P36 “H” total average output current (Note 1) P00–P07, P10–P16, P20–P27,

“L” total average output current (Note 1) P00–P07, P10–P16, P20–P27,

“L” total average output current (Note 1) P30–P36 “H” peak output current (Note 2) P00–P07, P10–P16, P20–P27,

“L” peak output current (Note 2) P00–P07, P10–P16, P20–P27,

“L” peak output current (Note 2) P30–P36 “H” average output current (Note 3) P00–P07, P10–P16, P20–P27,

“L” average output current (Note 3) P00–P07, P10–P16, P20–P27,

“L” average output current (Note 3) P30–P36 Oscillation frequency (Note 4) VCC = 4.1 to 5.5 V

at ceramic oscillation or external clock input Double-speed mode

value measured over 100 ms. The total peak current is the peak value of all the currents.

f(XIN) =

6 MHz

P30–P37, P40, P41

____________

RESET, XIN

P30–P37, P40, P41

____________

RESET, CNVSS

P30–P37, P40, P41

P37, P40, P41

P30–P37, P40, P41

P37, P40, P41

P30–P37, P40, P41

P37 , P40, P41

P30–P37, P40, P41

P37, P40, P41

Min.

4.1

2.0

0.8 VCC

2.0

0.8 VCC

2.0 0

0 0 0 0

Limits

Typ.

5.0 0

Max.

5.5

VCC VCC

VCC VCC

3.6

0.3 VCC

0.8

0.2 VCC

0.8

0.16VCC –80

80

60

–40

40

30

–10

10

30 –5

5

15

6

V V V V

V V V

V

V V V

V

mA

mA

mA mA

mA

mA mA

mA mA

mA

mA

mA

MHz

38

Table 9 Electrical characteristics (1)

CC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

(V

Symbol Parameter

VOH

VOH

V

OL

VOL

VOL

V

T+–VT–

VT+–VT–

VT+–VT– VT+–VT– IIH

IIH IIH IIL

IIL IIL IIL

VRAM

Note 1:P1

2:R

“H” output voltage P00–P07, P10–P16, P20–P27,

0–P37, P40, P41 (Note 1)

P3

“H” output voltage D+, D-

“L” output voltage P0

0–P07, P10–P16, P20–P27,

P3

7, P40, P41

“L” output voltage D+, D-

“L” output voltage P3

0–P36

Hysteresis D+, DHysteresis CNTR

Hysteresis R

0, INT0, INT1 (Note 2),

P0

0–P07(Note 3)

XD, SCLK, SDATA (Note 2)

Hysteresis RESET “H” input current P0

0–P07, P10–P16, P20–P27, 0–P37, P40, P41

P3

“H” input current RESET “H” input current X

IN

“L” input current P00–P07, P10–P16, P20–P27,

P3

0–P37, P40, P41

“L” input current RESET, CNVSS “L” input current XIN “L” input current P00–P07, P30–P37

RAM hold voltage

1 is measured when the P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.

XD, SCLK, SDATA, INT0 and INT1 have hystereses only when bits 0, 1 and 2 of the port P1P3 control register are set to “0” (CMOS level).

3:It is available only when operating key-on wake-up.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Test conditions

OH = –5 mA

I V

CC = 4.1 to 5.5 V

OH = –1.0 mA

I

CC = 4.1 to 5.5 V

V V

CC = 4.4 to 5.25 V

Pull-down through 15kΩ ±5 % for D+, DPull-up through 1.5kΩ ±5 % by USBVREFOUT for D- (Ta = 0 to 70 °C)

OL = 5 mA

I V

CC = 4.1 to 5.5 V

OL = 1.5 mA

I

CC = 4.1 to 5.5 V

V V

CC = 4.4 to 5.25 V

Pull-down through 15kΩ ±5 % for D+, DPull-up through 1.5kΩ ±5 % by USBVREFOUT for D-(Ta = 0 to 70 °C)

OL = 15 mA

I V

CC = 4.1 to 5.5 V

OL = 1.5 mA

I

CC = 4.1 to 5.5 V

V

I = VCC

V (Pin floating. Pull-up transistors “off”)

I = VCC

V VI = VCC VI = VSS

(Pin floating. Pull-up transistors “off”)

I = VSS

V VI = VSS

VI = VSS (Pull-up transistors“on”)

When clock stopped

MITSUBISHI MICROCOMPUTERS

7536 Group

Limits

Min. Typ. Max.

VCC–1.5

CC–1.0

V

2.8

0.15

0.4

0.5

0.5

4

–4

–0.2

2.0

3.6

1.5

0.3

0.3

2.0

0.3

5.0

5.0

–5.0

–5.0

–0.5

5.5

Unit

V

V

V

V

V

V

V

V

V V

V V

µA

µA µA µA

µA µA

mA

V

39

Table 10 Electrical characteristics (2)

CC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

(V

Symbol Parameter

I

CC

Power source current 6

Double-speed mode, f(X

IN) = 6 MHz,

Output transistors “off”

IN) = 6 MHz, (in WIT state)

f(X Output transistors “off”

Increment when A-D conversion is executed

IN) = 6 MHz, VCC = 5 V

f(X All oscillation stopped (in STP state)

Output transistors “off” V

CC = 4.4 V to 5.25 V

Oscillation stopped in USB mode USB (SUSPEND), (pull-up resistor output not included) (Fig. 45)

Table 11 A-D Converter characteristics (1)

CC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

(V

Symbol Parameter

— —

Resolution Linearity error

VCC = 4.1 to 5.5 V Ta = 25 °C

—

Differential nonlinear error

V Ta = 25 °C

OT

V VFST tCONV RLADDER IVREF

Zero transition voltage Full scale transition voltage Conversion time Ladder resistor Reference power source input current

VCC = VREF = 5.12 V V

VREF = 5.0 V V

II(AD)

A-D port input current

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Test conditions

Ta = 25 °C Ta = 85 °C

Ta = 0 to 70 °C

Test conditions

CC = 4.1 to 5.5 V

CC = VREF = 5.12 V

REF = 3.0 V

MITSUBISHI MICROCOMPUTERS

7536 Group

Limits

Min. Typ. Max.

10

1.6

3.2

0.8

0.1

1.0 10

300

Limits

Min. Typ. Max.

10

±3

±0.9

0520

5105

5115 5125 mV

122 tc(XIN)

55 50 30

150

70

200 120

5.0

Unit mA

mA

mA

µA µA µA

Unit Bits

LSB

LSB

mV

kΩ

µA

µA

V

CC

I

CC

V

CC

USBV

REFOUT

1.5 kΩ

D-

V

SS

Rating value = ICC – I

I

OUT

15 kΩ

OUT

Fig. 45 Power source current measurement circuit in USB mode at oscillation stop

40

Table 12 Timing requirements

CC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

(V

Symbol Parameter

____________

tW(RESET)

C(XIN)

t t

WH(XIN) WL(XIN)

t

C(CNTR)

t

WH(CNTR)

t

WL(CNTR)

t

C(SCLK)

t t

WH(SCLK) WL(SCLK)

t

su(SCLK–SDATA)

t

h(SCLK–SDATA)

t

Reset input “L” pulse width External clock input cycle time

External clock input “H” pulse width External clock input “L” pulse width CNTR

0 input cycle time

CNTR

0, INT0, INT1 input “H” pulse width 0, INT0, INT1 input “L” pulse width

CNTR Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Min.

15

166

70 70

200

80 80

1000

400 400 200 200

Limits

Typ. Max.

Unit

µs ns ns ns ns ns ns ns ns ns ns ns

Table 13 Switching characteristics

CC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

(V

Symbol Parameter

tWH(SCLK)

WL(SCLK)

t t

d(SCLK–SDATA) v(SCLK–SDATA)

t

r(SCLK)

t

f(SCLK)

t

r(CMOS)

t

f(CMOS)

t t

r(D+), tr(D-) f(D+), tf(D-)

t

Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note) CMOS output falling time (Note) USB output rising time, C USB output falling time, C

L = 350 pF, Ta = 0 to 70 °C

L = 350 pF, Ta = 0 to 70 °C

Note: XOUT pin is excluded.

Measured pin

100 pF

CMOS output

Fig. 46 Switching characteristics measurement circuit

Limits

Min. Typ. Max.

t

C(SCLK)/2–30 C(SCLK)/2–30

t

0

10

10 100 100

200 200

140

30 30 30

30 300 300

Unit

ns ns ns ns ns ns ns ns ns ns

41

CNTR

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

tC(CNTR)

tWH(CNTR)

0.8V

0

CC

0.2V

tWL(CNTR)

CC

INT0/INT

RESET

X

IN

S

CLK

tWH(INT)

0.8V

1

CC

0.2V

tWL(INT)

CC

tW(RESET)

0.8V

0.2V

CC

CC

tC(XIN)

CC

CC

tWL(XIN)

CLK

)

tWH(XIN)

0.8V

CC

tC(S

CLK

t

f

0.2V

CC

tWL(S

CLK

) tWH(S

0.2V

)

t

r

0.8V

S

S

D+, D-

Fig. 47 Timing chart

42

DATA

DATA

(at receive)

(at transmit)

td(S

CLK-SDATA

t

f

0.1V0H

tsu(S

)

DATA-SCLK

0.8V

CC

0.2V

CC

)th(S

CLK-SDATA

)

tv(S

CLK-SDATA

t

r

)

0.9V0H

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MARK SPECIFICATION FORM

42P4B (42-PIN SHRINK DIP) MARK SPECIFICATION FORM

Mitsubishi IC catalog name

Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed).

A. Standard Mitsubishi Mark

42

Mitsubishi lot number

(6-digit or 7-digit)

22

Mitsubishi IC catalog name

1

B. Customer’s Parts Number + Mitsubishi Catalog Name

42

Mitsubishi lot number

(6-digit or 7-digit)

1

C. Special Mark Required

42

1

21

22

Customer’s Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned.

2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer’s Parts Number can be up to 15 characters : Only 0 ~

21

9, A ~ Z, +, –, /, (, ), &, ,. (periods),, (commas) are usable.

4 : If the Mitsubishi logo is not required, check the box below.

Mitsubishi logo is not required

22

Note1 : If the Special Mark is to be Printed, indicate the desired

layout of the mark in the left figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked.

2 : If the customer’s trade mark logo must be used in the

Special Mark, check the box below. Please submit a clean original of the logo. For the new special character fonts a clean font original

21

(ideally logo drawing) must be submitted.

Special logo required

3 : The standard Mitsubishi font is used for all characters

except for a logo.

43

PACKAGE OUTLINE

SDIP42-P-600-1.78

Weight(g)

–

JEDEC Code

4.1

EIAJ Package Code

Lead Material

Alloy 42/Cu Alloy

42P4B

Plastic 42pin 600mil SDIP

Symbol

Min Nom Max

A

A

2

b

b

1

b

2

c

E

D

L

Dimension in Millimeters

A

1

0.51 – – –3.8–

0.35 0.45 0.55

0.9 1.0 1.3

0.63 0.73 1.03

0.22 0.27 0.34

36.5 36.7 36.9

12.85 13.0 13.15 – 1.778 – – 15.24 –

3.0 – – 0° –15°

– – 5.5

e

e

1

42

22

21

1

E

c

e

1

A

2

A

1

b

b

1

b

2

e

LA

SEATING PLANE

D

MITSUBISHI MICROCOMPUTERS

7536 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

© 1999 MITSUBISHI ELECTRIC CORP. New publication, effective Jun. 1999. Specifications subject to change without notice.

44

Keep safety first in your circuit designs!

• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

• These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.

• Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials.

• All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein.

• Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

• The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.

• If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.

• Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.

REVISION DESCRIPTION LIST 7536 Group DATA SHEET

Rev. Rev.

No. date

1.0 First Edition 980109

2.0 Most of the contents (Functional Description, Electrical characteristics, and so on) are updated. 990716

2.1 Updated as follows: 991110

Page 1; Power dissipation to 30 mW Page 7; Fig.7 Start address of Interrupt vector area to FFEC16 Page 40; Table 11; Parameter to Linearity error from former Linear error

2.2 Page 11; Fig.11 Note revised 000614

Page 28; Fig.31 Note revised Page 31; Description revised; RESET “L” pulse width 2 µs → 15 µs Page 39; Table 9 Hysteresis “RESET” added Page 41; Table 12 tw(RESET) revised; 2 → 15

2.3 Pages 11, 12, 31: Character fonts errors revised 000905

Revision Description

(1/2)

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