Mitsubishi M37534M4-XXXFP, M37534E8SP, M37534E8FP, M37534RSS, M37534M4-XXXSP Datasheet
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 7534 Group is the 8-bit microcomputer based on the 740 family
core technology.
The 7534 Group has a USB, 8-bit timers, and an A-D converter, and
is useful for an input device for personal computer peripherals.
FEATURES
Basic machine-language instructions....................................... 69
•
The minimum instruction execution time .......................... 0.34 µs
•
•
•
•
•
(at 6 MHz oscillation frequency for the shortest instruction)
Memory size
ROM ............................................... 8K to 16K bytes
RAM ..............................................256 to 384 bytes
Programmable I/O ports ...................................... 28 (36-pin type)
............................................................................ 24 (32-pin type)
............................................................................ 33 (42-pin type)
Interrupts .................................................... 14 sources, 8 vectors
Timers ............................................................................ 8-bit ✕ 3
PIN CONFIGURATION (TOP VIEW)
P1
2/SCLK
P13/S
DATA
P14/CNTR
P20/AN
P21/AN
P22/AN
P23/AN
P24/AN
P25/AN
6
/AN
P2
P27/AN
V
REF
RESET
CNV
Vcc
X
X
OUT
V
0
0
1
2
3
4
5
6
7
SS
IN
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Serial I/O1 ................................ used only for Low Speed in USB
•
Serial I/O2 ...................................................................... 8-bit ✕ 1
•
A-D converter ................................................ 10-bit ✕ 8 channels
•
Clock generating circuit ............................................. Built-in type
•
(connect to external ceramic resonator or quartz-crystal oscillator )
Watchdog timer ............................................................ 16-bit ✕ 1
•
Power source voltage
•
At 6 MHz X
................................4.1 to 5.5 V(4.4 to 5.25 V at USB operation)
Power dissipation ............................................ 30 mW (standard)
•
Operating temperature range................................... –20 to 85 °C
•
Built-in USB 3.3 V Regulator + transceiver based on USB Spec.
•
Rev.1.1
IN oscillation frequency at ceramic resonator
APPLICATION
Input device for personal computer peripherals
36
35
34
M37534M4-XXXFP
M37534E8FP
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
P11/TXD/D+
P10/RXD/DP0
P0
P0
P0
P0
P0
P0
P0
USBV
P3
P35(LED5)
P3
P3
P3
P31(LED1)
P30(LED0)
(based on USBSpec. Rev.1.1)
(USB/UART)
(Clock-synchronized)
(0 to 70 °C at USB operation)
7
6
5
4
3
2
1
0
REFOUT
7
/INT
0
4
(LED4)
3
(LED3)
2
(LED2)
Package type: 36P2R-A
Fig. 1 Pin configuration of M37534M4-XXXFP, M37534E8FP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PIN CONFIGURATION (TOP VIEW)
6
P0
5
P0
4
P0
3
P0
2
P0
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
REFOUT
0
1
P0
P0
USBV
P0
P10/RXD/D-
P1
1/TX
D/D+
P1
2/SCLK
P13/S
DATA
P14/CNTR
P20/
AN
P21/
AN
23
2
3
/AN
3
P2
22
3
4
/AN
4
P2
24
7
0
0
1
25
26
27
28
M37534M4-XXXGP
29
30
31
32
1
2
/AN
2
P2
21
4
5
/AN
5
P2
20
19
6
5
REF
V
RESET
18
17
7
8
SS
CNV
CC
V
16
15
14
13
12
11
10
P34(LED4)
P3
3
(LED3)
P3
2
(LED2)
1
(LED1)
P3
P3
0
(LED0)
V
SS
X
OUT
9
X
IN
Fig. 2 Pin configuration of M37534M4-XXXGP
2
Outline 32P6U-A
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PIN CONFIGURATION (TOP VIEW)
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
P14/CNTR
P1
P1
P20/AN
1
/AN
P2
NC
P22/AN
3
/AN
P2
P24/AN
P25/AN
P26/AN
P27/AN
P4
P4
REF
V
RESET
CNV
Vcc
X
X
OUT
V
SS
IN
SS
0
5
6
0
1
2
3
4
5
6
7
0
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
M37534RSS
M37534M4-XXXSP
M37534E8SP
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P13/S
P12/S
P1
1/TX
DATA
CLK
D/D+
P10/RXD/DP0
7
P0
6
P0
5
P0
4
P0
3
P0
2
P0
1
P0
0
USBV
P37/INT
REFOUT
0
P36(LED6)/INT
P35(LED5)
P3
4
(LED4)
3
(LED3)
P3
P3
2
(LED2)
P31(LED1)
P30(LED0)
1
Outline 42S1M, 42P4B
Fig. 3 Pin configuration of M37534RSS, M37534M4-XXXSP, M37534E8SP
3
PRELIMINARY
SI/O1(8)
USB(LS)
R A M
R O M
C P U
A
X
Y
S
PC
H
PCL
PS
V
SS
18
RESET
13
VCC
15
14
CNVSS
CNTR0
P0(8)
34
32 30 28
33
31 29 27
P1(5)
3135236
7
56
4
P2(8)
P3(7)
12
16 17
11
9
10
8
VREF
0
26
INT
0
2023 21 1922
2425
SI/O2(8)
USBVREFOUT
XIN
XOUT
Clock input
Clock output
Clock generating circuit
Watchdog timer
Reset
A-D
converter
(10)
I/O port P3 I/O port P2 I/O port P1 I/O port P0
Key-on wake up
Timer 1 (8)
Timer 2 (8)
Timer X (8)
Prescaler 12 (8)
Prescaler X (8)
Reset input
Notice: This is not a final specification.
Some parametric limits are subject to change.
FUNCTIONAL BLOCK
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL BLOCK DIAGRAM (Package: 36P2R)
Fig. 4 Functional block diagram (36P2R package type)
4
PRELIMINARY
SI/O1(8)
USB(LS)
R A M
R O M
C P U
A
X
Y
S
PC
H
PC
L
PS
V
SS
11
RESET
6
V
CC
8
7
CNV
SS
CNTR
0
P0(8)
25
23 21 19
24
22 20 18
P1(5)
30 28 2629 27
32 31
P2(6)
P3(5)
5
910
4
2
3
1
V
REF
0
17
1316 14 1215
SI/O2(8)
USBV
REFOUT
X
IN
X
OUT
Clock input
Clock output
Clock generating circuit
Watchdog timer
Reset
A-D
converter
(10)
I/O port P3 I/O port P2 I/O port P1 I/O port P0
Key-on wake up
Timer 1 (8)
Timer 2 (8)
Timer X (8)
Prescaler 12 (8)
Prescaler X (8)
Reset input
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL BLOCK DIAGRAM (Package: 32P6U-A)
Fig. 5 Functional block diagram (32P6U-A package type)
5
PRELIMINARY
Timer 1 (8)
Timer 2 (8)
Timer X (8)
Prescaler 12 (8)
Prescaler X (8)
X
IN OUT
X
R A M
R O M
C P U
A
X
Y
S
PC
H
PC
L
PS
V
SS
21
RESET
16
VCC
18
17
CNVSS
CNTR0
P1(7)
P2(8)
P3(8)
19 20
VREF
0
INT0
USBVREFOUT
INT1
P4(2)
SI/O1(8)
USB(LS)
SI/O2(8)
Clock generating circuit
Watchdog timer
Reset
A-D
converter
(10)
I/O port P3 I/O port P2 I/O port P1 I/O port P0
I/O port P4
Key-on wakeup
Clock input
Clock output
Reset input
13
14 15
2427 25 23262829 22
857412 1011 9
30
3141242 3940
P0(8)
38 36 34 3237 35 33 31
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 6 Functional block diagram (42P4B package type)
6
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PIN DESCRIPTION
Table 1 Pin description
Pin
Vcc, Vss
REF
V
USBVREFOUT
CNVss
RESET
XIN
XOUT
P00–P07
P10/RxD/D-
1/TxD/D+
P1
2/SCLK
P1
P13/SDATA
P14/CNTR0
P15, P16
P20/AN0–
P2
7/AN7
P30–P35
P36/INT1
P37/INT0
P40, P41
Name
Power source
Analog reference
voltage
USB reference
voltage output
CNVss
Reset input
Clock input
Clock output
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Function
•Apply voltage of 4.1 to 5.5 V to Vcc, and 0 V to Vss.
•Reference voltage input pin for A-D converter
•Output pin for pulling up a D- line with 1.5 kΩ external resistor
•Chip operating mode control pin, which is always connected to Vss.
•Reset input pin for active “L”
•Input and output pins for main clock generating circuit
•Connect a ceramic resonator or quartz crystal oscillator between the X
•If an external clock is used, connect the clock source to the X
•8-bit I/O port.
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level
•CMOS 3-state output structure
•Whether a built-in pull-up resistor is to be used or not can be
determined by program.
•7-bit I/O port
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level
•CMOS 3-state output structure
•CMOS/TTL level can be switched for P1
•When using the USB function, input level of ports P1
P1
1 becomes USB input level, and output level of them
0, P12, P13.
0 and
becomes USB output level.
•8-bit I/O port having almost the same function as P0
•CMOS compatible input level
•CMOS 3-state output structure
•8-bit I/O port
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level (CMOS/TTL level can be switched for P3
•CMOS 3-state output structure
0 to P36 can output a large current for driving LED.
•P3
•Whether a built-in pull-up resistor is to be used or not can be
determined by program.
•2-bit I/O port
•I/O direction register allows each pin to be individually programmed as either input or output.
Function expect a port function
IN and XOUT pins.
IN pin and leave the XOUT pin open.
•Key-input (key-on wake up
interrupt input) pins
•Serial I/O1 function pin
•Serial I/O2 function pin
•Timer X function pin
•Input pins for A-D converter
6, P37).
•Interrupt input pins
7
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Mitsubishi plans to expand the 7534 group as follow:
Memory type
Support for Mask ROM version, One Time PROM version, and Emulator MCU .
Memory size
ROM/PROM size ..................................................8 K to 16 K bytes
RAM size................................................................256 to 384 bytes
ROM size
(Byte)
16K
8K
Package
36P2R-A .....................................0.8 mm-pitch plastic molded SOP
32P6U-A ................................... 0.8 mm-pitch plastic molded LQFP
42P4B ................................................... 42 pin plastic molded SDIP
42SIM...................................... 42 pin shrink ceramic PIGGY BACK
M37534E8
M37534M4
0
Fig. 7 Memory expansion plan
Currently supported products are listed below.
Table 2 List of supported products
Product
M37534M4-XXXFP
M37534M4-XXXGP
M37534M4-XXXSP
M37534E8FP
M37534E8SP
M37534RSS
8
(P) ROM size (bytes)
ROM size for User ()
8192 (8062)
8192 (8062)
8192 (8062)
16384 (16254)
16384 (16254)
128
RAM size
(bytes)
256
256
256
384
384
384
256 384
Package
36P2R-A
32P6U-A
42P4B
36P2R-A
42P4B
42S1M
Mask ROM version
Mask ROM version
Mask ROM version
One Time PROM version (blank)
One Time PROM version (blank)
Emulator MCU
RAM size
(Byte)
Remarks
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The 7534 Group uses the standard 740 family instruction set. Refer
to the table of 740 family addressing modes and machine-language
instructions or the 740 Family Software Manual for details on each
instruction set.
Machine-resident 740 family instructions are as follows:
1. The FST and SLW instructions cannot be used.
2. The MUL and DIV instructions cannot be used.
3. The WIT instruction can be used.
4. The STP instruction can be used.
b7 b0
CPU mode register
(CPUM: address 003B
Processor mode bits
b1 b0
0 0 Single-chip mode
0 1
1 0
1 1
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (returns “0” when read)
(Do not write “1” to these bits )
[CPU Mode Register] CPUM
The CPU mode register contains the stack page selection bit.
This register is allocated at address 003B
16
)
Not available
16.
Main clock division ratio selection bits
b7 b6
0 0 : f(φ) = f(X
0 1 : f(φ) = f(X
1 0 : applied from ring oscillator
1 1 : f(φ) = f(X
Fig. 8 Structure of CPU mode register
Switching method of CPU mode register
Switch the CPU mode register (CPUM) at the head of program after
releasing Reset in the following method.
After releasing reset
Wait until establish ceramic oscillator
clock.
Switch the clock division ratio
selection bits (bits 6 and 7 of CPUM)
Main routine
Note. After releasing reset the operation starts by starting a ring oscillator automatically.
Do not use a ring oscillator at ordinary operation.
Fig. 9 Switching method of CPU mode register
IN
)/2 (High-speed mode)
IN
)/8 (Middle-speed mode)
IN
) (Double-speed mode)
Start with a built-in ring oscillator (Note)
Switch to other mode except a ring oscillator
(Select one of 1/1, 1/2, and 1/8)
9
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Memory
Special function register (SFR) area
The SFR area in the zero page contains control registers such as I/O
ports and timers.
RAM
RAM is used for data storage and for a stack area of subroutine calls
and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is a user area for storing programs.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
RAM
RAM area
RAM capacity
(bytes)
256
384
address
XXXX
013F
01BF
16
16
16
Zero page
The 256 bytes from addresses 0000
16 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
Special page
The 256 bytes from addresses FF00
16 to FFFF16 are called the spe-
cial page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
0000
16
0040
0100
XXXX
0440
YYYY
ZZZZ
SFR area
16
16
16
Reserved area
16
Not used
16
Reserved ROM area
(128 bytes)
16
Zero page
ROM area
ROM capacity
(bytes)
8192
16384
Fig. 10 Memory map diagram
10
address
YYYY
E000
C000
ROM
FF00
16
address
16
16
16
ZZZZ
E080
C080
16
16
16
FFEC
FFFE
FFFF
16
Interrupt vector area
16
Reserved ROM area
16
Special page
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port P0 (P0)
0000
16
Port P0 direction register (P0D)
0001
16
Port P1 (P1)
0002
16
Port P1 direction register (P1D)
0003
16
Port P2 (P2)
0004
16
Port P2 direction register (P2D)
0005
16
Port P3 (P3)
0006
16
Port P3 direction register (P3D)
0007
16
Port P4 (P4)
0008
16
Port P4 direction register (P4D)
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
Pull-up control register (PULL)
0016
16
Port P1P3 control register (P1P3C)
0017
16
Transmit/Receive buffer register (TB/RB)
0018
16
USB status register (USBSTS)/UART status register (UARTSTS)
0019
16
Serial I/O1 control register (SIO1CON)
001A
16
UART control register (UARTCON)
001B
16
Baud rate generator (BRG)
001C
16
USB data toggle synchronization register ( TRSYNC)
001D
16
USB interrupt source discrimination register 1 (USBIR1)
001E
16
USB interrupt source discrimination register 2 (USBIR2)
001F
16
USB interrupt control register (USBICON)
0020
16
USB transmit data byte number set register 0 (EP0BYTE)
0021
16
USB transmit data byte number set register 1 (EP1BYTE)
0022
16
USBPID control register 0 (EP0PID)
0023
16
USBPID control register 1 (EP1PID)
0024
16
USB address register (USBA)
0025
16
USB sequence bit initialization register (INISQ1)
0026
16
0027
16
USB control register (USBCON)
Prescaler 12 (PRE12)
0028
16
Timer 1 (T1)
0029
16
Timer 2 (T2)
002A
16
Timer X mode register
002B
16
Prescaler X
002C
16
(TX)
Timer X
002D
16
Timer count source set register (TCSS)
002E
16
002F
16
Serial I/O2 control register (SIO2CON)
0030
16
Serial I/O2 register (SIO2)
0031
16
0032
16
0033
16
A-D control register (ADCON)
0034
16
A-D conversion register (low-order) (ADL)
0035
16
A-D conversion register (high-order) (ADH)
0036
16
0037
16
MISRG
0038
16
Watchdog timer control register (WDTCON)
0039
16
Interrupt edge selection register
003A
16
CPU mode register (CPUM)
003B
16
Interrupt request register 1 (IREQ1)
003C
16
003D
16
Interrupt control register 1 (ICON1)
003E
16
003F
16
(PREX)
(TM)
(INTEDGE)
Fig. 11 Memory map of special function register (SFR)
11
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O Ports
[Direction registers] PiD
The I/O ports have direction registers which determine the input/output direction of each pin. Each bit in a direction register corresponds
to one pin, and each pin can be set to be input or output.
When “1” is set to the bit corresponding to a pin, this pin becomes an
output port. When “0” is set to the bit, the pin becomes an input port.
When data is read from a pin set to output, not the value of the pin
itself but the value of port latch is read. Pins set to input are floating,
and permit reading pin values.
If a pin set to input is written to, only the port latch is written to and the
pin remains floating.
b7 b0
[Pull-up control] PULL
By setting the pull-up control register (address 0016
P3 can exert pull-up control by program. However, pins set to output
are disconnected from this control and cannot exert pull-up control.
[Port P1P3 control] P1P3C
By setting the port P1P3 control register (address 0017
input level or a TTL input level can be selected for ports P1
P13, P36 and P37 by program.
Then, as for the 36-pin version, set “1” to each bit 6 of the port P3
direction register and port P3 register.
As for the 32-pin version, set “1” to respective bits 5, 6, 7 of the port
P3 direction register and port P3 register.
Pull-up control register
(PULL: address 0016
16
)
16), ports P0 and
16), a CMOS
0, P12,
P00 pull-up control bit
1
pull-up control bit
P0
P0
2
, P03 pull-up control bit
4
– P07 pull-up control bit
P0
P3
0
– P33 pull-up control bit
Note : Pins set to output ports are disconnected from pull-up control.
Fig. 12 Structure of pull-up control register
b7 b0
4
pull-up control bit
P3
P3
5
, P36 pull-up control bit
P3
7
pull-up control bit
Port P1P3 control register
(P1P3C: address 0017
P37/INT0 input level selection bit
0 : CMOS level
1 : TTL level
P3
6
/INT1 input level selection bit
0 : CMOS level
1 : TTL leve
P1
0
,P12,P13 input level selection bit
0 : CMOS level
1 : TTL level
Not used
16
)
0: Pull-up off
1: Pull-up on
Initial value: FF
16
Fig. 13 Structure of port P1P3 control register
12
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 3 I/O port function table
Pin
0–P07
P0
P10/RxD/D-
1/TxD/D+
P1
2/SCLK
P1
P13/SDATA
P14/CNTR0
P15, P16
P20/AN0–
P2
7/AN7
P30–P35
P36/INT1
P37/INT0
P40, P41
Note: Port P10, P12, P13, P36, P37 is CMOS/TTL level.
Name
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
Input/output
I/O individual
bits
•CMOS compatible input level
•CMOS 3-state output
•USB input/output level when
selecting USB function
•CMOS compatible input level
•CMOS 3-state output
(Note)
I/O format
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Non-port function
Key input interrupt
Serial I/O1 function
input/output
Serial I/O2 function
input/output
Timer X function input/output
A-D conversion input
External interrupt input
Related SFRs
Pull-up control register
Serial I/O1 control
register
Serial I/O2 control
register
Timer X mode register
A-D control register
Interrupt edge selection
register
Diagram No.
(1)
(2)
(3)
(4)
(5)
(6)
(10)
(7)
(8)
(9)
(10)
13
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Port P0
Pull-up control
Direction
register
Data bus
(3) Port P1
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
Data bus
Port latch
To key input interrupt
1
P-channel output disable bit
Transmit enable bit
Direction
register
Port latch
generating circuit
(2) Port P1
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
Data bus
0
Receive enable bit
Direction
register
Port latch
+
Serial I/O1 input
D- input
D- output
USB output enable
(internal signal)
USB differential input
0
,P12,P13 input
P1
level selection bit
*
Serial I/O1 output
(4) Port P1
Data bus
2
CLK
pin selection bit
S
Direction
register
Port latch
Serial I/O2 clock output
Serial I/O2 clock input
: P1
0
, P12, P13, P36, P37 input levels are switched to the CMOS/TTL level by the port P1P3 control register.
*
When the TTL level is selected, there is no hysteresis characteristics.
Fig. 14 Block diagram of ports (1)
D+ input
D+ output
USB output enable
(internal signal)
P1
0
,P12,P13 input
level selection bit
(5) Port P1
Data bus
*
3
Signals during the
DATA
output action
S
S
DATA
pin selection bit
Serial I/O2 clock output
Direction
register
Port latch
Serial I/O2 clock input
DATA
pin
S
selection bit
P1
0
,P12,P13 input
level selection bit
*
14
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(6) Port P1
4
Data bus
Pulse output mode
(8) Ports P30 – P3
Data bus
Direction
register
Port latch
Timer output
5
Pull-up
Direction
register
Port latch
CNTR
0
interrupt input
control
(7) Ports P20 – P2
Data bus
(9) Port P36, P3
Data bus
7
7
Direction
register
Port latch
A-D conversion input
Pull-up
Direction
register
Port latch
Analog input pin selection bit
control
P3
7
/INT0 input
level selection bit
(10) Ports P1
Data bus
5, P16
, P4
0, P41
Direction
register
Port latch
Fig. 15 Block diagram of ports (2)
INT
interrupt input
*
: P1
0
, P12, P13, P36, P37 input levels are switched to the CMOS/TTL level by the port P1P3 control register.
*
When the TTL level is selected, there is no hysteresis characteristics.
15
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupts
Interrupts occur by 14 different sources : 4 external sources, 9 internal sources and 1 software source.
Interrupt control
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit, and they are controlled by the
interrupt disable flag. When the interrupt enable bit and the interrupt
request bit are set to “1” and the interrupt disable flag is set to “0”, an
interrupt is accepted.
The interrupt request bit can be cleared by program but not be set.
The interrupt enable bit can be set and cleared by program.
It becomes usable by switching CNTR
with bit 7 of the interrupt edge selection register, timer 2 and serial I/
O2 interrupt sources with bit 6, timer X and key-on wake-up interrupt
sources with bit 5, and serial I/O transmit and INT
with bit 4.
The reset and BRK instruction interrupt can never be disabled with
any flag or bit. All interrupts except these are disabled when the interrupt disable flag is set.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Table 6 Interrupt vector address and priority
Interrupt source
Reset (Note 2)
UART receive
Priority
1
2
USB IN token
UART transmit
USB SETUP/OUT token
Reset/Suspend/Resume
3
INT1
INT0
Timer X
4
5
Key-on wake-up
Timer 1
Timer 2
6
7
Serial I/O2
0
CNTR
8
A-D conversion
BRK instruction
9
Note 1: Vector addressed contain internal jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
0 and A-D interrupt sources
1 interrupt sources
Vector addresses (Note 1)
High-order
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
Low-order
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
Interrupt request generating conditions
At reset input
At completion of UART data receive
At detection of IN token
At completion of UART transmit shift or
when transmit buffer is empty
At detection of SETUP/OUT token or
At detection of Reset/ Suspend/ Resume
At detection of either rising or falling edge
1 input
of INT
At detection of either rising or falling edge
0 input
of INT
At timer X underflow
At falling of conjunction of input logical
level for port P0 (at input)
At timer 1 underflow
At timer 2 underflow
At completion of transmit/receive shift
At detection of either rising or falling edge
of CNTR
At completion of A-D conversion
At BRK instruction execution
Interrupt operation
Upon acceptance of an interrupt the following operations are automatically performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status register are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. Concurrently with the push operation, the interrupt destination
address is read from the vector table into the program counter.
Notes on use
When the active edge of an external interrupt (INT
0, INT1, CNTR0) is
set, the interrupt request bit may be set.
Therefore, please take following sequence:
1. Disable the external interrupt which is selected.
2. Change the active edge in interrupt edge selection register. (in
case of CNTR
0: Timer X mode register)
3. Clear the set interrupt request bit to “0”.
4. Enable the external interrupt which is selected.
Remarks
Non-maskable
Valid in UART mode
Valid in USB mode
Valid in UART mode
Valid in USB mode
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (valid at falling)
STP release timer underflow
External interrupt (active edge
0 input
selectable)
Non-maskable software interrupt
16
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