PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 7534 Group is the 8-bit microcomputer based on the 740 family
core technology.
The 7534 Group has a USB, 8-bit timers, and an A-D converter, and
is useful for an input device for personal computer peripherals.
FEATURES
Basic machine-language instructions....................................... 69
•
The minimum instruction execution time .......................... 0.34 µs
•
•
•
•
•
(at 6 MHz oscillation frequency for the shortest instruction)
Memory size
ROM ............................................... 8K to 16K bytes
RAM ..............................................256 to 384 bytes
Programmable I/O ports ...................................... 28 (36-pin type)
............................................................................ 24 (32-pin type)
............................................................................ 33 (42-pin type)
Interrupts .................................................... 14 sources, 8 vectors
Timers ............................................................................ 8-bit ✕ 3
PIN CONFIGURATION (TOP VIEW)
P1
2/SCLK
P13/S
DATA
P14/CNTR
P20/AN
P21/AN
P22/AN
P23/AN
P24/AN
P25/AN
6
/AN
P2
P27/AN
V
REF
RESET
CNV
Vcc
X
X
OUT
V
0
0
1
2
3
4
5
6
7
SS
IN
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Serial I/O1 ................................ used only for Low Speed in USB
•
Serial I/O2 ...................................................................... 8-bit ✕ 1
•
A-D converter ................................................ 10-bit ✕ 8 channels
•
Clock generating circuit ............................................. Built-in type
•
(connect to external ceramic resonator or quartz-crystal oscillator )
Watchdog timer ............................................................ 16-bit ✕ 1
•
Power source voltage
•
At 6 MHz X
................................4.1 to 5.5 V(4.4 to 5.25 V at USB operation)
Power dissipation ............................................ 30 mW (standard)
•
Operating temperature range................................... –20 to 85 °C
•
Built-in USB 3.3 V Regulator + transceiver based on USB Spec.
•
Rev.1.1
IN oscillation frequency at ceramic resonator
APPLICATION
Input device for personal computer peripherals
36
35
34
M37534M4-XXXFP
M37534E8FP
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
P11/TXD/D+
P10/RXD/DP0
P0
P0
P0
P0
P0
P0
P0
USBV
P3
P35(LED5)
P3
P3
P3
P31(LED1)
P30(LED0)
(based on USBSpec. Rev.1.1)
(USB/UART)
(Clock-synchronized)
(0 to 70 °C at USB operation)
7
6
5
4
3
2
1
0
REFOUT
7
/INT
0
4
(LED4)
3
(LED3)
2
(LED2)
Package type: 36P2R-A
Fig. 1 Pin configuration of M37534M4-XXXFP, M37534E8FP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PIN CONFIGURATION (TOP VIEW)
6
P0
5
P0
4
P0
3
P0
2
P0
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
REFOUT
0
1
P0
P0
USBV
P0
P10/RXD/D-
P1
1/TX
D/D+
P1
2/SCLK
P13/S
DATA
P14/CNTR
P20/
AN
P21/
AN
23
2
3
/AN
3
P2
22
3
4
/AN
4
P2
24
7
0
0
1
25
26
27
28
M37534M4-XXXGP
29
30
31
32
1
2
/AN
2
P2
21
4
5
/AN
5
P2
20
19
6
5
REF
V
RESET
18
17
7
8
SS
CNV
CC
V
16
15
14
13
12
11
10
P34(LED4)
P3
3
(LED3)
P3
2
(LED2)
1
(LED1)
P3
P3
0
(LED0)
V
SS
X
OUT
9
X
IN
Fig. 2 Pin configuration of M37534M4-XXXGP
2
Outline 32P6U-A
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PIN CONFIGURATION (TOP VIEW)
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
P14/CNTR
P1
P1
P20/AN
1
/AN
P2
NC
P22/AN
3
/AN
P2
P24/AN
P25/AN
P26/AN
P27/AN
P4
P4
REF
V
RESET
CNV
Vcc
X
X
OUT
V
SS
IN
SS
0
5
6
0
1
2
3
4
5
6
7
0
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
M37534RSS
M37534M4-XXXSP
M37534E8SP
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P13/S
P12/S
P1
1/TX
DATA
CLK
D/D+
P10/RXD/DP0
7
P0
6
P0
5
P0
4
P0
3
P0
2
P0
1
P0
0
USBV
P37/INT
REFOUT
0
P36(LED6)/INT
P35(LED5)
P3
4
(LED4)
3
(LED3)
P3
P3
2
(LED2)
P31(LED1)
P30(LED0)
1
Outline 42S1M, 42P4B
Fig. 3 Pin configuration of M37534RSS, M37534M4-XXXSP, M37534E8SP
3
PRELIMINARY
SI/O1(8)
USB(LS)
R A M
R O M
C P U
A
X
Y
S
PC
H
PCL
PS
V
SS
18
RESET
13
VCC
15
14
CNVSS
CNTR0
P0(8)
34
32 30 28
33
31 29 27
P1(5)
3135236
7
56
4
P2(8)
P3(7)
12
16 17
11
9
10
8
VREF
0
26
INT
0
2023 21 1922
2425
SI/O2(8)
USBVREFOUT
XIN
XOUT
Clock input
Clock output
Clock generating circuit
Watchdog timer
Reset
A-D
converter
(10)
I/O port P3 I/O port P2 I/O port P1 I/O port P0
Key-on wake up
Timer 1 (8)
Timer 2 (8)
Timer X (8)
Prescaler 12 (8)
Prescaler X (8)
Reset input
Notice: This is not a final specification.
Some parametric limits are subject to change.
FUNCTIONAL BLOCK
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL BLOCK DIAGRAM (Package: 36P2R)
Fig. 4 Functional block diagram (36P2R package type)
4
PRELIMINARY
SI/O1(8)
USB(LS)
R A M
R O M
C P U
A
X
Y
S
PC
H
PC
L
PS
V
SS
11
RESET
6
V
CC
8
7
CNV
SS
CNTR
0
P0(8)
25
23 21 19
24
22 20 18
P1(5)
30 28 2629 27
32 31
P2(6)
P3(5)
5
910
4
2
3
1
V
REF
0
17
1316 14 1215
SI/O2(8)
USBV
REFOUT
X
IN
X
OUT
Clock input
Clock output
Clock generating circuit
Watchdog timer
Reset
A-D
converter
(10)
I/O port P3 I/O port P2 I/O port P1 I/O port P0
Key-on wake up
Timer 1 (8)
Timer 2 (8)
Timer X (8)
Prescaler 12 (8)
Prescaler X (8)
Reset input
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL BLOCK DIAGRAM (Package: 32P6U-A)
Fig. 5 Functional block diagram (32P6U-A package type)
5
PRELIMINARY
Timer 1 (8)
Timer 2 (8)
Timer X (8)
Prescaler 12 (8)
Prescaler X (8)
X
IN OUT
X
R A M
R O M
C P U
A
X
Y
S
PC
H
PC
L
PS
V
SS
21
RESET
16
VCC
18
17
CNVSS
CNTR0
P1(7)
P2(8)
P3(8)
19 20
VREF
0
INT0
USBVREFOUT
INT1
P4(2)
SI/O1(8)
USB(LS)
SI/O2(8)
Clock generating circuit
Watchdog timer
Reset
A-D
converter
(10)
I/O port P3 I/O port P2 I/O port P1 I/O port P0
I/O port P4
Key-on wakeup
Clock input
Clock output
Reset input
13
14 15
2427 25 23262829 22
857412 1011 9
30
3141242 3940
P0(8)
38 36 34 3237 35 33 31
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 6 Functional block diagram (42P4B package type)
6
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PIN DESCRIPTION
Table 1 Pin description
Pin
Vcc, Vss
REF
V
USBVREFOUT
CNVss
RESET
XIN
XOUT
P00–P07
P10/RxD/D-
1/TxD/D+
P1
2/SCLK
P1
P13/SDATA
P14/CNTR0
P15, P16
P20/AN0–
P2
7/AN7
P30–P35
P36/INT1
P37/INT0
P40, P41
Name
Power source
Analog reference
voltage
USB reference
voltage output
CNVss
Reset input
Clock input
Clock output
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Function
•Apply voltage of 4.1 to 5.5 V to Vcc, and 0 V to Vss.
•Reference voltage input pin for A-D converter
•Output pin for pulling up a D- line with 1.5 kΩ external resistor
•Chip operating mode control pin, which is always connected to Vss.
•Reset input pin for active “L”
•Input and output pins for main clock generating circuit
•Connect a ceramic resonator or quartz crystal oscillator between the X
•If an external clock is used, connect the clock source to the X
•8-bit I/O port.
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level
•CMOS 3-state output structure
•Whether a built-in pull-up resistor is to be used or not can be
determined by program.
•7-bit I/O port
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level
•CMOS 3-state output structure
•CMOS/TTL level can be switched for P1
•When using the USB function, input level of ports P1
P1
1 becomes USB input level, and output level of them
0, P12, P13.
0 and
becomes USB output level.
•8-bit I/O port having almost the same function as P0
•CMOS compatible input level
•CMOS 3-state output structure
•8-bit I/O port
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level (CMOS/TTL level can be switched for P3
•CMOS 3-state output structure
0 to P36 can output a large current for driving LED.
•P3
•Whether a built-in pull-up resistor is to be used or not can be
determined by program.
•2-bit I/O port
•I/O direction register allows each pin to be individually programmed as either input or output.
Function expect a port function
IN and XOUT pins.
IN pin and leave the XOUT pin open.
•Key-input (key-on wake up
interrupt input) pins
•Serial I/O1 function pin
•Serial I/O2 function pin
•Timer X function pin
•Input pins for A-D converter
6, P37).
•Interrupt input pins
7
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Mitsubishi plans to expand the 7534 group as follow:
Memory type
Support for Mask ROM version, One Time PROM version, and Emulator MCU .
Memory size
ROM/PROM size ..................................................8 K to 16 K bytes
RAM size................................................................256 to 384 bytes
ROM size
(Byte)
16K
8K
Package
36P2R-A .....................................0.8 mm-pitch plastic molded SOP
32P6U-A ................................... 0.8 mm-pitch plastic molded LQFP
42P4B ................................................... 42 pin plastic molded SDIP
42SIM...................................... 42 pin shrink ceramic PIGGY BACK
M37534E8
M37534M4
0
Fig. 7 Memory expansion plan
Currently supported products are listed below.
Table 2 List of supported products
Product
M37534M4-XXXFP
M37534M4-XXXGP
M37534M4-XXXSP
M37534E8FP
M37534E8SP
M37534RSS
8
(P) ROM size (bytes)
ROM size for User ()
8192 (8062)
8192 (8062)
8192 (8062)
16384 (16254)
16384 (16254)
128
RAM size
(bytes)
256
256
256
384
384
384
256 384
Package
36P2R-A
32P6U-A
42P4B
36P2R-A
42P4B
42S1M
Mask ROM version
Mask ROM version
Mask ROM version
One Time PROM version (blank)
One Time PROM version (blank)
Emulator MCU
RAM size
(Byte)
Remarks
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The 7534 Group uses the standard 740 family instruction set. Refer
to the table of 740 family addressing modes and machine-language
instructions or the 740 Family Software Manual for details on each
instruction set.
Machine-resident 740 family instructions are as follows:
1. The FST and SLW instructions cannot be used.
2. The MUL and DIV instructions cannot be used.
3. The WIT instruction can be used.
4. The STP instruction can be used.
b7 b0
CPU mode register
(CPUM: address 003B
Processor mode bits
b1 b0
0 0 Single-chip mode
0 1
1 0
1 1
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (returns “0” when read)
(Do not write “1” to these bits )
[CPU Mode Register] CPUM
The CPU mode register contains the stack page selection bit.
This register is allocated at address 003B
16
)
Not available
16.
Main clock division ratio selection bits
b7 b6
0 0 : f(φ) = f(X
0 1 : f(φ) = f(X
1 0 : applied from ring oscillator
1 1 : f(φ) = f(X
Fig. 8 Structure of CPU mode register
Switching method of CPU mode register
Switch the CPU mode register (CPUM) at the head of program after
releasing Reset in the following method.
After releasing reset
Wait until establish ceramic oscillator
clock.
Switch the clock division ratio
selection bits (bits 6 and 7 of CPUM)
Main routine
Note. After releasing reset the operation starts by starting a ring oscillator automatically.
Do not use a ring oscillator at ordinary operation.
Fig. 9 Switching method of CPU mode register
IN
)/2 (High-speed mode)
IN
)/8 (Middle-speed mode)
IN
) (Double-speed mode)
Start with a built-in ring oscillator (Note)
Switch to other mode except a ring oscillator
(Select one of 1/1, 1/2, and 1/8)
9
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Memory
Special function register (SFR) area
The SFR area in the zero page contains control registers such as I/O
ports and timers.
RAM
RAM is used for data storage and for a stack area of subroutine calls
and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is a user area for storing programs.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
RAM
RAM area
RAM capacity
(bytes)
256
384
address
XXXX
013F
01BF
16
16
16
Zero page
The 256 bytes from addresses 0000
16 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
Special page
The 256 bytes from addresses FF00
16 to FFFF16 are called the spe-
cial page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
0000
16
0040
0100
XXXX
0440
YYYY
ZZZZ
SFR area
16
16
16
Reserved area
16
Not used
16
Reserved ROM area
(128 bytes)
16
Zero page
ROM area
ROM capacity
(bytes)
8192
16384
Fig. 10 Memory map diagram
10
address
YYYY
E000
C000
ROM
FF00
16
address
16
16
16
ZZZZ
E080
C080
16
16
16
FFEC
FFFE
FFFF
16
Interrupt vector area
16
Reserved ROM area
16
Special page
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port P0 (P0)
0000
16
Port P0 direction register (P0D)
0001
16
Port P1 (P1)
0002
16
Port P1 direction register (P1D)
0003
16
Port P2 (P2)
0004
16
Port P2 direction register (P2D)
0005
16
Port P3 (P3)
0006
16
Port P3 direction register (P3D)
0007
16
Port P4 (P4)
0008
16
Port P4 direction register (P4D)
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
Pull-up control register (PULL)
0016
16
Port P1P3 control register (P1P3C)
0017
16
Transmit/Receive buffer register (TB/RB)
0018
16
USB status register (USBSTS)/UART status register (UARTSTS)
0019
16
Serial I/O1 control register (SIO1CON)
001A
16
UART control register (UARTCON)
001B
16
Baud rate generator (BRG)
001C
16
USB data toggle synchronization register ( TRSYNC)
001D
16
USB interrupt source discrimination register 1 (USBIR1)
001E
16
USB interrupt source discrimination register 2 (USBIR2)
001F
16
USB interrupt control register (USBICON)
0020
16
USB transmit data byte number set register 0 (EP0BYTE)
0021
16
USB transmit data byte number set register 1 (EP1BYTE)
0022
16
USBPID control register 0 (EP0PID)
0023
16
USBPID control register 1 (EP1PID)
0024
16
USB address register (USBA)
0025
16
USB sequence bit initialization register (INISQ1)
0026
16
0027
16
USB control register (USBCON)
Prescaler 12 (PRE12)
0028
16
Timer 1 (T1)
0029
16
Timer 2 (T2)
002A
16
Timer X mode register
002B
16
Prescaler X
002C
16
(TX)
Timer X
002D
16
Timer count source set register (TCSS)
002E
16
002F
16
Serial I/O2 control register (SIO2CON)
0030
16
Serial I/O2 register (SIO2)
0031
16
0032
16
0033
16
A-D control register (ADCON)
0034
16
A-D conversion register (low-order) (ADL)
0035
16
A-D conversion register (high-order) (ADH)
0036
16
0037
16
MISRG
0038
16
Watchdog timer control register (WDTCON)
0039
16
Interrupt edge selection register
003A
16
CPU mode register (CPUM)
003B
16
Interrupt request register 1 (IREQ1)
003C
16
003D
16
Interrupt control register 1 (ICON1)
003E
16
003F
16
(PREX)
(TM)
(INTEDGE)
Fig. 11 Memory map of special function register (SFR)
11
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O Ports
[Direction registers] PiD
The I/O ports have direction registers which determine the input/output direction of each pin. Each bit in a direction register corresponds
to one pin, and each pin can be set to be input or output.
When “1” is set to the bit corresponding to a pin, this pin becomes an
output port. When “0” is set to the bit, the pin becomes an input port.
When data is read from a pin set to output, not the value of the pin
itself but the value of port latch is read. Pins set to input are floating,
and permit reading pin values.
If a pin set to input is written to, only the port latch is written to and the
pin remains floating.
b7 b0
[Pull-up control] PULL
By setting the pull-up control register (address 0016
P3 can exert pull-up control by program. However, pins set to output
are disconnected from this control and cannot exert pull-up control.
[Port P1P3 control] P1P3C
By setting the port P1P3 control register (address 0017
input level or a TTL input level can be selected for ports P1
P13, P36 and P37 by program.
Then, as for the 36-pin version, set “1” to each bit 6 of the port P3
direction register and port P3 register.
As for the 32-pin version, set “1” to respective bits 5, 6, 7 of the port
P3 direction register and port P3 register.
Pull-up control register
(PULL: address 0016
16
)
16), ports P0 and
16), a CMOS
0, P12,
P00 pull-up control bit
1
pull-up control bit
P0
P0
2
, P03 pull-up control bit
4
– P07 pull-up control bit
P0
P3
0
– P33 pull-up control bit
Note : Pins set to output ports are disconnected from pull-up control.
Fig. 12 Structure of pull-up control register
b7 b0
4
pull-up control bit
P3
P3
5
, P36 pull-up control bit
P3
7
pull-up control bit
Port P1P3 control register
(P1P3C: address 0017
P37/INT0 input level selection bit
0 : CMOS level
1 : TTL level
P3
6
/INT1 input level selection bit
0 : CMOS level
1 : TTL leve
P1
0
,P12,P13 input level selection bit
0 : CMOS level
1 : TTL level
Not used
16
)
0: Pull-up off
1: Pull-up on
Initial value: FF
16
Fig. 13 Structure of port P1P3 control register
12
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 3 I/O port function table
Pin
0–P07
P0
P10/RxD/D-
1/TxD/D+
P1
2/SCLK
P1
P13/SDATA
P14/CNTR0
P15, P16
P20/AN0–
P2
7/AN7
P30–P35
P36/INT1
P37/INT0
P40, P41
Note: Port P10, P12, P13, P36, P37 is CMOS/TTL level.
Name
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
Input/output
I/O individual
bits
•CMOS compatible input level
•CMOS 3-state output
•USB input/output level when
selecting USB function
•CMOS compatible input level
•CMOS 3-state output
(Note)
I/O format
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Non-port function
Key input interrupt
Serial I/O1 function
input/output
Serial I/O2 function
input/output
Timer X function input/output
A-D conversion input
External interrupt input
Related SFRs
Pull-up control register
Serial I/O1 control
register
Serial I/O2 control
register
Timer X mode register
A-D control register
Interrupt edge selection
register
Diagram No.
(1)
(2)
(3)
(4)
(5)
(6)
(10)
(7)
(8)
(9)
(10)
13
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Port P0
Pull-up control
Direction
register
Data bus
(3) Port P1
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
Data bus
Port latch
To key input interrupt
1
P-channel output disable bit
Transmit enable bit
Direction
register
Port latch
generating circuit
(2) Port P1
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
Serial I/O1 mode selection bit (b7)
Serial I/O1 mode selection bit (b6)
Data bus
0
Receive enable bit
Direction
register
Port latch
+
Serial I/O1 input
D- input
D- output
USB output enable
(internal signal)
USB differential input
0
,P12,P13 input
P1
level selection bit
*
Serial I/O1 output
(4) Port P1
Data bus
2
CLK
pin selection bit
S
Direction
register
Port latch
Serial I/O2 clock output
Serial I/O2 clock input
: P1
0
, P12, P13, P36, P37 input levels are switched to the CMOS/TTL level by the port P1P3 control register.
*
When the TTL level is selected, there is no hysteresis characteristics.
Fig. 14 Block diagram of ports (1)
D+ input
D+ output
USB output enable
(internal signal)
P1
0
,P12,P13 input
level selection bit
(5) Port P1
Data bus
*
3
Signals during the
DATA
output action
S
S
DATA
pin selection bit
Serial I/O2 clock output
Direction
register
Port latch
Serial I/O2 clock input
DATA
pin
S
selection bit
P1
0
,P12,P13 input
level selection bit
*
14
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(6) Port P1
4
Data bus
Pulse output mode
(8) Ports P30 – P3
Data bus
Direction
register
Port latch
Timer output
5
Pull-up
Direction
register
Port latch
CNTR
0
interrupt input
control
(7) Ports P20 – P2
Data bus
(9) Port P36, P3
Data bus
7
7
Direction
register
Port latch
A-D conversion input
Pull-up
Direction
register
Port latch
Analog input pin selection bit
control
P3
7
/INT0 input
level selection bit
(10) Ports P1
Data bus
5, P16
, P4
0, P41
Direction
register
Port latch
Fig. 15 Block diagram of ports (2)
INT
interrupt input
*
: P1
0
, P12, P13, P36, P37 input levels are switched to the CMOS/TTL level by the port P1P3 control register.
*
When the TTL level is selected, there is no hysteresis characteristics.
15
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupts
Interrupts occur by 14 different sources : 4 external sources, 9 internal sources and 1 software source.
Interrupt control
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit, and they are controlled by the
interrupt disable flag. When the interrupt enable bit and the interrupt
request bit are set to “1” and the interrupt disable flag is set to “0”, an
interrupt is accepted.
The interrupt request bit can be cleared by program but not be set.
The interrupt enable bit can be set and cleared by program.
It becomes usable by switching CNTR
with bit 7 of the interrupt edge selection register, timer 2 and serial I/
O2 interrupt sources with bit 6, timer X and key-on wake-up interrupt
sources with bit 5, and serial I/O transmit and INT
with bit 4.
The reset and BRK instruction interrupt can never be disabled with
any flag or bit. All interrupts except these are disabled when the interrupt disable flag is set.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Table 6 Interrupt vector address and priority
Interrupt source
Reset (Note 2)
UART receive
Priority
1
2
USB IN token
UART transmit
USB SETUP/OUT token
Reset/Suspend/Resume
3
INT1
INT0
Timer X
4
5
Key-on wake-up
Timer 1
Timer 2
6
7
Serial I/O2
0
CNTR
8
A-D conversion
BRK instruction
9
Note 1: Vector addressed contain internal jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
0 and A-D interrupt sources
1 interrupt sources
Vector addresses (Note 1)
High-order
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
Low-order
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
Interrupt request generating conditions
At reset input
At completion of UART data receive
At detection of IN token
At completion of UART transmit shift or
when transmit buffer is empty
At detection of SETUP/OUT token or
At detection of Reset/ Suspend/ Resume
At detection of either rising or falling edge
1 input
of INT
At detection of either rising or falling edge
0 input
of INT
At timer X underflow
At falling of conjunction of input logical
level for port P0 (at input)
At timer 1 underflow
At timer 2 underflow
At completion of transmit/receive shift
At detection of either rising or falling edge
of CNTR
At completion of A-D conversion
At BRK instruction execution
Interrupt operation
Upon acceptance of an interrupt the following operations are automatically performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status register are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. Concurrently with the push operation, the interrupt destination
address is read from the vector table into the program counter.
Notes on use
When the active edge of an external interrupt (INT
0, INT1, CNTR0) is
set, the interrupt request bit may be set.
Therefore, please take following sequence:
1. Disable the external interrupt which is selected.
2. Change the active edge in interrupt edge selection register. (in
case of CNTR
0: Timer X mode register)
3. Clear the set interrupt request bit to “0”.
4. Enable the external interrupt which is selected.
Remarks
Non-maskable
Valid in UART mode
Valid in USB mode
Valid in UART mode
Valid in USB mode
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (valid at falling)
STP release timer underflow
External interrupt (active edge
0 input
selectable)
Non-maskable software interrupt
16
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 16 Interrupt control
b7 b0
BRK instruction
Interrupt edge selection register
(INTEDGE : address 003A
INT0 interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
INT
1
interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
Not used (returns “0” when read)
Serial I/O1 or INT
0 : Serial I/O1
1 : INT
1
Timer X or key-on wake up interrupt selection bit
0 : Timer X
1 : Key-on wake up
Timer 2 or serial I/O2 interrupt selection bit
0 : Timer 2
1 : Serial I/O2
CNTR
0
or AD converter interrupt selection bit
0 : CNTR
1 : AD converter
16
)
1
interrupt selection bit
0
Interrupt request
Reset
b7 b0
b7 b0
Interrupt request register 1
(IREQ1 : address 003C
UART receive/USB IN token interrupt request bit
UART transmit/USB SETUP/OUT token/ Reset/Suspend/Resume/INT interrupt request bit
0
interrupt request bit
INT
Timer X or key-on wake up interrupt request bit
Timer 1 interrupt request bit
Timer 2 or serial I/O2 interrupt request bit
CNTR
0
or AD converter interrupt request bit
Not used (returns “0” when read)
Interrupt control register 1
(ICON1 : address 003E
UART receive/USB IN token interrupt enable bit
UART transmit/USB SETUP/OUT token/ Reset/Suspend/Resume/INT interrupt enable bit
0
interrupt enable bit
INT
Timer X or key-on wake up interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 or serial I/O2 interrupt enable bit
CNTR
0
or AD converter interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
16
)
16
)
Fig. 17 Structure of Interrupt-related registers
1
0 : No interrupt request issued
1 : Interrupt request issued
1
0 : Interrupts disabled
1 : Interrupts enabled
17
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Key Input Interrupt (Key-On Wake-Up)
A key-on wake-up interrupt request is generated by applying “L” level
to any pin of port P0 that has been set to input mode.
In other words, it is generated when the AND of input level goes from
“1” to “0”. An example of using a key input interrupt is shown in Figure 18, where an interrupt request is generated by pressing one of
the keys provided as an active-low key matrix which uses ports P0
to P03 as input ports.
Port PXx
“L” level output
PULL register
bit 3 = “0”
***
Port P0
P07 output
latch
0
7
Port P0
Direction register = “1”
7
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Key input interrupt request
Falling edge
detection
P0
P0
P0
P0
P0
P0
P0
6 output
5 output
4 output
3 input
2 input
1 input
0 input
PULL register
bit 3 = “0”
***
PULL register
bit 3 = “0”
***
PULL register
bit 3 = “0”
***
PULL register
bit 2 = “1”
***
PULL register
bit 2 = “1”
***
PULL register
bit 1 = “1”
***
PULL register
bit 0 = “1”
***
Port P0
Direction register = “1”
6
Port P0
latch
Port P0
Direction register = “1”
5
Port P0
latch
Port P0
Direction register = “1”
4
Port P0
latch
Port P0
Direction register = “0”
Port P0
3
latch
Port P0
Direction register = “0”
Port P0
2
latch
Port P0
Direction register = “0”
Port P0
1
latch
Port P0
Direction register = “0”
Port P0
0
latch
6
5
4
3
2
1
0
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Port P0
Input read circuit
* P-channel transistor for pull-up
** CMOS output buffer
Fig. 18 Connection example when using key input interrupt and port P0 block diagram
18
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Timers
The 7534 Group has 3 timers: timer X, timer 1 and timer 2.
The division ratio of every timer and prescaler is 1/(n+1) provided
that the value of the timer latch or prescaler is n.
All the timers are down count timers. When a timer reaches “0”, an
underflow occurs at the next count pulse, and the corresponding timer
latch is reloaded into the timer. When a timer underflows, the interrupt request bit corresponding to each timer is set to “1”.
●Timer 1, Timer 2
Prescaler 12 always counts f(XIN)/16. Timer 1 and timer 2 always
count the prescaler output and periodically sets the interrupt request
bit.
●Timer X
Timer X can be selected in one of 4 operating modes by setting the
timer X mode register.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7 b0
Timer X mode register
(TM : Address 002B
Timer X operating mode bits
b1 b0
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
0
active edge switch bit
CNTR
0 : Interrupt at falling edge
Count at rising edge
(in event counter mode)
1 : Interrupt at rising edge
Count at falling edge
(in event counter mode)
Timer X count stop bit
0 : Count start
1 : Count stop
Not used (return “0” when read)
16
)
• Timer Mode
The timer counts the signal selected by the timer X count source
selection bit.
• Pulse Output Mode
The timer counts the signal selected by the timer X count source
selection bit, and outputs a signal whose polarity is inverted each
time the timer value reaches “0”, from the CNTR
When the CNTR
0 pin is started with an “H” output.
CNTR
0 active edge switch bit is “0”, the output of the
0 pin.
At “1”, this output is started with an “L” output. When using a timer in
this mode, set the port P1
4 direction register to output mode.
• Event Counter Mode
The operation in the event counter mode is the same as that in the
timer mode except that the timer counts the input signal from the
0 pin.
CNTR
When the CNTR
the rising edge of the CNTR
counts the falling edge of the CNTR
0 active edge switch bit is “0”, the timer counts
0 pin. When this bit is “1”, the timer
0 pin.
• Pulse Width Measurement Mode
When the CNTR
0 active edge switch bit is “0”, the timer counts the
signal selected by the timer X count source selection bit while the
0 pin is “H”. When this bit is “1”, the timer counts the signal
CNTR
while the CNTR
0 pin is “L”.
In any mode, the timer count can be stopped by setting the timer X
count stop bit to “1”. Each time the timer overflows, the interrupt
request bit is set.
Fig. 19 Structure of timer X mode register
b7 b0
Note : To switch the timer X count source selection bit ,
stop the timer X count operation.
Timer count source set register
(TCSS : Address 002E
Timer X count source selection bit (Note)
IN
0 : f(X
1 : f(X
Not used (return “0” when read)
)/16
IN
)/2
Fig. 20 Timer count source set register
16
)
19
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
P14/CNTR
f(XIN)/16
f(XIN)/2
0
Port P14 direction
register
Pulse output mode
f(XIN)/16
Timer X count
source selection bit
CNTR
0
active
edge switch bit
“0”
“1”
Port P1
Prescaler 12 (8)
4
latch
Pulse width
measurement
mode
Event
counter
mode
CNTR
edge switch bit
Timer mode
pulse output mode
Timer X count stop bit
0
active
Prescaler X latch (8)
Prescaler X (8)
“1”
Q
Toggle
T
flip-flop
Q
“0”
Timer 1 (8) Timer 2 (8)
R
Data bus
Timer 2 latch (8)Timer 1 latch (8)Prescaler 12 latch (8)
Timer X latch (8)
Timer X (8)
Timer X latch write
Pulse output mode
To timer 2
interrupt
request bit
To timer 1
interrupt
request bit
To timer X
interrupt
request bit
To CNTR
interrupt
request bit
0
Fig. 21 Block diagram of timer X, timer 1 and timer 2
20
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O
●Serial I/O1
• Asynchronous serial I/O (UART) mode
Serial I/O1 can be used as an asynchronous (UART) serial I/O. A
dedicated timer (baud rate generator) is also provided for baud rate
generation when serial I/O1 is in operation.
Eight serial data transfer formats can be selected, and the transfer
formats to be used by a transmitter and a receiver must be identical.
Each of the transmit and receive shift registers has a buffer register
Data bus
Address
(0018
Receive Buffer Register
OE
Character length selection bit
0/RX
D
P1
P11/TXD
Fig. 22 Block diagram of UART serial I/O
ST Detector
BRG count source selection bit
X
IN
1/4
7-bit
8-bit
Character length selection bit
Continuous transmit valid bit
Receive Shift Register
PE FE
SP Detector
ST/SP/PA Generator
Data bus
(the same address on memory). Since the shift register cannot be
written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the respective buffer registers. These buffer registers can also hold the next data to be transmitted and receive 2-byte receive data in succession.
By selecting “1” for continuous transmit valid bit (bit 2 of SIO1CON),
continuous transmission of the same data is made possible.
This can be used as a simplified PWM.
Serial I/O1 control register
16
)
Division ratio 1/(n+1)
Baud Rate Generator
Address (001C
1/16
Transmit Shift Register
Transmit Buffer Register
Address
(0018
16
Address (001A
Receive buffer full flag (RBF)
Receive interrupt request (RI)
1/16
Clock Control Circuit
16
)
Transmit interrupt source selection bit
Serial I/O1 status register
)
16
)
UART Control Register
Address (001B
Transmit shift register shift
completion flag (TSC)
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Address (0019
16
)
16
)
Transmit/Receive Clock
Transmit Buffer Register
Write Signal
TBE=0
TSC=0
TBE=1
X
Serial Output T
Receive Buffer Register
Read Signal
Serial Input R
D
X
D
Notes
1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer when TSC = 1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC = 0.
ST SP
ST
Fig. 23 Operation of UART serial I/O function
TBE=0
1
1 Start Bit
7 or 8 Data Bit
1 or 0 Parity Bit
1 or 2 Stop Bit
1
TBE=1
STD0D
D
SP
RBF=1
SP D0D
0
STD0D
D
1
* Generated at second bit in 2-stop -bit
mode
RBF=0
1
TSC=1*
RBF=1
SP
21
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Serial I/O1 control register] SIO1CON
The serial I/O1 control register consists of eight control bits for the
serial I/O1 function.
[UART control register] UARTCON
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set the
data format of an data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P1
1/TxD pin.
[UART status register] UARTSTS
The read-only UART status register consists of seven flags (bits 0 to
6) which indicate the operating status of the UART function and various errors. This register functions as the UART status register
(UARTSTS) when selecting the UART.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer, and the
receive buffer full flag is set. A write to the UART status register clears
all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively).
Writing “0” to the serial I/O1 mode selection bits MOD1 and MOD0
(bit 7 and 6 of the Serial I/O1 control register ) also clears all the
status flags, including the error flags.
All bits of the serial I/O1 status register are initialized to “81
16” at
reset, but if the transmit enable bit (bit 4) of the serial I/O1 control
register has been set to “1”, the continuous transmit valid bit (bit 2)
becomes “1”.
[Baud Rate Generator] BRG
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
[Transmit/Receive buffer register] TB/RB
The transmit buffer and the receive buffer are located at the same
address. The transmit buffer is write-only and the receive buffer is
read-only. If a character bit length is 7-bit, the MSB of data stored in
the receive buffer is “0”.
Transmit/Receive Clock
Transmit Buffer Register
Write Signal
TBE=0
TSC=0
TBE=1
Serial Output T
Notes
X
D
1 : When the serial I/O1 mode selection bits (b7, b6) is “10”, the transmit enable bit is “1”, and continuous transmit valid bit is “1”, writing on the
transmit buffer initiates continuous transmission of the same data.
2 : Select 0 for continuous transmit valid bit to stop continuous transmission.
The T
3 : If the transmit buffer contents are rewritten during a continuous transmission, transmission of the rewritten data will be started after
completing transmission of 1 byte.
ST SP
X
D pin will stop at high level after completing transmission of 1 byte.
1
1 Start Bit
7 or 8 Data Bit
1 or 0 Parity Bit
1 or 2 Stop Bit
STD0D
D
0
D
SP
1
ST
Fig. 24 Continuous transmission operation of UART serial I/O
22
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
• Universal serial bus (USB) mode
By setting bits 7 and 6 of the serial I/O1 control register (address
16) to “11”, the USB mode is selected.
001A
This mode conforms to “Low Speed device” of USB Specification
1.1. In this mode serial I/O1 interrupt have 5 sources; USB in and
out token receive, USB reset, suspend, and resume. The USB
1.5 MHz
Bus state
detection
NRZI,
bit stuffing encoder
EOP generating unit
XIN
P10/D-
1/D+
P1
USB
transceiver
6 MHz
Digital
PLL
Differential input and
Single end input
Output data and
I/O control
USB transmit unit
status/UART status register functions as the USB status register
(USBSTS).There is the USBV
voltage output, and a D-line with 1.5 kΩ external resistor can be pull
up. USB mode block and USB transceiver block show in figures 25
and 26.
Data bus
NRZI,
bit stuffing decoder
BSTFE
EOP
Reset interrupt request
Suspend interrupt request
Resume interrupt request
CRC encoder
Data bus
Receive buffer register
Address 001816
Receive shift register
Transmit shift register
Transmit buffer register
Address 001816
REFOUT pin for the USB reference
RxRDY
SYNC decoder
PID decoder
Address
comparative unit
End pointer
decoder
CRC check
PIDE
CRCE
RxPID
OPID
USBA
RxEP
TxRDY
EP0BYTE
EP1BYTE
Token interrupt request
SYNC, PID
generating unit
EP0PID
EP1PID
Fig. 25 USB mode block diagram
Serial I/O1 control register
MOD0
MOD1
USB reference
power source voltage
Fig. 26 USB transceiver block diagram
USB control register
(initial value “0”)
Output enable signal
UVOE
Internal D- output signal
Internal D+ output signal
(internal signal)
Voltage input
Voltage input
Suspend
Signal for function stop
OE
Output enable signal
Differential input
Single end input
Single end input
Output amplifier USBV
D+/D-
output amplifier
+
D-
D+
REFOUT
23
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
b7 b0
b7 b0
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Transmit buffer register
(TB: address 0018
After setting data to address 0018
16
)
16
, a content of the
transmit buffer register transfers to the transmit shift
register automatically.
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Receive buffer register
16
(RB: address 0018
By reading data from address 0018
)
16
, a content of the
receive buffer register can be read out.
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
7534 Group
b7 b0
USB status register
(USBSTS: address 0019
Transmit buffer empty flag
0: Buffer full
1: Buffer empty
EOP detection flag
0: Not detected
1: Detect
False EOP error flag
0: No error
1: False EOP error
CRC error flag
0: No error
1: CRC error
PID error flag
0: No error
1: PID error
Bit stuffing error flag
0: No error
1: Bit stuffing error
Summing error flag
0: No error
1: Summing error
16
)
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
CPU read: Enabled
CPU write: Clear
Hardware read: Not used
Hardware write: Set
Receive buffer full flag
0: Buffer empty
1: Buffer full
Fig. 27 Structure of serial I/O1-related registers (1)
24
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
b7 b0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
USB data toggle synchronization register
(TRSYNC: address 001D
16
)
Not used (return “1” when read)
MITSUBISHI MICROCOMPUTERS
7534 Group
b7 b0
b7 b0
Sequence bit toggle flag
0: No toggle
1: Sequence toggle
CPU read: Enabled
CPU write: Clear
Hardware read: Not used
Hardware write: Set
USB interrupt source discrimination register 1
(USBIR1: address 001E
16
)
Not used (return “1” when read)
Endpoint determination flag
0: Endpoint 0 interrupt
1: Endpoint 1 interrupt
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
USB interrupt source discrimination register 2
16
(USBIR2: address 001F
)
Not used (return “1” when read)
Suspend request flag
0: No request
1: Suspend request
USB reset request flag
0: No request
1: Reset request
CPU read: Enabled
CPU write: Clear
Hardware read: Not used
Hardware write: Set
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
Not used (return “1” when read)
Token PID determination flag
0: SETUP interrupt
1: OUT interrupt
Token interrupt flag
0: No request
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
1: Token request
b7 b0
USB interrupt control register
(USBICON: address 0020
Not used (return “1” when read)
Endpoint 1 enable
0: Endpoint 1 invalid
1: Endpoint 1 valid
USB reset interrupt enable
0: USB reset invalid
1: USB reset valid
Resume interrupt enable
0: Resume invalid
1: Resume valid
Token interrupt enable
0: Token invalid
1: Token valid
USB enable flag
0: USB invalid
1: USB valid
Fig. 28 Structure of serial I/O1-related registers (2)
16
)
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
25
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
b7 b0
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
USB transmit data byte number set register 0
(EP0BYTE: address 0021
Set a number of data byte for transmitting with endpoint 0.
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Not used (return “0” when read)
16
)
MITSUBISHI MICROCOMPUTERS
7534 Group
b7 b0
b7 b0
b7 b0
b7 b0
USB transmit data byte number set register 1
(EP1BYTE: address 0022
Set a number of data byte for transmitting with endpoint 1.
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
16
)
Not used (return “0” when read)
USB PID control register 0
(EP0PID: address 0023
16
)
Not used (return “1” when read)
Endpoint 0 enable flag
0: Endpoint 0 invalid
1: Endpoint 0 valid
Endpoint 0 PID selection flag
1xxx: IN token interrupt of DATA0/1 is valid
01xx: STALL handshake is valid for IN token
00xx: NACK handshake is valid for IN token
xxx1: STALL handshake is valid for OUT token (Note)
xx10: ACK handshake is valid for OUT token
xx00: NACK handshake is valid for OUT token
x: any data
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
b4, b5, b6
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
b7
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Clear
Note: In the status stage of the control read transfer, when PID
of data packet = DATA0 (incorrect PID), this bit is set forcibly
by hardware and STALL handshake is valid.
USB PID control register 1
(EP1PID: address 0024
Not used (return “1” when read)
Endpoint 1 PID selection flag
1x: IN token interrupt of DATA0/1 is valid
01: STALL handshake is valid for IN token
00: NACK handshake is valid for IN token
USB address register
(USBA: address 0025
Set an address allocated by the USB host.
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
16
)
b6
CPU read: Enabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
b7
CPU read: Enabled
x: any data
16
)
CPU write: Set/Clear
Hardware read: Used
Hardware write: Clear
Not used (returns “1” when read)
Fig. 29 Structure of serial I/O1-related registers (3)
26
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7 b0
b7 b0
b7 b0
USB sequence bit initialization register
(INISQ1: address 0026
A sequence bit of endpoint 1 is initialized.
CPU read: Disabled
CPU write: Dummy
Hardware read: Not used
Hardware write: Not used
16)
USB control register
(USBCON: address 0027
16)
Not used (return “1” when read)
REFOUT output valid flag
USBV
0: Output off
1: Output on
Remote wake up request flag
0: No request
1: Remote wake up request
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
CPU read: Disabled
CPU write: Set
Hardware read: Used
Hardware write: Clear
UART status register
(UARTSTS: address 0019
16)
Transmit buffer empty flag
0: Buffer full
1: Buffer empty
Receive buffer full flag
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag
0: No error
1: Overrun error
Parity error flag
0: No error
1: Parity error
Framing error flag
0: No error
1: Framing error
Summing error flag
0: No error
1: Summing error
Not used (returns “1” when read)
CPU read: Enabled
CPU write: Disabled
Hardware read: Not used
Hardware write: Set/Clear
CPU read: Enabled
CPU write: Clear
Hardware read: Not used
Hardware write: Set
b7 b0
Baud rate generator
(BRG: address 001C
This register is valid only when selecting the UART mode.
A baud rate value is set.
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Fig. 30 Structure of serial I/O1-related registers (4)
16)
27
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7 b0
b7 b0
UART control register
16
(UARTCON: address 001B
)
Character length selection bit
0: 8 bits
1: 7 bits
Parity enable bit
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit
0: Even parity
1: Odd parity
Stop bit length selection bit
0: 1 stop bit
1: 2 stop bits
P-channel output disable bit
0: CMOS output
1: N-channel open-drain output
Not used (returns “1” when read)
Serial I/O1 control register
(SIO1CON: address 001A
16
)
BRG count source selection bit
IN
)
0: f(X
IN
)/4
1: f(X
Not used (returns “1” when read)
Continuous transmit valid bit
0: Continuous transmit invalid
1: Continuous transmit valid
Transmit interrupt source selection bit
0: Interrupt when transmit buffer has
emptied
1: Interrupt when transmit shift
operation is completed
Transmit enable bit
0: Transmit disabled
1: Transmit enabled
Receive enable bit
0: Receive disabled
1: Receive enabled
Serial I/O1 mode selection bits
00: I/O port
01: Not available
10: UART mode
11: USB mode
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
CPU read: Disabled
CPU write: Set/Clear
Hardware read: Used
Hardware write: Not used
Fig. 31 Structure of serial I/O1-related registers (5)
28
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Note on using USB mode
Handling of SE0 signal in program (at receiving)
7534 group has the border line to detect as USB RESET or EOP
(End of Packet) on the width of SE0 (Single Ended 0).
A response apposite to a state of the device is expected.
The name of the following short words which is used in table 5 shows
as follow.
•TKNE: Token interrupt enable (bit 6 of address 20
•RSME: Resume interrupt enable (bit 5 of address 20
•RSTE: USB reset interrupt enable (bit 4 of address 20
•Spec: A response of the device requested by USB Specification 1.1
•SIE: Hardware operation in 7534 group
•F/W: Recommendation process in the program
•FEOPE: False EOP error flag (bit 2 of address 19
•RxPID: Token interrupt flag (bit 7 of address 1F
Table 5 Relation of the width of SE0 and the state of the device
Idle state
Width of SE0
0 µ sec.
0.5 µ sec.
0.5 µ sec.
2.5 µ sec.
2.5 µ sec.
2.67 µ sec.
2.67 µ sec.
Spec
SIE
F/W
Spec
SIE
F/W
Spec
SIE
F/W
Spec
SIE
F/W
TKNE = X
RSME = 0
RSTE =1
Ignore
Keep counting suspend
timer
Not acknowledge
Keep alive
Initialize suspend timer
count value
Not acknowledge
Keep alive or Reset
may determine as keep
alive and Reset interrupt
Keep alive in case of no
interrupt request
Reset processing in case
of interrupt request
Reset
Reset interrupt request
Reset processing
16)
16)
16)
16)
16)
End of Token in transaction
TKNE = 1
RSME = 0
RSTE =1
Ignore
Not detected as EOP(in
case of no detection EOP,
SIE returns idle state as
time out. FEOPE flag is
set.)
Not acknowledge
EOP
Token interrupt request
Token interrupt processing
execute
EOP or Reset
may determine as EOP and
Reset interrupt
RxPID = 1> Token interrupt
RxPID = 0> Reset interrupt
Reset
Reset interrupt request
Reset processing
State of device
processing
processing
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
End of data or handshake
in transaction
TKNE = 0
RSME = 0
RSTE = 0 or 1
Ignore
Not detected as EOP(in
case of no detection EOP,
SIE returns idle state as
timeup. FEOPE flag is
set.)
Wait for the next EOP flag
EOP
Set EOP flag
After checking the set of
EOP flag, go to the next
processing
EOP or Reset
may determine as EOP
and Reset interrupt
Continue the processing
in case of no interrupt
request
Reset processing in case
of interrupt request
Reset
Reset interrupt request
Reset processing
Suspend state
Spec
SIE
F/W
TKNE = 0
RSME = 1
RSTE = 0
Reset or resume
Reset interrupt
request
Reset interrupt
processing
Resume interrupt
processing
• Function of USBPID control register 0 (address 0023
Bit 4 (STALL handshake control for OUT token) of this register is forcibly set by SIE under the special condition shown below.
Set condition; when PID of data packet = DATA0 (incorrect PID) in the status stage of the control read transfer.
• SYNC field at reception
Normally, the SYNC field consists of “KJKJKJKK” (8 bits). However, as for SIE of the 7534 Group, when the low-order 6 bits are “KJKJKK”, it is
determined as SYNC.
16)
29
PRELIMINARY
Serial I/O2 control register
(SIO2CON: address 0030
16
)
S
DATA
pin selection bit (Note)
0 : I/O port/S
DATA
input
1 : S
DATA
output
Internal synchronous clock selection bits
000 : f(X
IN
)/8
001 : f(X
IN
)/16
010 : f(X
IN
)/32
011 : f(X
IN
)/64
110 : f(X
IN
)/128
111 : f(X
IN
)/256
b7 b0
Not used
(returns “0” when read)
Transfer direction selection bit
0 : LSB first
1 : MSB first
S
CLK
pin selection bit
0 : External clock (S
CLK
is an input)
1 : Internal clock (S
CLK
is an output)
Transmit / receive shift completion flag
0 : shift in progress
1 : shift completed
Note : When using it as an S
DATA
input, set the port P13
direction register to “0”.
Notice: This is not a final specification.
Some parametric limits are subject to change.
●Serial I/O2
The serial I/O2 function can be used only for clock synchronous serial I/O.
For clock synchronous serial I/O2 the transmitter and the receiver
must use the same clock. When the internal clock is used, transfer is
started by a write signal to the serial I/O2 register.
[Serial I/O2 control register] SIO2CON
The serial I/O2 control register contains 8 bits which control various
serial I/O functions.
• For receiving, set “0” to bit 3.
• When receiving, bit 7 is cleared by writing dummy data to serial I/
O2 register after shift is completed.
• Bit 7 is set earlier a half cycle of shift clock than completion of shift
operation. Accordingly, when checking shift completion by using
this bit, the setting is as follows:
(1) check that this bit is set to “1”,
(2) wait a half cycle of shift clock,
(3) read/write to serial I/O2 register.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 32 Structure of serial I/O2 control registers
Fig. 33 Block diagram of serial I/O2
30
X
P12/S
CLK
P13/S
DATA
IN
S
S
CLK pin selection bit
“0”
“1”
DATA pin selection bit
“0”
“1”
S
DATA pin selection bit
P12 latch
P13 latch
S
CLK
S
CLK pin
selection bit
1/8
1/16
1/32
1/64
Divider
1/128
1/256
“1”
Internal synchronous
clock selection bits
“0”
Serial I/O counter 2 (3)
Serial I/O shift register 2 (8)
Data bus
Serial I/O2
interrupt request
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Serial I/O2 operation
By writing to the serial I/O2 register(address 0031
counter is set to “7”.
After writing, the S
DATA pin outputs data every time the transfer clock
shifts from a high to a low level. And, as the transfer clock shifts from
a low to a high, the S
DATA pin reads data, and at the same time the
contents of the serial I/O2 register are shifted by 1 bit.
When the internal clock is selected as the transfer clock source, the
following operations execute as the transfer clock counts up to 8.
• Serial I/O2 counter is cleared to “0”.
• Transfer clock stops at an “H” level.
• Interrupt request bit is set.
• Shift completion flag is set.
Also, the S
DATA pin is in a high impedance state after the data trans-
fer is complete. Refer to Figure 34.
When the external clock is selected as the transfer clock source, the
interrupt request bit is set as the transfer clock counts up to 8, but
external control of the clock is required since it does not stop. Notice
that the S
DATA pin is not in a high impedance state on the completion
of data transfer.
16) the serial I/O2
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Synchronous clock
Transfer clock
Serial I/O2 register
write signal
S
DATA
at serial I/O2
output transmit
S
DATA
at serial I/O2
input receive
Note : When the internal clock is selected as the transfer and the direction register of P13/S
the S
DATA
pin is in a high impedance state after the data transfer is completed.
Fig. 34 Serial I/O2 timing (LSB first)
(Note)
D
0
D
1
D
2
D
3
D
4
D5D6D
Serial I/O2 interrupt request bit set
DATA
pin is set to the input mode,
7
31
PRELIMINARY
d
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D Converter
The functional blocks of the A-D converter are described below.
[A-D conversion register] AD
The A-D conversion register is a read-only register that stores the
result of A-D conversion. Do not read out this register during an A-D
conversion.
[A-D control register] ADCON
The A-D control register controls the A-D converter. Bit 2 to 0 are
analog input pin selection bits. Bit 4 is the AD conversion completion
bit. The value of this bit remains at “0” during A-D conversion, and
changes to “1” at completion of A-D conversion.
A-D conversion is started by setting this bit to “0”.
[Comparison voltage generator]
The comparison voltage generator divides the voltage between V
and VREF by 1024 by a resistor ladder, and outputs the divided voltages. Since the generator is disconnected from V
REF pin and VSS
pin, current is not flowing into the resistor ladder.
[Channel Selector]
The channel selector selects one of ports P2
7/AN7 to P20/AN0, and
inputs the voltage to the comparator.
[Comparator and control circuit]
The comparator and control circuit compares an analog input voltage with the comparison voltage and stores its result into the A-D
conversion register. When A-D conversion is completed, the control
circuit sets the AD conversion completion bit and the AD interrupt
request bit to “1”. Because the comparator is constructed linked to a
capacitor, set f(X
IN) to 500 kHz or more during A-D conversion.
SS
b7 b0
A-D control register
(ADCON : address 0034
Analog input pin selection bits
000 : P2
001 : P21/AN
010 : P22/AN
011 : P23/AN
100 : P24/AN
101 : P25/AN
110 : P26/AN
111 : P27/AN
Not used (returns “0” when read)
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
Not used (returns “0” when read)
0
/AN
Fig. 35 Structure of A-D control register
Read 8-bit (Read only address 003516)
b7 b0
16
(Address 0035
Read 10-bit (read in order address 0036
(Address 0036
(Address 0035
High-order 6-bit of address 0036
)
b9 b8 b7 b6 b5 b4 b3 b2
16
b7
16
)
b7
16
)
b7 b6 b5 b4 b3 b2 b1 b0
, 003516)
16
returns “0” when read.
Fig. 36 Structure of A-D conversion register
16
)
0
1
2
3
4
5
6
7
b0
b9 b8
b0
control register
b7 b0
dress 003416)
3
A-D interrupt request
(Address 0036
(Address 0035
16
)
16
)
Comparator
A-D control circuit
A-D conversion register (high-order)
A-D conversion register (low-order)
10
Channel selector
Resistor ladder
V
REF
V
SS
Fig. 37 Block diagram of A-D converter
32
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Watchdog Timer
The watchdog timer gives a means for returning to a reset status
when the program fails to run on its normal loop due to a runaway.
The watchdog timer consists of an 8-bit watchdog timer H and an 8bit watchdog timer L, being a 16-bit counter.
Standard operation of watchdog timer
The watchdog timer stops when the watchdog timer control register
(address 0039
the watchdog timer control register (address 0039
watchdog timer to start to count down. When the watchdog timer H
underflows, an internal reset occurs. Accordingly, it is programmed
that the watchdog timer control register (address 0039
before an underflow occurs.
When the watchdog timer control register (address 0039
the values of the high-order 6-bit of the watchdog timer H, STP instruction disable bit and watchdog timer H count source selection bit
are read.
Initial value of watchdog timer
By a reset or writing to the watchdog timer control register (address
16), the watchdog timer H is set to “FF16” and the watchdog
0039
timer L is set to “FF
16) is not set after reset. Writing an optional value to
16) causes the
16”.
16” to the
Write “FF
watchdog timer
XIN
control register
1/16
Watchdog timer L (8)
16) can be set
16) is read,
“0”
“1”
Watchdog timer H count
source selection bit
Operation of watchdog timer H count source selection bit
A watchdog timer H count source can be selected by bit 7 of the
watchdog timer control register (address 0039
“0”, the count source becomes a watchdog timer L underflow signal.
The detection time is 174.763 ms at f(X
When this bit is “1”, the count source becomes f(X
case, the detection time is 683 µs at f(X
This bit is cleared to “0” after reset.
Operation of STP instruction disable bit
When the watchdog timer is in operation, the STP instruction can be
disabled by bit 6 of the watchdog timer control register (address
16).
0039
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled, and an internal
reset occurs if the STP instruction is executed.
Once this bit is set to “1”, it cannot be changed to “0” by program.
This bit is cleared to “0” after reset.
Data bus
16” to the
Write “FF
watchdog timer
Watchdog timer H (8)
control register
16). When this bit is
IN)=6 MHz.
IN)/16. In this
IN)=6 MHz.
STP Instruction Disable Bit
RESET
Fig. 38 Block diagram of watchdog timer
STP Instruction
b7 b0
Watchdog timer control register(address 003916)
WDTCON
Watchdog timer H (read-only for high-order 6-bit)
STP instruction disable bit
0 : STP instruction enabled
1 : STP instruction disabled
Watchdog timer H count source selection bit
0 : Watchdog timer L underflow
1 : f(X
Fig. 39 Structure of watchdog timer control register
IN
)/16
Reset
circuit
Internal reset
33
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Reset Circuit
The microcomputer is put into a reset status by holding the RESET
pin at the “L” level for 15 µs or more when the power source voltage
is 4.1 to 5.5 V and X
After that, this reset status is released by returning the RESET pin to
the “H” level. The program starts from the address having the contents of address FFFD
address FFFC
Note that the reset input voltage should be 0.82 V or less when the
power source voltage passes 4.1 V.
IN is in stable oscillation.
16 as high-order address and the contents of
16 as low-order address.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Poweron
(Note)
0.2 V
CC
RESET
Power source
voltage
V
CC
0 V
Reset input
voltage
0 V
Note : Reset release voltage Vcc = 4.1 V
Clock from built-in
ring oscillator
φ
RESET
OUT
RESET
SYNC
Address
Data
??
8-13 clock cycles
RESET
Fig. 40 Example of reset circuit
???
?? ADLAD
???
1 : A built-in ring oscillator applies about 250 kHz frequency as clock f at average of Vcc = 5 V.
Notes
2 : The mark “?” means that the address is changeable depending on the previous state.
3 : These are all internal signals except RESET
FFFC FFFD
ADH,AD
H
V
CC
L
Reset address from the
vector table
Power source
voltage
detection circuit
Fig. 41 Timing diagram at reset
34
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1)
Port P0 direction register
(2)
Port P1 direction register
(3)
Port P2 direction register
(4)
Port P3 direction register
(5)
Port P4 direction register
(6)
Pull-up control register
(7)
USB/UART status register
(8)
Serial I/O1 control register
(9)
UART control register
(10)
USB data toggle synchronization register
(11)
USB interrupt source discrimination register 1
(12)
USB interrupt source discrimination register 2
(13)
USB interrupt control register
(14)
USB transmit data byte number set register 0
(15)
USB transmit data byte number set register 1
(16)
USBPID control register 0
(17)
USBPID control register 1
(18)
USB address register
(19)
USB sequence bit initialization register
(20)
USB control register
(21)
Prescaler 12
(22)
Timer 1
(23)
Timer 2
(24)
Timer X mode register
(25)
Prescaler X
(26)
Timer X
(27)
Timer count source set register
(28)
Serial I/O2 control register
(29)
A-D control register
(30)
MISRG
(31)
Watchdog timer control register
(32)
Interrupt edge selection register
(33)
CPU mode register
(34)
Interrupt request register 1
(35)
Interrupt control register 1
(36)
Processor status register
(37)
Program counter
Address
0001
16
0003
16
0005
16
0007
16
0009
16
0016
16
0019
16
16
001A
001B
16
001D
16
001E
16
001F
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
16
0030
0034
16
0038
16
0039
16
003A
16
003B
16
003C
16
003E
16
(PS)
(PCH)
(PC
L
)
Register contents
00
16
X00000
00
00
16
16
00
XXX 0 0XXX
FF
16
10000001
02
16
11100000
01111111
01111111
01110011
00000111
00
16
00
16
00000111
00111111
10000000
11111111
00111111
FF
16
01
16
00
16
00
16
FF
16
FF
16
00
16
00
16
10
16
00
16
00111111
00
16
10000000
00
16
00
16
XXXXX1XX
Contents of address FFFD
Contents of address FFFC
Note X : Undefined
16
16
Fig. 42 Internal status of microcomputer at reset
35
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Clock Generating Circuit
An oscillation circuit can be formed by connecting a resonator be-
IN and XOUT.
tween X
Use the circuit constants in accordance with the resonator
manufacturer's recommended values. No external resistor is needed
between X
●Oscillation control
• Stop mode
When the STP instruction is executed, the internal clock φ stops at
an “H” level and the X
“01
stabilization time set bit after release of the STP instruction is “0”.
On the other hand, timer 1 and prescaler 12 are not set when the
above bit is “1”. Accordingly, set the wait time fit for the oscillation
stabilization time of the oscillator to be used.
f(X
When an external interrupt is accepted, oscillation is restarted but
the internal clock φ remains at “H” until timer 1 underflows. As soon
as timer 1 underflows, the internal clock φ is supplied. This is
because when a ceramic oscillator is used, some time is required
until a start of oscillation.
In case oscillation is restarted by reset, no wait time is generated.
So apply an “L” level to the RESET pin while oscillation becomes
stable.
• Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock restarts
if a reset occurs or when an interrupt is received.
Since the oscillator does not stop, normal operation can be started
immediately after the clock is restarted.
To ensure that interrupts will be received to release the STP or WIT
state, interrupt enable bits must be set to “1” before the STP or
WIT instruction is executed.
When the STP status is released, prescaler 12 and timer 1 will start
counting clock which is X
rupt enable bit to “0” before the STP instruction is executed.
Note
For use with the oscillation stabilization set bit after release of the
STP instruction set to “1”, set values in timer 1 and prescaler
12 after fully appreciating the oscillation stabilization time of the
oscillator to be used.
• Clock mode
Operation is started by a built-in ring oscillator after releasing reset.
A division ratio (1/1,1/2,1/8) is selected by setting bits 7 and 6 of the
CPU mode register after releasing it.
IN and XOUT since a feed-back resistor exists on-chip.
IN oscillator stops. At this time, timer 1 is set to
16” and prescaler 12 is set to “FF16” when the oscillation
IN)/16 is forcibly connected to the input of prescaler 12.
______
IN divided by 16, so set the timer 1 inter-
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XIN
C
IN
Fig. 43 External circuit of ceramic resonator
XIN
External oscillation
circuit
CC
V
V
SS
Fig. 44 External clock input circuit
b7 b0
MISRG(Address 003816)
Oscillation stabilization time set bit after
release of the STP instruction
0: Set “01
in prescaler 12 automatically
1: Not set automatically
Reserved bits (return “0” when read)
(Do not write “1” to these bits)
Not used (return “0” when read)
X
OUT
16
” in timer1, and “FF16”
C
OUT
X
Open
OUT
36
Fig. 45 Structure of MISRG
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
X
IN
Rf
Ring oscillator
Ring oscillator
(Note)
SRQ
X
OUT
Rd
Main clock division ratio selection bit
Middle-speed, High-speed, double -speed mode
mode
1/2
Double-speed mode
1/8
Ring oscillator mode
1/4
High-speed mode
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1/2
Main clock division
ratio selection bit
Middle-speed mode
Q
S
Prescaler 12
MITSUBISHI MICROCOMPUTERS
7534 Group
Timer 1
Timing φ
(Internal clock)
S
Q
STP instruction
WIT
instruction
R
Reset
Interrupt disable flag l
Interrupt request
Fig. 46 Block diagram of system clock generating circuit (for ceramic resonator)
Note: Ring oscillator is used only for starting.
R
STP instruction
37
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after reset are
undefined except for the interrupt disable flag I which is “1”. After
reset, initialize flags which affect program execution. In particular, it
is essential to initialize the T flag and the D flag because of their
effect on calculations.
Interrupts
The contents of the interrupt request bit do not change even if the
BBC or BBS instruction is executed immediately after they are
changed by program because this instruction is executed for the previous contents. For executing the instruction for the changed contents, execute one instruction before executing the BBC or BBS instruction.
Decimal Calculations
• For calculations in decimal notation, set the decimal mode flag D to
“1”, then execute the ADC instruction or SBC instruction. In this
case, execute SEC instruction, CLC instruction or CLD instruction
after executing one instruction before the ADC instruction or SBC
instruction.
• In the decimal mode, the values of the N (negative), V (overflow)
and Z (zero) flags are invalid.
Timers
• When n (0 to 255) is written to a timer latch, the frequency division
ratio is 1/(n+1).
• When a count source of timer X is switched, stop a count of timer X.
Ports
• The values of the port direction registers cannot be read.
That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is “1”, addressing mode using direction register values as qualifiers, and bit test instructions such
as BBC and BBS.
It is also impossible to use bit operation instructions such as CLB
and SEB and read/modify/write instructions of direction registers
for calculations such as ROR.
For setting direction registers, use the LDM instruction, STA instruction, etc.
• As for the 36-pin version, set "1" to each bit 6 of the port P3 direction register and the port P3 register.
• As for the 32-pin version, set “1” to respective bits 5, 6, 7 of the port
P3 direction register and port P3 register.
Instruction Execution Timing
The instruction execution time can be obtained by multiplying the
frequency of the internal clock φ by the number of cycles mentioned
in the machine-language instruction table.
The frequency of the internal clock f is the same as that of the
XIN in double-speed mode, twice the XIN cycle in high-speed
mode and 8 times the X
IN cycle in middle-speed mode.
NOTES ON USE
Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor suitable
for high frequencies as bypass capacitor between power source pin
(Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to
as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of
0.1 µF is recommended.
Handling of USBVREFOUT Pin
In order to prevent the instability of the USBVREFOUT output due to
external noise, connect a capacitor as bypass capacitor between
REFOUT pin and GND pin (VSS pin). Besides, connect the ca-
USBV
pacitor to as close as possible. For bypass capacitor, a ceramic or
electrolytic capacitor of 0.1 µF is recommended.
One Time PROM Version
The CNVss pin is connected to the internal memory circuit block by a
low-ohmic resistance, since it has the multiplexed function to be a
programmable power source pin (V
To improve the noise reduction, connect a track between CNVss pin
and Vss pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNVss pin has no operational interference even if it is connected via a resistor.
PP pin) as well.
A-D Converter
The comparator uses internal capacitors whose charge will be lost if
the clock frequency is too low.
Make sure that f(X
Do not execute the STP instruction during A-D conversion.
38
IN) is 500kHz or more during A-D conversion.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production:
(1) Mask ROM Order Confirmation Form
(2) Mark Specification Form
(3) Data to be written to ROM, in EPROM form
(three identical copies)
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version can be
read or programmed with a general-purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area.
Table 6 Special programming adapter
Package
36P2R-A
42P4B
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in
Figure 47 is recommended to verify programming.
Programming with
PROM programmer
Screening (Caution)
(150 °C for 40 hours)
Verification with PROM
Name of Programming Adapter
PCA7435FP
PCA7435SP
programmer
Functional check in
target device
Caution:
Fig. 47 Programming and testing of One Time PROM version
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
39
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Table 7 Absolute maximum ratings
CC
V
VI
VI
VI
VO
Pd
Topr
Tstg
Notes 1: It is a rating only for the One Time PROM version. Connect to V
Power source voltage
Input voltage P0
Input voltage RESET, XIN
Input voltage CNVSS (Note 1)
Output voltage P0
Power dissipation (Note 2)
Operating temperature
Storage temperature
2: The rating value depends on packages.
3: The value of the 36-pin version is 300 mW.
The value of the 32-pin version is 200 mW.
0–P07, P10–P16, P20–P27, P30–
7, VREF, P40, P41
P3
0–P07, P10–P16, P20–P27, P30–
7, XOUT, USBVREFOUT, P40, P41
P3
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ConditionsSymbol
All voltages are
based on V
Output transistors
are cut off.
Ta = 25°C
SS for mask ROM version.
SS.
Ratings
–0.3 to 7.0
CC + 0.3
–0.3 to V
–0.3 to V
CC + 0.3
–0.3 to 13
–0.3 to V
CC + 0.3
1000 (Note 3)
–20 to 85
–40 to 125
7534 Group
UnitParameter
V
V
V
V
V
mW
°C
°C
40
MITSUBISHI MICROCOMPUTERS
7534 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Recommended Operating Conditions
Table 8 Recommended operating conditions
CC = 4.1 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
(V
Symbol Parameter Unit
VCC
VSS
VREF
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
∑IOH(peak)
∑IOL(peak)
∑IOL(peak)
∑IOH(avg)
∑IOL(avg)
∑IOL(avg)
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOL(avg)
IOL(avg)
f(XIN)
Note 1:The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average
2: The peak output current is the peak current flowing in each port.
3: The average output current I
4: When the oscillation frequency has a duty cycle of 50 %.
Power source voltage
f(XIN) =
6 MHz
Power source voltage
Analog reference voltage
“H” input voltage P0
0–P07, P10–P16, P20–P27,
P3
0–P37, P40, P41
“H” input voltage (TTL input level selected) P10, P12, P13, P36, P37
“H” input voltage RESET, XIN
“H” input voltage D+, D“L” input voltage P0
0–P07, P10–P16, P20–P27,
0–P37, P40, P41
P3
“L” input voltage (TTL input level selected) P10, P12, P13, P36, P37
“L” input voltage RESET, CNVSS
“L” input voltage D+, D“L” input voltage X
IN
“H” total peak output current (Note 1) P00–P07, P10–P16, P20–P27,
0–P37, P40, P41
P3
“L” total peak output current (Note 1) P00–P07, P10–P16, P20–P27,
7, P40, P41
P3
“L” total peak output current (Note 1) P30–P36
“H” total average output current (Note 1) P00–P07, P10–P16, P20–P27,
0–P37, P40, P41
P3
“L” total average output current (Note 1) P00–P07, P10–P16, P20–P27,
P3
7, P40, P41
“L” total average output current (Note 1) P30–P36
“H” peak output current (Note 2) P00–P07, P10–P16, P20–P27,
0–P37, P40, P41
P3
“L” peak output current (Note 2) P00–P07, P10–P16, P20–P27,
P3
7 , P40, P41
“L” peak output current (Note 2) P30–P36
“H” average output current (Note 3) P00–P07, P10–P16, P20–P27,
P3
0–P37, P40, P41
“L” average output current (Note 3) P00–P07, P10–P16, P20–P27,
P3
7, P40, P41
“L” average output current (Note 3) P30–P36
Oscillation frequency (Note 4) VCC = 4.1 to 5.5 V
at ceramic oscillation or external clock input Double-speed mode
value measured over 100 ms. The total peak current is the peak value of all the currents.
OL (avg), IOH (avg) in an average value measured over 100 ms.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Limits
Min.
4.1
2.0
0.8 VCC
2.0
CC
0.8 V
2.0
0
0
0
0
0
Typ.
5.0
0
Max.
5.5
V
VCC
VCC
VCC
3.6
0.3 V
0.8
0.2 V
0.8
0.16V
–80
80
60
–40
40
30
–10
10
30
–5
15
V
V
CC
V
V
V
V
V
CC
V
V
V
CC
V
CC
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
5
mA
MHz
6
41
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Electrical Characteristics
Table 9 Electrical characteristics (1) (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol Parameter
VOH
VOH
V
OL
VOL
VOL
V
T+–VT–
VT+–VT–
VT+–VT–
VT+–VT–
IIH
IIH
IIH
IIL
IIL
IIL
IIL
VRAM
Note 1:P1
2:R
“H” output voltage P00–P07, P10–P16, P20–P27,
0–P37, P40, P41 (Note 1)
P3
“H” output voltage D+, D-
“L” output voltage P0
0–P07, P10–P16, P20–P27,
P3
7, P40, P41
“L” output voltage D+, D-
“L” output voltage P3
0–P36
Hysteresis D+, DHysteresis CNTR
Hysteresis R
0, INT0, INT1 (Note 2),
P0
0–P07(Note 3)
XD, SCLK, SDATA (Note 2)
Hysteresis RESET
“H” input current P0
0–P07, P10–P16, P20–P27,
P3
0–P37, P40, P41
“H” input current RESET
“H” input current X
IN
“L” input current P00–P07, P10–P16, P20–P27,
P3
0–P37, P40, P41
“L” input current RESET, CNVSS
“L” input current XIN
“L” input current P00–P07, P30–P37
RAM hold voltage
1 is measured when the P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
XD, SCLK, SDATA, INT0 and INT1 have hystereses only when bits 0, 1 and 2 of the port P1P3 control register are set to “0” (CMOS level).
3:It is available only when operating key-on wake-up.
Test conditions
OH = –5 mA
I
V
CC = 4.1 to 5.5 V
OH = –1.0 mA
I
CC = 4.1 to 5.5 V
V
V
CC = 4.4 to 5.25 V
Pull-down through
15kΩ ±5 % for D+, DPull-up through 1.5kΩ
±5 % by USBVREFOUT
for D- (Ta = 0 to 70 °C)
OL = 5 mA
I
V
CC = 4.1 to 5.5 V
OL = 1.5 mA
I
CC = 4.1 to 5.5 V
V
V
CC = 4.4 to 5.25 V
Pull-down through
15kΩ ±5 % for D+, DPull-up through 1.5kΩ
±5 % by USBVREFOUT
for D-(Ta = 0 to 70 °C)
OL = 15 mA
I
V
CC = 4.1 to 5.5 V
OL = 1.5 mA
I
CC = 4.1 to 5.5 V
V
I = VCC
V
(Pin floating. Pull-up
transistors “off”)
V
I = VCC
VI = VCC
VI = VSS
(Pin floating. Pull-up
transistors “off”)
I = VSS
V
VI = VSS
VI = VSS
(Pull-up transistors“on”)
When clock stopped
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Limits
Min. Typ. Max.
VCC–1.5
CC–1.0
V
2.8
0.15
0.4
0.5
0.5
–4
–0.2
2.0
7534 Group
3.6
1.5
0.3
0.3
2.0
0.3
5.0
5.0
4
–5.0
–5.0
–0.5
5.5
Unit
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
mA
V
42
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 10 Electrical characteristics (2)
CC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
(V
Symbol Parameter
CC
I
Power source current 6
A-D Converter Characteristics
Double-speed mode, f(X
Output transistors “off”
IN) = 6 MHz, (in WIT state)
f(X
Output transistors “off”
Increment when A-D conversion is executed
IN) = 6 MHz, VCC = 5 V
f(X
All oscillation stopped (in STP state)
Output transistors “off”
V
CC = 4.4 V to 5.25 V
Oscillation stopped in USB mode
USB (SUSPEND), (pull-up resistor
output included) (Fig. 48)
Test conditions
IN) = 6 MHz,
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Limits
Min. Typ. Max.
10 mA
Ta = 25 °C
Ta = 85 °C
Ta = 0 to 70 °C
1.6
0.8
0.1
3.2
1.0
10
300
Unit
mA
mA
µA
µA
µA
Table 11 A-D Converter characteristics (1) (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol Parameter
—
—
Resolution
Linearity error
Test conditions
VCC = 4.1 to 5.5 V
Min.
Limits
Typ. Max.
Ta = 25 °C
—
Differential nonlinear error
V
CC = 4.1 to 5.5 V
Ta = 25 °C
OT
V
VFST
tCONV
RLADDER
IVREF
II(AD)
Zero transition voltage
Full scale transition voltage
Conversion time
Ladder resistor
Reference power source input current
A-D port input current
V
CC
I
CC
V
CC
USBV
REFOUT
V
CC = VREF = 5.12 V
V
CC = VREF = 5.12 V
VREF = 5.0 V
VREF = 3.0 V
0520
5105
5115 5125
55
50
30
150
70
1.5 kΩ
D-
10
±3
±0.9
122
200
120
5.0
Unit
Bits
LSB
LSB
mV
mV
tc(X
µA
IN)
kΩ
µA
V
SS
I
OUT
is included to this ratings.
I
OUT
15 kΩ
Fig. 48 Power source current measurement circuit in USB mode
at oscillation stop
43
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Timing Requirements
Table 12 Timing requirements (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol Parameter
W(RESET)
t
C(XIN)
t
t
WH(XIN)
WL(XIN)
t
C(CNTR)
t
WH(CNTR)
t
WL(CNTR)
t
C(SCLK)
t
t
WH(SCLK)
WL(SCLK)
t
su(SDATA–SCLK)
t
h(SCLK–SDATA)
t
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
0 input cycle time
CNTR
CNTR
0, INT0, INT1 input “H” pulse width
0, INT0, INT1 input “L” pulse width
CNTR
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Min. Typ. Max.
15
166
70
70
200
80
80
1000
400
400
200
200
7534 Group
Limits
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Characteristics
Table 13 Switching characteristics (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol Parameter
tWH(SCLK)
WL(SCLK)
t
d(SCLK–SDATA)
t
v(SCLK–SDATA)
t
r(SCLK)
t
t
f(SCLK)
r(CMOS)
t
f(CMOS)
t
r(D+), tr(D-)
t
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note)
CMOS output falling time (Note)
USB output rising time, C
L = 200 to 450 pF, Ta = 0 to 70 °C, VCC =
tC(SCLK)/2–30
C(SCLK)/2–30
t
Limits
Min.
0
75
4.4 to 5.25 V
f(D+), tf(D-)
t
USB output falling time, C
L = 200 to 450 pF, Ta = 0 to 70 °C, VCC =
75
4.4 to 5.25 V
Notes: XOUT pin is excluded.
Measured
output pin
100 pF
Typ. Max.
140
30
30
10
10
150
150
30
30
300
300
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMOS output
Fig. 49 Output switching characteristics measurement circuit
44
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
CNTR
0
0.8V
tWH(CNTR)
CC
tC(CNTR)
0.2V
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
tWL(CNTR)
CC
INT0/INT
RESET
X
IN
S
CLK
tWH(INT)
0.8V
1
CC
0.2V
tWL(INT)
CC
tW(RESET)
0.8V
0.2V
CC
CC
tC(XIN)
0.2V
CC
CC
tWL(XIN)
CLK
)
tWH(XIN)
0.8V
CC
tC(S
CLK
)
t
t
f
0.2V
CC
tWL(S
CLK
) tWH(S
r
0.8V
S
DATA
(at receive)
S
DATA
(at transmit)
D+, D-
Fig. 50 Timing chart
td(S
CLK-SDATA
t
f
0.1V0H
tsu(S
)
DATA-SCLK
0.8V
CC
0.2V
CC
)th(S
CLK-SDATA
)
tv(S
CLK-SDATA
t
r
)
0.9V0H
45
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Description of improved USB function for 7534 Group
Table 14 Description of improved USB function for 7534 Group
No.
Response at Control transfer
1
D+/D- transceiver circuit
2
Power dissipation at Suspend
3
STALL in Status stage
4
6-bit decode of SYNC field
5
Parameter
Not deal with the host which performs the Control
transfer in parallel to plural device.
USB function can be used only at the condition of
L = 150 pF to 350 pF.
C
Rating is Max. 300 µA not including the output current of USBV
ACK is returned once to OUT (DATA0) to be valid
in Status stage.
SYNC is detected only when 8-bit full code (80
is complete.
7532 Group
REFOUT.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
Connectable to the host which performs the Control transfer in parallel to plural device.
Deal with the the following USB Spefification Rev.
1.1.
L = 200 pF to 450 pF,
C
Trise and Tfall: 75 ns to 300 ns,
Tr/Tf: 80 % to 125 %,
Cross over Voltage: 1.3 V to 2.0 V.
Rating is Max. 300 µA including the output current
REFOUT, by low-power dissipation of D+/
of USBV
D- input circuit and 3.3 V-regulator.
STALL is set automaticcally by hardware when
OUT (DATA0) is received in Status stage.
16)
SYNC is detected only the low-order 6 bits even if
the high-order 2 bits are corrupted.
Differences among 32-pin, 36-pin and 42-pin
The 7534 Group has three package types, and each of the number
of I/O ports are different. Accordingly, when the pins which have the
function except a port function are eliminated, be careful that the
functions are also eliminated.
Table 15 Differences among 32-pin, 36-pin and 42-pin
I/O port
Port P1
Port P2
Port P3
Port P4
0–P16 (7-bit structure)
P1
0–P27 (8-bit structure)
P2
(A-D converter 8-channel)
0–P37 (8-bit structure)
P3
(INT
P4
0, P41 (2-bit structure)
42-pin SDIP
0, INT1 available)
P1
P2
(A-D converter 8-channel)
P3
(INT
No port
36-pin SSOP
0–P14 (5-bit structure)
0–P27 (8-bit structure)
0–P35, P37 (7-bit structure)
0 available)
32-pin LQFP
0–P14 (5-bit structure)
P1
P2
0–P25 (6-bit structure)
(A-D converter 6-channel)
0–P34 (5-bit structure)
P3
(INT function not available)
No port
46
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Additionally, there are differences of SFR usage and functional definitions.
Table 16 Differences among 32-pin, 36-pin and 42-pin (SFR)
Register (Address)
Port P1/Direction
16/0316)
(02
Port P2/Direction
16/0516)
(04
Port P3/Direction
(06
16/0716)
Port P4/Direction
16/0916)
(08
Pull-up control
16)
(16
Port P1P3 control
(17
16)
A-DControl
16)
(34
Interrupt edge
selection
16)
(3A
Interrupt request
16)
(3C
Interrupt control
16)
(3E
Bit 7 not available
All bits available
All bits available
Bits 2 to 7 not available
Bit 6 definition:
“P3
Bit 7 definition:
“P3
Bit 0 definition:
“P3
Bit 1 definition:
“P3
Bits 0 to 2
“Input pins selected by setting these
bits to 000 to 111”
Bit 0 definition
“INT
Bit 1 definition
“INT
Bit 4 definition
“Serial I/O1, INT
Bit 1 definition
“UART transmission, USB (except IN),
INT
Bit 2 definition
“INT
Bit 1 definition
“UART transmission, USB (except IN),
INT
Bit 2 definition
“INT
42-pin SDIP
5, P36 pull-up control”
7 pull-up control”
7/INT0 input level selection”
6/INT1 input level selection”
0 interrupt edge selection”
1 interrupt edge selection”
1 interrupt selection”
1”
0”
1”
0”
Bits 5 to 7 not available
All bits available
Bit 6 not available
All bits not available
Bit 6 definition:
“P3
Bit 7 definition:
“P3
Bit 0 definition:
“P3
Bit 1 not available
Bits 0 to 2
“Input pins selected by setting these
bits to 000 to 111”
Bit 0 definition
“INT
Bits 1 and 4 not available
Bit 1 definition
“UART transmission, USB (except IN)”
Bit 2 definition
“INT
Bit 1 definition
“UART transmission, USB (except IN)”
Bit 2 definition
“INT
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
36-pin SSOP
5 pull-up control”
7 pull-up control”
7/INT0 input level selection”
0 interrupt edge selection”
0”
0”
MITSUBISHI MICROCOMPUTERS
7534 Group
32-pin LQFP
Bits 5 to 7 not available
Bits 6 and 7 not available
Bits 5 to 7 not available
All bits not available
Bits 6 and 7 not available
Bits 0 and 1 not available
Bits 0 to 2
“Input pins selected by setting these
bits to 000 to 101”
Bits 0, 1 and 4 not available
Bit 1 definition
“UART transmission, USB (except IN)”
Bit 2 not available
Bit 1 definition
“UART transmission, USB (except IN)”
Bit 2 not available
47
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Description supplement for use of USB function stably
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
P1
2/SCLK
P13/S
DATA
P14/CNTR
P20/AN
P21/AN
P22/AN
P23/AN
P24/AN
P25/AN
P2
6
/AN
P27/AN
REF
V
RESET
CNV
Vcc
X
X
OUT
V
SS
IN
SS
1
2
0
0
1
2
3
4
5
6
7
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
M37534M4-XXXFP
M37534E8FP
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
P11/TXD/D+
P10/RXD/DP0
7
P0
6
P0
5
P0
4
P0
3
P0
2
P0
1
P0
0
USBV
P3
7
/INT
REFOUT
0
P35(LED5)
4
(LED4)
P3
P3
3
(LED3)
2
(LED2)
P3
P31(LED1)
P30(LED0)
1.5kΩ
Outline 36P2R-A
➁
Connect a bypass capacitor to a device
➀
as close as possible. For the capacitor,
a ceramic capacitor or an electrolytic
capacitor of 1.0 µF is recommended.
Reason of ➀ is to reduce the effect by switcing noise of microcomputer to the
analog circuit generating USBV
REFOUT
output. Use the bigger capacitor and
connect to device at the shortest distance.
Reason of ➁ is to prevent the instability of the USBV
external noise.
Fig. 51 Handling of VCC, USBVREFOUT pins of M37534M4-XXXFP, M37534E8FP
48
Connect a capacitor to a device as
close as possible. For the capacitor,
a ceramic capacitor or an electrolytic
capacitor of 0.22 µF is recommended.
REFOUT
output due to
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
1.5kΩ
P0
24
6
5
P0
23
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Connect a capacitor to a device as
➁
close as possible. For the capacitor,
a ceramic capacitor or an electrolytic
capacitor of 0.22 µF is recommended.
REFOUT
0
1
2
3
4
P0
USBV
P0
P0
P0
P0
21
201718
22
19
7534 Group
P0
P10/RXD/D-
P1
1/TX
D/D+
P1
2/SCLK
P13/S
DATA
P14/CNTR
P20/
AN
P21/
AN
7
25
26
27
28
M37534M4-XXXGP
29
0
30
0
31
1
32
3
2
1
2
3
4
/AN
/AN
/AN
3
4
2
P2
P2
P2
Outline 32P6U-A
16
15
14
13
12
11
10
4
5
5
REF
/AN
V
5
P2
Connect a bypass capacitor to a device
➀
8
7
6
SS
CNV
RESET
CC
V
9
P34(LED4)
P3
3
(LED3)
P3
2
(LED2)
P3
1
(LED1)
P3
0
(LED0)
V
SS
X
OUT
X
IN
as close as possible. For the capacitor,
a ceramic capacitor or an electrolytic
capacitor of 1.0 µF is recommended.
Reason of ➀ is to reduce the effect by switcing noise of microcomputer to the
analog circuit generating USBV
REFOUT
output. Use the bigger capacitor and
connect to device at the shortest distance.
Reason of ➁ is to prevent the instability of the USBV
external noise.
Fig. 52 Handling of VCC, USBVREFOUT pins of M37534M4-XXXGP
REFOUT
output due to
49
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
P14/CNTR
P1
P1
P20/AN
1
/AN
P2
NC
P22/AN
3
/AN
P2
P24/AN
P25/AN
P26/AN
P27/AN
P4
P4
REF
V
RESET
CNV
Vcc
X
X
OUT
V
SS
IN
SS
10
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
19
20
21
M37534E8SP
M37534M4-XXXSP
M37534RSS
0
5
6
0
1
2
3
4
5
6
7
0
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P13/S
DATA
P12/S
CLK
1/TX
P1
D/D+
P10/RXD/DP0
7
P0
6
P0
5
P0
4
P0
3
P0
2
P0
1
P0
0
USBV
P37/INT
REFOUT
0
P36(LED6)/INT
P35(LED5)
4
(LED4)
P3
P3
3
(LED3)
P3
2
(LED2)
P31(LED1)
P30(LED0)
1.5kΩ
1
Outline 42P4B
➁
Connect a bypass capacitor to a device
➀
as close as possible. For the capacitor,
a ceramic capacitor or an electrolytic
capacitor of 1.0 µF is recommended.
Reason of ➀ is to reduce the effect by switcing noise of microcomputer to the
analog circuit generating USBV
REFOUT output. Use the bigger capacitor and
connect to device at the shortest distance.
Reason of ➁ is to prevent the instability of the USBV
external noise.
Fig. 53 Handling of VCC, USBVREFOUT pins of M37534E8SP, M37534M4-XXXSP, M37534RSS
50
Connect a capacitor to a device as
close as possible. For the capacitor,
a ceramic capacitor or an electrolytic
capacitor of 0.22 µF is recommended.
REFOUT output due to
PRELIMINARY
SSOP36-P-450-0.80
Weight(g)
–
JEDEC Code
0.53
EIAJ Package Code
Lead Material
Alloy 42
36P2R-A
Plastic 36pin 450mil SSOP
Symbol
Min Nom Max
A
A
2
b
c
D
E
L
L
1
y
Dimension in Millimeters
H
E
A
1
I
2
–
–
.350
.050
.130
.814
.28
–
.6311
.30
–
–
–
.271
–
–
.02
.40
.150
.015
.48
.80
.9311
.50
.7651
–
.4311
–
–
.42
–
.50
.20
.215
.68
–
.2312
.70
–
.150
–
b
2
–.50–
–
0° –10°
e
e
1
36
19
18
1
H
E
E
D
b
e
y
F
A
A
2
A
1
L
1
L
c
e
b
2
e
1
I
2
Recommended Mount Pad
Detail F
Notice: This is not a final specification.
Some parametric limits are subject to change.
PACKAGE OUTLINE
MITSUBISHI MICROCOMPUTERS
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
51
MITSUBISHI MICROCOMPUTERS
7534 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
42P4B
EIAJ Package Code
SDIP42-P-600-1.78
SEATING PLANE
42
1
LA
JEDEC Code
–
Weight(g)
e
4.1
Lead Material
Plastic 42pin 600mil SDIP
Alloy 42/Cu Alloy
22
E
21
Symbol
D
1
b
b
b
2
A
A
1
2
A
2
A
1
A
b
1
b
b
2
c
D
E
e
e
1
L
c
1
e
Dimension in Millimeters
Min Nom Max
– – 5.5
0.51 – –
–3.8–
0.35 0.45 0.55
0.9 1.0 1.3
0.63 0.73 1.03
0.22 0.27 0.34
36.5 36.7 36.9
12.85 13.0 13.15
– 1.778 –
– 15.24 –
3.0 – –
0° –15°
HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN
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• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
material or (iii) prevention against any malfunction or mishap.
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© 2000 MITSUBISHI ELECTRIC CORP.
KI-0001 Printed in Japan (ROD)
New publication, effective Jan. 2000.
Specifications subject to change without notice.
II
REVISION DESCRIPTION LIST 7534 Group DATA SHEET
Rev. Rev.
No. date
1.0 First Edition 000118
1.1 Page 2: package type revised; 32P6B-A → 32P6U-A 000614
Page 5: package type revised; 32P6B-A → 32P6U-A
Page 8 package type revised; 32P6B-A → 32P6U-A
Page 34: Description revised; RESET “L” pulse width 2 µs → 15 µs
Page 43: Table 11 revised; Absolute accuracy (excluding quantization error) → Linearity error
Page 44: Table 12 revised; tw(RESET): 2 → 15
Page 48: Fig. 51 Description ➀, ➁ revised
Page 49: Fig. 52 Description ➀, ➁ and package type revised; 32P6B-A → 32P6U-A
Page 50: Fig. 53 Description ➀, ➁ revised
Page 51: Package outline revised; 32P6B-A → 32P6U-A
1.2 Page 34: Character fonts errors revised 000905
Revision Description
(1/2)
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