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M37271EFSP
Datasheet
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Mitsubishi M37271MF-XXXSP, M37271EFSP, M37271EF-XXXSP Datasheet

MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER

DESCRIPTION

The M37271MF-XXXSP is a single-chip microcomputer designed with CMOS silicon gate technology. It is housed in a 52-pin shrink plastic molded DIP. In addition to their simple instruction sets, the ROM, RAM and I/O addresses are placed on the same memory map to enable easy pro­gramming. The M37271MF-XXXSP has a OSD function and a data slicer func­tion, so it is useful for a channel selection system for TV with a closed caption decoder. The features of the M37271EF-XXXSP and the M37271EFSP are similar to those of the M37271MF-XXXSP except that these chips have a built-in PROM which can be written electri­cally.

FEATURES

Number of basic instructions .....................................................71
•
Memory size
•
The minimum instruction execution time
•
.......................................... 0.5
Power source voltage .................................................. 5 V ± 10 %
•
Subroutine nesting............................................. 128 levels (Max.)
•
Interrupts....................................................... 18 types, 16 vectors
•
8-bit timers .................................................................................. 6
•
Programmable I/O ports (Ports P0, P1, P2, P30, P31) .............. 26
•
Input ports (Ports P40–P46, P63, P64)......................................... 9
•
Output ports (Ports P52–P55) ......................................................4
•
12 V withstand ports ..................................................................11
•
LED drive ports ........................................................................... 2
•
Serial I/O ............................................................ 8-bit ✕ 1 channel
•
Multi-master I2C-BUS interface ............................... 1 (2 systems)
•
A-D converter (8-bit resolution) ................................... 4 channels
•
PWM output circuit...........................................................8-bit ✕ 7
•
Interrupt interval determination circuit ......................................... 1
•
Power dissipation
•
In high-speed mode .......................................................... 165mW
(at VCC = 5.5V, 8MHz oscillation frequency, CRT on, and Data slicer on)
In low-speed mode .......................................................... 0.33mW
(at VCC = 5.5V, 32kHz oscillation frequency)
Data slicer
•
ROM ........................................................60 K bytes
RAM........................................................1024 bytes
ROM for OSD ....................................... 14464 bytes
RAM for OSD ......................................... 1920 bytes
µs
(at 8 MHz oscillation frequency)
OSD function
•
Display characters ...............................40 characters ✕ 16 lines
Kinds of characters ..................................................... 320 kinds
(In EXOSD mode, they can be combined with 32 kinds of extra
fonts)
Dot structure ........................................CC mode : 16 ✕ 26 dots
OSD mode : 16 ✕ 20 dots
EXOSD mode : 16 ✕ 26 dots
Kinds of character sizes................................CC mode : 2 types
OSD mode : 14 types
EXOSD mode : 6 types
It can be specified by a character unit (maximum 7 kinds).
Character font coloring, character background coloring
It can be specified by a screen unit (maximum 7 kinds).
Extra font coloring, raster coloring, border coloring
Kinds of character colors ............... CC mode : 7 kinds (R, G, B)
OSD mode : 15 kinds (R, G, B, I)
EXOSD mode : 7 kinds (R, G, B, I1, I2)
Display position
Horizontal................................................................ 256 levels
Vertical .................................................................. 1024 levels
Attribute...................... CC mode : smooth italic, underline, flash
OSD mode : border EXOSD mode : border,
extra font (32 kinds) Automatic solid space function Window function Dual layer OSD function

APPLICATION

TV with a closed caption decoder
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER

PIN CONFIGURATION (TOP VIEW)

SYNC
H V
SYNC
P40/AD4
P4
1
/INT2
P4
2
/TIM2
P4
3
/TIM3
P2
4
/AD3
P2
5
/AD2
P26/AD1
P2
P00/PWM4 P0
1
/PWM5
P0
2
/PWM6
7/SIN
P1
P44/INT1
5/SOUT
P4
P4
6/SCLK
AV
HLF
RVCO V
HOLD
CV
CNV
X
X
OUT
V
CC
SS
SS
1 2 3 4
5 6
M37271EF-XXXSP, M37271EFSP
7 8 9
10
7
11 12
13 14
15
16
17 18
19 20
21 22
IN
23
IN
24 25
26
52
P52/R
51
P5
3
/G
4
/B
P5
50
P5
5
49 48 47
M37271MF-XXXSP
46 45 44 43
42 41 40 39
38 37 36
35 34 33 32 31 30
29 28 27
/OUT1
P0
4
/PWM0
P0
5
/PWM1 P06/PWM2 P07/PWM3
0
P2
1
P2 P2
2
P2
3 0
/OUT2
P1
1
/SCL1
P1
2
/SCL2
P1 P1
3
/SDA1 P1
4
/SDA2
5
/I1
P1 P1
6
/I2/INT3 P0
3 0
P3 P31 RESET
4
/OSC2/X
P6 P63/OSC1/X
V
CC
COUT CIN
Outline 52P4B
2
Clock input Clock output
X
IN
X
OUT
Reset input
AV
CC
V
CC
V
SS
CNV
SS
Pins for data slicer
Clock output for OSD/
sub-clock output
Input ports P6
3
, P6
4
OSC1 OSC2
Clock input for OSD/
sub-clock input
P1 (8)
Multi-master
I
2
C-BUS interface
P3 (2)
SDA1
SCL2
SCL1
SDA2
P2 (8)
P0 (8)
P4 (7)
S
IN
S
CLK
S
OUT
SI/O (8)
P6 (2)
INT1
INT2
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
P5 (4)
OUT1
B
G
R
H
SYNC
V
SYNC
OUT2
A-D
converter
8-bit
PWM circuit
8-bit
arithmetic
and
logical unit
Accumulator
A (8)
Timer 6
T6 (8)
Timer 5
T5 (8)
Timer 4
T4 (8)
Timer 3
T3 (8)
Timer 2
T2 (8)
Timer 1
T1 (8)
Timer count source
selection circuit
TIM2
TIM3
Data slicer
Instruction
register (8)
Instruction
decoder
Control signal
CRT circuit
Processor
status
register
PS (8)
Stack
pointer
S (8)
Index
register
Y (8)
Index
register
X (8)
ROM
60 K bytes
Program
counter
PC
L
(8)
Progam
counter
PC
H
(8)
RAM
1024 bytes
Data bus
Clock
generating
circuit
24 25
30
RESET
18 27 26 23
CV
IN
22 21 20 19
V
HOLD
RVCO
HLF
28 29
Address bus
31 14 34 35 36 37 38 39 40 10 9 8 7 41 42 43 44 45 46 47 48 33 13 12 11 17 16 15 6 5 4 3 49 50 51 52 2 1
I/O ports
P3
0
, P3
1
I/O port P1 I/O port P2 I/O port P0 Input ports P4
0
–P4
6
Output port P5
Sync
signal input
INT3
32
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER

FUNCTIONAL BLOCK DIAGRAM of M37271MF-XXXSP

3
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER

FUNCTIONS

Parameter Number of basic instructions Instruction execution time
Clock frequency Memory size
Input/Output ports
Serial I/O Multi-master I2C-BUS interface A-D converter PWM output circuit Timers Subroutine nesting Interrupt interval determination circuit Interrupt
Clock generating circuit
Data slicer
ROM RAM OSD ROM OSD RAM P00–P02,
P04–P07 P03 P10, P15–P17
P11–P14
P2 P30, P31 P40–P44
P45, P46
P52–P55 P63 P64
I/O
I/O I/O
I/O
I/O I/O
Input
Input
Output
Input Input
71
0.5 µs (the minimum instruction execution time, at 8 MHz oscillation fre­quency)
8 MHz (maximum) 60 K bytes 1024 bytes 14464 bytes 1920 bytes 7-bit ✕ 1 (N-channel open-drain output structure, can be used as PWM
output pins) 1-bit ✕ 1 (CMOS input/output structure) 4-bit ✕ 1 (CMOS input/output structure, can be used as OSD output pin,
INT input pin, serial input pin) 4-bit ✕ 1 (N-channel open-drain output structure, can be used as multi-
master I2C-BUS interface) 8-bit ✕ 1 (CMOS input/output structure, can be used as A-D input pins) 2-bit ✕ 1 (CMOS input/output structure) 5-bit ✕ 1 (can be used as A-D input pins, INT input pins, external clock
input pins) 2-bit ✕ 1 (N-channel open-drain output structure when serial I/O is used,
can be used as serial I/O pins) 4-bit ✕ 1 (CMOS output structure, can be used as OSD output) 1-bit ✕ 1 (can be used as sub-clock input pin, OSD clock input pin) 1-bit ✕ 1 (CMOS output structure when LC is oscillating, can be used as
sub-clock output pin, OSD clock output pin) 8-bit ✕ 1 1 4 channels (8-bit resolution) 8-bit ✕ 7 8-bit timer ✕ 6 128 levels (maximum) 1 External interrupt ✕ 3, Internal timer interrupt ✕ 6, Serial I/O interrupt ✕ 1,
OSD interrupt ✕ 1, Multi-master I2C-BUS interface interrupt ✕ 1, Data slicer interrupt ✕ 1, f(XIN)/4092 interrupt ✕ 1, VSYNC interrupt ✕ 1, A­D conversion interrupt ✕ 1, BRK instruction interrupt ✕ 1
2 built-in circuits (externally connected a ceramic resonator or a quartz­crystal oscillator)
Built in
Functions
4
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
FUNCTIONS (continued)
and ON-SCREEN DISPLAY CONTROLLER
OSD function
Power source voltage Power dissipation
Operating temperature range Device structure Package
In high-speed mode
In low-speed mode
In stop mode
Number of display characters Dot structure
Kinds of characters
Kinds of character sizes
Kinds of character colors
Display position (horizontal, vertical)
OSD ON OSD OFF OSD OFF
Data slicer ON Data slicer OFF Data slicer OFF
40 characters ✕ 16 lines CC mode: 16 ✕ 26 dots (character part : 16 ✕ 20 dots) OSD mode: 16 ✕ 20 dots EXOSD mode: 16 ✕ 26 dots 320 kinds (In EXOSDmode, they can be combined with 32 kinds of extra fonts) CC mode: 2 kinds OSD mode: 14 kinds EXOSD mode: 6 kinds CC mode: 7 kinds (R, G, B) OSD mode: 15 kinds (R, G, B, I1) EXOSD mode: 7 kinds (R, G, B, I1, I2)
256 levels (horizontal) ✕ 1024 levels (vertical) 5 V ± 10 % 165 mW typ. (at oscillation frequency fCPU = 8 MHz, fOSD = 13 MHz)
82.5 mW typ. (at oscillation frequency fCPU = 8 MHz)
0.33mW typ. (at oscillation frequency fCLK = 32 kHz, f(XIN) = stopped)
0.055 mW (maximum) –10 °C to 70 °C CMOS silicon gate process 52-pin shrink plastic molded DIP
5
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER

PIN DESCRIPTION

Pin Name Name
VCC, AVCC, VSS.
CNVSS
_____
RESET
XIN XOUT
P00/PWM4– P02/PWM6, P03, P04/PWM0– P07/PWM3
P10/OUT2, P11/SCL1, P12/SCL2, P13/SDA1, P14/SDA2, P15/I1, P16/I2/INT3, P17/SIN
P20–P23 P24/AD3– P26/AD1, P27
Power source
CNVSS Reset input
Clock input Clock output
I/O port P0
PWM output
I/O port P1
OSD output
Multi-master I2C-BUS interface
Serial I/O data input
I/O port P2
Analog input
Input/
Output
Input
Input
Output
I/O
Output
I/O
Output
Output
Input
I/O
Input
Apply voltage of 5 V ± 10 % (typical) to VCC and AVCC, and 0 V to VSS.
This is connected to VSS. To enter the reset state, the reset input pin must be kept at a “L” for 2 µs or more (under
normal VCC conditions). If more time is needed for the quartz-crystal oscillator to stabilize, this “L” condition should be maintained for the required time.
This chip has an internal clock generating circuit. To control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and XOUT. If an external clock is used, the clock source should be connected to the XIN pin and the XOUT pin should be left open.
Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually programmed as input or output. At reset, this port is set to input mode. The output structure of P03 is CMOS output, that of P00–P02 and P04–P07 are N-channel open-drain output. The note out of this Table gives a full of port P0 function.
Pins P00–P02 and P04–P07 are also used as PWM output pins PWM4–PWM6 and PWM0– PWM3 respectively. The output structure is N-channel open-drain output.
Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output structure of P10 and P15–P17 is CMOS output, that of P11–P14 is N-channel open-drain output.
Pins P10, P15, P16 are also used as OSD output pins OUT2, I1, I2 respectively. The output structure is CMOS output.
Pins P11–P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master I2C-BUS interface is used. The output structure is N-channel open-drain output.
P17 pin is also used as serial I/O data input pin SIN.
Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output.
Pins P24–P26 are also used as analog input pins AD3–AD1 respectively.
P30, P31
P40/AD4, P41/INT2, P42/TIM2, P43/TIM3, P44/INT1, P45/SOUT, P46/SCLK,
P52/R,P53/G, P54/B, P55/OUT1
I/O port P3
Input port P4 Analog input External interrupt
input External clock input Serial I/O data
output Serial I/O
synchronizing clock input/output
Output port P5 OSD output
I/O
Input Input Input
Input
Output
I/O
Output Output
Ports P30 and P31 are a 2-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output.
Ports P40–P46 are a 7-bit input port. P40 pin is also used as analog input pin AD4. Pins P41, P44 are also used as external interrupt input INT2, INT1.
Pins P42 and P43 are also used as external clock input pins TIM2, TIM3 respectively. P45 pin is used as serial I/O data output pin SOUT. The output structure is N-channel open-
drain output. P46 pin is used as serial I/O synchronizing clock input/output pin SCLK. The output struc-
ture is N-channel open-drain output.
Ports P52–P55 are a 4-bit output port. The output structure is CMOS output. Pins P52–P55 are also used as OSD output pins R, G, B, OUT1 respectively.
6
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
PIN DESCRIPTION (continued)
P63/OSC1/ XCIN, P64/OSC2/ XCOUT
CVIN VHOLD RVCO HLF HSYNC VSYNC
Note : As shown in the memory map (Figure 3), port P0 is accessed as a memory at address 00C016 of zero page. Port P0 has the port P0
Input port Clock input for OSD Clock output for OSD Sub-clock output Sub-clock input I/O for data slicer
HSYNC input VSYNC input
direction register (address 00C116 of zero page) which can be used to program each bit as an input (“0”) or an output (“1”). The pins programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the output “L” voltage has risen, for example, because a light emitting diode was directly driven. The input pins are in the floating state, so the values of the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state.
Input
Input Output Output
Input
Input
Input
Input
Input
Ports P63 and P64 are 2-bit input port. P63 pin is also used as OSD clock input pin OSC1. P64 pin is also used as OSD clock output pin OSC2. The output structure is CMOS output. P64 pin is also used as sub-clock output pin XCOUT. The output structure is CMOS output. P63 pin is also used as sub-clock input pin XCIN. Input composite video signal through a capacitor. Connect a capacitor between VHOLD and VSS. Connect a resistor between RVCO and VSS. Connect a filter using of a capacitor and a resistor between HLF and VSS. This is a horizontal synchronizing signal input for OSD. This is a vertical synchronizing signal input for OSD.
and ON-SCREEN DISPLAY CONTROLLER
7
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
FUNCTIONAL DESCRIPTION Central Processing Unit (CPU)
The M37271MF-XXXSP uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine in­structions or the SERIES 740 < Software > User’s Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST, SLW instruction cannot be used. The MUL, DIV, WIT and STP instruction can be used.
70
11 00
CPU mode register (CPUM (CM) : address 00FB
Processor mode bits
b1 b0
0 0 : Single-chip mode 0 1 : 1 0 : 1 1 :
Stack page selection bit (Note) 0 : Zero page
1 : 1 page Fix these bits to “1.”
COUT drivability selection bit
X 0 : Low drive 1 : High drive
Main colock (X 0 : Oscillating 1 : Stopped
Internal system clock selection bit 0 : X 1 : X
CPU Mode Register
The CPU mode register contains the stack page selection bit and internal system clock selection bit. The CPU mode register is allo­cated at address 00FB16.
16)
Not available
IN–XOUT) stop bit
IN–XOUT selected (high-speed mode) CIN–XCOUT selected (low-speed mode)
Note: Please beware of this bit when programming because it
Fig. 1. Structure of CPU mode register
is set to “1” after the reset release.
8
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
MEMORY Special Function Register (SFR) Area
The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts.
ROM
ROM is used for storing user programs as well as the interrupt vector area.
RAM for OSD
RAM for display is used for specifying the character codes and col­ors to display.
ROM for OSD
ROM for display is used for storing character data.
0000
16
Zero page
RAM
(1024 bytes)
RAM for OSD (Note)
(1920 bytes)
00C0 00FF
0200 023F
0300
053F
0800 0FFF
1000
16 16
16
16
16
16
16
16
16
SFR1 area
SFR2 area
Not used
Not used
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.
Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the spe­cial page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.
10000
ROM for OSD
(14464 bytes)
10800
1567F
18000
16
16
16
16
Not used
Not used
ROM
(60 K bytes)
Fig. 2. Memory map
FF00 FFDE
FFFF
16
16
Interrupt vector area
16
Special page
1E43F
1FFFF
16
16
Not used
9
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■SFR1 area (addresses C016 to DF16)
: Nothing is allocated
: Fix this bit to “0” ( do not write “1”) : “0” immediately after reset
0 ?
: undefined immediately after reset
Address
C0
16
C1
16
C2
16
C3
16
C4
16
C5
16
C6
16
C7
16
C8
16
C9
16
CA
16
CB
16
CC
16
CD
16
CE
16
CF
16
D0
16
D1
16
D2
16
D3
16
D4
16
D5
16
D6
16
D7
16
D8
16
D9
16
DA
16
DB
16
DC
16
DD
16
DE
16
DF
16
Register
Port P0 (P0) Port P0 direction register (D0) Port P1 (P1) Port P1 direction register (D1) Port P2 (P2) Port P2 direction register (D2) Port P3 (P3) Port P3 direction register (D3) Port P4 (P4)
Port P4 direction register (D4) Port P5 (P5) OSD port control register (PF)
Port P6 (P6)
OSD control register (OC) Horizontal position register (HP) Block control register 1 (BC1) Block control register 2 (BC2) Block control register 3 (BC3) Block control register 4 (BC4) Block control register 5 (BC5) Block control register 6 (BC6) Block control register 7 (BC7) Block control register 8 (BC8) Block control register 9 (BC9) Block control register 10 (BC10) Block control register 11 (BC11) Block control register 12 (BC12)
Block control register 13 (BC13) Block control register 14 (BC14) Block control register 15 (BC15) Block control register 16 (BC16)
b7
Bit allocation State immediately after reset
OUT1OUT2
OC6OC7 OC4OC5 OC2OC3 OC0OC1 HP6HP7 HP4HP5 HP2HP3 HP0HP1
b0
b7
b0
?
16
00
?
16
00
?
16
00
???
????? 00000000 ???????? 0000000 ???????
RI2I1GB
00000000
0
?
????????
?
00
16
00
16 BC11BC12BC13BC14BC15BC16BC17BC18 BC21BC22BC23BC24BC25BC26BC27BC28 BC31BC32BC33BC34BC35BC36BC37BC38 BC41BC42BC43BC44BC45BC46BC47BC48 BC51BC52BC53BC54BC55BC56BC57BC58 BC61BC62BC63BC64BC65BC66BC67BC68 BC71BC72BC73BC74BC75BC76BC77BC78 BC81BC82BC83BC84BC85BC86BC87BC88 BC91BC92BC93BC94BC95BC96BC97BC98
BC101BC102BC103BC104BC105BC106BC107BC108 BC111BC112BC113BC114BC115BC116BC117BC118 BC121BC122BC123BC124BC125BC126BC127BC128 BC131BC132BC133BC134BC135BC136BC137BC138 BC141BC142BC143BC144BC145BC146BC147BC148 BC151BC152BC153BC154BC155BC156BC157BC158 BC161BC162BC163BC164BC165BC166BC167BC168
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
Fig. 3. Memory map of special function register 1 (SFR1) (1)
10
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
■SFR1 area (addresses E016 to FF16)
: Nothing is allocated
: Fix this bit to “0” ( do not write “1”) : Fix this bit to “1” ( do not write “0”)
: “0” immediately after reset
0
: “1” immediately after reset
1 ?
: undefined immediately after reset
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
and ON-SCREEN DISPLAY CONTROLLER
Address Register
Caption position register (CP)
E0
16
Start bit position register (SP)
E1
16
E2
16
Window register (WN)
E3
16
Sync slice register (SSL)
E4
16
Data register 1 (CD1)
E5
16
Data register 2 (CD2)
E6
16
Clock run-in register 1 (CR1) Clock run-in register 2 (CR2)
E7
16
Clock run-in detect register 1 (CRD1)
E8
16
Clock run-in detect register 2 (CRD2)
E9
16
Data slicer control register 1 (DSC1)
EA
16
Data slicer control register 2 (DSC2)
EB
16
EC
16
Data register 3 (CD3) Data register 4 (CD4)
ED
16
A-D conversion register (AD)
EE
16
EF
16
A-D control register (ADCON)
F0
16
Timer 1 (TM1) Timer 2 (TM2)
F1
16
F2
16
Timer 3 (TM3)
F3
16
Timer 4 (TM4)
F4
16
Timer mode register 1 (TM1)
F5
16
Timer mode register 2 (TM2)
I2C
F6 F7 F8
F9 FA FB FC FD FE FF
data shift register (S0)
16 16
I2C
address register (S0D)
I2C
status register (S1)
16
I2C
control register (S1D)
16
I2C
clock control register (S2)
16 16
CPU mode
16
Interrupt request
16
Interrupt request Interrupt control
16 16
Interrupt control
register (CPUM)
register 1 (ICON1) register 2 (ICON2)
b7
register 1 (IREQ1) register 2 (IREQ2)
SSL7
ACK
Bit allocation State immediately after reset
b0
b7
1 00?? ?? ?
CP0CP1CP2CP3CP4
00
SP0SP1SP2SP3SP4SP5SP6SP7
0 0000 00 0
WN0WN1WN2WN3WN4WN5
16
0 0000 01 1
? ?
CR11 CR21
0 1010000 1 00111 10
CRD10CRD11CRD12CRD15CRD17CRD15 CRD15CRD15
000 00 00 0
CRD20CRD21CRD22CRD25CRD27CRD25 CRD25CRD25
000 01 00 1
DSC10DSC11DSC12DSC15DSC17 DSC20DSC21DSC22DSC25DSC27
? 0000 00 0
0
00 00
?
16
16
?
ADVREF
ADV
TM15TM16TM17
TM25
TM26TM27
ADSTR
ADIN0ADIN1
TM10TM11TM12TM13TM14 TM20TM21TM22TM23TM24
?000?000
16
FF 07
16
FF
16
07
16
00000000 00000000
?
BSEL0BSEL1
ACK BIT
ADE
10 BIT SAD
FAST MODE
IICRT56R
IICET56ET56S
INT2R
CK0
1MSR
1MSE
CM2
SAD0SAD1SAD2SAD3SAD4SAD5SAD6 RBW
LRBAD0AASALPINBBTRXMST BC0BC1BC2ES0ALS CCR0CCR1CCR2CCR3CCR4 CM0CM1CM7 CM5CM6
TM1RTM2RTM3RTM4RCRTRVSCRADR
INT1R
DSRSIOR
TM1ETM2ETM3ETM4ECRTEVSCE INT1EDSESIOEINT2E
0
0111 00 0000 0000
0000 00
00
0000 0000 0000 0000
00
16
000001?0
00
16
00
16
CK0
b0
1
Fig. 4. Memory map of special function register 1 (SFR2) (2)
11
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■SFR2 area (addresses 20016 to 21F16)
: Nothing is allocated
: Fix this bit to “0” ( do not write “1”) : “0” immediately after reset
0
: “1” immediately after reset
1 ?
: undefined immediately after reset
Address Register
200 201 202 203
204 205 206
207 208 209 20A 20B 20C
20D 20E 20F 210
211 212 213 214 215
216 217 218
219 21A 21B 21C 21D 21E 21F
PWM0 register (PWM0)
16 16
PWM1 register (PWM1)
16
PWM2 register (PWM2)
16
PWM3 register (PWM3)
16
PWM4 register (PWM4)
16
PWM5 register (PWM5)
16
PWM6 register (PWM6)
16
Clock run-in detect register (CRD3)
16 16
Clock run-in register (CR3)
16
PWM mode register 1 (PN)
16
PWM mode register 2 (PW)
16
Timer 5 (TM5) Timer 6 (TM6)
16 16
Sync pulse counter register (SYC)
16
Data slicer control register 3 (DSC3)
16
Interrupt interval determination register (RI)
16
Interrupt interval determination control register (RE)
16
Serial I/O mode register (SM)
16
Serial I/O register (SIO)
16 16 16
Clock source control register (CS)
16
I/O polarity control register (PC)
16
Raster color register (RC)
Extra font color register (EC)
16
16 16
Border color register (FC) Window H register 1 (WH1)
16 16
Window L register 1 (WH1) Window H register 2 (WH2)
16
Window L register 2 (WH2)
16
b7
Bit allocation State immediately after reset
DSC36 DSC34DSC33
INT3
INT3
AD/INT3
AD/INT3 SEL
SEL
POL
POL INT3
AD/INT3 SEL
POL
INT3
AD/INT3 SEL
POL INT3
AD/INT3 SEL
POL INT3
AD/INT3 SEL
POL INT3
AD/INT3 SEL
POL
CRD31CRD32CRD33CRD34CRD35
POL
FC2
b0
b7
b0
? ? ? ? ? ?
? 0000 00 0
? 0 0000 00 0 ??? ?? ?? ?
ENABLE
? ???0 ?? 0 0 ???? ?? ?
PW0PW1PW2PW3PW4PW5PW6
07
16
FF
16
?
SYC0
SYC1SYC2SYC3SYC4SYC5
DSC30DSC31DSC32DSC37 DSC35
?000000?
00
16
?
00
RE0RE1RE2RE3RE4RE5
RE1RE2RE3RE4RE5
SM0RE1RE2RE3SM4RE5
SM1SM2SM3SM5
16
000000 00 ? ?
RE1RE2RE3RE5
CS0CS4 CS1CS2CS3CS5CS6 PC0RE1RE2RE3PC4RE5
PC1PC2PC3PC5PC6PC7
RC0RE1RE2RE3RC4RE5
RC1RC2RC3RC5RC6RC7 RE1RE2RE3RE5
00
?0 ???? ??
010000 00
16
0? ? ?00 00 ?
FC0FC1FC3FC4
0? ? ?00 00 ?
?
WH20WH21
???
WL20WL21
??????
?????
??
Fig. 5. Memory map of special function register 2 (SFR2) (1)
12
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
■SFR2 area (addresses 22016 to 23F16)
: Nothing is allocated
?
: undefined immediately after reset
and ON-SCREEN DISPLAY CONTROLLER
Address Register
220 221 222 223
224 225 226
227 228 229 22A 22B 22C
22D 22E 22F
230 231
232 233 234 235
236 237 238
239 23A 23B 23C 23D 23E 23F
Vertical position register 1
16
Vertical position register 1
16
Vertical position register 1
16
Vertical position register 14 (VP14)
16
Vertical position register 1
16
Vertical position register 1
16
Vertical position register 1
16
Vertical position register 18 (VP18)
16
Vertical position register 1
16
Vertical position register 1
16
Vertical position register 1
16
Vertical position register 1
16
Vertical position register 1
16
Vertical position register 1
16
Vertical position register 1
16
Vertical position register 1
16
Vertical position register 2
16
Vertical position register 2
16
Vertical position register 2
16
Vertical position register 2
16 16
Vertical position register 2
16
Vertical position register 2 Vertical position register 27 (VP27)
16 16
Vertical position register 2 Vertical position register 2
16
Vertical position register 2
16
Vertical position register 2
16
Vertical position register 2
16
Vertical position register 2
16
Vertical position register 2
16 16
Vertical position register 2
16
Vertical position register 2
(VP11)
1
(VP12)
2
(VP13)
3
(VP15)
5
(VP16)
6
(VP17)
7
(VP19)
9
(VP110)
10
(VP111)
11
(VP112)
12
(VP113)
13
(VP114)
14
(VP115)
15
(VP116)
16
(VP21)
1
(VP22)
2
(VP23)
3
(VP24)
4
(VP25)
5
(VP26)
6
(VP28)
8
(VP29)
9
(VP210)
10
(VP211)
11
(VP212)
12
(VP213)
13
(VP214)
14
(VP215)
15
(VP216)
16
b7
Bit allocation State immediately after reset
b0
b7
VP111
VP112VP113VP114VP115VP116VP117VP118
VP121VP122VP123VP124VP125VP126VP127VP128 VP131VP132VP133VP134VP135VP136VP137VP138 VP141VP142VP143VP144VP145VP146VP147VP148 VP151VP152VP153VP154VP155VP156VP157VP158 VP161VP162VP163VP164VP165VP166VP167VP168 VP171VP172VP173VP174VP175VP176VP177VP178 VP181VP182VP183VP184VP185VP186VP187VP188 VP191VP192VP193VP194VP195VP196VP197VP198
VP1101VP1102VP1103VP1104VP1105VP1106VP1107VP1108 VP1111VP1112VP1113VP1114VP1115VP1116VP1117VP1118 VP1121VP1122VP1123VP1124VP1125VP1126VP1127VP1128 VP1131VP1132VP1133VP1134VP1135VP1136VP1137VP1138 VP1141VP1142VP1143VP1144VP1145VP1146VP1147VP1148 VP1151VP1152VP1153VP1154VP1155VP1156VP1157VP1158 VP1161VP1162VP1163VP1164VP1165VP1166VP1167VP1168
VP211VP212 VP221VP222 VP231VP232 VP241VP242 VP251VP252 VP261VP262 VP271VP272 VP281VP282 VP291VP292
VP2101VP2102 VP2111VP2112 VP2121VP2122 VP2131VP2132 VP2141VP2142 VP2151VP2152 VP2161VP2162
? ? ? ? ? ? ? ? ?
? ? ? ?
? ? ?
b0
???????? ???????? ???????? ????????
???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ???????? ????????
Fig. 6. Memory map of special function register 2 (SFR2) (2)
13
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
: Nothing is allocated
1
: “1” immediately after reset
?
: undefined immediately after reset
Register
b7
Processor status register (PS) Program counter (PCH)
Program counter (PCL)
Fig. 7. Internal state of processor status register and program counter at reset
Bit allocation State immediately after reset
I ZCDBTVN???????
b0
b7
Contents of address FFFF Contents of address FFFE
b0
1
16 16
14
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER

INTERRUPTS

Interrupts can be caused by 18 different sources consisting of 4 ex­ternal, 12 internal, 1 software, and reset. Interrupts are vectored in­terrupts with priorities shown in Table 1. Reset is also included in the table because its operation is similar to an interrupt. When an interrupt is accepted, (1) The contents of the program counter and processor status
register are automatically stored into the stack.
(2) The interrupt disable flag I is set to “1” and the corresponding
interrupt request bit is set to “0.”
(3) The jump destination address stored in the vector address enters
the program counter. Other interrupts are disabled when the interrupt disable flag is set to “1.” All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit. The interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are in interrupt control registers 1 and 2. Figure 8 shows the structure of the interrupt-related registers. Interrupts other than the BRK instruction interrupt and reset are ac­cepted when the interrupt enable bit is “1,” interrupt request bit is “1,” and the interrupt disable flag is “0.” The interrupt request bit can be set to “0” by a program, but not set to “1.” The interrupt enable bit can be set to “0” and “1” by a program. Reset is treated as a non-maskable interrupt with the highest priority. Figure 9 shows interrupt control.
Interrupt Causes
(1) VSYNC and OSD interrupts
The VSYNC interrupt is an interrupt request synchronized with the vertical sync signal. The OSD interrupt occurs after character block display to the CRT is completed.
(2) INT1, INT2, INT3 interrupts
With an external interrupt input, the system detects that the level of a pin changes from “L” to “H” or from “H” to “L,” and generates an interrupt request. The input active edge can be selected by bits 3, 4 and 6 of the interrupt interval determination control reg­ister (address 021216) : when this bit is “0,” a change from “L” to “H” is detected; when it is “1,” a change from “H” to “L” is de­tected. Note that all bits are cleared to “0” at reset.
(3) Timer 1, 2, 3 and 4 interrupts
An interrupt is generated by an overflow of timer 1, 2, 3 or 4.
(4) Serial I/O interrupt
This is an interrupt request from the clock synchronous serial I/O function.
(5) f(XIN)/4096 interrupt
This interrupt occurs regularly with a f(XIN)/4096 period. Set bit 0 of the PWM mode register 1 to “0.”
(6) Data slicer interrupt
An interrupt occurs when slicing data is completed.
(7) Multi-master I2C-BUS interface interrupt
This is an interrupt request related to the multi-master I2C-BUS interface.
(8) A-D conversion interrupt
An interrupt occurs at the completion of A-D conversion. Since A-D conversion interrupt and the INT3 interrupt share the same vector, an interrupt source is selected by bit 7 of the interrupt interval determination control register (address 021216).
Table 1. Interrupt vector addresses and priority
Interrupt source Reset OSD interrupt INT1 interrupt Data slicer interrupt Serial I/O interrupt Timer 4 interrupt f(XIN)/4096 interrupt VSYNC interrupt Timer 3 interrupt Timer 2 interrupt Timer 1 interrupt A-D convertion · INT3 interrupt INT2 interrupt Multi-master I2C-BUS interface interrupt Timer 5 · 6 interrupt BRK instruction interrupt
Priority
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16
Vector addresses FFFF16, FFFE16 FFFD16, FFFC16 FFFB16, FFFA16 FFF916, FFF816 FFF716, FFF616 FFF516, FFF416 FFF316, FFF216 FFF116, FFF016 FFEF16, FFEE16 FFED16, FFEC16 FFEB16, FFEA16 FFE916, FFE816 FFE716, FFE616 FFE516, FFE416 FFE316, FFE216 FFDF16, FFDE16
Remarks
Non-maskable
Active edge selectable
Active edge selectable
Active edge selectable Active edge selectable
Non-maskable (software interrupt)
15
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(9)Timer 5 · 6 interrupt
An interrupt is generated by an overflow of timer 5 or 6. Their priorities are same, and can be switched by software.
(10)BRK instruction interrupt
This software interrupt has the least significant priority. It does not have a corresponding interrupt enable bit, and it is not af­fected by the interrupt disable flag I (non-maskable).
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset
Interrupt request
Fig. 9. Interrupt control
7
0
Interrupt request register 1 (IREQ1: address 00FC
Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Timer 4 interrupt request bit OSD interrupt request bit V
SYNC
interrupt request bit
A-D conversion ⋅ INT3 interrupt request bit
7
16
)
0
0
Interrupt request register 2 (IREQ2: address 00FD
16
)
INT1 interrupt request bit Data slicer interrupt request bit Serial I/O interrupt request bit f(XIN)/4096 interrupt request bit
INT2 interrupt request bit Multi-master I2C-BUS
interface interrupt request bit Timer 5 ⋅ 6 interrupt request bit
Fix this bit to “0.”
0 : No interrupt request issued 1 : Interrupt request issued
7
0
Interrupt control register 1 ( ICON1: address 00FE
Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit Timer 4 interrupt enable bit OSD interrupt enable bit V
SYNC
interrupt enable bit
A-D conversion ⋅ INT3 interrupt request bit
Fig. 8. Structure of interrupt-related registers
16
7
16
)
0 : Interrupt disabled 1 : Interrupt enabled
0
Interrupt control register 2 ( ICON2 : address 00FF
INT1 interrupt enable bit Data slicer interrupt enable bit Serial I/O interrupt enable bit f(XIN)/4096 interrupt enable bit
INT2 interrupt enable bit
2
Multi-master I
C-BUS
interface enable bit Timer 5 ⋅ 6 interrupt enable bit
Timer 5 ⋅ 6 interrupt switch bit
0 : Timer 5 1 : Timer 6
16
)
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER

TIMERS

The M37271MF-XXXSP has 6 timers: timer 1, timer 2, timer 3, timer 4, timer 5, and timer 6. All timers are 8-bit timers with the 8-bit timer latch. The timer block diagram is shown in Figure 11. All of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. The value is set to a timer at the same time by writing a count value to the corresponding timer latch (addresses 00F016 to 00F316 : timers 1 to 4, addresses 020C16 and 020D16 : timers 5 and 6). The count value is decremented by 1. The timer interrupt request bit is set to “1” by a timer overflow at the next count pulse after the count value reaches “0016”.
(1) Timer 1
Timer 1 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
f(XIN)/4096 or f(XCIN)/4096
•
External clock from the P42/TIM2 pin
•
The count source of timer 1 is selected by setting bits 5 and 0 of the timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 1 interrupt request occurs at timer 1 overflow.
(2) Timer 2
Timer 2 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
Timer 1 overflow signal
•
External clock from the P42/TIM2 pin
•
The count source of timer 2 is selected by setting bits 4 and 1 of the timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8­bit prescaler. Timer 2 interrupt request occurs at timer 2 overflow.
(3) Timer 3
Timer 3 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
f(XCIN)
•
External clock from the P43/TIM3 pin
•
The count source of timer 3 is selected by setting bit 0 of the timer mode register 2 (address 00F516) and bit 6 at address 00C716. Ei­ther f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 3 interrupt request occurs at timer 3 overflow.
(5) Timer 5
Timer 5 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
Timer 2 overflow signal
•
Timer 4 overflow signal
•
The count source of timer 3 is selected by setting bit 6 of the timer mode register 1 (address 00F416) and bit 7 of the timer mode regis­ter 2 (address 00F516). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 5 interrupt request occurs at timer 5 overflow.
(6) Timer 6
Timer 6 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
Timer 5 overflow signal
•
The count source of timer 6 is selected by setting bit 7 of the timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 5 overflow signal is a count source for the timer 6, the timer 5 functions as an 8-bit prescaler. Timer 6 interrupt request occurs at timer 6 overflow.
At reset, timers 3 and 4 are connected by hardware and “FF16” is automatically set in timer 3; “0716” in timer 4. The f(XIN) ✽ /16 is se­lected as the timer 3 count source. The internal reset is released by timer 4 overflow at these state, the internal clock is connected. At execution of the STP instruction, timers 3 and 4 are connected by hardware and “FF16” is automatically set in timer 3; “0716” in timer 4. However, the f(XIN) ✽ /16 is not selected as the timer 3 count source. So set both bit 0 of the timer mode register 2 (address 00F516) and bit 6 at address 00C716 to “0” before the execution of the STP in­struction (f(XIN) ✽ /16 is selected as the timer 3 count source). The internal STP state is released by timer 4 overflow at these state, the internal clock is connected. Because of this, the program starts with the stable clock. ✽ : When bit 7 of the CPU mode register (CM7) is “1,” f(XIN) be-
comes f(XCIN).
The structure of timer-related registers is shown in Figure 10.
(4) Timer 4
Timer 4 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
f(XIN)/2 or f(XCIN)/2
•
f(XCIN)
•
The count source of timer 3 is selected by setting bits 4 and 1 of the timer mode register 2 (address 00F516). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8­bit prescaler. Timer 4 interrupt request occurs at timer 4 overflow.
17
70
Timer mode register 1 (TMR1 : address 00F416)
Timer 1 count source selection bit 1 0 : f(X
IN
)/16 or f(X
CIN
)/16 (Note)
1 : Count source selected by bit 5
of TMR1
Timer 2 count source selection bit 1 0 : Count source selected by bit 4 of
TMR1
1 : External clock from P42/TIM2 pin
Timer 1 count stop bit 0 : Count start 1 : Count stop
Timer 2 count stop bit 0 : Count start 1 : Count stop
Timer 2 count source selection bit 2 0 : f(XIN)/16 or f(X
CIN
)/16 (Note)
1 : Timer 1 overflow
Timer 1 count source selection bit 2 0 : f(XIN)/4096 or f(X
CIN
)/4096 (Note)
1 : External clock from P42/TIM2
pin
Timer 5 count source selection bit 2 0 : Timer 2 overflow 1 : Timer 4 overflow
Timer 6 count source selection bit 0 : f(XIN)/16 or f(X
CIN
)/16 (Note)
1 : Timer 5 overflow
70
Timer mode register 2 (TMR2 : address 00F5
16
)
Timer 3 count stop bit 0 : Count start 1 : Count stop
Timer 4 count stop bit 0 : Count start 1 : Count stop
Timer 5 count stop bit 0 : Count start 1 : Count stop
Timer 6 count stop bit 0 : Count start 1 : Count stop
Timer 5 count source selection bit 1 0 : f(XIN)/16 or f(X
CIN
)/16 (Note)
1 : Count source selected by bit 6
of TMR1
Timer 3 count source selection bit
0 0 : f(XIN)/16 or f(X
CIN
)/16 (Note)
1 0 : f(X
CIN
) 0 1 : 1 1 :
(Bit 6 at address 00C7
16
)
External clock from P43/TIM3 pin
Timer 4 count source selection bits b4 b1 0 0 : Timer 3 overflow 0 1 : f(XIN)/16 or f(X
CIN
)/16 (Note)
1 0 : f(XIN)/2 or f(X
CIN
)/2 (Note)
1 1 : f(X
CIN
)
b0
Note : Either f(X
IN
) or f(X
CIN
) is selected by bit 7 of the CPU mode register.
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Fig. 10. Structure of timer-related registers
18
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
CIN
X
XIN
P42/TIM2
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
CM7
1/2
TMR15
1/8
TMR10
TMR12
TMR14
Timer 2 latch (8)
TMR11
TMR13
1/4096
and ON-SCREEN DISPLAY CONTROLLER
Data bus
8
Timer 1 latch (8)
8
Timer 1 (8)
8
8
8
Timer 2 (8)
8
Timer 1 interrupt request
Timer 2 interrupt request
P4
3/TIM3
Selection gate : Connected to
TMR1 : Timer mode register 1 TMR2 : Timer mode register 2 TM3EL : Timer 3 count source switch bit (address 00C7 CM : CPU mode register
TMR21
black colored side at reset
16)
TMR20
TMR24
TMR27
TM3EL
TMR22
TMR21
TMR23
TMR16
TMR25
Timer 3 latch (8)
8
Timer 3 (8)
Timer 4 latch (8)
8
Timer 4 (8)
Timer 5 latch (8)
8
Timer 5 (8)
8
FF16
8
8
0716
8
8
8
8
Reset STP instruction
Timer 3 interrupt request
Timer 4 interrupt request
Timer 5 interrupt request
Notes 1: “H” pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more.
2: When the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal. 3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.
Fig. 11. Timer block diagram
TMR17
TMR26
Timer 6 latch (8)
8
Timer 6 (8)
Timer 6 interrupt request
8
19
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER

SERIAL I/O

The M37271MF-XXXSP has a built-in serial I/O which can either trans­mit or receive 8-bit data in serial in the clock synchronous mode. The serial I/O block diagram is shown in Figure 12. The synchroniz­ing clock I/O pin (SCLK), and data output pin (SOUT) also function as port P4, data input pin (SIN) also functions as port P1. Bit 2 of the serial I/O mode register (address 021316) selects whether the synchronizing clock is supplied internally or externally (from the P46/SCLK pin). When an internal clock is selected, bits 1 and 0 select whether f(XIN) is divided by 8, 16, 32, or 64. To use P45/SOUT and P46/SCLK pins for serial I/O, set the corresponding bits of the port P4 direction register (address 00C916) to “0.” To use P17/SIN pin for serial I/O, set the corresponding bit of the port P1 direction register (address 00C316) to “0.”
X
CIN
1/2
X
P46/S
CLK
IN
1/2
CM7
1/2
Synchronization
circuit
SM2
S
Serial I/O counter (8)
The operation of the serial I/O function is described below. The func­tion of the serial I/O differs depending on the clock source; external clock or internal clock.
Data bus
Frequency divider
1/2
1/81/4 1/16
SM1 SM0
Selection gate: Connect to
black colored side at reset.
CM : CPU mode register SM : Serial I/O mode register
Serial I/O interrupt request
P45/S
OUT
: LSB
MSB
SM5
(Note)
P17/S
IN
Serial I/O shift register (8)
(Address 021416)
8
Note : When the data is set in the serial I/O register (address 021416), the register functions as the serial I/O shift register.
Fig. 12. Serial I/O block diagram
20
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Internal clock—the serial I/O counter is set to “7” during write cycle into the serial I/O register (address 021416), and transfer clock goes “H” forcibly. At each falling edge of the transfer clock after the write cycle, serial data is output from the SOUT pin. Transfer direction can be selected by bit 5 of the serial I/O mode register. At each rising edge of the transfer clock, data is input from the SIN pin and data in the serial I/O register is shifted 1 bit. After the transfer clock has counted 8 times, the serial I/O counter becomes “0” and the transfer clock stops at “H.” At this time the inter­rupt request bit is set to “1.” External clock—when an external clock is selected as the clock source, the interrupt request is set to “1” after the transfer clock has counted 8 times. However, transfer operation does not stop, so con­trol the clock externally. Use the external clock of 500kHz or less with a duty cycle of 50%. The serial I/O timing is shown in Figure 13. When using an external clock for transfer, the external clock must be held at “H” for initializing the serial I/O counter. When switching between an internal clock and an external clock, do not switch during transfer. Also, be sure to ini­tialize the serial I/O counter after switching.
Notes 1: On programming, note that the serial I/O counter is set by
writing to the serial I/O register with the bit managing in­structions as SEB and CLB instructions.
2: When an external clock is used as the synchronizing clock,
write transmit data to the serial I/O register at “H” of the transfer clock input level.
7
0
and ON-SCREEN DISPLAY CONTROLLER
0
0
Serial I/O mode register (SM : address 0213
Internal synchronizing clock selection bits b1 b0
0 0 : f(X
IN)/8 or f(XCIN)/8
0 1 : f(XIN)/16 or f(XCIN)/16 1 0 : f(X
IN)/32 or f(XCIN)/32
1 1 : f(XIN)/64 or f(XCIN)/64
Synchronizing clock selection bit
0 : External clock 1 : Internal clock
Port function selection bit
1, P13 functions as port
0 : P1 1 : SCL1, SDA1
Port function selection bit
0 : P12, P14 functions as port 1 : SCL2, SDA2
Transfer direction selection bit
0 : LSB first 1 : MSB first
Fix these bits to “0”
16)
Synchroninzing clock
Transfer clock
Serial I/O register write signal
Serial I/O output S
Serial I/O input
Note : When an internal clock is selected, the S
S
OUT
IN
Fig. 13. Serial I/O timing (for LSB first)
Fig. 14. Structure of serial I/O mode register
D
0
D
1
D
2
D
3
D
4
D
OUT
pin is at high-impedance after transfer is completed.
(Note)
5
D
6
D
7
Interrupt request bit is set to “1”
21
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER

PWM OUTPUT FUNCTION

The M37271MF-XXXSP is equipped with seven 8-bit PWMs (PWM0– PWM6). PWM0–PWM6 have the same circuit structure and an 8-bit resolution with minimum resolution bit width of 4 µs (for f(XIN) = 8 MHz) and repeat period of 1024 µs. Figure 15 shows the PWM block diagram. The PWM timing generat­ing circuit applies individual control signals to PWM0–PWM6 using f(XIN) divided by 2 as a reference signal.
(1) Data Setting
When outputting PWM0–PWM6, set 8-bit output data in the PWMi register (i means 0 to 6; addresses 020016 to 020616).
(2) Transmitting Data from Register to PWM circuit
Data transfer from the 8-bit PWM register to 8-bit PWM circuit is executed at writing data to the register. The signal output from the 8-bit PWM output pin corresponds to the contents of this register.
(3) Operating of 8-bit PWM
The following is the explanation about PWM operation. At first, set the bit 0 of PWM mode register 1 (address 020A16) to “0” (at reset, bit 0 is already set to “0” automatically), so that the PWM count source is supplied. PWM0–PWM3 are also used as pins P04–P07, PWM4–PWM6 are also used as pins P00–P02, respectively. Set the corresponding bits of the port P0 direction register to “1” (output mode). And select each output polarity by bit 3 of the PWM mode register 1 (address 020A16). Then, set bits 7 to 0 of the PWM output control register 2 to “1” (PWM output). The PWM waveform is output from the PWM output pins by setting these registers. Figure 16 shows the 8-bit PWM timing. One cycle (T) is composed of 256 (28) segments. The 8 kinds of pulses relative to the weight of each bit (bits 0 to 7) are output inside the circuit during 1 cycle. Refer to Figure 16 (a). The 8-bit PWM outputs waveform which is the logi­cal sum (OR) of pulses corresponding to the contents of bits 0 to 7 of the 8-bit PWM register. Several examples are shown in Figure 16 (b). 256 kinds of output (“H” level area: 0/256 to 255/256) are se­lected by changing the contents of the PWM register. A length of entirely “H” output cannot be output, i.e. 256/256.
(4) Output after Reset
At reset, the output of ports P00–P02 and P04–P07 is in the high­impedance state, port P50 outputs “L,” and the contents of the PWM register and the PWM circuit are undefined. Note that after reset, the PWM output is undefined until setting the PWM register.
22
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
Data bus
X
PWM0 register (Address 0200
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
16
PWM timing
generating
circuit
)
IN
1/2
ENABLE
b7 b0
and ON-SCREEN DISPLAY CONTROLLER
Selection gate :
Connected to black colored
side at reset.
Inside of
8
8-bit PWM circuit
PWM1 register (Address 020116)
PWM2 register (Address 020216)
PWM3 register (Address 020316)
PWM4 register (Address 020416)
PWM5 register (Address 020516)
PWM6 register (Address 020616)
is as same contents with the others.
POL
P0
D0
4
4
PW0
D0
P0
5
5
PW1
D0
P0
6
6
PW2
D0
P0
7
7
PW3
D0
P0
0
0
PW4
D0
P0
1
1
PW5
D0
P0
2
2
PW6
: PWM mode register 1 (address 020A
PN
: PWM mode register 2 (address 020B
PW
: Port P0 register (address 00C0
P0
: Port P0 direction register (address 00C1
D0
16
)
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
16 16
) )
16
)
Fig. 15. PWM block diagram
23
(a) Pulses showing the weight of each bit
1 3 5 7 9 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 255
4 12 20 28 36 44 52 60 68 76 84 92 100 108 116 124 132 140 148 156 164 172 180 188 196 204 212 220 228 236 244 252
8
16 48 80 112 144 176 208 240
24
40 56
72 88
104 120
136 152
168 184
200 216
232 248
32
96
160
224
64
192
Bit 7
2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
128
Bit 0
PWM output t = 4
µ
s T = 1024
µ
s
f(X
IN
) = 8 MHz
(b) Example of 8-bit PWM
t
00
16
(0)
01
16
(1)
18
16
(24)
FF
16
(255)
T = 256 t
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Fig. 16. 8-bit PWM timing
24
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
PWM mode register 1 (PN: address 020A
16
)
0
and ON-SCREEN DISPLAY CONTROLLER
07
PWM mode register 2 (PW: address 020B
16
)
PWM count source selection bit 0 : Count source supply 1 : Count source stop
PWM output polarity selection bit 0 : Positive polarity 1 : Negative polarity
P04/PWM0 output selection bit 0 : P0
4
output
1 : PWM0 output
5
/PWM1 output selection bit
P0
5
0 : P0
output
1 : PWM1 output
P0
6
/PWM2 output selection bit
6
0 : P0
output
1 : PWM2 output
P0
7
/PWM3 output selection bit
7
0 : P0
output
1 : PWM3 output
P0
0
/PWM4 output selection bit
0
0 : P0
output
1 : PWM4 output
1
/PWM5 output selection bit
P0
1
0 : P0
output
1 : PWM5 output
P0
2
/PWM6 output selection bit
2
0 : P0
output
1 : PWM6 output
Fig. 17. Structure of PWM-related registers
Fix this bit to “0.”
25
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
A-D CONVERTER (1)A-D Conversion Register (AD)
A-D conversion reigister is a read-only register that stores the result of an A-D conversion. This register should not be read during A-D conversion.
(2)A-D Control Register (ADCON)
The A-D control register controls A-D conversion. Bits 1 and 0 of this register select analog input pins. When these pins are not used as anlog input pins, they are used as ordinary I/O pins. Bit 3 is the A-D conversion completion bit, A-D conversion is started by writing “0” to this bit. The value of this bit remains at “0” during an A-D conversion, then changes to “1” when the A-D conversion is completed. Bit 4 controls connection between the resistor ladder and VCC. When not using the A-D converter, the resistor ladder can be cut off from the internal VCC by setting this bit to “0.” This can realize the low­power dissipation.
(3)Comparison Voltage Generator (Resistor
Ladder)
The voltage generator divides the voltage between VSS and VCC by 256, and outputs the divided voltages to the comparator as the refer­ence voltage Vref.
(4)Channel Selector
The channel selector connects an analog input pin selected by bits 1 and 0 of the A-D control register to the comparator.
(5)Comparator and Control Circuit
The conversion result of the analog input voltage and the reference voltage “Vref” is stored in the A-D conversion register. The A-D con­version completion bit and A-D conversion interrupt request bit are set to “1” at the completion of A-D conversion.
70 0
Fig. 18. Structure of A-D control register
A-D control register (ADCON: address 00EF16)
Analog input pin selection bits
b1 b0 0 0 : P26/AD1 0 1 : P25/AD2 1 0 : P24/AD3 1 1 : P40/AD4
A-D conversion completion bit 0 : Conversion in purogress 1 : Conversion completed
VCC connection selection bit
0 : OFF 1 : ON Fix this bit to “0.”
A-D control register (address 00EF
P26/AD1
5
/AD2
P2
4
/AD3
P2 P4
0
/AD4
Fig. 19. A-D comparator block diagram
16
)
Compa­rator
Channel selector
Data bus
b7 b0
2
A-D control circuit
A-D conversion register
Switch tree
Resistor ladder
VSSV
8
(address 00EE16)
CC
A-D conversion interrupt request
26
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(6) Conversion Method
1Set bit 7 of the interrupt interval determination control register (ad-
dress 021216) to “1” to generate an interrupt request at comple­tion of A-D conversion.
2Set the A-D conversion · INT3 interrupt request bit to “0” (even
when A-D conversion is started, the A-D conversion · INT3 inter­rupt bit is not set to “0” automatically).
3When using A-D conversion interrupt, enable interrupts by setting
A-D conversion · INT3 interrupt request bit to “1” and setting the interrupt disable flag to “0.”
4Set the VCC connection selection bit to “1” to connect VCC to the
resistor ladder.
5Select analog input pins by setting the analog input selection bit of
the A-D control register.
6Set the A-D conversion completion bit to “0.” This write operation
starts the A-D conversion. Do not read the A-D conversion regis­ter during the A-D conversion.
7Verify the completion of the conversion by the state (“1”) of the
A-D conversion completion bit, that (“1”) of A-D conversion · INT3 interrupt bit, or the occurrence of an A-D conversion interrupt.
8Read the A-D conversion register to obtain the conversion results.
Note : When the ladder resistor is disconnect from VCC, set the VCC
connection selection bit to “0” between steps 7and 8.
(7) Internal Operation
At the time when the A-D conversion starts, the following operations are automatically performed.
1The A-D conversion register is set to “0016.” 2The most significant bit of the A-D conversion register becomes
“1, ” and the comparison voltage “Vref” is input to the comparator. At this point, Vref is compared with the analog input voltage “VIN .”
3Bit 7 is determined by the comparison result as follows.
When Vref < VIN : bit 7 holds “1”
When Vref > VIN : bit 7 becomes “0” With the above operations, the analog value is converted into a digi­tal value. The A-D conversion terminates in a maximum 50 machine cycles (12.5 µs at f(XIN) = 8 MHz) after it starts, and the conversion result is stored in the A-D conversion register. An A-D conversion interrupt request occurs at the same time of A-D conversion completion, the A-D conversion · INT3 interrupt request bit becomes “1.” The A-D conversion completion bit also becomes “1.”
Table 2. Expression for Vref and VREF
A-D conversion register contents “n”
(decimal notation)
00
Note: VREF indicates the voltage of internal VCC.
VREF
256
Vref (V)
✕ (n – 0.5)1 to 255
A-D conversion start
1st comparison start
2nd comparison start
3rd comparison start
Contents of A-D conversion register
00000000
1
0000000 1000000
1 12
100000
Reference voltage (V
V
REF
–
2
V
REF
±
2
V
REF
±
2
V
REF
8th comparison start
A-D conversion completion
(8th comparison completion)
Fig. 20. Changes in A-D conversion register and comparison voltage during A-D conversion
1234567
1
12345678
Digital value corresponding to
analog input voltage.
m
: Value determined by mth (m = 1 to 8) result
±±±
2
V
REF
512
V
REF
4
V
REF
4
V
REF
4
.......
ref
)
[V]
0
V
REF
–
512
V
REF
±
8
V
REF
8
REF
V
±
256
V
REF
–
512
.....
REF
V
–
512
27
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(8) Definition of A-D Conversion Accuracy
The definition of A-D conversion accuracy is described below. 1Relative accuracy
· Zero transition error (V0T)
The deviation of the input voltage at which A-D conversion output data changes from “0” to “1,” from the corresponding ideal A-D conversion characteristics between 0 and VREF.
V0T =
· Full-scale transition error (VFST)
The deviation of the input voltage at which A-D conversion output data changes from “255” to “254,” from the corresponding ideal A­D conversion characteristics between 0 and VREF.
VFST =
· Non-linearity error
The deviation of the actual A-D conversion characteristics, from the ideal A-D conversion characteristics between V0 and V254.
Non-linearity error =
(V0 –1/2 ✕ VREF/256)
1LSB
(VREF – 3/2 ✕ VREF/256) – V254
1LSB
Vn – (1LSB ✕ n + V0)
1LSB
[LSB]
[LSB]
[LSB]
· Differential non-linearity error
The deviation of the input voltage required to change output data by “1,” from the corresponding ideal A-D conversion characteris­tics between 0 and VREF.
(Vn+1 – Vn) – 1LSB
1LSB
2Absolute accuracy
· Absolute accuracy error
The deviation of the actual A-D conversion characteristics, from the ideal A-D conversion characteristics between 0 and VREF.
Absolute accuracy error =
Note: The analog input voltage “Vn” at which A-D conversion output
data changes from “n” to “n + 1” (n ; 0 to 254) is as follows (refer to Figure 18).
1LSB with respect to relative accuracy =
1LSBA with respect to absolute accuracy =
Vn – 1LSBA ✕ (n+1/2)
1LSBA
V254 – V0
254
VREF
256
[LSB]Differential non-linearity error =
[LSB]
[V]
[V]
Output data
255 254
n+1
n
Actual A-D conversion characteristics
1 2
0
Full-scale transition error (V
FST
)
Differential non­linearity error
A
1LSB
A
LSB
1LSB
V
0
V
1
Zero transition error (V0T)
1LSB
Non-linearity error
Absolute accuracy
Ideal A-D conversion characteristics between V
VnV
0
and V
n+1
254
V
254
3
LSB
A
2
Analog input
V
REF
voltage (V)
Fig. 21. Definition of A-D conversion precision
28
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER

DATA SLICER

The M37271MF-XXXSP includes the data slicer function for the closed caption decoder (referred to as the CCD). This function takes out the caption data superimposed in the vertical blanking interval of a composite video signal. A composite video signal which makes the sync chip’s polarity negative is input to the CVIN pin.
Composite video signal
Hundred of kiloohms to 1 MΩ
V
HOLD
1000 pF
External circuit
Note: Make the length of wiring which is
connected to V and CV so that a leakage current may not be generated when mounting a resistor or a capacitor on each pin.
HOLD, HLF, RVCO
IN pin as short as possible
Sync slice
(address
0.1µF
Low-pass filter
Reference voltage generating circuit
register 3
00E316)
0000101
470Ω
IN
CV
Clamping circuit
Sync slice circuit
+ –
Comparator
Data slicer control register 3 (address 0210
Clock run-in detect register 3 (address 0208
Clock run-in register 3 (address 0209
Data register 2 (address 00E5
16)
16)
16)
16)
560 pF
Data register 4 (address 00ED
1µF
H
When the data slicer function is not used, the data slicer circuit can be cut off by setting bit 0 of the data slicer control register 1 (address 00EA16) to “0.” Also, the timing signal generating circuit can be cut off by setting bit 0 of data slicer control register 2 (address 00EB16) to “0.” These settings can realize the low-power dissipation.
1 kΩ
200 pF
SYNC
Synchronizing signal counter
Synchronizing separation circuit
Timing signal generating circuit
Clock run-in determination circuit
Data slice line specification circuit
Start bit detecting circuit
Data clock generating circuit
16-bit shift register
high-order low-order
Data register 1 (address 00E4
16)
15 kΩ
HLF RVCO
16)
Interrupt request generating circuit
Data register 3 (address 00EC
Sync pulse counter register
16
(address 020F
)
Clock run-in register 2
16
(address 00E7
)
01 0111
Data slicer control register 2
16
(address 00EB
00
)
0
Data slicer control register 1
16
(address 00EA
)
000
Data slicer ON/OFF
Window register (address 00E2
16
)
00
0101
Clock run-in register 1 (address 00E6
16
)
100
Caption position register (address 00E0
16
)
Start bit position register
16
(address 00E1
)
Clock run-in detect register 1 (address 00E8
16
)
Clock run-in detect register 2 (address 00E9
16
)
Data slicer interrupt request
16)
Data bus
Fig. 22. Data slicer block diagram
29
MITSUBISHI MICROCOMPUTERS
M37271MF-XXXSP
M37271EF-XXXSP, M37271EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Figure 23 shows the structure of the data slicer control registers.
000
b2 b1 0 0 F2 0 1 F1 1 0 F1 and F2 1 1 F1 and F2
07
Data slicer control register 1
16
(DSC1: address 00EA
)
Data slicer control bit 0: Data slicer stopped 1: Data slicer operating
Field to be sliced data selection bit
Field of main data slice line
Field for setting reference voltage
F2 F1 F2 F1
Fix these bits to “0.”
Field determination flag
sep
0 :
H
sep
V
sep
H
1 :
sep
V
000
07
Data slicer control register 2 (DSC2: address 00EB
16
)
Timing signal generating circuit control bit 0: Stopped 1: Operating
Reference clock source selection bit 0: Video signal
SYNC
1: H
signal
Test bit: read-only
Fix these bits to “0.”
V-pulse shape determination flag 0: Match
1: Mismatch
Fix this bit to “0.”
Fix this bit to “0.”
Data latch completion flag for caption data in main data slice line
0: Data is not yet latched 1: Data is latched
Definition of fields 1 (F1) and 2 (F2)
sep
H
F1 :
SYNC
V
sep
V
sep
H
F2 :
SYNC
V
sep
V
Fig. 23. Structure of data slicer control registers
Test bit: read-only
07
Data slicer control register 3 (DSC3: address 0210
Line selection bit for slice voltage 0: Main data slice line
1: Sub-data slice line
Field to be sliced data selection bit
Field of sub-data
b2 b1
slice line
0 0 F2 0 1 F1 1 0 F1 and F2 1 1 F1 and F2
Setting bit of sub-data slice line
16
)
Field for setting reference voltage
F2 F1 F2 F1
30
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