Mitsubishi M37270EF-XXXSP, M37270MF-XXXSP, M37270EFSP Datasheet
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
DESCRIPTION
The M37270MF-XXXSP is a single-chip microcomputer designed with
CMOS silicon gate technology. It is housed in a 64-pin shrink plastic
molded DIP.
In addition to their simple instruction sets, the ROM, RAM and I/O
addresses are placed on the same memory map to enable easy programming.
The M37270MF-XXXSP has a OSD function and a data slicer function, so it is useful for a channel selection system for TV with a closed
caption decoder. The features of the M37270EF-XXXSP and the
M37270EFSP are similar to those of the M37270MF-XXXSP except
that these chips have a built-in PROM which can be written electrically.
FEATURES
Number of basic instructions .....................................................71
•
Memory size
•
The minimum instruction execution time
•
.......................................... 0.5µs (at 8 MHz oscillation frequency)
Power source voltage ..................................................5 V ± 10 %
•
Subroutine nesting ............................................. 128 levels (Max.)
•
Interrupts....................................................... 18 types, 16 vectors
•
8-bit timers .................................................................................. 6
•
Programmable I/O ports (Ports P0, P1, P2, P30, P31) .............. 26
•
Input ports (Ports P40–P46, P63, P64)......................................... 9
•
Output ports (Ports P32, P47, P5, P60–P62, P65–P67) ............. 16
•
12 V withstand ports ..................................................................11
•
LED drive ports ........................................................................... 2
•
Serial I/O ............................................................ 8-bit ✕ 1 channel
•
Multi-master I2C-BUS interface ............................... 1 (2 systems)
•
A-D converter (8-bit resolution) ................................... 4 channels
•
PWM output circuit........................................................... 8-bit ✕ 8
•
Interrupt interval determination circuit .........................................1
•
Power dissipation
•
In high-speed mode .......................................................... 165mW
(at V
slicer on)
In low-speed mode .......................................................... 0.33mW
(at V
Data slicer
•
ROM ........................................................60 K bytes
RAM........................................................1024 bytes
ROM for OSD ....................................... 14464 bytes
RAM for OSD ......................................... 1920 bytes
CC = 5.5V, 8MHz oscillation frequency, CRT on, and Data
CC = 5.5V, 32kHz oscillation frequency)
OSD function
•
Display characters ...............................40 characters ✕ 16 lines
Kinds of characters .....................................................320 kinds
(In EXOSD mode, they can be combined with 32 kinds of extra
fonts)
Dot structure ........................................CC mode : 16 ✕ 26 dots
Kinds of character sizes................................CC mode : 2 types
It can be specified by a character unit (maximum 7 kinds).
It can be specified by a screen unit (maximum 7 kinds).
Kinds of character colors ...............CC mode : 7 kinds (R, G, B)
Display position
Attribute......................CC mode : smooth italic, underline, flash
Automatic solid space function
Window function
Dual layer OSD function
APPLICATION
TV with a closed caption decoder
and ON-SCREEN DISPLAY CONTROLLER
OSD mode : 16 ✕ 20 dots
EXOSD mode : 16 ✕ 26 dots
OSD mode : 14 types
EXOSD mode : 6 types
Character font coloring, character background coloring
Extra font coloring, raster coloring, border coloring
OSD mode : 15 kinds (R, G, B, I)
EXOSD mode : 7 kinds (R, G, B, I1, I2)
Horizontal................................................................ 256 levels
Vertical .................................................................. 1024 levels
OSD mode : border
EXOSD mode : border,
extra font (32 kinds)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
PIN CONFIGURATION (TOP VIEW)
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
and ON-SCREEN DISPLAY CONTROLLER
SYNC
H
VSYNC
P40/AD4
P4
1/INT2
P4
2/TIM2
P4
3/TIM3
P2
4/AD3
P2
5/AD2
6/AD1
P2
P2
P00/PWM4
P50/PWM7
P0
1/PWM5
P4
P02/PWM6
P51
P17/SIN
P32
P44/INT1
P5
P4
5/SOUT
P57
P46/SCLK
AVCC
HLF
RVCO
VHOLD
CVIN
CNVSS
XIN
XOUT
VSS
1
2
3
4
5
6
7
8
9
M37270EF-XXXSP, M37270EFSP
10
7
11
12
13
14
7
15
16
17
18
19
6
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
M37270MF-XXXSP
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P52/R
P5
3/G
P5
4/B
P5
5/OUT1
P0
4/PWM0
P0
5/PWM1
P6
0
P06/PWM2
P6
1
P07/PWM3
P6
2
P20
P21
P22
P23
P10/OUT2
P65
1/SCL1
P1
P66
2/SCL2
P1
P67
3/SDA1
P1
P1
4/SDA2
P1
5/I1
P1
6/I2/INT3
P03
P3
0
P31
RESET
P6
4/OSC2/XCOUT
P63/OSC1/XCIN
VCC
Outline 64P4B
2
Clock input Clock output
X
IN
X
OUT
Reset input
AV
CC
V
CC
V
SS
CNV
SS
Pins for data slicer
Clock output for OSD/
sub-clock output
Input ports P6
3
, P6
4
OSC1 OSC2
Clock input for OSD/
sub-clock input
P1 (8)
Multi-master
I
2
C-BUS interface
P3 (3)
SDA1
SCL2
SCL1
SDA2
P2 (8)
P0 (8)
P4 (8)
S
IN
S
CLK
S
OUT
SI/O (8)
P6 (8)
INT1
INT2
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
P5 (8)
OUT1
B
G
R
H
SYNC
V
SYNC
OUT2
A-D
converter
8-bit
PWM circuit
8-bit
arithmetic
and
logical unit
Accumulator
A (8)
Timer 6
T6 (8)
Timer 5
T5 (8)
Timer 4
T4 (8)
Timer 3
T3 (8)
Timer 2
T2 (8)
Timer 1
T1 (8)
Timer count source
selection circuit
TIM2
TIM3
Data slicer
Instruction
register (8)
Instruction
decoder
Control signal
CRT circuit
Processor
status
register
PS (8)
Stack
pointer
S (8)
Index
register
Y (8)
Index
register
X (8)
ROM
60 K bytes
Program
counter
PC
L
(8)
Progam
counter
PC
H
(8)
RAM
1024 bytes
Data bus
Clock
generating
circuit
30 31
36
RESET
24 33 32 29
CV
IN
28 27 26 25
V
HOLD
RVCO
HLF
34 35
Address bus
36 17 40 41 42 43 45 47 49 10 9 8 7 50 51 5253 55 57 59 60 39 15 13 11 23 2119 6 5 4 3 61 62 63 64 2 1
I/O ports
P3
0
, P3
1
I/O port P1 I/O port P2 I/O port P0 Input ports P4
0
–P4
6
Output port P5
Sync
signal input
Output port P4
7
20 22
16 12
56 5844
Output ports
P6
0
–P4
2
, P6
5
–P4
7
14
18
Output port
P3
2
INT3
PWM7
37
48 54
46
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
FUNCTIONAL BLOCK DIAGRAM of M37270MF-XXXSP
3
FUNCTIONS
Parameter
Number of basic instructions
Instruction execution time
Clock frequency
Memory size
Input/Output ports
Serial I/O
Multi-master I2C-BUS interface
A-D converter
PWM output circuit
Timers
Subroutine nesting
Interrupt interval determination circuit
Interrupt
Clock generating circuit
Data slicer
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
ROM
RAM
OSD ROM
OSD RAM
P00–P02,
P04–P07
P03
P10, P15–P17
P11–P14
P2
P30, P31
P32
P40–P44
P45, P46
P47
P50, P51, P56,
P57
P52–P55
P60–P62,
P65–P67
P63
P64
I/O
I/O
I/O
I/O
I/O
I/O
Output
Input
Input
Output
Output
Output
Output
Input
Input
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
and ON-SCREEN DISPLAY CONTROLLER
Functions
71
0.5 µs (the minimum instruction execution time, at 8 MHz oscillation frequency)
8 MHz (maximum)
60 K bytes
1024 bytes
14464 bytes
1920 bytes
7-bit ✕ 1 (N-channel open-drain output structure, can be used as PWM
output pins)
1-bit ✕ 1 (CMOS input/output structure)
4-bit ✕ 1 (CMOS input/output structure, can be used as OSD output pin,
INT input pin, serial input pin)
4-bit ✕ 1 (N-channel open-drain output structure, can be used as multi-
master I2C-BUS interface)
8-bit ✕ 1 (CMOS input/output structure, can be used as A-D input pins)
2-bit ✕ 1 (CMOS input/output structure)
1-bit ✕ 1 (N-channel open-drain output structure)
5-bit ✕ 1 (can be used as A-D input pins, INT input pins, external clock
input pins)
2-bit ✕ 1 (N-channel open-drain output structure when serial I/O is used,
can be used as serial I/O pins)
1-bit ✕ 1 (N-channel open-drain output structure)
4-bit ✕ 1 (N-channel open-drain output structure, can be used as PWM
output pins)
4-bit ✕ 1 (CMOS output structure, can be used as OSD output)
6-bit ✕ 1 (N-channel open-drain output)
1-bit ✕ 1 (can be used as sub-clock input pin, OSD clock input pin)
1-bit ✕ 1 (CMOS output structure when LC is oscillating, can be used as
sub-clock output pin, OSD clock output pin)
8-bit ✕ 1
1
4 channels (8-bit resolution)
8-bit ✕ 8
8-bit timer ✕ 6
128 levels (maximum)
1
External interrupt ✕ 3, Internal timer interrupt ✕ 6, Serial I/O interrupt ✕ 1,
OSD interrupt ✕ 1, Multi-master I
Data slicer interrupt ✕ 1, f(XIN)/4092 interrupt ✕ 1, VSYNC interrupt ✕ 1, AD conversion interrupt ✕ 1, BRK instruction interrupt ✕ 1
2 built-in circuits (externally connected a ceramic resonator or a quartzcrystal oscillator)
Built in
2
C-BUS interface interrupt ✕ 1,
4
FUNCTIONS (continued)
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
OSD function
Power source voltage
Power dissipation
Operating temperature range
Device structure
Package
In high-speed
mode
In low-speed
mode
In stop mode
Number of display characters
Dot structure
Kinds of characters
Kinds of character sizes
Kinds of character colors
Display position (horizontal, vertical)
OSD ON
OSD OFF
OSD OFF
Data slicer ON
Data slicer OFF
Data slicer OFF
40 characters ✕ 16 lines
CC mode: 16 ✕ 26 dots (character part : 16 ✕ 20 dots)
OSD mode: 16 ✕ 20 dots
EXOSD mode: 16 ✕ 26 dots
320 kinds
(In EXOSDmode, they can be combined with 32 kinds of extra fonts)
CC mode: 2 kinds
OSD mode: 14 kinds
EXOSD mode: 6 kinds
CC mode: 7 kinds (R, G, B)
OSD mode: 15 kinds (R, G, B, I1)
EXOSD mode: 7 kinds (R, G, B, I1, I2)
256 levels (horizontal) ✕ 1024 levels (vertical)
5 V ± 10 %
165 mW typ. (at oscillation frequency fCPU = 8 MHz, fOSD = 13 MHz)
82.5 mW typ. (at oscillation frequency fCPU = 8 MHz)
0.33mW typ. (at oscillation frequency fCLK = 32 kHz, f(XIN) = stopped)
0.055 mW (maximum)
–10 °C to 70 °C
CMOS silicon gate process
64-pin shrink plastic molded DIP
5
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
PIN DESCRIPTION
Pin Name Functions
VCC,
AVCC,
VSS.
CNVSS
RESET
XIN
XOUT
P00/PWM4–
P02/PWM6,
P03,
P04/PWM0–
P07/PWM3
P10/OUT2,
P11/SCL1,
P12/SCL2,
P13/SDA1,
P14/SDA2,
P15/I1,
P16/I2/INT3,
P17/SIN
P20–P23
P24/AD3–
P26/AD1,
P27
Power source
CNVSS
Reset input
Clock input
Clock output
I/O port P0
PWM output
I/O port P1
OSD output
Multi-master
2
C-BUS interface
I
Serial I/O data
input
I/O port P2
Analog input
Input/
Output
Input
Input
Output
I/O
Output
I/O
Output
Output
Input
I/O
Input
Apply voltage of 5 V ± 10 % (typical) to V
This is connected to VSS.
To enter the reset state, the reset input pin must be kept at a “L” for 2 µs or more (under
normal VCC conditions).
If more time is needed for the quartz-crystal oscillator to stabilize, this “L” condition should
be maintained for the required time.
This chip has an internal clock generating circuit. To control generating frequency, an
external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and
XOUT. If an external clock is used, the clock source should be connected to the XIN pin and
the XOUT pin should be left open.
Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually
programmed as input or output. At reset, this port is set to input mode. The output structure
of P03 is CMOS output, that of P00–P02 and P04–P07 are N-channel open-drain output.
The note out of this Table gives a full of port P0 function.
Pins P0
0–P02 and P04–P07 are also used as PWM output pins PWM4–PWM6 and PWM0–
PWM3 respectively. The output structure is N-channel open-drain output.
Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure of P10 and P15–P17 is CMOS output, that of P11–P14 is N-channel open-drain
output.
Pins P10, P15, P16 are also used as OSD output pins OUT2, I1, I2 respectively. The output
structure is CMOS output.
Pins P11–P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master
I2C-BUS interface is used. The output structure is N-channel open-drain output.
P17 pin is also used as serial I/O data input pin SIN.
Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output.
Pins P24–P26 are also used as analog input pins AD3–AD1 respectively.
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
and ON-SCREEN DISPLAY CONTROLLER
CC and AVCC, and 0 V to VSS.
P30, P31
P32
P40/AD4,
P41/INT2,
P42/TIM2,
P43/TIM3,
P44/INT1,
P45/SOUT,
P46/SCLK,
P47
P50/PWN7,
P51, P52/R,
P53/G, P54/B,
P55/OUT1,
P56, P57
I/O port P3
Output port P3
Input port P4
Analog input
External interrupt
input
External clock input
Serial I/O data
output
Serial I/O
synchronizing clock
input/output
Output port P4
Output port P5
PWM output
OSD output
I/O
Output
Input
Input
Input
Input
Output
I/O
Output
Output
Output
Output
Ports P30 and P31 are a 2-bit I/O port and has basically the same functions as port P0. The
output structure is CMOS output.
Port P32 is a 1-bit output port. The output structure is N-channel open-drain output.
Ports P40–P46 are a 7-bit input port.
P40 pin is also used as analog input pin AD4.
Pins P41, P44 are also used as external interrupt input INT2, INT1.
Pins P42 and P43 are also used as external clock input pins TIM2, TIM3 respectively.
P45 pin is used as serial I/O data output pin SOUT. The output structure is N-channel open-
drain output.
P46 pin is used as serial I/O synchronizing clock input/output pin SCLK. The output struc-
ture is N-channel open-drain output.
Port P47 is a 1-bit output port. The output structure is N-channel open-drain output.
Ports P50–P57 are an 8-bit output port. The output structure of P50, P51, P56, P57 are Nchannel open-drain output, that of P52–P55 is CMOS output.
P50 pin is also used as PWM output pin PWM7.
Pins P5
2–P55 are also used as OSD output pins R, G, B, OUT1 respectively.
6
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
PIN DESCRIPTION (continued)
P60–P62,
P65–P67
P63/OSC1/
XCIN,
P64/OSC2/
XCOUT
CVIN
VHOLD
RVCO
HLF
HSYNC
VSYNC
Note : As shown in the memory map (Figure 3), port P0 is accessed as a memory at address 00C016 of zero page. Port P0 has the port P0
Output port
Input port
Clock input for OSD
Clock output for OSD
Sub-clock output
Sub-clock input
I/O for data slicer
H
SYNC input
VSYNC input
direction register (address 00C116 of zero page) which can be used to program each bit as an input (“0”) or an output (“1”). The pins
programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are
programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the
output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the
output “L” voltage has risen, for example, because a light emitting diode was directly driven. The input pins are in the floating state, so the
values of the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the
floating state.
Output
Input
Input
Output
Output
Input
Input
Input
Input
Input
Ports P60–P62, P65–P67 are a 6–bit output port. The output structure is N-channel opendrain output.
Ports P63 and P64 are 2-bit input port.
P63 pin is also used as OSD clock input pin OSC1.
P64 pin is also used as OSD clock output pin OSC2. The output structure is CMOS output.
P64 pin is also used as sub-clock output pin XCOUT. The output structure is CMOS output.
P63 pin is also used as sub-clock input pin XCIN.
Input composite video signal through a capacitor.
Connect a capacitor between VHOLD and VSS.
Connect a resistor between RVCO and VSS.
Connect a filter using of a capacitor and a resistor between HLF and VSS.
This is a horizontal synchronizing signal input for OSD.
This is a vertical synchronizing signal input for OSD.
and ON-SCREEN DISPLAY CONTROLLER
7
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The M37270MF-XXXSP uses the standard 740 family instruction set.
Refer to the table of 740 family addressing modes and machine instructions or the SERIES 740 <Software> User’s Manual for details
on the instruction set.
Machine-resident 740 family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instruction can be used.
70
11 00
CPU mode register
(CPUM (CM) : address 00FB16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 :
1 1 :
Stack page selection bit (Note)
0 : Zero page
1 : 1 page
Fix these bits to “1.”
COUT drivability selection bit
X
0 : Low drive
1 : High drive
Main colock (X
0 : Oscillating
1 : Stopped
Internal system clock selection bit
0 : X
1 : XCIN–XCOUT selected (low-speed mode)
CPU Mode Register
The CPU mode register contains the stack page selection bit and
internal system clock selection bit. The CPU mode register is allocated at address 00FB
Not available
IN–XOUT) stop bit
IN–XOUT selected (high-speed mode)
16.
Note: Please beware of this bit when programming because it
is set to “1” after the reset release.
Fig. 1. Structure of CPU mode register
8
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
MEMORY
Special Function Register (SFR) Area
The special function register (SFR) area in the zero page contains
control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
ROM
ROM is used for storing user programs as well as the interrupt vector
area.
RAM for OSD
RAM for display is used for specifying the character codes and colors to display.
ROM for OSD
ROM for display is used for storing character data.
000016
Zero page
RAM
(1024 bytes)
RAM for OSD (Note)
(1920 bytes)
00C016
00FF16
020016
023F16
030016
053F
080016
0FFF16
100016
SFR1 area
SFR2 area
Not used
16
Not used
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
ROM for OSD
(14464 bytes)
1000016
10800
1567F
1800016
16
16
Not used
Not used
ROM
(60 K bytes)
Fig. 2. Memory map
FF0016
FFDE16
FFFF
Interrupt vector area
16
Special page
1E43F
1FFFF16
16
Not used
9
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
00C0
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00C816
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
00D216
00D316
00D416
00D516
00D616
00D716
00D816
00D916
00DA16
00DB16
00DC16
00DD16
00DE16
00DF16
16
Port P0
Port P0 direction register
Port P1
Port P1 direction register
Port P2
Port P2 direction register
Port P3
Port P3 direction register
Port P4
Port P4 direction register
Port P5
OSD port control register
Port P6
OSD control register
Horizontal position register
Block control register 1
Block control register 2
Block control register 3
Block control register 4
Block control register 5
Block control register 6
Block control register 7
Block control register 8
Block control register 9
Block control register 10
Block control register 11
Block control register 12
Block control register 13
Block control register 14
Block control register 15
Block control register 16
00E0
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
00EF16
00F016
00F116
00F216
00F316
00F416
00F516
00F616
00F716
00F816
00F916
00FA16
00FB16
00FC16
00FD16
00FE16
00FF16
16
Caption position register
Start bit position register
Window register
Sync slice register
Data register 1
Data register 2
Clock run-in register 1
Clock run-in register 2
Clock run-in detect register 1
Clock run-in detect register 2
Data slicer control register 1
Data slicer control register 2
Data register 3
Data register 4
A-D register
A-D control register
Timer 1
Timer 2
Timer 3
Timer 4
Timer mode register 1
Timer mode register 2
2
I C data shift register
2
I C address register
2
I C status register
2
I C control register
2
I C clock control register
CPU mode register
Interrupt request register 1
Interrupt request register 2
Interrupt control register 1
Interrupt control register 2
Fig. 3. Memory map of special function register 1 (SFR1)
10
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
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0200
020116
020216
020316
020416
020516
020616
020716
020816
020916
020A16
020B16
020C16
020D16
020E16
020F16
021016
021116
021216
021316
021416
021516
021616
021716
021816
021916
021A16
021B16
021C16
021D16
021E16
021F16
16
PWM0 register
PWM1 register
PWM2 register
PWM3 register
PWM4 register
PWM5 register
PWM6 register
PWM7 register
Clock run-in detect register 3
Clock run-in register 3
PWM mode register 1
PWM mode register 2
Timer 5
Timer 6
Sync pulse counter register
Data slicer control register 3
Interrupt interval determination register
Interrupt interval determination control register
Serial I/O mode register
Serial I/O register
Clock source control register
I/O polarity control register
Raster color register
Extra font color register
Border color register
Window H register 1
Window L register 1
Window H register 2
Window L register 2
0220
022116
022216
022316
022416
022516
022616
022716
022816
022916
022A16
022B16
022C16
022D16
022E16
022F16
023016
023116
023216
023316
023416
023516
023616
023716
023816
023916
023A16
023B16
023C16
023D16
023E16
023F16
16
Vertical register 11
Vertical register 12
Vertical register 13
Vertical register 14
Vertical register 15
Vertical register 16
Vertical register 17
Vertical register 18
Vertical register 19
Vertical register 110
Vertical register 111
Vertical register 112
Vertical register 113
Vertical register 114
Vertical register 115
Vertical register 116
Vertical register 21
Vertical register 22
Vertical register 23
Vertical register 24
Vertical register 25
Vertical register 26
Vertical register 27
Vertical register 28
Vertical register 29
Vertical register 210
Vertical register 211
Vertical register 212
Vertical register 213
Vertical register 214
Vertical register 215
Vertical register 216
Fig. 4. Memory map of special function register 2 (SFR2)
11
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
INTERRUPTS
Interrupts can be caused by 18 different sources consisting of 4 external, 12 internal, 1 software, and reset. Interrupts are vectored interrupts with priorities shown in Table 1. Reset is also included in the
table because its operation is similar to an interrupt.
When an interrupt is accepted,
(1) The contents of the program counter and processor status
register are automatically stored into the stack.
(2) The interrupt disable flag I is set to “1” and the corresponding
interrupt request bit is set to “0.”
(3) The jump destination address stored in the vector address enters
the program counter.
Other interrupts are disabled when the interrupt disable flag is set to
“1.”
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits are
in interrupt request registers 1 and 2 and the interrupt enable bits are
in interrupt control registers 1 and 2. Figure 5 shows the structure of
the interrupt-related registers.
Interrupts other than the BRK instruction interrupt and reset are accepted when the interrupt enable bit is “1,” interrupt request bit is “1,”
and the interrupt disable flag is “0.” The interrupt request bit can be
set to “0” by a program, but not set to “1.” The interrupt enable bit can
be set to “0” and “1” by a program.
Reset is treated as a non-maskable interrupt with the highest priority.
Figure 6 shows interrupt control.
Interrupt Causes
(1) VSYNC and OSD interrupts
The V
SYNC interrupt is an interrupt request synchronized with
the vertical sync signal.
The OSD interrupt occurs after character block display to the
CRT is completed.
(2) INT1, INT2, INT3 interrupts
With an external interrupt input, the system detects that the level
of a pin changes from “L” to “H” or from “H” to “L,” and generates
an interrupt request. The input active edge can be selected by
bits 3, 4 and 6 of the interrupt interval determination control register (address 0212
“H” is detected; when it is “1,” a change from “H” to “L” is detected. Note that all bits are cleared to “0” at reset.
(3) Timer 1, 2, 3 and 4 interrupts
An interrupt is generated by an overflow of timer 1, 2, 3 or 4.
(4) Serial I/O interrupt
This is an interrupt request from the clock synchronous serial
I/O function.
(5) f(X
IN)/4096 interrupt
This interrupt occurs regularly with a f(X
of the PWM mode register 1 to “0.”
(6) Data slicer interrupt
An interrupt occurs when slicing data is completed.
(7) Multi-master I
This is an interrupt request related to the multi-master I
interface.
(8) A-D conversion interrupt
An interrupt occurs at the completion of A-D conversion. Since
A-D conversion interrupt and the INT3 interrupt share the same
vector, an interrupt source is selected by bit 7 of the interrupt
interval determination control register (address 0212
16) : when this bit is “0,” a change from “L” to
IN)/4096 period. Set bit 0
2
C-BUS interface interrupt
16).
2
C-BUS
Table 1. Interrupt vector addresses and priority
Interrupt source
Reset
OSD interrupt
INT1 interrupt
Data slicer interrupt
Serial I/O interrupt
Timer 4 interrupt
f(XIN)/4096 interrupt
VSYNC interrupt
Timer 3 interrupt
Timer 2 interrupt
Timer 1 interrupt
A-D convertion · INT3 interrupt
INT2 interrupt
Multi-master I2C-BUS interface interrupt
Timer 5 · 6 interrupt
BRK instruction interrupt
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Vector addresses
FFFF16, FFFE16
FFFD16, FFFC16
FFFB16, FFFA16
FFF916, FFF816
FFF716, FFF616
FFF516, FFF416
FFF316, FFF216
FFF116, FFF016
FFEF16, FFEE16
FFED16, FFEC16
FFEB16, FFEA16
FFE916, FFE816
FFE716, FFE616
FFE516, FFE416
FFE316, FFE216
FFDF16, FFDE16
Remarks
Non-maskable
Active edge selectable
Active edge selectable
Active edge selectable
Active edge selectable
Non-maskable (software interrupt)
12
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
(9)Timer 5 · 6 interrupt
An interrupt is generated by an overflow of timer 5 or 6. Their
priorities are same, and can be switched by software.
(10)BRK instruction interrupt
This software interrupt has the least significant priority. It does
not have a corresponding interrupt enable bit, and it is not affected by the interrupt disable flag I (non-maskable).
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Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset
Interrupt
request
Fig. 6. Interrupt control
7
0
Interrupt request register 1
(IREQ1: address 00FC
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Timer 4 interrupt request bit
OSD interrupt request bit
VSYNC interrupt request bit
A-D conversion INT3 interrupt
•
request bit
16)
7
0
0
Interrupt request register 2
(IREQ2: address 00FD
16)
INT1 interrupt request bit
Data slicer interrupt request bit
Serial I/O interrupt request bit
f(XIN)/4096 interrupt request bit
INT2 interrupt request bit
Multi-master I2C-BUS
interface interrupt request bit
Timer 5 6 interrupt request bit
•
Fix this bit to “0.”
0 : No interrupt request issued
1 : Interrupt request issued
7
0
Interrupt control register 1
( ICON1: address 00FE
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
Timer 4 interrupt enable bit
OSD interrupt enable bit
VSYNC interrupt enable bit
A-D conversion INT3 interrupt
request bit
Fig. 5. Structure of interrupt-related registers
16)
•
0 : Interrupt disabled
1 : Interrupt enabled
7
0
Interrupt control register 2
( ICON2 : address 00FF
16)
INT1 interrupt enable bit
Data slicer interrupt enable bit
Serial I/O interrupt enable bit
f(XIN)/4096 interrupt enable bit
INT2 interrupt enable bit
2
Multi-master I
C-BUS
interface enable bit
Timer 5 6 interrupt enable bit
•
Timer 5 6 interrupt switch bit
•
0 : Timer 5
1 : Timer 6
13
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
TIMERS
The M37270MF-XXXSP has 6 timers: timer 1, timer 2, timer 3,
timer 4, timer 5, and timer 6. All timers are 8-bit timers with the 8-bit
timer latch. The timer block diagram is shown in Figure 8.
All of the timers count down and their divide ratio is 1/(n+1), where n
is the value of timer latch. The value is set to a timer at the same time
by writing a count value to the corresponding timer latch (addresses
00F0
16 to 00F316 : timers 1 to 4, addresses 020C16 and 020D16 :
timers 5 and 6).
The count value is decremented by 1. The timer interrupt request bit
is set to “1” by a timer overflow at the next count pulse after the count
value reaches “00
16”.
(1) Timer 1
Timer 1 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
f(XIN)/4096 or f(XCIN)/4096
•
External clock from the P42/TIM2 pin
•
The count source of timer 1 is selected by setting bits 5 and 0 of the
timer mode register 1 (address 00F4
selected by bit 7 of the CPU mode register.
Timer 1 interrupt request occurs at timer 1 overflow.
16). Either f(XIN) or f(XCIN) is
(2) Timer 2
Timer 2 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
Timer 1 overflow signal
•
External clock from the P42/TIM2 pin
•
The count source of timer 2 is selected by setting bits 4 and 1 of the
timer mode register 1 (address 00F4
selected by bit 7 of the CPU mode register. When timer 1 overflow
signal is a count source for the timer 2, the timer 1 functions as an 8bit prescaler.
Timer 2 interrupt request occurs at timer 2 overflow.
16). Either f(XIN) or f(XCIN) is
(3) Timer 3
Timer 3 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
f(XCIN)
•
External clock from the P43/TIM3 pin
•
The count source of timer 3 is selected by setting bit 0 of the timer
mode register 2 (address 00F5
ther f(X
IN) or f(XCIN) is selected by bit 7 of the CPU mode register.
Timer 3 interrupt request occurs at timer 3 overflow.
16) and bit 6 at address 00C716. Ei-
(5) Timer 5
Timer 5 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
Timer 2 overflow signal
•
Timer 4 overflow signal
•
The count source of timer 3 is selected by setting bit 6 of the timer
mode register 1 (address 00F4
ter 2 (address 00F5
the CPU mode register.
Timer 5 interrupt request occurs at timer 5 overflow.
16). Either f(XIN) or f(XCIN) is selected by bit 7 of
16) and bit 7 of the timer mode regis-
(6) Timer 6
Timer 6 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
Timer 5 overflow signal
•
The count source of timer 6 is selected by setting bit 7 of the timer
mode register 1 (address 00F4
by bit 7 of the CPU mode register. When timer 5 overflow signal is a
count source for the timer 6, the timer 5 functions as an 8-bit prescaler.
Timer 6 interrupt request occurs at timer 6 overflow.
At reset, timers 3 and 4 are connected by hardware and “FF
automatically set in timer 3; “07
lected as the timer 3 count source. The internal reset is released by
timer 4 overflow at these state, the internal clock is connected.
At execution of the STP instruction, timers 3 and 4 are connected by
hardware and “FF
However, the f(X
So set both bit 0 of the timer mode register 2 (address 00F5
bit 6 at address 00C7
struction (f(X
internal STP state is released by timer 4 overflow at these state, the
internal clock is connected.
Because of this, the program starts with the stable clock.
✽ : When bit 7 of the CPU mode register (CM
comes f(X
The structure of timer-related registers is shown in Figure 7.
16” is automatically set in timer 3; “0716” in timer 4.
✽
IN)
/16 is not selected as the timer 3 count source.
✽
IN)
/16 is selected as the timer 3 count source). The
CIN).
16). Either f(XIN) or f(XCIN) is selected
16” is
16” in timer 4. The f(XIN)
16 to “0” before the execution of the STP in-
✽
/16 is se-
16) and
7) is “1,” f(XIN) be-
(4) Timer 4
Timer 4 can select one of the following count sources:
f(XIN)/16 or f(XCIN)/16
•
f(XIN)/2 or f(XCIN)/2
•
f(XCIN)
•
The count source of timer 3 is selected by setting bits 4 and 1 of the
timer mode register 2 (address 00F5
selected by bit 7 of the CPU mode register. When timer 3 overflow
signal is a count source for the timer 4, the timer 3 functions as an 8bit prescaler.
Timer 4 interrupt request occurs at timer 4 overflow.
14
16). Either f(XIN) or f(XCIN) is
MITSUBISHI MICROCOMPUTERS
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70
Timer mode register 1
(TMR1 : address 00F4
Timer 1 count source selection bit 1
IN
0 : f(X
)/16 or f(X
1 : Count source selected by bit 5
of TMR1
Timer 2 count source selection bit 1
0 : Count source selected by bit 4 of
TMR1
1 : External clock from P4
Timer 1 count stop bit
0 : Count start
1 : Count stop
Timer 2 count stop bit
0 : Count start
1 : Count stop
Timer 2 count source selection bit 2
0 : f(X
IN
)/16 or f(X
1 : Timer 1 overflow
Timer 1 count source selection bit 2
0 : f(X
IN
)/4096 or f(X
1 : External clock from P4
pin
Timer 5 count source selection bit 2
0 : Timer 2 overflow
1 : Timer 4 overflow
16
)
CIN
)/16 (Note)
CIN
)/16 (Note)
CIN
2
/TIM2 pin
)/4096 (Note)
2
/TIM2
70
Timer mode register 2
(TMR2 : address 00F5
Timer 3 count source selection bit
(Bit 6 at
address
16
)
00C7
b0
0 0 : f(X
1 0 : f(X
0 1 :
1 1 :
IN
)/16 or f(X
CIN
External clock from
3
/TIM3 pin
P4
Timer 4 count source selection bits
b4 b1
0 0 : Timer 3 overflow
0 1 : f(X
1 0 : f(X
1 1 : f(X
IN
)/16 or f(X
IN
)/2 or f(X
CIN
Timer 3 count stop bit
0 : Count start
1 : Count stop
Timer 4 count stop bit
0 : Count start
1 : Count stop
Timer 5 count stop bit
0 : Count start
1 : Count stop
16
)
CIN
)/16 (Note)
)
CIN
)/16 (Note)
CIN
)/2 (Note)
)
Timer 6 count source selection bit
IN
0 : f(X
)/16 or f(X
1 : Timer 5 overflow
Note : Either f(X
IN
) or f(X
CIN
) is selected by bit 7 of the CPU mode register.
Fig. 7. Structure of timer-related registers
CIN
)/16 (Note)
Timer 6 count stop bit
0 : Count start
1 : Count stop
Timer 5 count source selection bit 1
0 : f(X
IN
)/16 or f(X
CIN
)/16 (Note)
1 : Count source selected by bit 6
of TMR1
15
X
CIN
X
IN
P42/TIM2
CM
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
7
TMR1
1/4096
1/2
5
1/8
TMR1
0
TMR1
TMR1
4
TMR1
1
TMR1
Timer 1 latch (8)
Timer 1 (8)
2
Timer 2 latch (8)
Timer 2 (8)
3
and ON-SCREEN DISPLAY CONTROLLER
Data bus
8
8
Timer 1
interrupt request
8
8
8
Timer 2
interrupt request
8
P4
3
/TIM3
TMR2
1
Selection gate :
Connected to
black colored
side at reset
TMR1 : Timer mode register 1
TMR2 : Timer mode register 2
TM3EL : Timer 3 count source
switch bit (address 00C7
CM : CPU mode register
TMR2
TMR2
TM3EL
0
TMR2
TMR2
4
TMR2
TMR1
Timer 3 latch (8)
2
1
Timer 4 latch (8)
3
6
8
Timer 3 (8)
8
Timer 4 (8)
8
FF
16
8
8
07
16
8
8
Reset
STP instruction
Timer 3
interrupt request
Timer 4
interrupt request
Timer 5 latch (8)
8
7
TMR2
TMR2
16
)
Timer 5 (8)
5
8
8
Timer 5
interrupt request
Notes 1: “H” pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more.
2: When the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal.
3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.
Fig. 8. Timer block diagram
16
TMR1
7
TMR2
Timer 6 latch (8)
Timer 6 (8)
6
8
Timer 6
interrupt request
8
MITSUBISHI MICROCOMPUTERS
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SERIAL I/O
The M37270MF-XXXSP has a built-in serial I/O which can either transmit or receive 8-bit data in serial in the clock synchronous mode.
The serial I/O block diagram is shown in Figure 9. The synchronizing
clock I/O pin (S
P4, data input pin (S
Bit 2 of the serial I/O mode register (address 0213
the synchronizing clock is supplied internally or externally (from the
P4
6/SCLK pin). When an internal clock is selected, bits 1 and 0 select
whether f(X
S
OUT and P46/SCLK pins for serial I/O, set the corresponding bits of
the port P4 direction register (address 00C9
pin for serial I/O, set the corresponding bit of the port P1 direction
register (address 00C3
CLK), and data output pin (SOUT) also function as port
IN) also functions as port P1.
16) selects whether
IN) or f(XCIN) is divided by 8, 16, 32, or 64. To use P45/
16) to “0.” To use P17/SIN
16) to “0.”
XCIN
1/2
IN
X
1/2
1/2
CM7
Synchronization
circuit
P46/SCLK
SM2
S
Serial I/O counter (8)
The operation of the serial I/O function is described below. The function of the serial I/O differs depending on the clock source; external
clock or internal clock.
Data bus
Frequency divider
1/2
1/81/4 1/16
SM1
SM0
Selection gate: Connect to
black colored
side at reset.
CM : CPU mode register
SM : Serial I/O mode register
Serial I/O
interrupt request
P45/SOUT
SM
MSB
5 : LSB
(Note)
P17/SIN
Serial I/O shift register (8)
(Address 021416)
8
Note : When the data is set in the serial I/O register (address 021416), the register functions as the serial I/O shift register.
Fig. 9. Serial I/O block diagram
17
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Internal clock—the serial I/O counter is set to “7” during write cycle
into the serial I/O register (address 0214
“H” forcibly. At each falling edge of the transfer clock after the write
cycle, serial data is output from the S
be selected by bit 5 of the serial I/O mode register. At each rising
edge of the transfer clock, data is input from the S
the serial I/O register is shifted 1 bit.
After the transfer clock has counted 8 times, the serial I/O counter
becomes “0” and the transfer clock stops at “H.” At this time the interrupt request bit is set to “1.”
External clock—when an external clock is selected as the clock
source, the interrupt request is set to “1” after the transfer clock has
counted 8 times. However, transfer operation does not stop, so control the clock externally. Use the external clock of 500kHz or less
with a duty cycle of 50%.
The serial I/O timing is shown in Figure 10. When using an external
clock for transfer, the external clock must be held at “H” for initializing
the serial I/O counter. When switching between an internal clock and
an external clock, do not switch during transfer. Also, be sure to initialize the serial I/O counter after switching.
Notes 1: On programming, note that the serial I/O counter is set by
writing to the serial I/O register with the bit managing instructions as SEB and CLB instructions.
2: When an external clock is used as the synchronizing clock,
write transmit data to the serial I/O register at “H” of the
transfer clock input level.
16), and transfer clock goes
OUT pin. Transfer direction can
IN pin and data in
MITSUBISHI MICROCOMPUTERS
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7
0
0
0
Serial I/O mode register
(SM : address 0213
16
)
Internal synchronizing clock
selection bits
b1 b0
IN
)/8 or f(X
0 0 : f(X
0 1 : f(X
1 0 : f(X
1 1 : f(X
IN
IN
IN
)/16 or f(X
)/32 or f(X
)/64 or f(X
CIN
CIN
CIN
CIN
Synchronizing clock selection bit
0 : External clock
1 : Internal clock
Port function selection bit
1
, P13 functions as port
0 : P1
1 : SCL1, SDA1
Port function selection bit
2
, P14 functions as port
0 : P1
1 : SCL2, SDA2
Transfer direction selection bit
0 : LSB first
1 : MSB first
Fix these bits to “0”
)/8
)/16
)/32
)/64
Synchroninzing clock
Transfer clock
Serial I/O register
write signal
Serial I/O output
OUT
S
Serial I/O input
IN
S
Note : When an internal clock is selected, the S
Fig. 10. Serial I/O timing (for LSB first)
Fig. 11. Structure of serial I/O mode register
D
0
D
1
D
2
D
3
D
4
D
OUT
pin is at high-impedance after transfer is completed.
(Note)
5
D
6
D
7
Interrupt request bit is set to “1”
18
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
PWM OUTPUT FUNCTION
The M37270MF-XXXSP is equipped with eight 8-bit PWMs (PWM0–PWM7). PWM0–PWM7 have the same circuit structure and an 8bit resolution with minimum resolution bit width of 4µs (for f(X
8 MHz) and repeat period of 1024µs.
Figure 12 shows the PWM block diagram. The PWM timing generating circuit applies individual control signals to PWM0–PWM7 using
f(X
IN) divided by 2 as a reference signal.
IN) =
(1) Data Setting
When outputting PWM0–PWM7, set 8-bit output data in the PWMi
register (i means 0 to 7; addresses 0200
16 to 020716).
(2) Transmitting Data from Register to PWM circuit
Data transfer from the 8-bit PWM register to 8-bit PWM circuit is
executed at writing data to the register.
The signal output from the 8-bit PWM output pin corresponds to the
contents of this register.
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(3) Operating of 8-bit PWM
The following is the explanation about PWM operation.
At first, set the bit 0 of PWM mode register 1 (address 020A
(at reset, bit 0 is already set to “0” automatically), so that the PWM
count source is supplied.
PWM0–PWM3 are also used as pins P0
also used as pins P0
spectively. Set the corresponding bits of the port P0 direction register to “1” (output mode). And select each output polarity by bit 3 of
the PWM mode register 1 (address 020A
the PWM output control register 2 to “1” (PWM output).
The PWM waveform is output from the PWM output pins by setting
these registers.
Figure 13 shows the 8-bit PWM timing. One cycle (T) is composed
of 256 (2
each bit (bits 0 to 7) are output inside the circuit during 1 cycle. Refer
to Figure 13 (a). The 8-bit PWM outputs waveform which is the logical sum (OR) of pulses corresponding to the contents of bits 0 to 7 of
the 8-bit PWM register. Several examples are shown in Figure 13
(b). 256 kinds of output (“H” level area: 0/256 to 255/256) are selected by changing the contents of the PWM register. A length of
entirely “H” output cannot be output, i.e. 256/256.
8
) segments. The 8 kinds of pulses relative to the weight of
0–P02, PWM7 is also used as pins P50, re-
4–P07, PWM4–PWM6 are
16). Then, set bits 7 to 0 of
16) to “0”
(4) Output after Reset
At reset, the output of ports P00–P02 and P04–P07 is in the highimpedance state, port P5
register and the PWM circuit are undefined. Note that after reset, the
PWM output is undefined until setting the PWM register.
0 outputs “L,” and the contents of the PWM
19
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Data bus
XIN
PWM0 register
(Address 020016)
1/2
b7 b0
PN0
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
and ON-SCREEN DISPLAY CONTROLLER
PWM timing
generating
circuit
8
8-bit PWM circuit
PWM1 register (Address 020116)
PWM2 register (Address 020216)
PWM3 register (Address 020316)
PWM4 register (Address 020416)
PWM5 register (Address 020516)
PWM6 register (Address 020616)
PN3
P04
PW0
P05
PW1
P06
PW2
P07
PW3
P00
PW4
P01
PW5
P02
PW6
P50
D04
D05 PWM1
D06 PWM2
D07 PWM3
D00 PWM4
D01
D02
PWM0
PWM5
PWM6
PWM7
Selection gate :
Connected to
black colored
side at reset.
Inside of
Fig. 12. PWM block diagram
20
PWM7 register (Address 020716)
is as same contents with the others.
PW7
: PWM mode register 1 (address 020A
PN
: PWM mode register 2 (address 020B16)
PW
: Port P0 register address 00C016)
P0
: Port P0 direction register (address 00C116)
D0
(
16)
MITSUBISHI MICROCOMPUTERS
(a) Pulses showing the weight of each
bit
13579 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 255
412 202836
44 52 60 68 76 84
92 100 108 116 124 132 140 148 156 164 172 180 188 196 204 212 220 228 236 244 252
8
16 48 80
112 144 176 208 240
24
40
56 72
88 104
120 136
152 168
184 200
216 232
248
32
96
160
224
64
192
Bit 7
2
14 18
22 26 30
34
38
42
46 50
54 58
62 66
70
74 78
82 86
90
94
98 102
106
110
114
118
122
126
130
134 138
142 146
150 154 158 162 166
170 174 178
182
186
190 194
198
202
206
210
214
218
222
226 230
234
238 242
246
250
254
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
128
Bit 0
PWM output
t = 4 µs T = 1024 µs
f(X
IN) = 8 MHz
(b) Example of 8-bit PWM
t
00
16 (0)
0116 (1)
18
16 (24)
FF16 (255)
T = 256 t
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Fig. 13. 8-bit PWM timing
10
6
21
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
PWM mode register 1
(PN: address 020A
16)
and ON-SCREEN DISPLAY CONTROLLER
07
PWM mode register 2
(PW: address 020B
16)
PWM count source selection bit
0 : Count source supply
1 : Count source stop
PWM output polarity selection bit
0 : Positive polarity
1 : Negative polarity
P04/PWM0 output selection bit
4 output
0 : P0
1 : PWM0 output
P0
5/PWM1 output selection bit
5 output
0 : P0
1 : PWM1 output
P0
6/PWM2 output selection bit
6 output
0 : P0
1 : PWM2 output
P0
7/PWM3 output selection bit
7 output
0 : P0
1 : PWM3 output
0/PWM4 output selection bit
P0
0 output
0 : P0
1 : PWM4 output
1/PWM5 output selection bit
P0
0 : P0
1 output
1 : PWM5 output
P0
2/PWM6 output selection bit
0 : P0
2 output
1 : PWM6 output
0/PWM7 output selection bit
P5
0 : P5
0 output
1 : PWM7 output
Fig. 14. Structure of PWM-related registers
22
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
A-D CONVERTER
(1)A-D Conversion Register (AD)
A-D conversion reigister is a read-only register that stores the result
of an A-D conversion. This register should not be read during A-D
conversion.
(2)A-D Control Register (ADCON)
The A-D control register controls A-D conversion. Bits 1 and 0 of this
register select analog input pins. When these pins are not used as
anlog input pins, they are used as ordinary I/O pins. Bit 3 is the A-D
conversion completion bit, A-D conversion is started by writing “0” to
this bit. The value of this bit remains at “0” during an A-D conversion,
then changes to “1” when the A-D conversion is completed.
Bit 4 controls connection between the resistor ladder and V
not using the A-D converter, the resistor ladder can be cut off from
the internal V
power dissipation.
CC by setting this bit to “0.” This can realize the low-
CC. When
(3)Comparison Voltage Generator (Resistor
Ladder)
The voltage generator divides the voltage between VSS and VCC by
256, and outputs the divided voltages to the comparator as the reference voltage V
ref.
(4)Channel Selector
The channel selector connects an analog input pin selected by bits 1
and 0 of the A-D control register to the comparator.
(5)Comparator and Control Circuit
The conversion result of the analog input voltage and the reference
voltage “V
version completion bit and A-D conversion interrupt request bit are
set to “1” at the completion of A-D conversion.
Fig. 15. Structure of A-D control register
ref” is stored in the A-D conversion register. The A-D con-
7
0
0
A-D control register
(ADCON: address 00EF16)
Analog input pin selection bits
b1 b0
0 0 : P26/AD1
0 1 : P25/AD2
1 0 : P24/AD3
1 1 : P40/AD4
A-D conversion completion bit
0 : Conversion in purogress
1 : Conversion completed
VCC connection selection bit
0 : OFF
1 : ON
Fix this bit to “0.”
A-D control register
(address 00EF
P26/AD1
5/AD2
P2
P2
4/AD3
0/AD4
P4
Fig. 16. A-D comparator block diagram
16)
Comparator
Channel selector
Data bus
b7 b0
2
A-D control circuit
A-D conversion register
Switch tree
Resistor ladder
VSS VCC
8
(address 00EE16)
A-D conversion
interrupt request
23
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(6) Conversion Method
➀ Set bit 7 of the interrupt interval determination control register (ad-
dress 0212
tion of A-D conversion.
➁ Set the A-D conversion • INT3 interrupt request bit to “0” (even
when A-D conversion is started, the A-D conversion• INT3 interrupt bit is not set to “0” automatically).
➂ When using A-D conversion interrupt, enable interrupts by setting
A-D conversion • INT3 interrupt request bit to “1” and setting the
interrupt disable flag to “0.”
➃ Set the V
resistor ladder.
➄ Select analog input pins by setting the analog input selection bit of
the A-D control register.
➅ Set the A-D conversion completion bit to “0.” This write operation
starts the A-D conversion. Do not read the A-D conversion register during the A-D conversion.
➆ Verify the completion of the conversion by the state (“1”) of the
A-D conversion completion bit, that (“1”) of A-D conversion• INT3
interrupt bit, or the occurrence of an A-D conversion interrupt.
➇ Read the A-D conversion register to obtain the conversion results.
Note : When the ladder resistor is disconnect from V
16) to “1” to generate an interrupt request at comple-
CC connection selection bit to “1” to connect VCC to the
CC, set the VCC
connection selection bit to “0” between steps ➆ and ➇.
(7) Internal Operation
At the time when the A-D conversion starts, the following operations
are automatically performed.
➀ The A-D conversion register is set to “00
➁ The most significant bit of the A-D conversion register becomes
“1, ” and the comparison voltage “V
At this point, V
➂ Bit 7 is determined by the comparison result as follows.
When V
When V
With the above operations, the analog value is converted into a digital value. The A-D conversion terminates in a maximum 50 machine
cycles (12.5µs at f(X
result is stored in the A-D conversion register.
An A-D conversion interrupt request occurs at the same time of A-D
conversion completion, the A-D conversion • INT3 interrupt request
bit becomes “1.” The A-D conversion completion bit also becomes
“1.”
Table 2. Expression for V
A-D conversion register contents “n”
Note: VREF indicates the voltage of internal VCC.
ref is compared with the analog input voltage “VIN .”
ref < VIN : bit 7 holds “1”
ref > VIN : bit 7 becomes “0”
IN) = 8 MHz) after it starts, and the conversion
ref and VREF
(decimal notation)
0
255
to
16.”
ref” is input to the comparator.
ref (V)
V
0
VREF
✕(n – 0.5)1
256
A-D conv ersion start
1st comparison start
2nd comparison start
3rd comparison start
Contents of A-D conversion register
00000000
1
0000000
1000000
1
12
100000
Reference voltage (V
VREF2VREF
–
VREF2VREF4VREF
±
V
REF
±
2
VREF2VREF4VREF
8th comparison start
A-D conversion completion
(8th comparison completion)
Fig. 17. Changes in A-D conversion register and comparison voltage during A-D conversion
1234567
12345678
Digital value corresponding to
analog input voltage.
1
:
Value determined by mth (m = 1 to 8) resultm
±
ref) [V]
0
512
–
512
VREF4VREF8VREF
.......
±
±
±
8
VREF
256
–
512
.....
±
V
REF
–
512
24
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(8) Definition of A-D Conversion Accuracy
The definition of A-D conversion accuracy is described below.
Relative accuracy
• Zero transition error (V
The deviation of the input voltage at which A-D conversion output
data changes from “0” t o “1 ,” f rom t he co rresponding ideal A-D
conversion characteristics between 0 and V
V0T=
• Full-scale transition error (VFST)
The deviation of the input voltage at which A-D conversion output
data change s from “255” to “254 ,” from the cor r espondi ng ideal AD conversion charact er istics between 0 and V
VFST =
• Non-li near ity error
The deviation of the actual A-D conversion characteristics, from the
ideal A-D conversion charac t eristi cs betw een V
Non-linearity error =
(VREF –3/2✕VREF/256) –V254
0T)
(V
0 –1/2✕VREF/256)
1LSB
1LSB
Vn – (1LSB✕n+V0)
REF.
[ LSB ]
REF.
[LSB]
0 and V254.
[LSB]
1LSB
• Differential non-linearity error
The deviation of the input voltage required to change output data
by “1,” from the corresponding ideal A-D conversion characteristics between 0 and V
Absolute accuracy
• Absolute accuracy error
The deviation of the a ctu al A- D con versio n charact er i stics, from t he
ideal A-D conversion characteristics between 0 and V
Absolute accuracy error =
Note: The analog input voltage “Vn” at which A-D conversion output
data changes from “n” to “n + 1” (n ; 0 to 254) is as follows
(refer to Figure 18).
1LSB with respect to relative accuracy =
A with respect to absolute accuracy =
1LSB
REF.
(Vn+1–Vn)– 1LSB
1LSB
Vn – 1LSBA ✕(n +1/2)
1LSBA
V254 –V0
254
REF.
VREF
256
[LSB]Differential non-linearity error=
[LSB]
[V]
[V]
Output
data
255
254
n+1
n
Actual A-D
conversion
characteristics
1
2
0
Full-scale transition error
(V
FST)
Differential nonlinearity error
1LSB
Non-linearity error
Absolute accuracy
1LSB A
LSB
A
Ideal A-D conversion characteristics
between V
0 and V254
1LSB
V0 Vn Vn+1 V254 VREF
V1
Zero transition error (V0T)
3
2
LSBA
Analog input
voltage (V)
Fig. 18. Definition of A-D conversion precision
25
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
DATA SLICER
The M37270MF-XXXSP includes the data slicer function for the
closed caption decoder (referred to as the CCD). This function takes
out the caption data superimposed in the vertical blanking interval of
a composite video signal. A composite video signal which makes
the sync chip’s polarity negative is input to the CV
Composite
0.1 F
video
signal
Hundred of kiloohms
to 1 M
Low-pass
filter
V
HOLD
Reference
voltage
1000 pF
External circui
Note : Make the length of wiring which
is connected to V
RVCO and CV
possible so that a leakage
current may not be generated
when mounting a resistor or a
capacitor on each pin.
generating
circuit
t
HOLD
IN
pin as short as
Sync slice
00E316)
(address
Data slicer control
register 3
(address 0210
Clock run-in detect
register 3
(address 0208
Clock run-in
register 3
(address 0209
, HLF,
register 3
0000101
IN pin.
470
CV
Clamping
circuit
Sync slice
circuit
–
Comparator
Data register 2
(address 00E5
IN
+
16
16
16
560 pF
)
)
)
16
)
1 F
H
SYNC
high-order low-
Data register 4
(address 00ED
When the data slicer function is not used, the data slicer circuit can
be cut off by setting bit 0 of the data slicer control register 1 (address
00EA
16) to “0.” Also, the timing signal generating circuit can be cut
off by setting bit 0 of data slicer control register 2 (address 00EB
to “0.” These settings can realize the low-power dissipation.
1 k
200 pF
15 k
Sync pulse counter
register
(address 020F
16
HLF RVC O
Clock run-in register 2
Synchronizing
signal counter
(address 00E7
010111
16
Data slicer control register 2
Synchronizing
separation
circuit
(address 00EB
Data slicer control register 1
(address 00EA
Timing signal
16
000
16
000
)
)
generating
circuit
Data slicer ON/OFF
Window register
(address 00E2
16
00
Clock run-in
determination
circuit
Data slice line
specification
circuit
0101
Clock run-in register 1
(address 00E6
16
100
Caption position register
Start bit detecting
(address 00E0
16
)
circuit
Start bit position register
Data clock
generating circui
(address 00E1
t
16
)
Clock run-in detect register 1
16-bit shift register
order
Data register 1
(address 00E4
16
)
16
)
Interrupt request
generating circui
Data register 3
(address 00EC
(address 00E8
Clock run-in detect register 2
(address 00E9
16
t
)
16
)
16
)
Data slicer
interrupt
request
16)
)
)
)
)
Data bus
Fig. 19. Data slicer block diagram
26
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Figure 19 shows the structure of the data slicer control registers.
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
and ON-SCREEN DISPLAY CONTROLLER
000
07
Data slicer control register 1
(DSC1: address 00EA
Data slicer control bit
0: Data slicer stopped
1: Data slicer operating
Field to be sliced data selection bit
Field of main data
b2 b1
slice line
0 0 F2
0 1 F1
1 0 and F2
F1
1 1 and F2
F1
Fix these bits to “0.”
Field determination flag
sep
0 :
H
sep
V
sep
1 :
H
sep
V
16)
Field for setting
reference voltage
F2
F1
F2
F1
000
07
Data slicer control register 2
(DSC2: address 00EB16)
Timing signal generating circuit
control bit
0: Stopped
1: Operating
Reference clock source selection
bit
0: Video signal
1: HSYNC signal
Test bit: read-only
Fix these bits to “0.”
V-pulse shape determination flag
0: Match
1: Mismatch
Fix this bit to “0.”
Fix this bit to “0.”
Data latch completion flag for caption
data in main data slice line
0: Data is not yet latched
1: Data is latched
Definition of fields 1 (F1) and 2 (F2)
sep
H
F1 :
SYNC
V
sep
V
sep
H
F2 :
SYNC
V
sep
V
Fig. 20. Structure of data slicer control registers
Test bit: read-only
07
Data slicer control register 3
(DSC3: address 0210
Line selection bit for slice voltage
0: Main data slice line
1: Sub-data slice line
Field to be sliced data selection bit
b2 b1
Field of sub-data
slice line
0 0 F2
0 1 F1
1 0 F1 and F2
1 1 F1 and F2
Setting bit of sub-data slice line
16)
Field for setting
reference voltage
F2
F1
F2
F1
27
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
(1) Clamping Circuit and Low-pass Filter
This filter attenuates the noise of the composite video signal input
from the CV
input requires a capacitor (0.1 µF) coupling outside. Pull down the
CV
IN pin with a resistor of hundreds of kiloohms to 1 M . In addition,
we recommend to install externally a simple low-pass filter using a
resistor and a capacitor at the CV
IN pin. The CVIN pin to which composite video signal is
IN pin (refer to Figure 19).
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
and ON-SCREEN DISPLAY CONTROLLER
07
000
0011
Sync slice register
(SSL : address 00E3
Fix these bits to “00001012”
16)
(2) Sync Slice Circuit
This circuit takes out a composite sync signal from the output signal
of the low-pass filter. Figure 21 shows the structure of the sync slice
register.
(3) Synchronizing Signal Separation Circuit
This circuit separates a horizontal synchronizing signal and a vertical
synchronizing signal from the composite sync signal taken out in the
sync slice circuit.
➀ Horizontal synchronizing signal (H
A one-shot horizontal synchronizing signal Hsep is generated at
the falling edge of the composite sync signal.
➁ Vertical synchronizing signal (V
As a V
sep signal generating method, it is possible to select one of
the following 2 methods by using bit 7 of the sync slice register
(address 00E3
•Method 1 The “L” level width of the composite sync signal is
•Method 2 The “L” level width of the composite sync signal is
Figure 22 shows a V
in the figure is generated from the reference clock which the timing
generating circuit outputs.
Reading bit 5 of data slicer control register 2 permits determinating
the shape of the V-pulse portion of the composite sync signal. As
shown in Figure 23, when the A level matches the B level, this bit is
“0.” In the case of a mismatch, the bit is “1.”
For the pins RVCO and the HLF, connect a resistor and a capacitor
as shown in Figure 19. Make the length of wiring which is connected
to these pins as short as possible so that a leakage current may not
be generated.
16).
measured. If this width exceeds a certain time, a V
signal is generated in synchronization with the rising
of the timing signal immediately after this “L” level.
measured. If this width exceeds a certain time, it is
detected whether a falling of the composite sync
signal exits or not in the “L” level period of the timing
signal immediately after this “L” level. If a falling exists,
a V
sep signal is generated in synchronization with
the rising of the timing signal (refer to Figure 22).
sep generating timing. The timing signal shown
sep)
sep)
sep
Vertical synchronizing
signal (Vsep) generating
method selection bit
0 : Method 1
1 : Method 2
Fig. 21. Structure of sync slice register
Composite
sync signal
Measure “L” period
Timing
signal
V
sep signal
A V
sep signal is generated at a rising of the timing signal
immediately after the “L” level width of the composite
sync signal exceeds a certain time.
Fig. 22. Vsep generating timing (method 2)
Note: It takes a few tens of milliseconds until the reference clock
becomes stable after the data slicer and the timing signal
generating circuit are started. In this period, various timing
signals, H
this reason, take stabilization time into consideration when
programming.
28
sep signals and Vsep signals become unstable. For
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
(4) Timing Signal Generating Circuit
This circuit generates a reference clock which is 832 times as large
as the horizontal synchronizing signal frequency. It also generates
various timing signals on the basis of the reference clock, horizontal
synchronizing signal and vertical synchronizing signal. The circuit
operates by setting bit 0 of data slicer control register 2 (address
00EB
16) to “1.”
The reference clock can be used as a display clock for OSD function
in addition to the data slicer. The H
count source instead of the composite sync signal. However, when
the H
SYNC signal is selected, the data slicer cannot be used. A count
source of the reference clock can be selected by bit 1 of data slicer
control register 2 (address 00EB
SYNC signal can be used as a
16).
MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
and ON-SCREEN DISPLAY CONTROLLER
V-pulse
(“L” pulse width is long,
“H” pulse width is short)
Composite
sync signal
AB
Bit 5 of
DSC2
0
1
1
Fig. 23. Determination of V-pulse waveform
29
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