Mitsubishi M37224M3-XXXSP Datasheet
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
DESCRIPTION
The M37224M3-XXXSP is a single-chip microcomputer designed with
CMOS silicon gate technology. They are housed in a 42-pin shrink
plastic molded DIP.
In addition to their simple instruction sets, the ROM, RAM and I/O
addresses are placed on the same memory map to enable easy programming.
The M37224M3-XXXSP has a PWM output function and a OSD display function, so it is useful for a channel selection system for TV.
FEATURES
Number of basic instructions..................................................... 71
•
Memory size
•
Minimum instruction execution time
•
......................................... 0.5
Power source voltage...................................................5 V ± 10 %
•
Power dissipation ............................................................. 165 mW
•
(at 8 MHz oscillation frequency, VCC=5.5V, at CRT display)
Subroutine nesting ....................................... 96 levels (maximum)
•
Interrupts .......................................................13 types, 13 vectors
•
8-bit timers .................................................................................. 4
•
Programmable I/O ports (Ports P0, P1, P2, P30–P32).............. 27
•
Input ports (Ports P33, P34) ........................................................ 2
•
Output ports (Ports P52–P55)...................................................... 4
•
12 V withstand ports.................................................................... 6
•
LED drive ports ........................................................................... 4
•
Serial I/O ............................................................8-bit ✕ 1 channel
•
A-D comparator (6-bit resolution).................................6 channels
•
D-A converter (6-bit resolution) ................................................... 2
•
PWM output circuit ......................................... 14-bit ✕ 1, 8-bit ✕ 6
•
ROM correction function ........................................... 32 bytes ✕ 2
•
ROM ....................................................... 12 K bytes
RAM ..........................................................256 bytes
ROM for display ........................................ 8 K bytes
RAM for display .......................................... 96 bytes
µ
s (at 8 MHz oscillation frequency)
PIN CONFIGURATION (TOP VIEW)
H
SYNC
V
SYNC
P00/PWM0
1
/PWM1
P0
2
/PWM2
P0
3
/PWM3
P0
4
/PWM4
P0
5
/PWM5
P0
P06/INT2/A-D4
P0
7
/INT1
3
/TIM3
P2
4
/TIM2
P2
P2
P2
P2
D-A
P3
CNV
X
OUT
X
V
SS
IN
SS
1
2
3
4
5
6
7
M37224M3-XXXSP
8
9
10
11
12
5
13
6
14
7
15
16
2
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
Outline 42P4B
P52/R
3
/G
P5
4
/B
P5
5
/OUT
P5
0/SCLK
P2
P21/S
OUT
P22/S
IN
P1
0
P1
1
P1
2
P1
3
P1
4
P15/A-D1/INT3
P16/A-D2
P17/A-D3
P3
0
/A-D5/DA1
1
/A-D6/DA2
P3
RESET
OSC1/P3
OSC2/P3
V
3
4
CC
CRT display function
•
Number of display characters................ 20 characters ✕ 2 lines
(16 lines maximum)
Kinds of characters ..................................................... 128 kinds
Dot structure...........................................................12 ✕ 16 dots
Kinds of character sizes ..................................................3 kinds
Kinds of character colors (It can be specified by the character)
maximum 7 kinds (R, G, B)
Kinds of raster colors (maximum 7 kinds)
Display position
Horizontal ..................................................................64 levels
Vertical .................................................................... 128 levels
Bordering (horizontal and vertical)
APPLICATION
TV
4
P3
3,
23
OSC2
Clock output for display
24
OSC1
Input ports P3
Clock input for display
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
H
SYNC
1
V
SYNC
2
Synchronous
5
42
41
–P5
40
2
39
Output ports P5
signal input
Output for display
decoder
Instruction
Control signal
Instruction
register (8)
CRT circuit
P5 (4)
function
ROM correction
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
8-bit PWM circuit
S
OUT
S
CLK
S
IN
SI/O(8)
R
G
B
OUT
selection circuit
Timer count source
TIM3
SS
18
TIM2
T1 (8)
Timer 1
T2 (8)
Timer 2
T3 (8)
Timer 3
T4 (8)
Timer 4
CNV
SS
21
V
CC
22
V
25
RESET
Reset input
Data bus
ROM
12 K bytes
counter
Program
counter
Program
RAM
256 bytes
(8)
L
PC
(8)
H
PC
Stack
Index
Index
Processor
( ) Timing output
20
OUT
Clock output
X
IN
19
X
Clock input
Clock
circuit
generating
Address bus
8-bit
FUNCTIONAL BLOCK DIAGRAM of M37224M3-XXXSP
S (8)
pointer
Y (8)
register
X (8)
register
status
PS (8)
register
A (8)
Accumulator
and
arithmetic
logical unit
D-A
converter
2
interface
I C-BUS
Multi-master
P3 (3)
INT1
14-bit
INT2
PWM circuit
INT3
P2 (8)
A-D
comparator
P1 (8)
P0 (8)
2
–P3
0
27
26
17
I/O ports P3
16
D-A
38
37
36
11
12
13
I/O port P2
14
15
35
34
33
32
31
30
I/O port P1
29
28
3
4
5
6
7
8
I/O port P0
9
10
2
FUNCTIONS
Number of basic instructions
Instruction execution time
Clock frequency
Memory size
Input/Output ports
Serial I/O
A-D comparator
D-A converter
PWM output circuit
Timers
ROM correction function
Subroutine nesting
Interrupt
Clock generating circuit
Power source voltage
Power dissipation
Operating temperature range
Device structure
Package
CRT display function
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
Parameter
ROM
RAM
CRT ROM
CRT RAM
P0
P10–P17
P20, P21
P22–P27
P30, P31
P32
P33, P34
P52–P55
CRT ON
CRT OFF
In stop mode
Number of display characters
Dot structure
Kinds of characters
Kinds of character sizes
Kinds of character colors
Display position (horizontal, vertical)
Input
Output
I/O
I/O
I/O
I/O
I/O
I/O
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
with ON-SCREEN DISPLAY CONTROLLER
Functions
71
0.5 µs (the minimum instruction execution time, at 8 MHz oscillation frequency)
8 MHz (maximum)
12 K bytes
256 bytes
4 K bytes
80 bytes
8-bit ✕ 1 (N-channel open-drain output structure, can be used as PWM
output pins, INT input pins, A-D input pin)
8-bit ✕ 1 (CMOS input/output structure, can be used as A-D input pins, INT
input pin)
2-bit ✕ 1 (CMOS input/output or N-channel open-drain output structure,
can be used as serial I/O pins)
6-bit ✕ 1 (CMOS input/output structure, can be used as serial input pin,
external clock input pins)
2-bit ✕ 1 (CMOS input/output or N-channel open-drain output structure,
can be used as A-D input pins, D-A conversion output pins)
1-bit ✕ 1 (N-channel open-drain output structure)
2-bit ✕ 1 (can be used as CRT display clock I/O pins)
4-bit ✕ 1 (CMOS output structure, can be used as CRT output pins)
8-bit ✕ 1
6 channels (6-bit resolution)
2 (7-bit resolution)
14-bit ✕ 1, 8-bit ✕ 6
8-bit timer ✕ 4
32 bytes ✕ 2
96 levels (maximum)
External interrupt ✕ 3, Internal timer interrupt ✕ 4, Serial I/O interrupt ✕ 1,
CRT interrupt ✕ 1, f(XIN)/4096 interrupt ✕ 1, VSYNC interrupt ✕ 1,
BRK interrupt ✕ 1
2 built-in circuits (externally connected to a ceramic resonator or a quartzcrystal oscillator)
5 V ± 10 %
165 mW typ. (at oscillation frequency f(XIN) = 8 MHz, fCRT = 8 MHz)
110 mW typ. (at oscillation frequency f(XIN) = 8 MHz)
1.65 mW (maximum)
–10 °C to 70 °C
CMOS silicon gate process
42-pin shrink plastic molded DIP
20 characters ✕ 2 lines (maximum 16 lines by software)
12 ✕ 16 dots
128 kinds
3 kinds
Maximum 7 kinds (R, G, B); can be specified by the character
64 levels (horizontal) ✕ 128 levels (vertical)
3
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
PIN DESCRIPTION
Pin Name Functions
VCC,
VSS.
Power source
Input/
Output
Apply voltage of 5 V ± 10 % (typical) to VCC, and 0 V to VSS.
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
with ON-SCREEN DISPLAY CONTROLLER
CNVSS
______
RESET
XIN
XOUT
P00/PWM0–
P05/PWM5,
P06/INT2/
A-D4,
P07/INT1
P10–P14,
P15/A-D1/
INT3,
P16/A-D2,
P17/A-D3
P20/SCLK,
P21/SOUT,
P22/SIN,
P23/TIM3,
P24/TIM2,
P25–P27
P30/A-D5/
DA1,
P31/A-D6/
DA2,
P32
P33/OSC1,
P34/OSC2
CNVSS
Reset input
Clock input
Clock output
I/O port P0
PWM output
External interrupt
input
Analog input
I/O port P1
Analog input
External interrupt
input
I/O port P2
External clock input
Serial I/O synchro-
nous clock input/
output
Serial I/O data
output
Serial I/O data input
I/O port P3
Analog input
D-A conversion
output
Input port P3
Clock input for
CRT display
Clock output for
CRT display
Input
Input
Output
I/O
Output
Input
Input
I/O
Input
Input
I/O
Input
I/O
Output
Input
I/O
Input
Output
Input
Input
Output
Connected to VSS.
To enter the reset state, the reset input pin must be kept at a “L” for 2 µs or more (under
normal VCC conditions).
If more time is needed for the quartz-crystal oscillator to stabilize, this “L” condition should
be maintained for the required time.
This chip has an internal clock generating circuit. To control generating frequency, an
external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and
XOUT. If an external clock is used, the clock source should be connected to the XIN pin and
the XOUT pin should be left open.
Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually
programmed as input or output. At reset, this port is set to input mode. The output structure
is N-channel open-drain output. See notes at end of Table for full details of port P0 functions.
Pins P00–P05 are also used as PWM output pins PWM0–PWM5 respectively. The output
structure is N-channel open-drain output.
Pins P06 , P07 are also used as external interrupt input pins INT2, INT1 respectively.
P06 pin is also used as analog input pin A-D4.
Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output.
Pins P15–P17 are also used as analog input pins A-D1 to A-D3 respectively.
P15 pin is also used as external interrupt input pin INT3.
Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output.
Pins P23, P24 are also used as external clock input pins TIM3, TIM2 respectively.
P20 pin is also used as serial I/O synchronous clock input/output pin SCLK. The output
structure is N-channel open-drain output.
Pin P21 is also used as serial I/O data output pin SOUT. The output structure is N-channel
open-drain output.
Pin P22 is also used as serial I/O data input pin SIN.
Ports P30–P32 are 3-bit I/O ports and have basically the same functions as port P0. Either
CMOS output or N-channel open-drain output structure can be selected as the port P30
and P31. The output structure of port P32 is N-channel open-drain output.
Pins P30, P31 are also used as analog input pins A-D5, A-D6 respectively.
Pins P30, P31 are also used as D-A conversion output pins DA1, DA2 respectively.
Ports P33, P34 are 2-bit input ports.
P33 pin is also used as CRT display clock input pin OSC1.
P34 pin is also used as CRT display clock output pin OSC2. The output structure is CMOS
output.
4
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
PIN DESCRIPTION (continued)
Pin Name Functions
P52/R,
P53/G,
P54/B,
P55/OUT
HSYNC
VSYNC
D-A
Note : As shown in the memory map (Figure 5), port P0 is accessed as a memory at address 00C016 of zero page. Port P0 has the port P0
Output port P5
CRT output
HSYNC input
VSYNC input
DA output
direction register (address 00C116 of zero page) which can be used to program each bit as an input (“0”) or an output (“1”). The pins
programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are
programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the
output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the
output LOW voltage has risen, for example, because a light emitting diode was directly driven. The input pins are float, so the values of
the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state.
Input/
Output
Output
Output
Input
Input
Output
Ports P52–P55 are a 4-bit output port. The output structure is CMOS output.
Pins P52–P55 are also used as CRT output pins R, G, B, OUT respectively. The output
structure is CMOS output.
This is a horizontal synchronous signal input for CRT.
This is a vertical synchronous signal input for CRT.
This is a 14-bit PWM output pin.
5
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
Ports P0
0
–P05, P3
Data bus
Ports P1, P2, P30, P3
Data bus
2
Direction register
Port latch
1
Direction register
Port latch
N-channel open drain output
Ports P00–P05, P32
Note: Each port is also used as follows:
P00–P05 : PWM0–PWM5
CMOS output
Ports P1, P2, P30, P31
Note: Each port is also used as follows:
P15 : A-D1/INT3
P16 : A-D2
P17 : A-D3
P20 : SCLK
P21 : SOUT
P22 : SIN
P23 : TIM3
P24 : TIM2
P30 : A-D5/DA1
P31 : A-D6/DA2
Ports P06, P0
Data bus
Fig. 1. I/O Pin Block Diagram (1)
7
Direction register
Port latch
N-channel open-drain output
Ports P06, P07
Note: Each port is also used as follows:
P06 : INT2/A-D4
P07 : INT1
6
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
H
SYNC
, V
SYNC
Internal circuit
Fig. 2. I/O Pin Block Diagram (2)
Schmidt input
HSYNC, VSYNC
D-A, P52–P5
Internal circuit
5
CMOS output
D-A, P52–P55
Note: Each port is also used
as follows:
P52 : R
P53 : G
P54 : B
OUT : P55
7
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The M37224M3-XXXSP uses the standard 740 Family instruction
set. Refer to the table of 740 Family addressing modes and machine
instructions or the SERIES 740 <Software> User’s Manual for details on the instruction set.
Machine-resident 740 family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instructions can be used.
CPU Mode Register
b7b6 b5b4b3 b2b1b0
100
111
1
CPU mode register (CPUM (CM)) [Address FB16]
B
Processor mode bits
0, 1
Name Functions
(CM0, CM1)
CPU Mode Register
The CPU mode register contains the stack page selection bit. The
CPU mode register is allocated at address 00FB16.
After reset
b1 b0
0 0: Single-chip mode
0 1:
1 0: Not available
1 1:
RW
RW
0
Fig. 3. CPU Mode Register
Stack page selection
2
bit (CM2) (See note)
Fix these bits to “1.”
3
0: 0 page
1: 1 page
to
7
Note: This bit is set to “1” after the reset release.
RW
1
RW
1
8
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
MEMORY
Special Function Register (SFR) Area
The special function register (SFR) area in the zero page contains
control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
ROM
ROM is used for storing user programs as well as the interrupt vector
area.
RAM for Display
RAM for display is used for specifying the character codes and colors to display.
ROM for Display
ROM for display is used for storing character data.
0000
16
RAM
(256 bytes)
00C0
00FF
16
SFR area
16
Zero page
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
ROM Correction Memory (RAM)
This is used as the program area for ROM correction.
16
ROM
for display
(4K bytes)
10000
10FFF
16
RAM
for display
(Note)
(80 bytes)
ROM
(12K bytes)
013F
0217
021B
02C0
02FF
0600
06B3
D000
FF00
FFDE
FFFF
16
16
16
16
16
16
16
16
16
16
16
Not used
2 page register
Not used
Not used
Not used
Interrupt vector area
ROM correction memory (RAM)
Block 1: addresses 02C0
Block 2: addresses 02E016 to 02FF
Special page
Note: Refer to Table 8. Contents of CRT display RAM.
16
to 02DF
1FFFF
16
16
Not used
16
Fig. 4. Memory Map
9
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
■SFR Area (addresses C016 to DF16)
<Bit allocation>
:
Name
:
: No function bit
: Fix this bit to “0”
0
(do not write “1”)
: Fix this bit to “1”
1
(do not write “0”)
Function bit
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
with ON-SCREEN DISPLAY CONTROLLER
<State immediately after reset>
: “0” immediately after reset
0
1
: “1” immediately after reset
: Undefined immediately
?
after reset
Address
Port P0 (P0)
C0
16
Port P0 direction register (D0)
C1
16
Port P1 (P1)
C2
16
Port P1 direction register (D1)
C3
16
Port P2 (P2)
C4
16
Port P2 direction register (D2)
C5
16
Port P3 (P3)
C6
16
Port P3 direction register (D3)
C7
16
C8
16
C9
16
Port P5 (P5)
CA
16
Port P5 direction register (D5)
CB
16
CC
16
Port P3 output mode control register (P3S)
CD
16
DA-H register (DA-H)
CE
16
DA-L register (DA-L)
CF
16
PWM0 register (PWM0)
D0
16
PWM1 register (PWM1)
D1
16
PWM2 register (PWM2)
D2
16
PWM3 register (PWM3)
D3
16
PWM4 register (PWM4)
D4
16
PWM output control register 1 (PW)
D5
16
PWM output control register 2 (PN)
D6
16
D7
16
D8
16
D9
16
DA
16
DB
16
Serial I/O mode register (SM)
DC
16
Serial I/O regsiter (SIO)
DD
16
DA1 conversion register (DA1)
DE
16
DA2 conversion register (DA2)
DF
16
Register
b7 b0
DA17
DA27
Bit allocation State immediately after reset
DA1SDA2S
PN2PN3PN4
0
0
0
P30SP31S
PW0PW1PW2PW3PW4PW5PW6PW7
SM0SM1SM2SM3SM5SM6
DA10DA11DA12DA13DA14DA15
DA20DA21DA22DA23DA24DA25
b7 b0
?
16
00
?
16
00
?
16
00
000
00
16
?????
?
?
00
00
????
16
?
?
?
00
16
?
00
??????
?
?
?
?
?
16
00
00
16
?
?
?
?
?
00
16
?
?
?
Fig. 5. Memory Map of SFR (special function register) (1)
10
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
■
SFR Area (addresses E016 to FF16)
<
Bit allocation>
:
Name
:
: No function bit
: Fix this bit to “0”
0
(do not write “1”)
: Fix this bit to “1”
1
(do not write “0”)
Function bit
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
with ON-SCREEN DISPLAY CONTROLLER
<
State immediately after reset>
: “0” immediately after reset
0
1
: “1” immediately after reset
: Undefined immediately
?
after reset
Address
Horizontal register (HR)
E0
16
Vertical register 1 (CV1)
E1
16
Vertical register 1 (CV1)
E2
16
E3
16
Character size register (CS)
E4
16
Border selection register (MD)
E5
16
Color register 0 (CO0)
E6
16
Color register 1 (CO1)
E7
16
Color register 2 (CO2)
E8
16
Color register 3 (CO3)
E9
16
CRT control register (CO)
EA
16
EB
16
EC
16
CRT port control register (CRTP)
CRT clock selection register (CK)
ED
16
A-D control register 1 (AD1)
EE
16
A-D control register 2 (AD2)
EF
16
Timer 1 (TM1)
F0
16
Timer 2 (TM2)
F1
16
Timer 3 (TM3)
F2
16
Timer 4 (TM4)
F3
16
Timer 12 mode register (T12M)
F4
16
Timer 34 mode register (T34M)
F5
16
PWM5 register (PWM5)
F6
16
F7
16
F8
16
Interrupt input polarity register (RE)
F9
16
Test register (TEST)
FA
16
CPU mode register (CPUM)
FB
16
Interrupt request register 1 (IREQ1)
FC
16
Interrupt request register 2 (IREQ2)
FD
16
Interrupt control register 1 (ICON1)
FE
16
Interrupt control register 2 (ICON2)
FF
16
Register
b7 b0
0
1
0
Bit allocation State immediately after reset
HR0HR1HR2HR3HR4HR5
CV10CV11CV12CV13CV14CV15CV16
CV20CV21CV22CV23CV24CV25CV26
CS10CS11CS20CS21
MD10MD20
CO01CO02CO03CO05
0
CO11CO12CO13CO15
0
CO21CO22CO23CO25
0
CO31CO32CO33CO35
0
CC0CC1CC2
VSYC
OUTOP5OP6OP7
000000
0
T34M5
CK0RE5 RE4 RE3
16
00
1111
CK0MSR
00 00
R/G/B
0
CM2
S1R
S1EMSE
HSYC
CK0CK1
ADM0ADM1ADM2ADM4
ADC0ADC1ADC2ADC4ADC3ADC5
T12M0T12M1T12M2T12M3T12M4
T34M0T34M1T34M2T34M3T34M4
0
00
TM1RTM2RTM3RTM4RCRTRVSCRIT3R
IT1RIT2R
TM1ETM2ETM3ETM4ECRTEVSCEIT3E
IT1EIT2E
b7 b0
00
16
0
??????
?
?0??????
?
0000
00000 0
????
??
00
16
00
16
00
16
00
16
00
16
?
00
16
00
16
00 00000
?
00
FF
07
FF
07
00
00
16
16
16
16
16
16
16
?
?
?
0000 ?
000
CK0
00
FC
00
00
00
00
16
16
16
16
16
16
Fig. 6. Memory Map of SFR (special function register) (2)
11
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
■SFR Area (addresses 21716 to 21B16)
<
Bit allocation>
:
Function bit
Name
:
: No function bit
: Fix this bit to “0”
0
(do not write “1”)
: Fix this bit to “1”
1
(do not write “0”)
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
with ON-SCREEN DISPLAY CONTROLLER
<
State immediately after reset>
: “0” immediately after reset
0
1
: “1” immediately after reset
: Undefined immediately
?
after reset
Address
217
16
ROM correction address 1 (high-order)
218
16
ROM correction address 1 (low-order)
219
21A
21B
Fig. 7. Memory Map of 2 Page Register
ROM correction address 2 (high-order)
16
16
ROM correction address 2 (low-order)
16
ROM correction enable register (RCR)
Register
Register
Processor status register (PS)
Program counter (PCH)
Program counter (PCL)
b7
<Bit allocation>
:
Function bit
Name
:
: No function bit
: Fix this bit to “0”
0
(do not write “1”)
: Fix this bit to “1”
1
(do not write “0”)
Bit allocation State immediately after reset
b7
Bit allocation State immediately after reset
000
I ZCDBTVN?????
b0
b7
RC1RC0
<State immediately after reset>
0
1
?
b0
b7
????
: “0” immediately after reset
: “1” immediately after reset
: Undefined immediately
after reset
Contents of address FFFF
Contents of address FFFE
00
00
00
00
16
16
16
16
0
b0
??
1
16
16
b0
00
Fig. 8. Internal State of Processor Status Register and Program Counter at Reset
12
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
INTERRUPTS
Interrupts can be caused by 13 different sources consisting of 4 external, 7 internal, 1 software, and reset. Interrupts are vectored interrupts with priorities shown in Table 1. Reset is also included in the
table because its operation is similar to an interrupt.
When an interrupt is accepted,
(1) The contents of the program counter and processor status
register are automatically stored into the stack.
(2) The interrupt disable flag I is set to “1” and the corresponding
interrupt request bit is set to “0.”
(3) The jump destination address stored in the vector address enters
the program counter.
Other interrupts are disabled when the interrupt disable flag is set to
“1.”
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits are
in interrupt request registers 1 and 2 and the interrupt enable bits are
in interrupt control registers 1 and 2. Figures 10 to 14 show the interrupt-related registers.
Interrupts other than the BRK instruction interrupt and reset are accepted when the interrupt enable bit is “1,” interrupt request bit is “1,”
and the interrupt disable flag is “0.” The interrupt request bit can be
set to “0” by a program, but not set to “1.” The interrupt enable bit can
be set to “0” and “1” by a program.
Reset is treated as a non-maskable interrupt with the highest priority.
Figure 9 shows interrupt control.
Interrupt Causes
(1) VSYNC and CRT interrupts
The VSYNC interrupt is an interrupt request synchronized with
the vertical sync signal.
The CRT interrupt occurs after character block display to the CRT
is completed.
(2) INT1, INT2, INT3 interrupts
With an external interrupt input, the system detects that the level
of a pin changes from “L” to “H” or from “H” to “L,” and generates
an interrupt request. The input active edge can be selected by
bits 3, 4 and 5 of the interrupt input polarity register (address
00F916) : when this bit is “0,” a change from “L” to “H” is detected; when it is “1,” a change from “H” to “L” is detected. Note
that all bits are cleared to “0” at reset.
(3) Timer 1, 2, 3 and 4 interrupts
An interrupt is generated by an overflow of timer 1, 2, 3 or 4.
(4) Serial I/O interrupt
This is an interrupt request from the clock synchronous serial
I/O function.
Table 1. Interrupt Vector Addresses and Priority
Interrupt Source
Reset
CRT interrupt
INT2 interrupt
INT1 interrupt
Timer 4 interrupt
f(XIN)/4096 interrupt
VSYNC interrupt
Timer 3 interrupt
Timer 2 interrupt
Timer 1 interrupt
Serial I/O interrupt
INT3 interrupt
BRK instruction interrupt
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
Vector Addresses
FFFF16, FFFE16
FFFD16, FFFC16
FFFB16, FFFA16
FFF916, FFF816
FFF516, FFF416
FFF316, FFF216
FFF116, FFF016
FFEF16, FFEE16
FFED16, FFEC16
FFEB16, FFEA16
FFE916, FFE816
FFE516, FFE416
FFDF16, FFDE16
Remarks
Non-maskable
Active edge selectable
Active edge selectable
Active edge selectable
Active edge selectable
Non-maskable (software interrupt)
13
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
(5) f(XIN)/4096 interrupt
This interrupt occurs regularly with a f(XIN)/4096 period. Set bit 0
of the PWM output control register 1 to “0.”
(6) BRK instruction interrupt
This software interrupt has the least significant priority. It does
not have a corresponding interrupt enable bit, and it is not affected by the interrupt disable flag I (non-maskable).
Interrupt request bit
Interrupt enable bit
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
with ON-SCREEN DISPLAY CONTROLLER
Fig. 9. Interrupt Control
Interrupt disable flag I
BRK instruction
Reset
Interrupt request
14
Interrupt Request Register 1
b7b6 b5b4b3 b2b1b0
Interrupt request register 1 (IREQ1) [Address 00FC
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
16
]
Fig. 10. Interrupt Request Register 1
B Name Functions
0
Timer 1 interrupt
request bit (TM1R)
1 Timer 2 interrupt
request bit (TM2R)
2 Timer 3 interrupt
request bit (TM3R)
Timer 4 interrupt
3
request bit (TM4R)
4 CRT interrupt
request bit (CRTR)
5V
SYNC
interrupt
request bit (VSCR)
Nothing is assigned. This bit is a write disable bit.
6
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
When this bit is read out, the value is “0.”
INT3 interrupt
7
request bit (IT3R)
0 : No interrupt request issued
1 : Interrupt request issued
After reset
0 ✽
0 ✽
0 ✽
0 ✽
0 ✽
0 ✽
0
0
RW
R
R
R
R
R
R
—
R
✽
R
Interrupt Request Register 2
b7b6 b5b4b3 b2b1b0
0
Fig. 11. Interrupt Request Register 2
Interrupt request register 2 (IREQ2) [Address 00FD
B Name Functions
INT1 interrupt
0
request bit (ITIR)
INT2 interrupt
1
request bit (IT2R)
Serial I/O interrupt
2
request bit (SIR)
3,
Nothing is assigned. These bits are write disable bits.
5,
6
When these bits are read out, the values are “0.”
IN
)/4096 interrupt
f(X
4
request bit (MSR)
7
Fix this bit to “0.”
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
✽: “0” can be set by software, but “1” cannot be set.
16
]
After reset
RW
0 ✽
R
0 ✽
R
0 ✽
R
0
R—
0 ✽
R
0
RW
15
Interrupt Control Register 1
b7b6 b5b4 b3 b2b1b0
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
16
Interrupt control register 1 (ICON1) [Address 00FE
]
Fig. 12. Interrupt Control Register 1
Interrupt Control Register 2
b7b6 b5b4b3b2b1b0
00
0
0
B Name Functions
Timer 1 interrupt
0
enable bit (TM1E)
Timer 2 interrupt
1
enable bit (TM2E)
Timer 3 interrupt
2
enable bit (TM3E)
Timer 4 interrupt
3
enable bit (TM4E)
CRT interrupt enable bit
4
(CRTE)
SYNC
interrupt enable
V
5
bit (VSCE)
6
Nothing is assigned. This bit is a write disable
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
bit. When this bit is read out, the value is “0.”
7
INT3 interrupt enable bit
(IN3E)
0 : Interrupt disabled
1 : Interrupt enabled
Interrupt control register 2 (ICON2) [Address 00FF
After reset
0
0
0
0
0
0RW
0R
0
16
]
RW
RW
RW
RW
RW
RW
—
R
W
Fig. 13. Interrupt Control Register 2
16
B Name Functions
INT1 interrupt
0
enable bit (IT1E)
INT2 interrupt enable
1
bit (IT2E)
Serial I/O interrupt
2
enable bit (SIE)
Fix these bits to “0.”
3,
5
to
7
4
IN
)/4096 interrupt
f(X
enable bit (MSE)
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
After reset
0
0
0
0
0
RW
RW
RW
RW
RW
RW
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
Interrupt Input Polarity Register
b7 b6 b5 b4 b3 b2 b1 b0
000
Interrupt input polarity register(RE) [Address 00F9
B Name Functions After reset R W
Nothing is assigned. This bit is a write disable bit.
0
When this bit is read out, the value is indeterminate.
1, 2 0
Fix these bits to “0.”
INT1 polarity switch bit
3
(RE3)
INT2 polarity switch bit
4
(RE4)
INT3 polarity switch bit
5
(RE5)
Nothing is assigned. This bit is a write disable bit.
6
When this bit is read out, the value is “0.”
7
Fix this bit to “0.”
MITSUBISHI MICROCOMPUTERS
with ON-SCREEN DISPLAY CONTROLLER
16
0 : Positive polarity
1 : Negative polarity
0 : Positive polarity
1 : Negative polarity
0 : Positive polarity
1 : Negative polarity
M37224M3-XXXSP
]
Indeterminate
R—
RW
RW
0
RW
0
RW
0
R—
0
RW
0
Fig. 14. Interrupt Input Polarity Register
17
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
TIMERS
The M37224M3-XXXSP has 4 timers: timer 1, timer 2, timer 3, and
timer 4. All timers are 8-bit timer with the 8-bit timer latch. The timer
block diagram is shown in Figure 17.
All of the timers count down and their divide ratio is 1/(n+1), where n
is the value of timer latch. By writing a count value to the corresponding timer latch (addresses 00F016 to 00F316), the value is also set to
a timer, simultaneously.
The count value is decremented by 1. The timer interrupt request bit
is set to “1” by a timer overflow at the next count pulse, after the
count value reaches “0016”.
(1) Timer 1
Timer 1 can select one of the following count sources:
f(XIN)/16
•
f(XIN)/4096
•
The count source of timer 1 is selected by setting bit 0 of the timer 12
mode register (address 00F416).
Timer 1 interrupt request occurs at timer 1 overflow.
(2) Timer 2
Timer 2 can select one of the following count sources:
f(XIN)/16
•
Timer 1 overflow signal
•
External clock from the TIM2 pin
•
The count source of timer 2 is selected by setting bits 1 and 4 of
timer 12 mode register (address 00F416). When timer 1 overflow
signal is a count source for timer 2, timer 1 functions as an 8-bit
prescaler.
Timer 2 interrupt request occurs at timer 2 overflow.
At reset, timers 3 and 4 are connected by hardware and “FF16” is
automatically set in timer 3; “0716” in timer 4. The f(XIN)/16 is selected as the timer 3 count source. The internal reset is released by
timer 4 overflow in this state and the internal clock is connected.
At execution of the STP instruction, timers 3 and 4 are connected by
hardware and “FF16” is automatically set in timer 3; “0716” in timer 4.
However, the f(XIN)/16 is not selected as the timer 3 count source.
So set bit 0 of timer 34 mode register (address 00F516) to “0” before
execution of the STP instruction (f(XIN)/16 is selected as the timer 3
count source). The internal STP state is released by timer 4 overflow
in this state and the internal clock is connected.
As a result of the above procedure, the program can start under a
stable clock.
Timer-related registers are shown in Figures 15 and 16.
(3) Timer 3
Timer 3 can select one of the following count sources:
f(XIN)/16
•
External clock from the HSYNC pin
•
External clock from the TIM3 pin
•
The count source of timer 3 is selected by setting bits 0 and 5 of
timer 34 mode register (address 00F516)
Timer 3 interrupt request occurs at timer 3 overflow.
(4) Timer 4
Timer 4 can select one of the following count sources:
f(XIN)/16
•
f(XIN)/2
•
Timer 3 overflow signal
•
The count source of timer 3 is selected by setting bits 1 and 4 of
timer 34 mode register (address 00F516). When timer 3 overflow
signal is a count source for timer 4, timer 3 functions as an 8-bit
prescaler.
Timer 4 interrupt request occurs at timer 4 overflow.
18
Timer 12 Mode Register
b7b6 b5b4b3 b2b1b0
0
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
Timer 12 mode register (T12M) [Address 00F4
16
]
Fig. 15. Timer 12 Mode Register
Timer 34 Mode Register
B
0
Timer 1 count source
selection bit (T12M0)
1
Timer 2 count source
selection bit
(T12M1)
Timer 1 count
2
stop bit (T12M2)
Timer 2 count stop
3
bit (T12M3)
4
Timer 2 internal count
source selection bit
Name Functions
0: f(XIN)/16
1: f(X
IN
)/4096
0: Internal clock
1: External clock from
TIM2 pin
0: Count start
1: Count stop
0: Count start
1: Count stop
0: f(X
IN
)/16
1: Timer 1 overflow
(T12M4)
5
Fix this bit to “0.”
6,7
Nothing is assigned. These bits are write disable
bits. When these bits are read out, the values are
“0.”
After reset
0
0
0
0
0
0
0
R
W
WR
WR
WR
WR
WR
WR
—R
b7b6 b5b4b3 b2b1b0
Fig. 16. Timer 34 Mode Register
Timer 34 mode register (T34M) [Address 00F5
B
0
Timer 3 count source
selection bit (T34M0)
1
Timer 4 internal count
source selection bit
Name Functions
0: f(X
IN)/16
1: External clock
0: Timer 3 overflow
1: f(X
IN)/16
(T34M1)
Timer 3 count
2
stop bit (T34M2)
Timer 4 count stop
3
bit (T34M3)
Timer 4 count source
4
selection bit (T34M4)
Timer 3 external count
5
source selection bit (T34M5)
Nothing is assigned. These bits are write disable
6,7
0: Count start
1: Count stop
0: Count start
1: Count stop
0: Internal clock
1: f(X
IN)/2
0: External clock from TIM3 pin
1: External clock from H
bits. When these bits are read out, the values are
“0.”
16]
SYNC
pin
After reset
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
R—
19
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
Data bus
8
X
TIM2
HSYNC
TIM3
1/4096
IN
1/2
1/8
T12M0
T12M4
T12M1
T12M2
T12M3
T34M5
Timer 1 latch (8)
8
Timer 1 (8)
Timer 2 latch (8)
8
Timer 2 (8)
Timer 3 latch (8)
8
8
8
8
FF16
Timer 1
interrupt request
Timer 2
interrupt request
Reset
STP
instruction
8
Timer 3
interrupt request
T34M0
T34M2
Timer 3 (8)
8
Selection gate :
Connected to black
side at reset
T12M : Timer 12 mode register
T34M : Timer 34 mode register
Notes 1 : HIGH pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more.
2 :
When the external clock source is selected, timers 2 and 3 are counted at a rising edge
In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.
of input signal.
3 :
T34M1
Timer 4 latch (8)
8
Timer 4 (8)
T34M4
T34M3
Fig. 17. Timer Block Diagram
20
8
0716
Timer 4
interrupt request
8
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
SERIAL I/O
The M37224M3-XXXSP has a built-in serial I/O which can either transmit or receive 8-bit data serially in the clock synchronous mode.
The serial I/O block diagram is shown in Figure 18. The synchronous
clock I/O pin (SCLK), and data I/O pins (SOUT, SIN) also function as
port P2.
Bit 2 of the serial I/O mode register (address 00DC16) selects whether
the synchronous clock is supplied internally or externally (from the
P20/SCLK pin). When an internal clock is selected, bits 1 and 0 select
whether f(XIN) is divided by 4, 16, 32, or 64. Bit 3 selects whether
port P2 is used for serial I/O or not. To use the P22/SIN pin as the SIN
pin, set the bit 2 of the port P2 direction register (address 00C516) to
“0.”
The operation of the serial I/O is described below. The operation
differs depending on the clock source; external clock or internal
clock.
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
with ON-SCREEN DISPLAY CONTROLLER
X
IN
S
CLK
P2
1/2
0
latch
1/2
Synchronous circuit
SM3
1
latch
P2
S
OUT
SM5: LSB
SM3
S
IN
SM6
Note: When the data is set in the serial I/O register (address 00DD
Fig. 18. Serial I/O Block Diagram
Frequency
divider
SM2
S
Serial I/O counter (8)
MSB
(Note)
Serial I/O shift register (8)
(Address 00DD16)
16
), the register functions as the serial I/O shift register.
1/81/4 1/16
SM1
SM0
8
Data bus
Selection gate :
Connected to black
side at reset.
SM : Serial I/O mode register
Serial I/O interrupt
request
21
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
Internal clock: The serial I/O counter is set to “7” during the write
cycle into the serial I/O register (address 00DD16), and the transfer
clock goes “H” forcibly. At each falling edge of the transfer clock after
the write cycle, serial data is output from the SOUT pin. Transfer direction can be selected by bit 5 of the serial I/O mode register. At
each rising edge of the transfer clock, data is input from the SIN pin
and data in the serial I/O register is shifted 1 bit.
After the transfer clock has counted 8 times, the serial I/O counter
becomes “0” and the transfer clock stops at HIGH. At this time the
interrupt request bit is set to “1.”
External clock: When an external clock is selected as the clock source,
the interrupt request is set to “1” after the transfer clock has been
counted 8 counts. However, transfer operation does not stop, so the
clock should be controlled externally. Use the external clock of 1MHz
or less with a duty cycle of 50%.
The serial I/O timing is shown in Figure 19. When using an external
clock for transfer, the external clock must be held at HIGH for initializing the serial I/O counter. When switching between an internal clock
and an external clock, do not switch during transfer. Also, be sure to
initialize the serial I/O counter after switching.
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
with ON-SCREEN DISPLAY CONTROLLER
Notes 1: On programming, note that the serial I/O counter is set by
writing to the serial I/O register with the bit managing instructions, such as SEB and CLB.
2: When an external clock is used as the synchronous clock,
write transmit data to the serial I/O register when the transfer clock input level is HIGH.
Synchronous clock
Transfer clock
Serial I/O register
write signal
Serial I/O output
Serial I/O input
S
OUT
S
IN
D0 D1 D2 D3 D4 D5 D6 D7
(Note)
Note : When an internal clock is selected, the S
Fig. 19. Serial I/O Timing (for LSB first)
22
Interrupt request bit is set to “1”
OUT pin is at high-impedance after transfer is completed.
Serial I/O Mode Register
b7b6b5b4b3 b2b1b0
0
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
16
Serial I/O mode register (SM) [Address 00DC
]
B Name Functions
Internal synchronous
0, 1
clock selection bits
(SM0, SM1)
Synchronous clock
2
selection bit (SM2)
Serial I/O port
3
selection bit (SM3)
Fix this bit to “0.”
4
Transfer direction
5
selection bit (SM5)
6
Serial input pin
selection bit (SM6)
Nothing is assigned. This bit is a write disable bit.
7
When this bit is read out, the value is “0.”
b1 b0
0 0: f(X
0 1: f(X
1 0: f(X
1 1: f(X
IN
IN
IN
IN
)/4
)/16
)/32
)/64
0: External clock
1: Internal clock
0
, P21 functions
0: P2
as port
1: S
CLK
, S
OUT
0: LSB first
1: MSB first
Input signal from SIN pin
0:
1:
Input signal from S
OUT
pin
After reset
0
0
0
0
0
0
0
RW
RW
RW
RW
RW
RW
RW
R—
Fig. 20. Serial I/O Mode Register
23
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
Serial I/O Common Transmission/Reception Mode
By writing “1” to bit 6 of the serial I/O mode register, signals SIN and
SOUT are switched internally to be able to transmit or receive the
serial data.
Figure 21 shows signals on serial I/O common transmission/reception mode.
Note: When receiving the serial data after writing “FF16” to the serial
I/O register.
S
CLK
S
OUT
“1”
S
IN
“0”
SM6
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
with ON-SCREEN DISPLAY CONTROLLER
Clock
Serial I/O shift register (8)
SM: Serial I/O mode register
Fig. 21. Signals on Serial I/O Common Transmission/Reception Mode
24
MITSUBISHI MICROCOMPUTERS
M37224M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
PWM OUTPUT FUNCTION
The M37224M3-XXXSP is equipped with a 14-bit PWM (DA) and six
8-bit PWMs (PWM0–PWM5). DA has a 14-bit resolution with the
µ
minimum resolution bit width of 0.25
µ
s (for f(XIN) = 8 MHz). PWM0–PWM5 have the same circuit structure and an 8-bit resolution with minimum resolution bit width of 4 µs
and repeat period of 1024 µs (for f(XIN) = 8 MHz).
Figure 22 shows the PWM block diagram. The PWM timing generating circuit applies individual control signals to PWM0–PWM5 using
IN) divided by 2 as a reference signal.
f(X
s and a repeat period of 4096
(1) Data Setting
When outputting DA, first set the high-order 8 bits to the DA-H register (address 00CE16), then the low-order 6 bits to the DA-L register
(address 00CF16). When outputting PWM0–PWM5, set 8-bit output
data to the PWMi register (i means 0 to 5; addresses 00D0
00D4
16, 00F616).
16 to
(2) Transmitting Data from Register to PWM circuit
Data transfer from the 8-bit PWM register to the 8-bit PWM circuit is
executed at writing data to the register.
The signal output from the 8-bit PWM output pin corresponds to the
contents of this register.
Also, data transfer from the DA register (addresses 00CE16 and
00CF16) to the 14-bit PWM circuit is executed at writing data to the
DA-L register (address 00CF16). Reading from the DA-H register
(address 00CE16) means reading this transferred data. Accordingly,
it is possible to confirm the data being output from the D-A output pin
by reading the DA register.
(4) Operating of 14-bit PWM
As with 8-bit PWM, set the bit 0 of the PWM output control register 1
(address 00D516) to “0” (at reset, bit 0 is already set to “0” automatically), so that the PWM count source is supplied. Next, select the
output polarity by bit 2 of PWM output control register 2 (address
00D616). Then, the 14-bit PWM outputs from the D-A output pin by
setting bit 1 of PWM output control register 1 to “0” (at reset, this bit
already set to “0” automatically) to select the DA output.
The output example of the 14-bit PWM is shown in Figure 24.
The 14-bit PWM divides the data of the DA latch into the low-order 6
bits and the high-order 8 bits.
The fundamental waveform is determined with the high-order 8-bit
data “DH.” A “H” level area with a length τ ✕ DH(“H” level area of
fundamental waveform) is output every short area of “t” = 256τ =
64 µs (τ is the minimum resolution bit width of 0.25 µs). The “H” level
area increase interval (t
“D
L.” The “H” level are of smaller intervals “tm” shown in Table 6 is
longer by τ than that of other smaller intervals in PWM repeat period
“T” = 64t. Thus, a rectangular waveform with the different “H” width is
output from the D-A pin. Accordingly, the PWM output changes by τ
unit pulse width by changing the contents of the DA-H and DA-L
registers. A length of entirely “H” output cannot be output, i. e. 256/
256.
m) is determined with the low-order 6-bit data
(5) Output after Reset
At reset the output of port P00–P05 is in the high-impedance state,
and the contents of the PWM register and the PWM circuit are undefined. Note that after reset, the PWM output is undefined until setting
the PWM register.
(3) Operating of 8-bit PWM
The following explains PWM operation.
First, set the bit 0 of PWM output control register 1 (address 00D516)
to “0” (at reset, this bit 0 already set to “0” automatically), so that the
PWM count source is supplied.
PWM0–PWM5 are also used as pins P00–P05 respectively. For
PWM0–PWM5, set the corresponding bits of the port P0 direction
register to “1” (output mode). And select each output polarity by bit 3
of PWM output control register 2(address 00D616). Then, set bits 2
to 7 of PWM output control register 1 to “1” (PWM output).
The PWM waveform is output from the PWM output pins by setting
these registers.
Figure 23 shows the 8-bit PWM timing. One cycle (T) is composed
of 256 (28) segments. The 8 kinds of pulses, relative to the weight of
each bit (bits 0 to 7), are output inside the circuit during 1 cycle.
Refer to Figure 23 (a). The 8-bit PWM outputs waveform performed
a OR operation of pulses corresponding to the contents of bits 0 to 7
of the 8-bit PWM register. Several examples are shown in Figure 23
(b). 256 kinds of output (HIGH area: 0/256 to 255/256) are selected
by changing the contents of the PWM register. A length of entirely
HIGH cannot be output, i.e. 256/256.
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