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M37221M6-XXXSP
Datasheet
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Mitsubishi M37221M6-XXXSP Datasheet

MITSUBISHI MICROCOMPUTERS
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

DESCRIPTION

FEATURES

Number of basic instructions .....................................................71
•
Memory size
•
The minimum instruction execution time
•
..........................................0.5 s (at 8 MHz oscillation frequency)
Power source voltage ..................................................5 V ± 10 %
•
Power dissipation............................................................. 165 mW
•
(at 8 MHz oscillation frequency, V
Subroutine nesting....................................... 96 levels (maximum)
•
Interrupts....................................................... 14 types, 14 vectors
•
8-bit timers .................................................................................. 4
•
Programmable I/O ports (Ports P0, P1, P2, P30–P32).............. 27
•
Input ports (Ports P33, P34)......................................................... 2
•
Output ports (Ports P52–P55) ......................................................4
•
12 V withstand ports ....................................................................6
•
LED drive ports ........................................................................... 4
•
Serial I/O............................................................ 8-bit ✕ 1 channel
•
Multi-master I2C-BUS interface ............................... 1 (2 systems)
•
A-D comparator (6-bit resolution) ................................ 6 channels
•
PWM output circuit......................................... 14-bit ✕ 1, 8-bit ✕ 6
•
ROM ........................................................24 K bytes
RAM..........................................................384 bytes
ROM for display.........................................8 K bytes
RAM for display .......................................... 96 bytes
CC=5.5V, at CRT display)
M37221M6-XXXSP
with ON-SCREEN DISPLAY CONTROLLER
with ON-SCREEN DISPLAY CONTROLLER
M37221M6-XXXSP

PIN CONFIGURATION (TOP VIEW)

H
SYNC
V
SYNC
P00/PWM0 P0
1
/PWM1
P0
2
/PWM2
P0
3
/PWM3
P0
4
/PWM4
P0
5
/PWM5
P06/INT2/A-D4
P0
7
/INT1
P2
3
/TIM3
P2
4
/TIM2
P2 P2 P2
D-A
P3
CNV
X
X
OUT
V
SS
SS
1 2 3 4
5 6 7 8
9 10 11 12
5
13 14
6
15
7
16 17
2
18 19
IN
20 21
M37221M6-XXXSP
42
P52/R
41
P5
3
/G
P5
4
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
/B
P5
5
/OUT1
P2
0/SCLK
P21/S
P22/S
P10/OUT2 P1
1
/SCL1
P1
2
/SCL2
P1
3
/SDA1
P1
4
/SDA2
P1
5
/A-D1/INT3
P1
6
/A-D2
P17/A-D3
0
/A-D5
P3 P3
1
/A-D6
RESET OSC1/P3 OSC2/P3
V
CC
Outline 42P4B
OUT IN
3 4
CRT display function
•
Number of display characters ................24 characters ✕ 2 lines
(16 lines maximum)
Kinds of characters ..................................................... 256 kinds
Dot structure ..........................................................12 ✕ 16 dots
Kinds of character sizes.................................................. 3 kinds
Kinds of character colors (It can be specified by the character)
maximum 7 kinds (R, G, B)
Kinds of character background colors (It can be specified by the character)
maximum 7 kinds (R, G, B) Kinds of raster colors (maximum 7 kinds) Display position
Horizontal.................................................................. 64 levels
Vertical .................................................................... 128 levels
Bordering (horizontal and vertical)

APPLICATION

TV
1
MITSUBISHI MICROCOMPUTERS
OUT1
Clock input Clock output
X
IN
X
OUT
Reset input
V
CC
V
SS
CNV
SS
Clock output for display
Input ports P3
3,
P3
4
OSC1 OSC2
Clock input for display
INT2
INT1
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
P5 (4)
B
G
R
H
SYNC
V
SYNC
A-D
comparator
14-bit
PWM circuit
8-bit PWM circuit
Accumulator
A (8)
Timer 4
T4 (8)
Timer 3
T3 (8)
Timer 2
T2 (8)
Timer 1
T1 (8)
Timer count source
selection circuit
TIM2
TIM3
Instruction
register (8)
Instruction
decoder
Control signal
CRT circuit
Stack
pointer
S (8)
Index
register
Y (8)
Index
register
X (8)
Processor
status
register
PS (8)
8-bit
arithmetic
and
logical unit
ROM
24 K bytes
Program
counter
PC
L
(8)
Program
counter
PC
H
(8)
RAM
384 bytes
Data bus
Clock
generating
circuit
RESET
Output ports P5
2
–P5
5
Address bus
SI/O(8)
S
IN
S
CLK
S
OUT
INT3
10 9 8 7 6 5 4 3
I/O port P0
28 29 30 31 32 33 34 35
P1 (8)
I/O port P1
15 14 13 12 11 36 37 38
P2 (8)
I/O port P2
I/O ports P3
0
–P3
2
17 2627
16
P3 (3)
Multi-master
I C-BUS interface
P0 (8)
SDA
SCL
39
40
41
42 2 1
2019
25
22 21
18
24
23
( ) Timing output
OUT2
D-A
2
M37221M6-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
FUNCTIONAL BLOCK DIAGRAM of M37221M6-XXXSP
2
MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP

FUNCTIONS

Number of basic instructions Instruction execution time
Clock frequency Memory size
Input/Output ports
Serial I/O Multi-master I A-D comparator PWM output circuit Timers Subroutine nesting Interrupt
Clock generating circuit
Power source voltage Power dissipation
Operating temperature range Device structure Package CRT display function
2
C-BUS interface
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
Parameter
ROM RAM CRT ROM CRT RAM P0
P10, P15–P17
P11–P14
P20, P21
P22–P27
P30, P31
P32 P33, P34 P52–P55
CRT ON CRT OFF In stop mode
Number of display characters Dot structure Kinds of characters Kinds of character sizes Kinds of character colors Display position (horizontal, vertical)
Input
Output
I/O
I/O
I/O
I/O
I/O
I/O
I/O
with ON-SCREEN DISPLAY CONTROLLER
Functions
71
0.5 µs (the minimum instruction execution time, at 8 MHz oscillation fre­quency)
8 MHz (maximum) 24 K bytes 384 bytes 8 K bytes 96 bytes 8-bit ✕ 1 (N-channel open-drain output structure, can be used as PWM
output pins, INT input pins, A-D input pin) 4-bit ✕ 1 (CMOS input/output structure, can be used as CRT output pin,
A-D input pins, INT input pin) 4-bit ✕ 1 (CMOS input/output or N-channel open-drain output structure,
can be used as multi-master I 2-bit ✕ 1 (CMOS input/output or N-channel open-drain output structure,
can be used as serial output pins) 6-bit ✕ 1 (CMOS input/output structure, can be used as serial input pin,
external clock input pins) 2-bit ✕ 1 (CMOS input/output or N-channel open-drain output structure,
can be used as A-D input pins) 1-bit ✕ 1 (N-channel open-drain output structure) 2-bit ✕ 1 (can be used as CRT display clock I/O pins) 4-bit ✕ 1 (CMOS output structure, can be used as CRT output pins) 8-bit ✕ 1 1 (2 systems) 6 channels (6-bit resolution) 14-bit ✕ 1, 8-bit ✕ 6 8-bit timer ✕ 4 96 levels (maximum) External interrupt ✕ 3, Internal timer interrupt ✕ 4, Serial I/O interrupt ✕ 1,
CRT interrupt ✕ 1, Multi-master I f(XIN)/4096 interrupt ✕ 1, VSYNC interrupt ✕ 1, BRK interrupt ✕ 1
2 built-in circuits (externally connected a ceramic resonator or a quartz­crystal oscillator)
5 V ± 10 % 165 mW typ. (at oscillation frequency fCPU = 8 MHz, fCRT = 8 MHz) 110 mW typ. (at oscillation frequency fCPU = 8 MHz)
1.65 mW (maximum) –10 °C to 70 °C CMOS silicon gate process 42-pin shrink plastic molded DIP 24 characters ✕ 2 lines (maximum 16 lines by software) 12 ✕ 16 dots 256 kinds 3 kinds Maximum 7 kinds (R, G, B); can be specified by the character 64 levels (horizontal) ✕ 128 levels (vertical)
2
C-BUS interface)
2
C-BUS interface interrupt ✕ 1,
3
MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

PIN DESCRIPTION

Pin Name Functions
V
CC,
VSS.
CNVSS
RESET
XIN XOUT
P00/PWM0– P05/PWM5, P06/INT2/ A-D4, P07/INT1
P10/OUT2, P11/SCL1, P12/SCL2, P13/SDA1, P14/SDA2, P15/A-D1/ INT3, P16/A-D2, P17/A-D3
P20/SCLK, P21/SOUT, P22/SIN, P23/TIM3, P24/TIM2, P25–P27
P30/A-D5, P31/A-D6, P32
P33/OSC1, P34/OSC2
Power source
SS
CNV Reset input
Clock input Clock output
I/O port P0
PWM output
External interrupt input
Analog input I/O port P1
CRT output Multi-master
2
C-BUS interface
I Analog input External interrupt
input I/O port P2
External clock input Serial I/O synchro-
nizing clock input/ output
Serial I/O data input/output
I/O port P3
Analog input Input port P3 Clock input for
CRT display Clock output for
CRT display
Input/
Output
Input
Input
Output
I/O
Output
Input
Input
I/O
Output
I/O
Input Input
I/O
Input
I/O
I/O
I/O
Input Input Input
Output
Apply voltage of 5 V ± 10 % (typical) to V
This is connected to VSS. To enter the reset state, the reset input pin must be kept at a “L” for 2 µs or more (under
normal VCC conditions). If more time is needed for the quartz-crystal oscillator to stabilize, this “L” condition should be maintained for the required time.
This chip has an internal clock generating circuit. To control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and XOUT. If an external clock is used, the clock source should be connected to the XIN pin and the XOUT pin should be left open.
Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually programmed as input or output. At reset, this port is set to input mode. The output structure is N-channel open-drain output. The note out of this Table gives a full of port P0 function.
Pins P0
0–P05 are also used as PWM output pins PWM0–PWM5 respectively. The output
structure is N-channel open-drain output. Pins P06 , P07 are also used as external interrupt input pins INT2, INT1 respectively.
P06 pin is also used as analog input pin A-D4. Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output. Pins P10 is also used as CRT output pin OUT2. The output structure is CMOS output. Pins P11–P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master
I2C-BUS interface is used. The output structure is N-channel open-drain output. Pins P15–P17 are also used as analog input pins A-D1 to A-D3 respectively. P15 pin is also used as external interrupt input pin INT3.
Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output.
Pins P23, P24 are also used as external clock input pins TIM3, TIM2 respectively. P20 pin is also used as serial I/O synchronizing clock input/output pin SCLK.
Pins P21, P22 are also used as serial I/O data input/output pins SOUT, SIN respectively. The output structure is N-channel open-drain output.
Ports P30–P32 are a 3-bit I/O port and has basically the same functions as port P0. Either CMOS output or N-channel open-drain output structure can be selected as the port P30 and P31. The output structure of port P32 is N-channel open-drain output.
Pins P30, P31 are also used as analog input pins A-D5, A-D6 respectively. Ports P33, P34 are a 2-bit input port. P33 pin is also used as CRT display clock input pin OSC1.
4 pin is also used as CRT display clock output pin OSC2. The output structure is CMOS
P3 output.
with ON-SCREEN DISPLAY CONTROLLER
CC, and 0 V to VSS.
4
MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER

PIN DESCRIPTION (continued)

P52/R, P53/G, P54/B, P55/OUT1
HSYNC VSYNC
D-A
Note : As shown in the memory map (Figure 3), port P0 is accessed as a memory at address 00C016 of zero page. Port P0 has the port P0
Output port P5 CRT output
HSYNC input VSYNC input DA output
direction register (address 00C116 of zero page) which can be used to program each bit as an input (“0”) or an output (“1”). The pins programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the output “L” voltage has risen, for example, because a light emitting diode was directly driven. The input pins are in the floating state, so the values of the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state.
Output Output
Input Input
Output
Ports P5
2–P55 are a 4-bit output port. The output structure is CMOS output.
Pins P52–P55 are also used as CRT output pins R, G, B, OUT1 respectively. The output structure is CMOS output.
This is a horizontal synchronizing signal input for CRT. This is a vertical synchronizing signal input for CRT. This is a 14-bit PWM output pin.
5
MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
FUNCTIONAL DESCRIPTION Central Processing Unit (CPU)
The M37221M6-XXXSP uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine in­structions or the SERIES 740 <Software> User’s Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST, SLW instruction cannot be used. The MUL, DIV, WIT and STP instruction can be used.
70 11111 00
with ON-SCREEN DISPLAY CONTROLLER
CPU Mode Register
The CPU mode register contains the stack page selection bit. The CPU mode register is allocated at address 00FB
CPU mode register (CPUM : address 00FB16)
Fix these bits to “0.”
16.
Fig. 1. Structure of CPU mode register
Stack page selection bit (Note)
0 : Zero page 1 : 1 page
Fix these bits to “1.”
Note :
Please beware of this bit when programming because it is set to “1” after the reset release.
6
MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
MEMORY Special Function Register (SFR) Area
The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts.
ROM
ROM is used for storing user programs as well as the interrupt vector area.
RAM for Display
RAM for display is used for specifying the character codes and col­ors to display.
ROM for Display
ROM for display is used for storing character data.
with ON-SCREEN DISPLAY CONTROLLER
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.
Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the spe­cial page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.
RAM
(384 bytes)
RAM
for display (Note)
(96 bytes)
ROM
(24 K bytes)
000016
00C016 00FF16
01BF16
060016
06B716
A00016
SFR area
Not used
Not used
Zero page
ROM
for display
(8 K bytes)
1000016
11FFF16
Not used
Fig. 2. Memory map
FF0016 FFDE16
FFFF
Interrupt vector area
16
Special page
1FFFF16
Note: Refer to Table 11. Contents of CRT display RAM.
7
MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
00C0 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16
16
Port P0 Port P0 direction register Port P1 Port P1 direction register Port P2 Port P2 direction register Port P3 Port P3 direction register
Port P5 Port P5 direction register
Port P3 output mode control register
DA-H register DA-L register PWM0 register PWM1 register PWM2 register PWM3 register PWM4 register PWM output control register 1 PWM output control register 2
2
C data shift register
I
2
I C address register
2
I
C status register
2
C control register
I
2
C clock control register
I Serial I/O mode register Serial I/O register
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
00E0 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA16 00FB16 00FC16 00FD16 00FE16 00FF16
Horizontal position register
16
Vertical position register 1 Vertical position register 2
Character size register
Border selection register Color register 0 Color register 1 Color register 2 Color register 3 CRT control register
CRT port control register CRT clock selection register A-D control register 1 A-D control register 2 ^C} 1
Timer 1 Timer 2
^C} 2 ^C} 3
Timer 3 Timer 4
^C} 4 Timer 12 mode register Timer 34 mode register PWM5 register
PWM5
Interrupt input polarity register
CPU mode register
Interrupt request register 1
Interrupt request register 2
Interrupt control register 1
Interrupt control register 2
Fig. 3. Memory map of special function register (SFR)
8
MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

INTERRUPTS

Interrupts can be caused by 14 different sources consisting of 4 ex­ternal, 8 internal, 1 software, and reset. Interrupts are vectored inter­rupts with priorities shown in Table 1. Reset is also included in the table because its operation is similar to an interrupt. When an interrupt is accepted, (1) The contents of the program counter and processor status
register are automatically stored into the stack.
(2) The interrupt disable flag I is set to “1” and the corresponding
interrupt request bit is set to “0.”
(3) The jump destination address stored in the vector address enters
the program counter. Other interrupts are disabled when the interrupt disable flag is set to “1.” All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit. The interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are in interrupt control registers 1 and 2. Figure 4 shows the structure of the interrupt-related registers. Interrupts other than the BRK instruction interrupt and reset are ac­cepted when the interrupt enable bit is “1,” interrupt request bit is “1,” and the interrupt disable flag is “0.” The interrupt request bit can be set to “0” by a program, but not set to “1.” The interrupt enable bit can be set to “0” and “1” by a program. Reset is treated as a non-maskable interrupt with the highest priority. Figure 5 shows interrupt control.
with ON-SCREEN DISPLAY CONTROLLER
Interrupt Causes
(1) VSYNC and CRT interrupts
The V
SYNC interrupt is an interrupt request synchronized with
the vertical sync signal. The CRT interrupt occurs after character block display to the CRT is completed.
(2) INT1, INT2, INT3 interrupts
With an external interrupt input, the system detects that the level of a pin changes from “L” to “H” or from “H” to “L,” and generates an interrupt request. The input active edge can be selected by bits 3, 4 and 5 of the interrupt input polarity register (address 00F9
16) : when this bit is “0,” a change from “L” to “H” is de-
tected; when it is “1,” a change from “H” to “L” is detected. Note that all bits are cleared to “0” at reset.
(3) Timer 1, 2, 3 and 4 interrupts
An interrupt is generated by an overflow of timer 1, 2, 3 or 4.
(4) Serial I/O interrupt
This is an interrupt request from the clock synchronous serial I/O function.
(5) f(X
IN)/4096 interrupt
This interrupt occurs regularly with a f(X of the PWM output control register 1 to “0.”
(6) Multi-master I
This is an interrupt request related to the multimaster I interface.
(7) BRK instruction interrupt
This software interrupt has the least significant priority. It does not have a corresponding interrupt enable bit, and it is not af­fected by the interrupt disable flag I (non-maskable).
2
C-BUS interface interrupt
IN)/4096 period. Set bit 0
2
C-BUS
Table 1. Interrupt vector addresses and priority
Interrupt source Reset CRT interrupt INT2 interrupt INT1 interrupt Timer 4 interrupt f(XIN)/4096 interrupt VSYNC interrupt Timer 3 interrupt Timer 2 interrupt Timer 1 interrupt Serial I/O interrupt Multi-master I2C-BUS interface interrupt INT3 interrupt BRK instruction interrupt
Priority
1 2 3 4 5 6 7 8
9 10 11 12 13 14
Vector addresses
FFFF16, FFFE16 FFFD16, FFFC16 FFFB16, FFFA16
FFF916, FFF816 FFF516, FFF416 FFF316, FFF216
FFF116, FFF016 FFEF16, FFEE16 FFED16, FFEC16 FFEB16, FFEA16
FFE916, FFE816
FFE716, FFE616
FFE516, FFE416 FFDF16, FFDE16
Remarks
Non-maskable
Active edge selectable Active edge selectable
Active edge selectable
Active edge selectable Non-maskable (software interrupt)
9
MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
7
7
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
0
Interrupt request register 1 (IREQ1 : address 00FC16)
Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Timer 4 interrupt request bit CRT interrupt request bit VSYNC interrupt request bit Multi-master I C-BUS
interface interrupt request bit INT3 interrupt request bit
0
Interrupt control register 1 (ICON1 : address 00FE
2
7 0
0 : No interrupt request issued 1 : Interrupt request issued
7 0
16)
00 0
with ON-SCREEN DISPLAY CONTROLLER
0
Interrupt request register 2 (IREQ2 : address 00FD
INT1 interrupt request bit INT2 interrupt request bit Serial I/O interrupt request bit f(XIN)/4096 interrupt request bit Fix this bit to “0.”
0
Interrupt control register 2 (ICON2 : address 00FF
16)
16)
Timer 1 interrupt enable bit Timer 2 interrupt enable bit
Timer 3 interrupt enable bit Timer 4 interrupt enable bit
CRT interrupt enable bit VSYNC interrupt enable bit Multi-master I2C-BUS
interface interrupt enable bit
INT3 interrupt enable bit
7 0 00
Interrupt input polarity register
0
(RE : address 00F9
Fix these bits to “0.”
INT1 polarity switch bit
INT2 polarity switch bit
INT3 polarity switch bit
Fix this bit to “0.”
INT1 interrupt enable bit INT2 interrupt enable bit
Serial I/O interrupt enable bit Fix this bit to “0.”
f(XIN)/4096 interrupt enable bit
Fix these bits to “0.”
0 : Interrupt disabled 1 : Interrupt enabled
16)
0 : Positive polarity 1 : Negative polarity
0 : Positive polarity 1 : Negative polarity
0 : Positive polarity 1 : Negative polarity
Fig. 4. Structure of interrupt-related registers
10
MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
Interrupt request bit
Interrupt enable bit
Fig. 5. Interrupt control
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
Interrupt disable flag I
BRK instruction
Reset
with ON-SCREEN DISPLAY CONTROLLER
Interrupt request
11
MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

TIMERS

The M37221M6-XXXSP has 4 timers: timer 1, timer 2, timer 3, and timer 4. All timers are 8-bit timers with the 8-bit timer latch. The timer block diagram is shown in Figure 7. All of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. The value is set to a timer at the same time by writing a count value to the corresponding timer latch (addresses 00F0
16 to 00F316).
The count value is decremented by 1. The timer interrupt request bit is set to “1” by a timer overflow at the next count pulse after the count value reaches “00
16”.
(1) Timer 1
Timer 1 can select one of the following count sources:
f(XIN)/16
•
f(XIN)/4096
•
The count source of timer 1 is selected by setting bit 0 of the timer 12 mode register (address 00F4 Timer 1 interrupt request occurs at timer 1 overflow.
16).
(2) Timer 2
Timer 2 can select one of the following count sources:
f(XIN)/16
•
Timer 1 overflow signal
•
External clock from the P24/TIM2 pin
•
The count source of timer 2 is selected by setting bits 4 and 1 of the timer 12 mode register (address 00F4 signal is a count source for the timer 2, the timer 1 functions as an 8­bit prescaler. Timer 2 interrupt request occurs at timer 2 overflow.
16). When timer 1 overflow
with ON-SCREEN DISPLAY CONTROLLER
At reset, timers 3 and 4 are connected by hardware and “FF automatically set in timer 3; “07 lected as the timer 3 count source. The internal reset is released by timer 4 overflow at these state, the internal clock is connected. At execution of the STP instruction, timers 3 and 4 are connected by hardware and “FF However, the f(X So set bit 0 of the timer 34 mode register (address 00F5 before the execution of the STP instruction (f(X the timer 3 count source). The internal STP state is released by timer 4 overflow at these state, the internal clock is connected. Because of this, the program starts with the stable clock. The structure of timer-related registers is shown in Figure 6.
16” is automatically set in timer 3; “0716” in timer 4.
IN)/16 is not selected as the timer 3 count source.
16” in timer 4. The f(XIN)/16 is se-
IN)/16 is selected as
16” is
16) to “0”
(3) Timer 3
Timer 3 can select one of the following count sources:
f(XIN)/16
•
External clock from the HSYNC pin
•
External clock from the P23/TIM3 pin
•
The count source of timer 3 is selected by setting bits 5 and 0 of the timer 34 mode register (address 00F5 Timer 3 interrupt request occurs at timer 3 overflow.
16)
(4) Timer 4
Timer 4 can select one of the following count sources:
f(XIN)/16
•
f(XIN)/2
•
Timer 3 overflow signal
•
The count source of timer 3 is selected by setting bits 4 and 1 of the timer 34 mode register (address 00F5 signal is a count source for the timer 4, the timer 3 functions as an 8­bit prescaler. Timer 4 interrupt request occurs at timer 4 overflow.
16). When timer 3 overflow
12
MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
70
0
Timer 12 mode register (T12M : address 00F416)
Timer 1 count source selection bit 0 : f(XIN)/16 1 : f(XIN)/4096
Timer 2 count source selection bit 0 : Internal clock 1 : External clock from P2
Timer 1 count stop bit 0 : Count start 1 : Count stop
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
70
Timer 34 mode register (T34M : address 00F516)
Timer 3 count source selection bit 0 : f(X 1 : External clock
4/TIM2 pin
Timer 3 count stop bit 0 : Count start 1 : Count stop
IN)/16
Timer 4 internal count source selection bit 0 : Timer 3 overflow 1 : f(X
IN)/16
Timer 2 count stop bit 0 : Count start 1 : Count stop
Timer 2 internal count source selection bit 0 : f(XIN)/16 1 : Timer 1 overflow
Fix this bit to “0.”
Fig. 6. Structure of timer-related registers
Timer 4 count stop bit 0 : Count start 1 : Count stop
Timer 4 count source selection bit 0 : Internal clock 1 : f(X
Timer 3 external count source selection bit 0 : External clock from P2 1 : External clock from HSYNC pin
IN)/2
3/TIM3 pin
13
MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
XIN
1/4096
1/2
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
Data bus
8
Timer 1 latch (8)
8
1/8
T12M0
T12M4
T12M2
Timer 1 (8)
8
8
Timer 2 latch (8)
8
Timer 1 interrupt request
P24/TIM2
HSYNC
P2
3/TIM3
Selection gate :
Connected to black colored side at reset
T12M : Timer 12 mode register T34M : Timer 34 mode register
T12M1
T34M0
T34M4
T12M3
T34M5
T34M2
T34M1
T34M3
Timer 2 (8)
Timer 3 latch (8)
8
Timer 3 (8)
Timer 4 latch (8)
8
Timer 4 (8)
8
8
8
8
8
FF16
0716
Timer 2 interrupt request
Reset STP instruction
Timer 3 interrupt request
Timer 4 interrupt request
Notes 1: “H” pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more.
2: When the external clock source is selected, timers 2 and 3 are counted at a rising edge of input signal.
3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.
Fig. 7. Timer block diagram
14
MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

SERIAL I/O

The M37221M6-XXXSP has a built-in serial I/O which can either trans­mit or receive 8-bit data in serial in the clock synchronous mode. The serial I/O block diagram is shown in Figure 8. The synchronizing clock I/O pin (S port P2. Bit 2 of the serial I/O mode register (address 00DC the synchronizing clock is supplied internally or externally (from the P2
0/SCLK pin). When an internal clock is selected, bits 1 and 0 select
whether f(X port P2 is used for serial I/O or not. To use the P2 pin, set the bit 2 of the port P2 direction register (address 00C516) to “0.” The operation of the serial I/O function is described below. The func­tion of the serial I/O differs depending on the clock source; external clock or internal clock.
CLK), and data I/O pins (SOUT, SIN) also function as
16) selects whether
IN) is divided by 4, 16, 32, or 64. Bit 3 selects whether
2/SIN pin as the SIN
XIN
P2
1/2
0 latch
1/2
Synchronization circuit
P20/SCLK
SM
3
P21 latch
5 : LSB
P21/SOUT
SM3
SM
P22/SIN
SM6
SM2
S
Serial I/O counter (8)
MSB
Serial I/O shift register (8)
Frequency divider
1/81/4 1/16
(Note)
(Address 00DD16)
8
with ON-SCREEN DISPLAY CONTROLLER
Data bus
SM1 SM0
Selection gate :
Connected to black colored side at reset.
SM : Serial I/O mode register
Serial I/O interrupt request
Note : When the data is set in the serial I/O register (address 00DD
Fig. 8. Serial I/O block diagram
16), the register functions as the serial I/O shift register.
15
MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
Internal clock—the serial I/O counter is set to “7” during write cycle into the serial I/O register (address 00DD “H” forcibly. At each falling edge of the transfer clock after the write cycle, serial data is output from the S be selected by bit 5 of the serial I/O mode register. At each rising edge of the transfer clock, data is input from the S the serial I/O register is shifted 1 bit. After the transfer clock has counted 8 times, the serial I/O counter becomes “0” and the transfer clock stops at “H.” At this time the inter­rupt request bit is set to “1.” External clock—when an external clock is selected as the clock source, the interrupt request is set to “1” after the transfer clock has counted 8 times. However, transfer operation does not stop, so con­trol the clock externally. Use the external clock of 1MHz or less with a duty cycle of 50%. The serial I/O timing is shown in Figure 10. When using an external clock for transfer, the external clock must be held at “H” for initializing the serial I/O counter. When switching between an internal clock and an external clock, do not switch during transfer. Also, be sure to ini­tialize the serial I/O counter after switching.
Notes 1: On programming, note that the serial I/O counter is set by
writing to the serial I/O register with the bit managing in­structions as SEB and CLB instructions.
2: When an external clock is used as the synchronizing clock,
write transmit data to the serial I/O register at “H” of the transfer clock input level.
16), and transfer clock goes
OUT pin. Transfer direction can
IN pin and data in
with ON-SCREEN DISPLAY CONTROLLER
7
0
0
Serial I/O mode register (SM : address 00DC
Internal synchronizing clock selection bits b1 b0
0 0 : f(XIN)/4 0 1 : f(XIN)/16 1 0 : f(XIN)/32 1 1 : f(XIN)/64
Synchronizing clock selection bit
0 : External clock 1 : Internal clock
Serial I/O port selection bit
0 : P20, P21 functions as port 1 : SCLK, SOUT
Fix this bit to “0.” Transfer direction selection bit
0 : LSB first 1 : MSB first
Serial input pin selection bit
0 : Input signal from SIN pin 1 : Input signal from SOUT pin
16)
Synchroninzing clock
Transfer clock
Serial I/O register write signal
Serial I/O output
Serial I/O input S
Fig. 10. Serial I/O timing (for LSB first)
SOUT
IN
Note : When an internal clock is selected, the S
Fig. 9. Structure of serial I/O mode register
(Note)
D0 D1 D2 D3 D4 D5 D6 D7
Interrupt request bit is set to “1”
OUT pin is at high-impedance after transfer is completed.
16
MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
(1) Serial I/O Common Transmission/Reception Mode
By writing “1” to bit 6 of the serial I/O mode register, signals SIN and S
OUT are switched internally to be able to transmit or receive the
serial data. Figure 11 shows signals on serial I/O common transmission/recep­tion mode.
Note: When receiving the serial data after writing “FF
I/O register.
P20/SCLK
P21/SOUT
P22/SIN
SM : Serial I/O mode register
16” to the serial
“1”
“0” SM6
with ON-SCREEN DISPLAY CONTROLLER
Clock
Serial I/O shift register (8)
Fig. 11. Signals on serial I/O common transmission/reception mode
17
MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER

MULTI-MASTER I2C-BUS INTERFACE

The multi-master I2C-BUS interface is a circuit for serial communica­tions conformed with the Philips I interface, having an arbitration lost detection function and a synchro­nous function, is useful for serial communications of the multi-mas­ter. Figure 12 shows a block diagram of the multi-master I face and Table 2 shows multi-master I This multi-master I ister, the I
2
control register, the I
2
C-BUS interface consists of the I2C address reg-
C data shift register, the I2C clock control register, the I2C
2
C status register and other control circuits.
2
C-BUS data transfer format. This
2
2
C-BUS interface functions.
C-BUS inter-
with ON-SCREEN DISPLAY CONTROLLER
Table 2. Multi-master I2C-BUS interface functions
Item
In conformity with Philips I standard:
Format
10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode
In conformity with Philips I2C-BUS standard:
Communication mode
Master transmission Master reception Slave transmission Slave reception
SCL clock frequency
16.1 kHz to 400 kHz (at φ = 4 MHz)
φ : System clock = f(XIN)/2
Note: We are not responsible for any third party’s infringement of
patent rights or other rights attributable to the use of the con­trol function (bits 6 and 7 of the I 00DA
16) for connections between the I
ports (SCL1, SCL2, SDA1, SDA2).
Function
2
C-BUS
2
C control register at address
2
C-BUS interface and
Serial data (SDA)
Serial clock (SCL)
Noise elimination circuit
Noise elimination circuit
Data control circuit
AL circuit
BB circuit
Clock control circuit
I2C address register
b7 b0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
S0D
Address comparator
b7 b0
I2C data shift register
S0
Internal data bus
b7 b0
ACK
BIT
S2
2
C clock control register
I
CCR4 CCR3 CCR2 CCR1CCR0
MODE
FAST
ACK
Clock division
b7
MST TRX BB PIN
S1
b7 b0
BSEL1 BSEL0
S1D
System clock (φ)
Interrupt generating circuit
10BIT
ALS ESO BC2 BC1 BC0
SAD
2
I
C control register
Interrupt request signal (IICIRQ)
b0
AL AAS AD0 LRB
I2C status register
Bit counter
Fig. 12. Block diagram of multimaster I
18
2
C-BUS interface
MITSUBISHI MICROCOMPUTERS
M37221M6-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
(1) I2C Data Shift Register
The I2C data shift register (S0 : address 00D716) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left.
2
The I
C data shift register is in a write enable status only when the ES0 bit of the I counter is reset by a write instruction to the I When both the ES0 bit and the MST bit of the I (address 00D9
2
the I
C data shift register. Reading data from the I2C data shift regis-
2
C control register (address 00DA16) is “1.” The bit
16) are “1,” the SCL is output by a write instruction to
2
C data shift register.
2
C status register
ter is always enabled regardless of the ES0 bit value.
Note: To write data into the I
2
C data shift register after setting the MST bit to “0” (slave mode), keep an interval of 8 machine cycles or more.
(2) I2C Address Register
The I2C address register (address 00D816) consists of a 7-bit slave address and a read/write bit. In the addressing mode, the slave ad­dress written in this register is compared with the address data to be received immediately after the START condition are detected.
■ Bit 0: Read/write bit (RBW) Not used in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I The RBW bit is cleared to “0” automatically when the stop condition is detected.
■ Bits 1 to 7: Slave address (SAD0–SAD6) These bits store slave addresses. Regardless of the 7-bit address­ing mode and the 10-bit addressing mode, the address data trans­mitted from the master is compared with the contents of these bits.
2
C address register.
with ON-SCREEN DISPLAY CONTROLLER
70
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
Fig. 13. Structure of I
2
C address register
2
C address register
I (S0D: address 00D816)
Read/write bit
Slave address
(3) I2C Clock Control Register
The I2C clock control register (address 00DB16) is used to set ACK control, SCL mode and SCL frequency.
■ Bits 0 to 4: SCL frequency control bits (CCR0–CCR4) These bits control the SCL frequency. Refer to Table 3.
■ Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to “0,” the stan­dard clock mode is set. When the bit is set to “1,” the high-speed clock mode is set.
■ Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clock this bit is set to “0,” the ACK return mode is set and make SDA “L” at the occurrence of an ACK clock. When the bit is set to “1,” the ACK non-return mode is set. The SDA is held in the “H” status at the oc­currence of an ACK clock. However, when the slave address matches the address data in the reception of address data at ACK BIT = “0,” the SDA is automatically made “L” (ACK is returned). If there is a mismatch between the slave address and the address data, the SDA is automatically made “H”(ACK is not returned).
✽ACK clock: Clock for acknowledgement
■ Bit 7: ACK clock bit (ACK)
This bit specifies a mode of acknowledgment which is an acknowl­edgment response of data transmission. When this bit is set to “0,” the no ACK clock mode is set. In this case, no ACK clock occurs after data transmission. When the bit is set to “1,” the ACK clock mode is set and the master generates an ACK clock upon comple­tion of each 1-byte data transmission.The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (make SDA “H”) and receives the ACK bit generated by the data receiving device.
✽
is generated. When
Note: Do not write data into the I
2
C clock control register during transmitting. If data is written during transmitting, the I generator is reset, so that data cannot be transmitted nor­mally.
2
C clock
19
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