Mitsubishi M37220M3-XXXSP Datasheet
MITSUBISHI MICROCOMPUTERS
M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
DESCRIPTION
The M37220M3-XXXSP is a single-chip microcomputer designed with
CMOS silicon gate technology. It is housed in a 42-pin shrink plastic
molded DIP.
In addition to their simple instruction sets, the ROM, RAM and I/O
addresses are placed on the same memory map to enable easy programming.
The M37220M3-XXXSP has a PWM output function and a OSD display function, so it is useful for a channel selection system for TV.
FEATURES
Number of basic instructions .....................................................71
•
Memory size
•
The minimum instruction execution time
•
..........................................0.5µs (at 8 MHz oscillation frequency)
Power source voltage .................................................. 5 V ± 10 %
•
Power dissipation............................................................. 165 mW
•
(at 8 MHz oscillation frequency, V
Subroutine nesting ....................................... 96 levels (maximum)
•
Interrupts....................................................... 13 types, 13 vectors
•
8-bit timers .................................................................................. 4
•
Programmable I/O ports (Ports P0, P1, P2, P30–P32) ..............27
•
Input ports (Ports P33, P34)......................................................... 2
•
Output ports (Ports P52–P55) ......................................................4
•
12 V withstand ports ....................................................................6
•
LED drive ports ........................................................................... 4
•
Serial I/O ............................................................ 8-bit ✕ 1 channel
•
A-D comparator (6-bit resolution) ................................ 6 channels
•
D-A converter (6-bit resolution) ...................................................2
•
PWM output circuit......................................... 14-bit ✕ 1, 8-bit ✕ 6
•
ROM ........................................................12 K bytes
RAM ......................................................... 256 bytes
ROM for display......................................... 4 K bytes
RAM for display.......................................... 80 bytes
CC=5.5V, at CRT display)
PIN CONFIGURATION (TOP VIEW)
HSYNC
VSYNC
P00/PWM0
P0
1/PWM1
P0
2/PWM2
P0
3/PWM3
P0
4/PWM4
P0
5/PWM5
P06/INT2/A-D4
P0
7/INT1
P2
3/TIM3
P2
4/TIM2
P2
P26
P27
D-A
P3
CNVSS
XIN
X
OUT
VSS
1
2
3
4
5
6
7
8
9
10
11
12
5
13
14
15
16
17
2
18
19
20
21
M37220M3-XXXSP
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
Outline 42P4B
P52/R
P5
3/G
P5
4/B
P5
5/OUT
P2
0/SCLK
P21/SOUT
P22/SIN
P10
P11
P12
P13
P14
P15/A-D1/INT3
P1
6/A-D2
P17/A-D3
0/A-D5/DA1
P3
P3
1/A-D6/DA2
RESET
OSC1/P3
3
OSC2/P34
VCC
CRT display function
•
Number of display characters ................24 characters ✕ 2 lines
(16 lines maximum)
Kinds of characters ..................................................... 128 kinds
Dot structure .......................................................... 12 ✕ 16 dots
Kinds of character sizes.................................................. 3 kinds
Kinds of character colors (It can be specified by the character)
maximum 7 kinds (R, G, B)
Kinds of raster colors (maximum 7 kinds)
Display position
Horizontal.................................................................. 64 levels
Vertical .................................................................... 128 levels
Bordering (horizontal and vertical)
APPLICATION
TV
OUT
Clock input Clock output
X
IN
X
OUT
Reset input
V
CC
V
SS
CNV
SS
Clock output for display
Input ports P3
3,
P3
4
OSC1 OSC2
Clock input for display
INT2
INT1
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
P5 (4)
B
G
R
H
SYNC
V
SYNC
A-D
comparator
14-bit
PWM circuit
8-bit PWM circuit
Accumulator
A (8)
Timer 4
T4 (8)
Timer 3
T3 (8)
Timer 2
T2 (8)
Timer 1
T1 (8)
Timer count source
selection circuit
TIM2
TIM3
Instruction
register (8)
Instruction
decoder
Control signal
CRT circuit
Stack
pointer
S (8)
Index
register
Y (8)
Index
register
X (8)
Processor
status
register
PS (8)
8-bit
arithmetic
and
logical unit
ROM
12 K bytes
Program
counter
PC
L
(8)
Program
counter
PC
H
(8)
RAM
256 bytes
Data bus
Clock
generating
circuit
RESET
Output ports P5
2
–P5
5
Address bus
SI/O(8)
S
IN
S
CLK
S
OUT
INT3
10 9 8 7 6 5 4 3
I/O port P0
28 29 30 31 32 3334 35
P1 (8)
I/O port P1
15 14 13 12 11 3637 38
P2 (8)
I/O port P2
I/O ports P3
0
–P3
2
17 2627
16
P3 (3)
P0 (8)
39 40
41 42
2 1
2019
25
22
21 18
24 23
( φ ) Timing output
D-A
D-A
converter
MITSUBISHI MICROCOMPUTERS
M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
2
FUNCTIONAL BLOCK DIAGRAM of M37220M3-XXXSP
FUNCTIONS
Number of basic instructions
Instruction execution time
Clock frequency
Memory size
Input/Output ports
Serial I/O
A-D comparatpr
D-A converter
PWM output circuit
Timers
Subroutine nesting
Interrupt
Clock generating circuit
Power source voltage
Power dissipation
Operating temperature range
Device structure
Package
CRT display function
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
Parameter
ROM
RAM
CRT ROM
CRT RAM
P0
P10–P17
P20, P21
P22–P27
P30, P31
P32
P33, P34
P52–P55
CRT ON
CRT OFF
In stop mode
Number of display characters
Dot structure
Kinds of characters
Kinds of character sizes
Kinds of character colors
Display position (horizontal, vertical)
Input
Output
I/O
I/O
I/O
I/O
I/O
I/O
MITSUBISHI MICROCOMPUTERS
M37220M3-XXXSP
with ON-SCREEN DISPLAY CONTROLLER
Functions
71
0.5 µs (the minimum instruction execution time, at 8 MHz oscillation frequency)
8 MHz (maximum)
12K bytes
256 bytes
4K bytes
80 bytes
8-bit ✕ 1 (N-channel open-drain output structure, can be used as PWM
output pins, INT input pins, A-D input pin)
8-bit ✕ 1 (CMOS input/output structure, can be used as A-D input pins, INT
input pin)
2-bit ✕ 1 (CMOS input/output or N-channel open-drain output structure,
can be used as serial output pins)
6-bit ✕ 1 (CMOS input/output structure, can be used as serial input pin,
external clock input pins)
2-bit ✕ 1 (CMOS input/output or N-channel open-drain output structure,
can be used as A-D input pins, D-A conversion output pins)
1-bit ✕ 1 (N-channel open-drain output structure)
2-bit ✕ 1 (can be used as CRT display clock I/O pins)
4-bit ✕ 1 (CMOS output structure, can be used as CRT output pins)
8-bit ✕ 1
6 channels (6-bit resolution)
2 (6-bit resolution)
14-bit ✕ 1, 8-bit ✕ 6
8-bit timer ✕ 4
96 levels (maximum)
External interrupt ✕ 3, Internal timer interrupt ✕ 4, Serial I/O interrupt ✕ 1,
CRT interrupt ✕ 1, XIN/4096 interrupt ✕ 1, VSYNC interrupt ✕ 1,
BRK interrupt ✕ 1
2 built-in circuits (externally connected a ceramic resonator or a quartzcrystal oscillator)
5 V ± 10 %
165 mW typ. (at oscillation frequency fCPU = 8 MHz, fCRT = 8 MHz)
110 mW typ. (at oscillation frequency fCPU = 8 MHz)
1.65 mW (maximum)
–10 °C to 70 °C
CMOS silicon gate process
42-pin shrink plastic molded DIP
20 characters ✕ 2 lines (maximum 16 lines by software)
12 ✕ 16 dots
128 kinds
3 kinds
Maximum 7 kinds (R, G, B); can be specified by the character
64 levels (horizontal) ✕ 128 levels (vertical)
3
PIN DESCRIPTION
Pin
VCC, VSS
Name
Power source
Input/
Output
MITSUBISHI MICROCOMPUTERS
M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
Functions
Apply voltage of 5 V ± 10 % (typical) to VCC, and 0 V to VSS.
CNVSS
RESET
XIN
XOUT
P00/PWM0–
P05/PWM5,
P06/INT2/
A-D4,
P07/INT1
P10–P14,
P15/A-D1
INT3,
P16/A-D2,
P17/A-D3
P20/SCLK,
P2
1/SOUT,
P22/SIN,
P23/TIM3,
P24/TIM2,
P25–P27
P30/A-D5/
DA1,
P31/A-D6/
DA2,
P32
P33/OSC1,
P34/OSC2
SS
CNV
Reset input
Clock input
Clock output
I/O port P0
PWM output
External interrupt
input
Analog input
I/O port P1
Analog input
External interrupt
input
I/O port P2
External clock
input
Serial I/O data
input/output
Serial I/O synchronizing clock input/
output
I/O port P3
Analog input
D-A conversion
output
Input port P3
Clock input for
CRT display
Clock output for
CRT display
Input
Input
Output
I/O
Output
Input
Input
I/O
Input
Input
I/O
Input
I/O
I/O
I/O
Input
Output
Input
Input
Output
This is connected to VSS.
To enter the reset state, the reset input pin must be kept at a “L” for 2 µs or more (under
normal VCC conditions).
If more time is needed for the quartz-crystal oscillator to stabilize, this “L” condition should
be maintained for the required time.
This chip has an internal clock generating circuit. To control generating frequency, an
external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and
XOUT. If an external clock is used, the clock source should be connected to the XIN pin and
the XOUT pin should be left open.
Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually
programmed as input or output. At reset, this port is set to input mode. The output structure
is N-channel open-drain output. The note out of this Table gives a full of port P0 function.
Pins P00–P05 are also used as PWM output pins PWM0–PWM5 respectively.The output
structure is N-channel open-drain output.
Pins P06, P07 are also used as external interrupt input pins INT2, INT1 respectively.
Pins P06 is also used as an analog interrupt input pin A-D4.
Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output.
Pins P15–P17 are also used as an analog input pins A-D1 to A-D3.
Pin P15 is also used as an external interrupt input pins INT3.
Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output
structure is CMOS output.
3, P24 is also used an external clock input pins TIM3, TIM2 respectively.
Pins P2
Pins P21, P22 are also used serial I/O data input/output pins SOUT, SIN respectively. The
output structure is N-channel open-drain output.
Pin P20 is also used serial I/O syncronizing clock input/output pin SCLK. The output structure is N-channel open-drain output.
Ports P30–P32 are a 3-bit I/O port and have basically the same functions as port P0. Either
CMOS output or N-channel open-drain output structure can be selected as the ports P30
and P31. The output structure of port P32 is N-channel open-drain output.
Pins P30, P31 are also used as analog input pins A-D5, A-D6 respectively.
Pins P30, P31 are also used as D-A conversion output pins DA1, DA2 respectively.
Ports P33, P34 are a 2-bit input port.
Pin P33 is also used as CRT display clock input pin OSC1.
4 is also used as CRT display clock output pin OSC2.The output structure is CMOS
Pin P3
output.
4
PIN DESCRIPTION (continued)
MITSUBISHI MICROCOMPUTERS
M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
P52/R,
P53/G,
P54/B,
P55/OUT
HSYNC
VSYNC
D-A
Note : As shown in the memory map (Figure 3), port P0 is accessed as a memory at address 00C016 of zero page. Port P0 has the port P0
direction register (address 00C1
programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are
programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the
output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the
output “L” voltage has risen, for example, because a light emitting diode was directly driven. The input pins are in the floating state, so the
values of the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the
floating state.
Output port
P5
CRT output
SYNC input
H
VSYNC input
DA output
Output
Output
Output
Ports P52–P55 are a 4-bit output port. The output structure is CMOS output.
Pins P52–P55 are also used as CRT output pins R, G, B, OUT respectively. The output structure is
CMOS output.
This is a horizontal synchronizing signal input for CRT display.
Input
This is a vertical synchronizing signal input for CRT display.
Input
This is an output pin for 14-bit PWM.
16 of zero page) which can be used to program each bit as an input (“0”) or an output (“1”). The pins
5
MITSUBISHI MICROCOMPUTERS
M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The M37220M3-XXXSP uses the standard 740 family instruction set.
Refer to the table of 740 family addressing modes and machine instructions or the SERIES 740 <Software> User’s Manual for details
on the instruction set.
Machine-resident 740 family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instruction can be used.
70
11111 00
CPU Mode Register
The CPU mode register contains the stack page selection bit. The
CPU mode register is allocated at address 00FB
CPU mode register
(CPUM : address 00FB16)
Fix these bits to “0.”
Stack page selection bit (Note)
0 : Zero page
1 : 1 page
16.
Fig. 1. Structure of CPU mode register
Fix these bits to “1.”
Note :
Please beware of this bit when programming because it
is set to “1” after the reset release.
6
MITSUBISHI MICROCOMPUTERS
M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
MEMORY
Special Function Register (SFR) Area
The special function register (SFR) area in the zero page contains
control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
ROM
ROM is used for storing user programs as well as the interrupt vector
area.
RAM for Display
RAM for display is used for specifying the character codes and colors to display.
ROM for Display
ROM for display is used for storing character data.
0000
16
00C0
00FF
16
SFR area
16
RAM
(256 bytes)
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
16
10000
ROM
Zero page
for display
(4 K bytes)
10FFF
16
RAM
for display (Note)
(80 bytes)
ROM
(12 K bytes)
Fig. 2. Memory map
013F
16
Not used
0600
16
06B3
16
Not used
D000
16
FF00
16
FFDE
16
Interrupt vector area
16
FFFF
Note : Refer to Table 8. Contents of CRT display RAM.
Special page
1FFFF
Not used
16
7
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
■SFR area (addresses C016 to DF16)
: Nothing is allocated
: Fix this bit to “0” (do not write “1”)
: “0” immediately after reset
0
1
: “1” immediately after reset
?
: undefined immediately after reset
MITSUBISHI MICROCOMPUTERS
M37220M3-XXXSP
with ON-SCREEN DISPLAY CONTROLLER
Address
Port P0 (P0)
C0
16
Port P0 direction register (D0)
C1
16
Port P1 (P1)
C2
16
Port P1 direction register (D1)
C3
16
Port P2 (P2)
C4
16
Port P2 direction register (D2)
C5
16
Port P3 (P3)
C6
16
Port P3 direction register (D3)
C7
16
C8
16
C9
16
Port P5 (P5)
CA
16
Port P5 direction register (D5)
CB
16
CC
16
Port P3 output mode control register (P3S)
CD
16
DA-H register (DA-H)
CE
16
DA-L register (DA-L)
CF
16
PWM0 register (PWM0)
D0
16
PWM1 register (PWM1)
D1
16
PWM2 register (PWM2)
D2
16
PWM3 register (PWM3)
D3
16
PWM4 register (PWM4)
D4
16
PWM output control register 1 (PW)
D5
16
PWM output control register 2 (PN)
D6
16
D7
16
D8
16
D9
16
DA
16
DB
16
Serial I/O mode register (SM)
DC
16
Serial I/O regsiter (SIO)
DD
16
DA1 conversion register (DA1)
DE
16
DA2 conversion register (DA2)
DF
16
Register
b7
Bit allocation
DA1SDA2S
PN2PN3PN4
State immediately after reset
b0
b7
00
00
00
000
00000000
00
00000000
P30SP31S
00000000
00
PW0PW1PW2PW3PW4PW5PW6PW7
00
00000000
SM0SM1SM2SM3SM5SM6
DA10DA11DA12DA13DA14DA15
DA20DA21DA22DA23DA24DA25
00000000
?00 ?????
?00 ?????
?
16
?
16
?
16
?????
?
?
?
?
????
?
?
??????
?
?
?
?
?
16
?
?
?
?
?
?
b0
Fig. 3. Memory map of SFR (special function register) (1)
8
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
A
A
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
AA
AA
AAAAAAAAAAAA
AA
AA
AA
AA
AA
■SFR area (addresses E016 to FF16)
: Nothing is allocated
: Fix this bit to “0” (do not write “1”)
: Fix this bit to “1” (do not write “0”)
: “0” immediately after reset
0
1
: “1” immediately after reset
?
: undefined immediately after reset
MITSUBISHI MICROCOMPUTERS
M37220M3-XXXSP
with ON-SCREEN DISPLAY CONTROLLER
Address
Horizontal position register (HR)
E016
Vertical register 1 (CV1)
E116
Vertical register 2 (CV2)
E216
Register
E316
Character size register (CS)
E416
Border selection register (MD)
E516
Color register 0 (CO0)
E616
Color register 1 (CO1)
E716
Color register 2 (CO2)
E816
Color register 3 (CO3)
E916
CRT control register (CC)
EA16
EB16
CRT port control register (CRTP)
EC16
CRT clock selection register (CK)
ED16
A-D control register 1 (AD1)
EE16
A-D control register 2 (AD2)
EF16
Timer 1 (TM1)
F016
Timer 2 (TM2)
F116
Timer 3 (TM3)
F216
Timer 4 (TM4)
F316
Timer 12 mode register (T12M)
F416
Timer 34 mode register (T34M)
F516
PWM5 register (PWM5)
F616
F716
F816
Interrupt input polarity register (RE)
F916
Test register (TEST)
FA16
CPU mode register (CPUM)
FB16
Interrupt request register 1 (IREQ1)
FC16
Interrupt request register 2 (IREQ2)
FD16
Interrupt control register 1 (ICON1)
FE16
Interrupt control register 2 (ICON2)
FF16
b7
Bit allocation
OUTOP5OP6OP7
A
T34M5
A
CK0RE5 RE4 RE3
CK0
MSR
A
A
ADC2ADC4 ADC3ADC5
CM2
S1R
S1EMSE
State immediately after reset
b0
b7
HR0HR1HR2HR3HR4HR5
00000000
CV10CV11CV12CV13CV14CV15CV16
0
CV20CV21CV22CV23CV24CV25CV26
??????
?
?0??????
b0
?
CS10CS11CS20CS21
0000
MD10MD20
00000 0
CO01CO02CO03CO05
CO11CO12CO13CO15
CO21CO22CO23CO25
CO31CO32CO33CO35
00000 00 0
00000 00 0
00000 00 0
00000 00 0
CC0CC1CC2
00000000
????
??
?
VSYCR/G/B
HSYC
CK0CK1
ADM0ADM1ADM2ADM4
ADC0ADC1
000000 0
0
00 00000
000000 00
A
0016
?
FF
A
16
0716
FF16
0716
T12M0
T12M1T12M2T12M3T12M4
T34M0
T34M1T34M2T34M3T34M4
000000 00
000000 00
?
?
?
11
A
A
CK0
00
CK0
16
A
A
1
0
1
0?
00
A
0000
0
1
1
TM1R
TM2RTM3RTM4RCRTRVSCRIT3R
1T1R1T2R
TM1E
TM2ETM3ETM4ECRTEVSCEIT3E
1T1E1T2E
0000 0000
0000 00
00
A
0000 0000
A
0000 0000
A
A
Fig. 4. Memory map of SFR (special function register) (2)
9
MITSUBISHI MICROCOMPUTERS
M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
INTERRUPTS
Interrupts can be caused by 13 different sources consisting of 3 external, 9 internal, and 1 software sources. Interrupts are vectored
interrupts with priorities shown in Table 1. Reset is also included in
the table because its operation is similar to an interrupt.
When an interrupt is accepted,
(1) The contents of the program counter and processor status
register are automatically stored into the stack.
(2) The interrupt disable flag I is set to “1” and the corresponding
interrupt request bit is set to “0.”
(3) The jump destination address stored in the vector address enters
the program counter.
Other interrupts are disabled when the interrupt disable flag is set to
“1.”
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits are
in interrupt request registers 1 and 2 and the interrupt enable bits are
in interrupt control registers 1 and 2. Figure 5 shows the structure of
the interrupt-related registers.
Interrupts other than the BRK instruction interrupt and reset are accepted when the interrupt enable bit is “1,” interrupt request bit is “1,”
and the interrupt disable flag is “0.” The interrupt request bit can be
set to “0” by a program, but not set to “1.” The interrupt enable bit can
be set to “0” and “1” by a program.
Reset is treated as a non-maskable interrupt with the highest priority.
Figure 6 shows interrupt control.
Interrupt Causes
(1) VSYNC and CRT interrupts
The V
SYNC interrupt is an interrupt request synchronized with
the vertical sync signal.
The CRT interrupt occurs after character block display to the CRT
is completed.
(2) INT1, INT2, INT3 interrupts
With an external interrupt input, the system detects that the level
of a pin changes from “L” to “H” or from “H” to “L,” and generates
an interrupt request. The input active edge can be selected by
bits 3, 4 and 5 of the interrupt input polarity register (address
00F9
16) : when this bit is “0,” a change from “L” to “H” is de-
tected; when it is “1,” a change from “H” to “L” is detected. Note
that all bits are cleared to “0” at reset.
(3) Timer 1, 2, 3 and 4 interrupts
An interrupt is generated by an overflow of timer 1, 2, 3 or 4.
(4) Serial I/O interrupt
This is an interrupt request from the clock synchronous serial
I/O function.
(5) X
IN/4096 interrupt
This interrupt occurs regularly with a f(X
of the PWM output control register 1 to “0.”
(6) BRK instruction interrupt
This software interrupt has the least significant priority. It does
not have a corresponding interrupt enable bit, and it is not affected by the interrupt disable flag I (non-maskable).
IN)/4096 period. Set bit 0
Table 1. Interrupt vector addresses and priority
Interrupt source
Reset
CRT interrupt
INT2 interrupt
INT1 interrupt
Timer 4 interrupt
XIN/4096 interrupt
VSYNC interrupt
Timer 3 interrupt
Timer 2 interrupt
Timer 1 interrupt
Serial I/O interrupt
INT3 interrupt
BRK instruction interrupt
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
Vector addresses
FFFF16, FFFE16
FFFD16, FFFC16
FFFB16, FFFA16
FFF916, FFF816
FFF516, FFF416
FFF316, FFF216
FFF116, FFF016
FFEF16, FFEE16
FFED16, FFEC16
FFEB16, FFEA16
FFE916, FFE816
FFE516, FFE416
FFDF16, FFDE16
Remarks
Non-maskable
Active edge selectable
Active edge selectable
Active edge selectable
Non-maskable (software interrupt)
10
MITSUBISHI MICROCOMPUTERS
M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
7
7
0
Interrupt request register 1
(IREQ1 : address 00FC
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Timer 4 interrupt request bit
CRT interrupt request bit
V
SYNC
interrupt request bit
INT3 interrupt request bit
0
Interrupt control register 1
(ICON1 : address 00FE
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
Timer 4 interrupt enable bit
CRT interrupt enable bit
V
SYNC
interrupt enable bit
INT3 interrupt enable bit
7
16
)
0
0 : No interrupt request issued
1 : Interrupt request issued
7
0
16
)
00 0
0
Interrupt request register 2
(IREQ2 : address 00FD
INT1 interrupt request bit
INT2 interrupt request bit
Serial I/O interrupt request bit
XIN/4096 interrupt request bit
Fix this bit to “0.”
0
Interrupt control register 2
(ICON2 : address 00FF
INT1 interrupt enable bit
INT2 interrupt enable bit
Serial I/O interrupt enable bit
Fix this bit to “0.”
XIN/4096 interrupt enable bit
Fix these bits to “0.”
16
)
16
)
7 0
00
Interrupt input polarity register
0
(RE : address 00F9
Fix these bits to “0.”
INT1 polarity switch bit
0 : Positive polarity
1 : Negative polarity
INT2 polarity switch bit
0 : Positive polarity
1 : Negative polarity
INT3 polarity switch bit
0 : Positive polarity
1 : Negative polarity
Fix this bit to “0.”
Fig. 5. Structure of interrupt-related registers
0 : Interrupt disabled
1 : Interrupt enabled
16
)
11
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
MITSUBISHI MICROCOMPUTERS
M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
Fig. 6. Interrupt control
BRK instruction
Reset
Interrupt request
12
MITSUBISHI MICROCOMPUTERS
M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
TIMERS
The M37220M3-XXXSP has 4 timers: timer 1, timer 2, timer 3, and
timer 4. All timers are 8-bit timers with the 8-bit timer latch. The timer
block diagram is shown in Figure 8.
All of the timers count down and their divide ratio is 1/(n+1), where n
is the value of timer latch. The value is set to a timer at the same time
by writing a count value to the corresponding timer latch (addresses
00F0
16 to 00F316).
The count value is decremented by 1. The timer interrupt request bit
is set to “1” by a timer overflow at the next count pulse after the count
value reaches “00
16”.
(1) Timer 1
Timer 1 can select one of the following count sources:
f(XIN)/16
•
f(XIN)/4096
•
The count source of timer 1 is selected by setting bit 0 of the timer 12
mode register (address 00F4
Timer 1 interrupt request occurs at timer 1 overflow.
16).
(2) Timer 2
Timer 2 can select one of the following count sources:
f(XIN)/16
•
Timer 1 overflow signal
•
External clock from the P24/TIM2 pin
•
The count source of timer 2 is selected by setting bits 4 and 1 of the
timer 12 mode register (address 00F4
signal is a count source for the timer 2, the timer 1 functions as an 8bit prescaler.
Timer 2 interrupt request occurs at timer 2 overflow.
16). When timer 1 overflow
At reset, timers 3 and 4 are connected by hardware and “FF
automatically set in timer 3; “07
lected as the timer 3 count source. The internal reset is released by
timer 4 overflow at these state, the internal clock is connected.
At execution of the STP instruction, timers 3 and 4 are connected by
hardware and “FF
However, the f(X
So set bit 0 of the timer 34 mode register (address 00F5
before the execution of the STP instruction (f(X
the timer 3 count source). The internal STP state is released by timer
4 overflow at these state, the internal clock is connected.
Because of this, the program starts with the stable clock.
The structure of timer-related registers is shown in Figure 7.
16” is automatically set in timer 3; “0716” in timer 4.
IN)/16 is not selected as the timer 3 count source.
16” in timer 4. The f(XIN)/16 is se-
IN)/16 is selected as
16” is
16) to “0”
(3) Timer 3
Timer 3 can select one of the following count sources:
f(XIN)/16
•
External clock from the HSYNC pin
•
External clock from the P23/TIM3 pin
•
The count source of timer 3 is selected by setting bits 5 and 0 of the
timer 34 mode register (address 00F5
Timer 3 interrupt request occurs at timer 3 overflow.
16)
(4) Timer 4
Timer 4 can select one of the following count sources:
f(XIN)/16
•
f(XIN)/2
•
Timer 3 overflow signal
•
The count source of timer 3 is selected by setting bits 4 and 1 of the
timer 34 mode register (address 00F5
signal is a count source for the timer 4, the timer 3 functions as an 8bit prescaler.
Timer 4 interrupt request occurs at timer 4 overflow.
16). When timer 3 overflow
13
MITSUBISHI MICROCOMPUTERS
M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
70
0
Timer 12 mode register
(T12M : address 00F416)
Timer 1 count source selection bit
0 : f(XIN)/16
1 : f(XIN)/4096
Timer 2 count source selection bit
0 : Internal clock
1 : External clock from P2
Timer 1 count stop bit
0 : Count start
1 : Count stop
Timer 2 count stop bit
0 : Count start
1 : Count stop
Timer 2 internal count source
selection bit
0 : f(XIN)/16
1 : Timer 1 overflow
4/TIM2 pin
70
Timer 34 mode register
(T34M : address 00F516)
Timer 3 count source selection bit
0 : f(X
1 : External clock
Timer 4 internal count source
selection bit
0 : Timer 3 overflow
1 : f(X
Timer 3 count stop bit
0 : Count start
1 : Count stop
Timer 4 count stop bit
0 : Count start
1 : Count stop
Timer 4 count source selection bit
0 : Internal clock
1 : f(X
IN)/16
IN)/16
IN)/2
Fix this bit to “0.”
Fig. 7. Structure of timer-related registers
Timer 3 external count source
selection bit
0 : External clock from P2
1 : External clock from HSYNC pin
3/TIM3 pin
14
MITSUBISHI MICROCOMPUTERS
M37220M3-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
Data bus
8
X
P24/TIM2
H
SYNC
3
/TIM3
P2
1/4096
IN
1/2
1/8
T12M0
T12M4
T12M1
T34M0
T12M2
T12M3
T34M5
T34M2
Timer 1 latch (8)
8
Timer 1 (8)
Timer 2 latch (8)
8
Timer 2 (8)
Timer 3 latch (8)
8
Timer 3 (8)
Timer 1
interrupt request
8
8
Timer 2
interrupt request
8
8
FF
16
8
Reset
STP
instruction
Timer 3
interrupt request
Selection gate :
Connected to black
colored side at reset
T12M : Timer 12 mode register
T34M : Timer 34 mode register
Notes 1 : “H” pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more.
2 :
When the external clock source is selected, timers 2 and 3 are counted at a rising edge
of input signal.
3 :In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used
T34M1
Timer 4 latch (8)
Timer 4 (8)
T34M4
T34M3
Fig. 8. Timer block diagram
8
07
16
8
Timer 4
interrupt request
8
15
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
SERIAL I/O
The M37220M3-XXXSP has a built-in serial I/O which can either transmit or receive 8-bit data in serial in the clock synchronous mode.
The serial I/O block diagram is shown in Figure 9. The synchronizing
clock I/O pin (S
port P2.
Bit 2 of the serial I/O mode register (address 00DC
the synchronizing clock is supplied internally or externally (from the
P2
0/SCLK pin). When an internal clock is selected, bits 1 and 0 select
whether f(X
port P2 is used for serial I/O or not. To use the P2
pin, set the bit 2 of the port P2 direction register (address 00C516) to
“0.”
The operation of the serial I/O function is described below. The function of the serial I/O differs depending on the clock source; external
clock or internal clock.
CLK), and data I/O pins (SOUT, SIN) also function as
16) selects whether
IN) is divided by 4, 16, 32, or 64. Bit 3 selects whether
2/SIN pin as the SIN
MITSUBISHI MICROCOMPUTERS
M37220M3-XXXSP
with ON-SCREEN DISPLAY CONTROLLER
IN
X
P2
1/2
0 latch
P20/SCLK
SM3
1 latch
P2
P21/SOUT
SM3
P22/SIN
Note: When the data is set in the serial I/O register (address 00DD
Fig. 9. Serial I/O block diagram
1/2
Synchronization circuit
SM5: LSB
SM6
Frequency
divider
SM2
S
Serial I/O counter (8)
MSB
(Note)
Serial I/O shift register (8)
(Address 00DD16)
16), the register functions as the serial I/O shift register.
1/81/4 1/16
SM1
SM0
8
Data bus
Selection gate :
Connected to black
colored side at reset.
SM : Serial I/O mode register
Serial I/O interrupt
request
16
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