Mitsubishi M37211M2-XXXSP, M37210M4-XXXSP, M37210M3-XXXSP, M37210M3-XXXFP, M37210E4SP Datasheet
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M37210M3-XXXSP
M37210M4-XXXSP
M37211M2-XXXSP
MITSUBISHI MICROCOMPUTERS
M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP
M37210E4-XXXSP/FP, M37210E4SP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
DESCRIPTION
The M37210M3-XXXSP/FP is a single-chip microcomputer designed
with CMOS silicon gate technology. It is housed in a 52-pin shrink
plastic molded DIP or a 64-pin plastic molded QFP. This single-chip
microcomputer is useful for the channel selection system for TVs
because it provides PWM function, OSD display function and so on.
In addition to their simple instruction sets, the ROM, RAM, and I/O
addresses are placed on the same memory map to enable easy programming.
The features of the M37210E4-XXXSP/FP and the M37210E4SP/FP
are similar to those of the M37210M4-XXXSP except that these
chips have a built-in PROM which can be written electrically.
The differences between the M37210M3-XXXSP/FP, the M37210
M4-XXXSP, and the M37211M2-XXXSP are the ROM size, the RAM
size, and the PWM outputs as shown below. Accordingly, the following descriptions will be for the M37210M3-XXXSP/FP unless otherwise noted.
Type name
M37210M3-XXXSP/FP
M37210M4-XXXSP
M37211M2-XXXSP
ROM size
12 K bytes
16 K bytes
8 K bytes
RAM size
256 bytes
320 bytes
192 bytes
6-bit PWM outputs
8
8
6
Note : After the reset, set the stack page selection bit which is set “1”
to “0” because the internal RAM of the M37211M2-XXXSP is
in only the zero page.
FEATURES
Number of basic instructions .....................................................69
•
Memory size ROM ................ 12 K bytes (M37210M3-XXXSP/FP)
•
RAM................. 256 bytes (M37210M3-XXXSP/FP)
ROM for display......................................... 3 K bytes
RAM for display.......................................... 72 bytes
The minimum instruction execution time
•
........................................... 0.5µs (at 8MHz oscillation frequency)
Power source voltage..................................................... 5V ± 10%
•
Pow er dissipation .............................................................. 110mW
•
(at 4MHz oscillation frequency, V
Subroutine nesting ............................................... 96 levels (Max.)
•
Interrupts ....................................................... 12 types, 12 vectors
•
8-bit timers .................................................................................. 4
•
Programmable I/O ports
•
(Ports P0, P1, P2, P3, P4) ......................................................... 25
Output ports (ports P5, P6) ..........................................................8
•
Output ports (ports P52, P56).....................................................12
•
12 V withstand ports ....................................................................4
•
Serial I/O ............................................................ 8-bit ✕ 1 channel
•
PWM output circuit ............... (14-bit ✕ 1, 6-bit ✕ 8) ... M37210M3
•
(14-bit ✕ 1, 6-bit ✕ 6).... M37211M2
1
16 K bytes (M37210M4-XXXSP)
8 K bytes (M37211M2-XXXSP)
320 bytes (M37210M4-XXXSP)
192 bytes (M37211M2-XXXSP)
CC = 5.5V, at CRT display)
M37210M4
PIN CONFIGURATION (TOP VIEW)
HSYNC
VSYNC
P60/PWM0
P6
1/PWM1
P6
2/PWM2
P6
3/PWM3
P0
0/PWM4
P0
1/PWM5
P0
2/PWM6
P0
3/PWM7
P4
2/SIN/A-D5
P4
1/SCLK
P40/SOUT (/IN)
P3
5/INT2/A-D4
P3
4/INT1
P3
3/TIM3
P3
2/TIM2
CNVSS
XOUT
D-A
P2
P25
P26
P27
XIN
VSS
→
→
←
←
←
←
↔
↔
↔
↔
→
↔
↔
←
→
→
→
→
↔
4
↔
↔
↔
→
→
←
→
P52/R
→
P5
→
P5
→
P5
↔
P2
↔
P21
↔
P22
↔
P23
↔
P04
↔
P05
↔
P06
↔
P07
↔
P10
↔
P11
↔
P12
↔
P13
↔
P14
←
P15/A-D1
←
P1
←
P1
↔
P3
↔
P31
←
RESET
←
OSC1
→
OSC2
V
3/G
4/B
5/OUT
0
6/A-D2
7/A-D3
0
CC
Outline 52P4B
Note : The M37211M2-XXXSP does not have the PWM6 and the PWM7.
A-D comparator (5-bit resolution) ................................ 5 channels
•
CRT display function
•
Display characters.....................................18 characters ✕ 2 lines
(16 lines max.)
Character kinds ................................................................ 96 kinds
Dot structure ............................................................. 12 ✕ 16 dots
Character size .................................................................... 3 kinds
Character color kinds (It can be specified by the character)
max. 7 kinds (R, G, B)
Raster color (max. 7 kinds)
Display layout
Horizontal ..................................................................... 64 levels
Vertical ....................................................................... 128 levels
Bordering (horizontal and vertical)
APPLICATION
TV
M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP
PIN CONFIGURATION (TOP VIEW)
MITSUBISHI MICROCOMPUTERS
M37210E4-XXXSP/FP, M37210E4SP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
/A-D1
/A-D2
/A-D3
5
6
P22P23P04P05P06P07P10NC
P11P12P13P14NC
P1
P1
7
P1
P2
NC
P2
P55 /OUT
P54 /B
3 /G
P5
2 /R
P5
NC
NC
SYNC
H
VSYNC
P60 /PWM0
P62 /PWM2
NC
3 /PWM3
P6
484746454443424140393837363534
49
1
50
51
0
52
53
54
55
56
57
58
59
60
61
P61 /PWM1
62
63
64
M37210M3-XXXFP
123456789
CLK
NC
/S
/A-D5
1
/PWM6
/PWM7
2
3
P0
P0
IN
/S
2
P4
P4
/PWM5
/PWM4
1
0
P0
P0
Outline 64P6N-A
10111213141516
)
IN
D-A
/(/
/INT1
4
OUT
P3
/S
0
/INT2/A-D4
5
P4
P3
/TIM3
/TIM2
3
2
P3
P3
P2
4P25P26
33
32
P30
31
NC
30
1
P3
29
RESET
28
OSC1
27
OSC2
26
Vcc
25
NC
24
NC
23
SS
V
22
XOUT
21
XIN
20
CNVSS
19
P27
18
NC
NC
17
NC : No connection
2
MITSUBISHI MICROCOMPUTERS
M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP
M37210E4-XXXSP/FP, M37210E4SP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
R
G
29 28
YSYNC OSC1OSC2
12
HSYNC
14
14-bit PWM circuit
6-bit PWM circuit
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
Control signal
Instruction decoder
CRT circuit
Instruction
register
SI/O(8)
B
OUT
P6(4)P3(6) P5(4)
SOUT
SCLK
SIN
CC VSS CNVSS D-A
V
(5V) (0V) (0V)
RESET
Reset input
Data bus
Timer count
Timer 1
source selection
circuit
T1 (8)
ROM
(Note 3)
12 K bytes
L(8)
Program
counter
PC
H(8)
Program
counter
PC
RAM
(Note 2)
256bytes
Timer 2
T2 (8)
TIM2
Timer 3
T3 (8)
Stack
pointer
Index
register Y
Index
register X
status
Processor
TIM3
(8)
(8)
(8)
PS(8)
register
Timer 4
T4 (8)
P4(3)
Interrupt interval
determination
circuit
INT1, INT2
INT1
INT2
compa-
A-D
rator
P2(8)P1(8)P0(8)
A-D5
A-D4
5
3
A-D3
A-D2
A-D1
Clock
output
24 25 30 27 26 23
Clock
input
XIN XOUT
Clock
generating
circuit
FUNCTIONAL BLOCK DIAGRAM of M37210M3-XXXSP
Address bus
Accumulator
8-bit
arithmetic
A(8)
and logical
unit
I/O port P0 I/O port P1 I/O port P2 I/O port P3 I/O port P4 Output port P6 Video signal output
4142434410 9 8 7 3334353637383940 2221201945464748 151617183132 111213 6 5 4 3 49505152
2 : 320 bytes for M37210M4-XXXSP and 192 bytes for M37211M2-XXXSP
3 : 16 K bytes for M37210M4-XXXSP and 8 K bytes for M37211M2-XXXSP
Notes 1 : The M37211M2-XXXSP does not have PWM outputs of pins 9 and 10.
3
M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP
M37210E4-XXXSP/FP, M37210E4SP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
FUNCTIONS
Parameter
Number of basic instructions
Instruction execution time
Clock frequency
M37210M3-XXXSP/FP
Memory size
Input/Output ports
Serial I/O
Timers
Subroutine nesting
Interrupt
Clock generating circuit
Power source voltage
Power dissipation
Operating temperature range
Device structure
Package
CRT display function
Note : The M37211M2-XXXSP can be also used as PWM4 and PWM5.
M37210M4-XXXSP
M37211M2-XXXSP
P0
P10 – P14
P15 – P17
P2
P30, P31
P32, P35
P40, P41
P42
P5
P6
at CRT display ON
at CRT display OFF
at stop mode
M37210M3-XXXSP, M37210M4-XXXSP, M37211M2-XXXSP
M37210M3-XXXFP
Number of character
Character dot construction
Kinds of characters
Character size
Kinds of color
Display position (horizontal, vertical)
Output
Output
ROM
RAM
ROM
RAM
ROM
RAM
I/O
I/O
Input
I/O
I/O
Input
I/O
Input
MITSUBISHI MICROCOMPUTERS
with ON-SCREEN DISPLAY CONTROLLER
Functions
69
0.5µs (the minimum instruction execution time, at 8MHz oscillation frequency)
8MHz
12 K bytes
256 bytes
16 K bytes
320 bytes
8 K bytes
192 bytes
8-bit ✕ 1 (can be used as N-channel open-drain output and PWM4-PWM7)(Note)
5-bit ✕ 1 (CMOS 3-state output)
3-bit ✕ 1 (can be used as A-D input)
8-bit ✕ 1 (CMOS 3-state output)
2-bit ✕ 1 (CMOS 3-state input/output)
4-bit ✕ 1 (can be used as timer input pins, INT input pins and A-D input pins)
2-bit ✕ 1 (can be used as N-channel open-drain output and serial I/O function pins)
1-bit ✕ 1 (can be used as serial I/O and A-D input)
4-bit ✕ 1 (can be used as R, G, B, OUT pins)
4-bit ✕ 1 (can be used as N-channel open-drain output and PWM0-PWM3 output pins)
8-bit ✕ 1
8-bit timer ✕ 4
96 levels (max.)
Two external interrupts, four internal timer interrupts,
one serial I/O interrupt, one CRT interrupt, one f(X
interrupt, one VSYNC interrupt, BRK instruction
Built-in circuit (externally connected a ceramic resonator or a quartz-crystal oscillator)
5V ± 10%
110mW (at 4MHz oscillation frequency, VCC = 5.5V, Typ.)
55mW (at 4MHz oscillation frequency, VCC = 5.5V, Typ.)
1.65mW (Max.)
−10 to 70°C
CMOS silicon gate process
52-pin shrink plastic molded DIP
64-pin plastic molded QFP
18 characters ✕ 2 lines : maximum 16 lines (by software)
12 ✕ 16 dots
96 kinds
3 kinds
7 kinds max, (R, G, B) : can be specified by character unit
64 levels (horizontal) ✕ 128 levels (vertical)
IN)/4096
4
M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP
PIN DESCRIPTION
Pin
CC,
V
VSS
CNVSS
RESET
XIN
XOUT
φ
P00 – P07
P11 – P14
P15 – P17
P20 – P27
P30, P31
P32 – P35
P40, P41
P42
P60 – P63
OSC1,
OSC2
HSYNC
VSYNC
R, G, B,
OUT
D-A
Name
Power source voltage
CNVSS
Reset input
Clock input
Clock output
Timing output
I/O port P0
I/O port P1
Input port P1
I/O port P2
I/O port P3
Input port P3
I/O port P4
Input port P4
Output port P6
Clock input for CRT
display
Clock output for CRT
display
SYNC input
H
VSYNC input
CRT output
DA Output
Input /
Output
Input
Input
Output
Output
I/O
I/O
Input
I/O
I/O
Input
I/O
Input
Output
Input
Output
Input
Input
Output
Output
MITSUBISHI MICROCOMPUTERS
M37210E4-XXXSP/FP, M37210E4SP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
Functions
Apply voltage of 5V ± 10% to V
This is connected to VSS.
To enter the reset state, the reset input pin must be kept at a “L” for 2µs or more (under nor-
mal VCC conditions).
If more time is needed for the crystal oscillator to stabilize, this “L” condition should be maintained for the required time.
This chip has an internal clock generating circuit. To control gener ating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between the XIN and
XOUT pins. If an external clock is used, the clock source should be connected the XIN pin and
the XOUT pin should be left open.
This is the timing output pin.
Port P0 is an 8-bit I/O port with directional registers allowing each I/O bit to be individually
programmed as input or output. At reset, this port is set to input mode. The output structure
is CMOS output.
The output structure is N-channel open-drain output. When PWM4, PWM5, PWM6 and
PWM7 are used, P00, P01, P02 and P03 are in common with PWM output pins of PWM4,
PWM5, PWM6 and PWM7.
Ports P10, P11, P12, P13 and P14 are 5-bit I/O ports and have basically the same functions
as port P0. The output structure is CMOS output.
Ports P15, P16 and P17 are 3-bit input ports and they are in common with input pins of A-D
comparator (A-D1, A-D2 and A-D3).
Port P2 is an 8-bit I/O port and has basically the same functions as port P0.
The output structure is CMOS output.
Ports P30 and P31 are 2-bit I/O ports and have basically the same functions as port P0.
The output structure is CMOS output.
Ports P32, P33, P34 and P35 are 4-bit input ports and ports P32 and P33 are in common
with external clock input pins of timers 2 and 3. Ports P34 and P35 are in common with
external interrupt input pins INT1 and INT2. Port P35 is in common with an input pin of A-D
comparator (A-D4).
Ports P40 and P41 are 2-bit I/O ports and have basically the same functions as port P0.
When serial I/O is used, ports P40 and P41 are in common with SOUT pin and SCLK pin, respectively.
Port P42 is an 1-bit Input port, and it is common with an input pin of A-D comparator (A-D5)
and serial input pin (SIN).
Port P6 is an 4-bit output port. The output structure is N-channel open-drain. This port is in
common with 6-bit PWM output pins PWM0-PWM3.
This is the I/O pins of the clock generating circuit for the CRT display function.
This is the horizontal synchronizing signal input for CRT display.
This is the vertical synchronizing signal input for CRT display.
This is a 4-bit output pin for CRT display. The output structure is CMOS output. This is in
common with port P52 – P55.
This is an output pin for 14-bit PWM.
CC, and 0V to VSS.
5
MITSUBISHI MICROCOMPUTERS
M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP
M37210E4-XXXSP/FP, M37210E4SP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The M37210M3-XXXSP/FP uses the standard 740 family instruction
set. Refer to the table of 740 family addressing modes and machine
instructions or the SERIES 740 〈Software〉 User’s Manual for details
on the instruction set.
Machine-resident 740 family instructions are as follows :
The FST and SLW instruction cannot be used.
The MUL, DIV, WIT, and STP instruction can be used.
70
0011111
Note : Please beware of this bit when programming because it is set to “1” after the reset release.
Especially the internal RAM of the M37211M2-XXXSP is in the zero page, so be sure to set this bit to “0”.
Fig. 1 Structure of CPU mode register
CPU Mode Register
The CPU mode register is allocated at address 00FB16. The CPU
mode register contains the stack page selection bit.
CPU mode register
(CPUM : address 00FB16)
Fix these bits to “002”
Stack page selection bit (Note)
0 : Zero page
1 : 1 page
Fix these bits to “11112”
6
MITSUBISHI MICROCOMPUTERS
M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP
M37210E4-XXXSP/FP, M37210E4SP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
MEMORY
Special Function Register (SFR) Area
The special function register (SFR) area in the zero page contains
control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
ROM
ROM is used for sroring user programs as well as the interrupt vector area.
RAM for Display
RAM for display is used for specifing the character codes and colors
to display.
ROM for Display
ROM for display is used for storing character data.
Fig. 2 Memory map
RAM
(320 bytes)
for
M37210M4
ROM
(16 K bytes)
for
M37210M4
RAM
(256 bytes)
for
M37210M3
RAM for display (Note)
ROM for display
ROM
(12 K bytes)
for
M37210M3
RAM
(192 bytes)
M37211M2
(72 bytes)
(3 K bytes)
(8 K bytes)
M37211M2
for
ROM
for
0000
00BF
00FF
013F
017F
2000
20B1
3000
35FF
3800
3DFF
C000
D000
E000
FF00
FFDE
FFFF
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the zero
page area. The inter nal RAM and the special function registers
(SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
SFR area
Not used
Not used
Not used
Not used
Interrupt vector area
Note : Refer to Table 6. Contents of CRT display RAM
Zero page
Special page
7
MITSUBISHI MICROCOMPUTERS
M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP
M37210E4-XXXSP/FP, M37210E4SP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
00C016
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00C816
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
00D216
00D316
00D416
00D516
00D616
00D716
00D816
00D916
00DA16
00DB16
00DC16
00DD16
00DE16
00DF16
Port P0
Port P0 directional register
Port P1
Port P1 directional register
Port P2
Port P2 directional register
Port P3
Port P3 directional register
Port P4
Port P4 directional register
Port P5
Port P5 control register
Port P6
Port P6 directional register
14DA-H register
14DA-L register
PWM0 register
PWM1 register
PWM2 register
PWM3 register
PWM4 register
PWM output control register 1
PWM output control register 2
Interrupt
Interrupt
Serial I/O mode register
Serial I/O register
determination register
Interval
determination control register
Interval
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
00EF16
00F016
00F116
00F216
00F316
00F416
00F516
00F616
00F716
00F816
00F916
00FA16
00FB16
00FC16
00FD16
00FE16
00FF16
Horizontal position register
Vertical position register 1 (block 1)
Vertical position register 2 (block 2)
Character size register
Border selection register
Color register 0
Color register 1
Color register 2
Color register 3
CRT control register
CRT port control register
A-D mode register
A-D control register
Timer 1
Timer 2
Timer 3
Timer 4
Timer 12 mode register
Timer 34 mode register
PWM5 register
PWM6 register (Note)
PWM7 register (Note)
mode register
CPU
Interrupt request register 1
Interrupt request register 2
Interrupt control register1
Interrupt control register2
Note : The M37211M2-XXXSP dose not have this register
Fig. 3 Memory map of special function register (SFR )
8
MITSUBISHI MICROCOMPUTERS
M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP
M37210E4-XXXSP/FP, M37210E4SP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
INTERRUPTS
Interrupts can be caused by 12 different sources consisting of 3 external, 7 internal, 1 software, and reset.
Interrupts are vectored interrupts with priorities shown in Table 1. Reset is also included in the table because its operation is similar to an
interrupt.
When an interrupt is accepted, the registers are pushed, interrupt
disable flag I is set, and the program jumps to the address specified
in the vector table. The interrupt request bit is cleared automatically.
The reset can never be disabled. Other interrupts are disabled when
the interrupt disable flag is set.
Table 1. Interrupt vector addresses and priority
Interrupt sources
Reset
CRT interrupt
INT2 interrupt
INT1 interrupt
Timer 4 interrupt
f(XIN)/4096 interrupt
VSYNC interrupt
Timer 3 interrupt
Timer 2 interrupt
Timer 1 interrupt
Serial I/O interrupt
BRK instruction interrupt
Priority
1
2
3
4
5
6
7
8
9
10
11
12
Vector addresses
FFFF
FFFD16, FFFC16
FFFB16, FFFA16
FFF916, FFF816
FFF516, FFF416
FFF316, FFF216
FFF116, FFF016
FFEF16, FFEE16
FFED16, FFEC16
FFEB16, FFEA16
FFE916, FFE816
FFDF16, FFDE16
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits are
in interrupt request registers 1 and 2 and the interrupt enable bits are
in interrupt control registers 1 and 2. Figure 4 shows the structure of
the interrupt request registers 1 and 2 and interrupt control registers
1 and 2.
Interrupts other than the BRK instruction interrupt and reset are accepted when the interrupt enable bit is “1”, interrupt request bit is “1”,
and the interrupt disable flag is “0”. The interrupt request bit can be
reset with a program, but not set. The interrupt enable bit can be set
and reset with a program.
Reset is treated as a non-maskable interrupt with the highest priority.
Figure 5 shows interrupts control.
Remarks
16, FFFE16
Non-maskable
Active edge selectable
Active edge selectable
Active edge selectable
Non-maskable software interrupt
9
MITSUBISHI MICROCOMPUTERS
M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP
M37210E4-XXXSP/FP, M37210E4SP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
70
Interrupt request register 1
(IREQ1 : address 00FC16)
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Timer 4 interrupt request bit
CRT interrupt request bit
V
SYNC
interrupt request bit
70
Interrupt control register 1
(ICON1 : address 00FE
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
Timer 4 interrupt enable bit
CRT interrupt enable bit
V
SYNC
interrupt enable bit
Fix these bits to “0”
70
0
0 : No interrupt request issued
1 : Interrupt request issued
70
00000
16
)
0 : Interrupt disabled
1 : Interrupt enabled
Interrupt request register 2
(IREQ2 : address 00FD
INT1 interrupt request bit
INT
Serial I/O1 interrupt request bit
f(X
Fix this bit to “0”
Interrupt control register 2
(ICON2 : address 00FF16)
INT1 interrupt enable bit
INT
Serial I/O1 interrupt enable bit
Fix this bit to “0”
f(X
Fix these bits to “0”
16
2
interrupt request bit
IN
)/4096 interrupt request bit
2
interrupt enable bit
IN
)/4096 interrupt enable bit
)
Fig. 4 Structure of interrupt-related registers
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
Fig. 5 Interrupt control
BRK instruction
reset
interrupt request
10
MITSUBISHI MICROCOMPUTERS
M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP
M37210E4-XXXSP/FP, M37210E4SP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
TIMERS
The M37210M3-XXXSP has 4 timers: timer 1, timer 2, timer 3 and
timer 4. All timers are 8-bit timers with the 8-bit timer latch. The timer
block diagram is shown in Figure 7.
All of the timers count down and their divide ratio is 1/(n+1), where n
is the value of timer latch. The value is set to a timer at the same time
by writing a count value to the corresponding timer latch (addresses
00F0
16 to 00F316 : timers 1 to 4).
The count value is decremented by 1. The timer interrupt request bit
is set to “1” by an timer overflow at the next count pulse after the
count value reaches “00
16.”
(1) Timer 1
Timer 1 can select one of the following count sources:
f(XIN)/16
•
f(XIN)/4096
•
The count source of timer 1 is selected by setting bit 0 of the timer 12
mode register (address 00F4
Timer 1 interrupt request occurs at timer 1 overflow.
16).
(2) Timer 2
Timer 2 can select one of the following count sources:
f(XIN)/16
•
Timer 1 overflow signal
•
External clock from the P32/TIM2 pin
•
The count source of timer 2 is selected by setting bits 4 and 1 of the
timer 12 mode register (address 00F4
signal is a count source for the timer 2, the timer 1 functions as an 8bit prescaler.
Timer 2 interrupt request occurs at timer 2 overflow.
16). When timer 1 overflow
(3) Timer 3
Timer 3 can select one of the following count sources:
f(XIN)/16
•
External clock from the P33/TIM3 pin and the HSYNC pin
•
The count source of timer 3 is selected by setting bits 5 and 0 of the
timer 34 mode register (address 00F5
Timer 3 interrupt request occurs at timer 3 overflow.
16).
(4) Timer 4
Timer 4 can select one of the following count sources:
f(XIN)/16
•
f(XIN)/2
•
Timer 3 overflow signal
•
The count source of timer 3 is selected by setting bits 4 and 1 of the
timer 34 mode register 2 (address 00F5
signal is a count source for the timer 4, the timer 3 functions as an 8bit prescaler.
Timer 4 interrupt request occurs at timer 4 overflow.
16). When timer 3 overflow
set bit 0 of the timer 34 mode register (address 00F5
the execution of the STP instruction (f(X
3 count source). The internal STP state is released by timer 4 overflow at these state, the internal clock is connected .
Because of this, the program starts with stable clock.
The structure of timer-related registers is shown in Figure 6.
70
Timer 12 mode register
(TM12MR : address 00F4
Timer 1 count source selection bit
0 : f (X
1 : 1024µs clock
Timer 2 count source selection bit
0 : Internal clock source
1 :
Timer 1 count stop bit
0 : Operation
1 : Stop
Timer 2 count stop bit
0 : Operation
1 : stop
Timer 2 internal count source
selection bit
0 : f (X
1 : Timer 1 overflow signal
Fix this bit to “0”
70
Timer 34 mode register
(TM34MR : address 00F5
Timer 3 count source selection bit
0 : f (X
1 : External clock source (bits)
Timer 4 internal count source
selection bit
0 : Timer 3 overflow signal
1 : f (X
Timer 3 count stop bit
0 : Operation
1 : Stop
Timer 4 count stop bit
0 : Operation
1 : Stop
Timer 4 count source selection bit
0 : Internal clock source
1 : f (X
IN)16 is selected as the timer
IN
) /16
External clock source from
IN
) /16
IN
) /16
IN
) /16
IN
) /2
16) to “0” before
16
)
P32/TIM2
pin
16
)
At reset, timers 3 and 4 are connected by hardware and “FF
automatically set in timer 3; “07
lected as the timer 3 count source. The internal reset is released by
timer 4 overflow at these state, the internal clock is connected .
At execution of the STP instruction, timers 3 and 4 are connected by
hardware and “FF
However, the f(X
16” is automatically set in timer 3; “0716” in timer 4.
IN)16 is not selected as the timer 3 count source. So
16” in timer 4. The f(XIN)/16 is se-
16” is
Timer 3 external count source
selection bit
3
0 : P3
1 : H
SYNC
Fig. 6 Structure of timer-related registers
/TIM3 pin input
pin input
11
MITSUBISHI MICROCOMPUTERS
M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP
M37210E4-XXXSP/FP, M37210E4SP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
Data bus
8
XIN
P32/TIM2
HSYNC
P33/TIM3
1/2 1/8
D.F.
D.F.
1/4096
T12M0
T12M4
T12M1
T12M3
T34M5
T12M2
Timer 1 latch (8)
8
Timer 1 (8)
Timer 2 latch (8)
8
Timer 2 (8)
Timer 3 latch (8)
8
8
8
8
8
FF16
Timer 1
interrupt request
Timer 2
interrupt request
Reset
STP instruction
T34M0
T34M2
T34M1
Timer 4 latch (8)
T34M
4
Selection gate : Connected to black
colored side at reset.
T12M : Timer 12 mode register
T34M : Timer 34 mode register
Notes 1 : “H” pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more.
2 :When the external clock source is selected, timers 2 and 3 are counted at a rising edge of input signal.
3 :In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.
T34M3
Fig. 7 Timer block diagram
Timer 3 (8)
8
Timer 4 (8)
Timer 3
interrupt request
8
8
0716
Timer 4
interrupt request
8
12
MITSUBISHI MICROCOMPUTERS
M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP
M37210E4-XXXSP/FP, M37210E4SP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
SERIAL I/O
M37210M3-XXXSP has a serial I/O.
A block diagram of the serial I/O is shown in Figure 8.
Synchronous input/output clock (S
S
IN) are used as port P4. The serial I/O mode registers (address
00DC
16) are 8-bit registers. Bits 0, 1 and 2 of these registers are
used to select a synchronous clock source.
XIN
P41 latch
P4
1/SCLK
P40 latch
P40/SOUT
P42/SIN
CLK), and the serial I/O pins (SOUT,
1/2 1/2
Synchronization
circuit
SM3
SM
5 : LSB
3
SM
SM6
Selection gate : Connected to black
colored side at reset.
↔
Bit 3 decides whether parts of P4 will be used as a serial I/O or not.
To use P4
2 as a serial input, set the directional register bit which cor-
responds to P4
ter, refer to the I/O pin section.
The serial I/O function is discussed below. The function of the serial
I/O differs depending on the clock source ; external clock or internal
clock.
SM2
Serial I/O counter (8)
MSB
Serial I/O shift register (8)
(address 00DD
2 to “0”. For more information on the directional regis-
Data bus
Frequency
divider
1/4 1/8 1/16
SM1
SM0
Serial I/O
interrupt request
16)
8
Fig. 8 Serial I/O block diagram
13
MITSUBISHI MICROCOMPUTERS
M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP
M37210E4-XXXSP/FP, M37210E4SP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
The serial I/O counter is set to 7 when data is stored in the serial I/O
register. At each falling edge of the transfer clock, serial data is output to S
OUT. During the rising edge of this clock, data can be input
from S
IN and the data in the serial I/O register will be shifted 1 bit.
T r ansfer direction can be selected by bit 5 of serial I/O mode register.
After the transfer clock has counted 8 times, the serial I/O register will
be empty and the transfer clock will remain at a high le v el. At this time
the interrupt request bit will be set.
External clock- If an external clock is used, the interrupt request will
be sent after the transfer clock has counted 8 times but transfer clock
will not stop.
Due to this reason, the external clock must be controlled from the
outside. The external clock should not exceed 1MHz at a duty cycle
Sync. clock
Transfer clock
Serial I/O register
write signal
Serial I/O output
SOUT
Serial I/O input
SIN
D0 D1 D2 D3 D4 D5 D6 D7
of 50%. The timing diagram is shown in Figure 9. When using an external clock for transfer, the external clock must be held at “H” level
when the serial I/O counter is initialized. When switching between the
internal clock and external clock, the switching must not be performed during transfer. Also, the serial I/O counter must be initialized
after switching.
Notes 1: On programming, note that the serial I/O counter is set by
writing to the serial I/O register with the bit managing instructions as SEB and CLB instructions.
2: When an external clock is used as the synchronizing clock,
write transmit data to the serial I/O register at “H” of the
transfer clock input level.
(Note 1)
Notes 1 : If internal clock is selected, the Sout pin is at high impedance after transfer is completed.
2 : When an external clock is used as the synchronous clock, write the transmit data to the
serial I/O shift register at “H” of the transfer clock input level.
Fig. 9 Serial I/O timing (for LSB first)
Interrupt request bit set
14
M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP
70
Serial l/O mode register
(SM : address 00DC16)
Internal synchronous clock
selection bits
00 : f (XIN) /4
01 : f (XIN) /16
10 : f (XIN) /32
11 : f (XIN) /64
Synchronous clock selection bit
0 : External clock
1 : Internal clock
Serial l/O port selection bit
0 : P40, P41
1 : SOUT1,SCLK signal output pins
Fix this bit to “0”
Transfer direction selection bit
0 : LSB first
1 : MSB first
Serial input pin selection bit
0 : Input from SIN pin
1 : Input from SOUT pin
MITSUBISHI MICROCOMPUTERS
M37210E4-XXXSP/FP, M37210E4SP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
Serial I/O common transmission/reception mode.
Write 1 to bit 6 of serial I/O mode register, and signals S
switch internal to be able to serial data transmission/reception.
Figure 11 shows signals on serial I/O common transmission/reception mode.
Note : Receive the serial data after writing “FF
register.
IN and SOUT
16” to the serial I/O
Fig. 10 Structure of serial I/O mode register
P41/SCLK
P40/SOUT (/IN)
P4
2/SIN
Fig. 11 Signals on serial I/O common transmission/reception mode
Input or output The transmission mode
“1”
6
SM
“0”
The reception mode
clock1
Serial I/O shift register
Port P42 data
15
MITSUBISHI MICROCOMPUTERS
M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP
M37210E4-XXXSP/FP, M37210E4SP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
PWM OUTPUT CIRCUIT
(1) Introduction
The M37210M3-XXXSP/FP and M37210M4-XXXSP are
equipped with one 14-bit PWM (DA) and eight 6-bit PWMs
(PWM0-PWM7), and the M37211M2-XXXSP is equipped with
six 6-bit PWMs (PWM0-PWM5). The 14-bit resolution gives DA
the minimum resolution bit width of 500ns (for f(X
and a repeat period of 8192µs. PWM0-PWM7 have a 6-bit resolution with minimum resolution bit width of 16ms and repeat period of 1024µs.
Block diagram of the PWM is shown in Figure 16.
The PWM timing generator section applies individual control
signals to DA and PWM0-7 using clock input X
as a reference signal.
IN) = 4MHz)
IN divided by 2
(2) Data Setting
The output pins PWM0-3 are in common with port P6 and
PWM4-7 are in common with port P0
For PWM output, each PWM output selection bit (bit 1 to 7 of
PWM output control register 1, bit 0, 1 of PWM output control
register 2, should be set. When DA is used for output, first set
the higher 8-bit of the DA-H register (address 00CE
lower 6-bit of the DA-L register (address 00CF
When one of the PWM0-7 is used for output, set the 6-bit in the
PWM0-7 register (address 00D0
00F8
16), respectively.
0-P03.
16), then the
16).
16 to 00D416, 00F616 to
(3) Transferring Data from Registers to PWM
Circuit
The data written to the PWM registers. 8 bits of the DA-H register is transferred to 14-bit PWM circuit when writing to lower 6
bits of the DA-L register.
(4) Operation of the 6-bit PWMs
The timing diagram of the eight 6-bit PWMs (PWM0-7) is shown
in Figure 13. One period (T) is composed of 64 (2
There are six different pulse types configured from bits 0 to 5
representing the significance of each bit. These are output
6
) segments.
within one period in the circuit internal section. Refer to Figure
13 (a).
Six different pulses can be output from the PWM.
These can be selected by bits 0 through 5. Depending on the
content of the 6-bit PWM latch, pulses from 5 to 0 are selected.
The PWM output is the difference of the sum of each of these
pulses. Several examples are shown in Figure 13 (b). Changes
in the contents of the PWM latch allows the selection of 64
lengths of high-level area outputs varying from 0/64 to 63/64. A
length of entirely high-level output cannot be output, i.e. 64/64.
(5) 14-bit PWM Operation
The output example of the 14-bit PWM is shown in Figure 14.
The 14-bit PWM divides the data within the PWM latch into the
lower 6 bits and higher 8 bits.
A high-level area within a length D
area of t = 256 τ =128µs as determined by data D
8 bits.
Thus, the time for the high-level area is equal to the time set by
the lower 8 bits or that plus τ. As a result, the short-area period
t ( = 128µs, approx. 7.8 kHz) becomes an approximately repetitive period.
H times τ is output every short
H of the higher
(6) Output after Reset
At reset the output of port P6 is in the high impedance state and
the contents of the PWM register and latch are undefined. Note
that after setting the PWM register, its data is transferred to the
latch.
Table 2. Relation between the low-order 6 bits of data and high-level
area increase space
6 low-order bits of data
0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 0 1 0
0 0 0 1 0 0
0 0 1 0 0 0
0 1 0 0 0 0
1 0 0 0 0 0
Area longer by τ than that of other tm (m = 0 to 63)
LSB
Nothing
m = 32
m = 16, 48
m = 8, 24, 40, 56
m = 4, 12, 20, 28, 36, 44, 52, 60
m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62
m = 1, 3, 5, 7, ................................................... 57, 59, 61, 63
16
MITSUBISHI MICROCOMPUTERS
M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP
M37210E4-XXXSP/FP, M37210E4SP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
Data bus
DA-H register
(address 00CE16)
bit 7 bit 0
(14-bit)
MSB
8
XIN
PWM0 register
(address 00D016)
bit 5
8
6-bit PWM circuit
6
14-bit PWM circuit
1/2
PW0
DA-L register
(address 00CF16)
14
Timing
generator
for PWM
bit 0
PN3
LSB
6
PN4
PW
D60
DA
1
D-A
PWM0
PN2
P60
Selection gate : connected to black
colored side at reset.
Pass gate
PW2
P61
D61
PWM1
PW3
P62
D62
PW4
P63
D63
PW5
P00
D00
PW6
P01
D01
PW7
P02
D02
PN0
P03
D03
PN1
Note : The M37211M2-XXXSP can not output the PWM.
Inside of is as same contents with the others.
PWM2
PWM3
PWM4
PWM5
PWM6(Note)
PWM7(Note)
PW : PWM output control register 1
PN : PWM output control register 2
D0 : Port P0 direction register
P0 : Port P0
D6 : Port P6 directional register
P6 : Port P6
Fig. 12 PWM block diagram
17
MITSUBISHI MICROCOMPUTERS
M37210M3-XXXSP/FP, M37210M4-XXXSP, M37211M2-XXXSP
M37210E4-XXXSP/FP, M37210E4SP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
13579 19 39 59
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00
(0)
0116
(1)
0616
(24)
3F16
(63)
2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62
4 12202836445260
8
16 48
16
24
32
(a) Pulses showing the weight of each bit
T = 64t
PWM output t = 10µs T = 1024µs
f (XIN) = 4MHz
40
56
Fig. 13 6-bit PWM timing
(b) Example of 6-bit PWM output
18
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