How it Works
Mitsubishi
Loading...
M30610SAGP
Datasheet
197 pgs2.74 Mb0
Table of contents
Loading...

Mitsubishi M30612M8A-XXXGP, M30612M8A-XXXFP, M30612M4A-XXXGP, M30612M4A-XXXFP, M30612E4GP Datasheet

...
Mitsubishi microcomputers
M16C / 61 Group

Description

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
The M16C/61 group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of in­struction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. They also feature a built-in multiplier and DMAC, making them ideal for controlling office, communi­cations, industrial equipment, and other high-speed processing applications. The M16C/61 group includes a wide range of products with different internal memory types and sizes and various package types.

Features

• Memory capacity............................................ROM (See Figure 1.1.4. ROM Expansion)
RAM 4K to 10K bytes
• Shortest instruction execution time................ 100ns (f(XIN)=10MHZ)
• Supply voltage ............................................... 4.0 to 5.5V (f(XIN)=10MHZ)
2.7 to 5.5V (f(XIN)=7MHZ with software one-wait)
• Low power consumption ................................18mW ( f(XIN)=7MHZ, with software one-wait, VCC = 3V)
• Interrupts........................................................20 internal and 5 external interrupt sources, 4 software
interrupt sources; 7 levels (including key input interrupt)
• Multifunction 16-bit timer................................5 output timers + 3 input timers
• Serial I/O (UART or clock synchronous)........ 3 channels
• DMAC ............................................................ 2 channels (trigger: 16 sources)
• A-D converter.................................................10 bits X 8 channels
(Expandable up to 10 channels)
• D-A converter.................................................8 bits X 2 channels
• CRC calculation circuit...................................1 circuit
• Watchdog timer..............................................1 line
• Programmable I/O .........................................87 lines
• Input port........................................................
• Memory expansion ........................................Available (to a maximum of 1M bytes)
• Chip select output ..........................................4 lines
• Clock generating circuit .................................2 built-in clock generation circuits
1 line (P85 shared with NMI pin)
(built-in feedback resistor, and external ceramic or quartz oscillator)
_______

Applications

Audio, cameras, office equipment, communications equipment, portable equipment
------Table of Contents------
Central Processing Unit (CPU) .....................11
Reset.............................................................14
Processor Mode............................................ 19
Clock Generating Circuit ...............................30
Protection......................................................39
Interrupts.......................................................40
Watchdog Timer............................................59
DMAC ...........................................................61
Timer.............................................................70
Serial I/O .......................................................87
A-D Converter .............................................114
D-A Converter .............................................124
CRC Calculation Circuit ..............................126
Programmable I/O Ports .............................128
Electrical Characteristics.............................142
1
Description

Pin Configuration

Figures 1.1.1 and 1.1.2 show the pin configurations (top view).
PIN CONFIGURATION (top view)
)
8
/D
0
P1
9
/D
1
P1
10
/D
2
P1
11
/D
3
P1
12
/D
4
P1
13
/D
5
P1
14
/D
6
P1
15
/D
7
P1
/-)
0
(/D
0
/A
0
P2
)
0
/D
1
(/D
1
/A
1
P2
)
1
/D
2
(/D
2
/A
2
P2
)
2
/D
3
(/D
3
/A
3
P2
3
/D
4
(/D
4
/A
4
P2
)
4
/D
5
(/D
5
/A
5
P2
)
5
/D
6
(/D
6
/A
6
P2
)
6
/D
7
(/D
7
/A
7
P2
Vss
)
7
(/-/D
8
/A
0
P3
Vcc
9
/A
1
P3
10
/A
2
P3
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
14
/A
6
P3
15
/A
7
P3
16
/A
0
P4
17
/A
1
P4
18
/A
2
P4
19
/A
3
P4
11
/A
3
P3
12
/A
4
P3
13
/A
5
P3
P07/D7 P06/D6 P05/D5 P04/D4 P03/D3 P02/D2 P01/D1
P00/D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0
P103/AN3 P102/AN2 P101/AN1
AVSS
P100/AN0
VREF
AVcc
P97/ADTRG
70
11
COUT
/X
6
P8
68
69
13
12
OUT
X
RESET
67
66
14
15
IN
SS
X
V
62
63
64
65
17
16
CC
V
/NMI
5
P8
18
2
/INT
4
P8
19
1
/INT
3
P8
61
20
0
/INT
2
P8
60
21
IN
/TA4
1
P8
59
22
OUT
/TA4
0
P8
58
23
IN
/TA3
7
P7
57
24
OUT
/TA3
6
P7
56
25
IN
/TA2
5
P7
55
26
OUT
/TA2
4
P7
54
27
IN
/TA1
2
/RTS
2
/CTS
3
P7
51
52
53
P44/CS0 P45/CS1 P46/CS2 P47/CS3 P50/WRL/WR P51/WRH/BHE
2/RD
P5 P53/BCLK P54/HLDA P55/HOLD P56/ALE P57/RDY/CLKOUT P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TXD0 P64/
CTS1/RTS1/CTS0/CLKS
P65/CLK1 P66/RxD1 P67/TXD1
Package: 100P6S-A
28
OUT
/TA1
2
/CLK
2
P7
30
29
(Note)
(Note)
IN
OUT
/TA0
2
/TA0
2
/RxD
1
/TxD
0
P7
P7
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
1
79
80
77
78
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
00
1
2
1
4
3
0
1
/DA
/DA
3
4
/ANEX1
/ANEX0
P9
P9
6
5
P9
P9
73
74
75
76
71
72
M16C/61 Group
8
7
6
5
IN
/TB2
2
P9
IN
/TB1
1
P9
IN
/TB0
0
P9
9
BYTE
CNVss
10
CIN
/X
7
P8
Note: P70 and P71 are N channel open-drain output pin.
Figure 1.1.1. Pin configuration (top view)
2
Description
PIN CONFIGURATION (top view)
P107/AN7/KI P106/AN6/KI P105/AN5/KI
P104/AN4/KI
P95/ANEX0
P12/D
P103/AN P102/AN P101/AN
P100/AN
P97/AD
P9
6
/ANEX1
P11/D P10/D
P07/D P06/D P05/D P04/D
P03/D P02/D P01/D
P0
0/D0
AV
V
AVcc
REF
TRG
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
)
)
)
)
)
)
)
2
1
0
/D
/D
/D
/-)
3
2
1
0
(/D
(/D
(/D
12
11
/D
/D
4
3
P1
P1
74
75
10
SS
76
9
77
8
78
7
79
6
80
5
81
4
82
3
83
2
84
1
85 86
3
87 88
2
89
1
90
0
91
3
92
2
93
1
94 95
0
96 97 98 99
100
2
1
(/D
3
2
1
15
14
13
0
/A
/A
/A
/A
/D
/D
/D
5
P1
73
6
P1
72
7
P1
71
0
P2
70
1
P2
3
2
P2
P2
67
68
69
M16C/61 Group
9
8
7
6
5
4
3
3
/D
4
(/D
4
/A
4
P2
66
10
4
/D
5
(/D
5
/A
5
P2
65
11
5
/D
6
(/D
6
/A
6
P2
64
12
6
/D
7
(/D
7
/A
7
P2
63
13
)
7
(/-/D
9
8
/A
/A
1
0
P3
Vcc
P3
Vss
62
59
60
61
15
14
17
16
10
/A
2
P3
58
18
11
/A
3
P3
57
19
12
/A
4
P3
56
20
13
/A
5
P3
55
21
14
/A
6
P3
54
22
15
/A
7
P3
53
23
16
/A
0
P4
52
24
17
/A
1
P4
51
25
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
P42/A
18
P43/A
19
P4
4
/CS0 P45/CS1 P46/CS2 P47/CS3 P50/WRL/WR P51/WRH/BHE P5
2
/RD P53/BCLK
P54/HLDA P5
5
/HOLD P56/ALE P57/RDY/CLK P60/CTS0/RTS P61/CLK
0
P62/RxD
0
P63/TXD
0
P6
4/
CTS1/RTS1/CTS0/CLKS
P65/CLK
1
P66/RxD
1
P67/TXD
1
P70/TxD2/TA0 P71/RxD2/TA0 P72/CLK2/TA1
OUT
0
OUT
IN OUT
1
(Note)
(Note)
0
1
/DA
4
P9
/DA
3
P9
IN
/TB2
2
P9
IN
/TB1
1
P9
IN
/TB0
0
P9
BYTE
CNVss
CIN
/X
7
P8
COUT
/X
6
P8
Note: P70 and P71 are N channel open-drain output pin.
Figure 1.1.2. Pin configuration (top view)
OUT
X
RESET
IN
CC
SS
X
V
V
/NMI
5
P8
/INT
4
P8
/INT
3
P8
/INT
2
P8
IN
/TA4
1
P8
OUT
/TA4
0
P8
IN
/TA3
7
P7
OUT
/TA3
6
P7
IN
/TA2
5
P7
OUT
/TA2
4
P7
IN
/TA1
2
/RTS
2
Package: 100P6Q-A
/CTS
3
0
1
2
P7
3
Description
A
A
AAAA
A
A

Block Diagram

Figure 1.1.3 is a block diagram of the M16C/61 group.
Block diagram of the M16C/61 group
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
8
I/O ports
Internal peripheral functions
Timer TA0 (16 bits) Timer TA1 (16 bits) Timer TA2 (16 bits) Timer TA3 (16 bits) Timer TA4 (16 bits) Timer TB0 (16 bits) Timer TB1 (16 bits) Timer TB2 (16 bits)
Watchdog timer
D-A converter
(8 bits X 2 channels)
Note 1: ROM size depends on MCU type. Note 2: RAM size depends on MCU type. Note 3: One of serial I/O can use for SIM interface.
Port P08Port P18Port P28Port P38Port P48Port P58Port P6
Timer
(15 bits)
DMAC
(2 channels)
A-D converter
(10 bits X 8 channels
Expandable up to 10 channels)
UART/clock synchronous SI/O
(8 bits X 3channels) (Note 3)
CRC arithmetic circuit (CCITT )
(Polynomial : X
M16C/60 series16-bit CPU core
Registers
R1H R1L
R1H R1L
R2
R2
R3
R3
A0
A0
A1
A1
FB
FB
SB FLG
16+X12+X5
R0LR0H
R0LR0H
+1)
Program counter
PC
Vector table
INTB
Stack pointer
ISP
USP
System clock generator
X
IN-XOUT
X
CIN-XCOUT
Memory
ROM
(Note 1)
AAAA
RAM
AAAA
(Note 2)
Multiplier
AA
Port P7
8
Port P8
7
Port P8
5
Port P9
8
Port P10
8
4
Figure 1.1.3. Block diagram of M16C/61 group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Performance Outline

Table 1.1.1 is a performance outline of M16C/61 group.
Table 1.1.1. Performance outline of M16C/61 group
Item Performance Number of basic instructions 91 instructions Shortest instruction execution time 100ns(f(XIN)=10MHZ) Memory ROM (See the Figure 4. ROM Expansion) capacity RAM 4K to 10K bytes I/O port P0 to P10 (except P85) 8 bits x 10, 7 bits x 1 Input port P85 1 bit x 1 Multifunction TA0, TA1, TA2, TA3, TA4 16 bits x 5 timer TB0, TB1, TB2 16 bits x 3 Serial I/O UART0, UART1, UART2 (UART or clock synchronous) x 3 A-D converter 10 bits x (8 + 2) channels D-A converter 8 bits x 2 DMAC 2 channels (trigger: 16 sources) CRC calculation circuit CRC - CCITT Watchdog timer 15 bits x 1 (with prescaler) Interrupt Clock generating circuit 2 built-in clock generation circuits
Supply voltage 4.0 to 5.5V (f(XIN ) = 10MHZ)
Power consumption I/O I/O withstand voltage 5V characteristics Output current 5mA Memory expansion Available (to a maximum of 1M bytes) Device configuration CMOS silicon gate Package 100-pin plastic mold QFP
20 internal and 5 external sources, 4 software sources, 7 levels
(built-in feedback resistor, and external ceramic or quartz oscillator)
2.7 to 5.5V(f(XIN)=7MHZ with software one-wait) 18mW (f(XIN) = 7MHZ with software one-wait,VCC = 3V)
Mitsubishi microcomputers
M16C / 61 Group
5
Mitsubishi microcomputers
M16C / 61 Group
Description
Mitsubishi plans to release the following products in the M16C/61 group: (1) Support for mask ROM version, external ROM version, one-time PROM version, and EPROM version (2) ROM capacity (3) Package
100P6S-A : Plastic molded QFP (mask ROM version and one-time PROM version) 100P6Q-A : Plastic molded QFP (mask ROM version and one-time PROM version) 100D0 : Ceramic LCC (EPROM version)
ROM
Size(Byte)
External ROM
128 K
96 K
M30610MCA-XXXFP/GP M30612MCA-XXXFP/GP
M30610MAA-XXXFP/GP M30612MAA-XXXFP/GP
M30610ECFP/GP M30610ECFS
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M30612SAFP/GP M30610SAFP/GP
64 K
32 K
M30610M8A-XXXFP/GP M30612M8A-XXXFP/GP
M30612M4A-XXXFP/GP
M30612E4FP/GP
Mask ROM version One-time PROM version EPROM version External ROM version
Figure 1.1.4. ROM expansion
The M16C/61 group products currently supported are listed in Table 2.
Table 1.1.2. M16C/61 group
RAM capacityROM capacity Package type RemarksType No M30612M4A-XXXFP M30612M4A-XXXGP 100P6Q-A M30610M8A-XXXFP
M30610M8A-XXXGP M30612M8A-XXXFP
M30612M8A-XXXGP 100P6Q-A M30610MAA-XXXFP M30610MAA-XXXGP 100P6Q-A M30612MAA-XXXFP M30612MAA-XXXGP M30610MCA-XXXFP M30610MCA-XXXGP M30612MCA-XXXFP M30612MCA-XXXGP 100P6Q-A M30612E4FP 100P6S-A M30612E4GP 100P6Q-A M30610ECFP M30610ECGP 100P6Q-A
M30610SAFP 100P6S-A M30610SAGP 100P6Q-A M30612SAFP 100P6S-A M30612SAGP 100P6Q-A
Note: Do not use the EPROM version for mass production, because it is a tool for program development
(for evaluation).
32K byte 4K byte
10K byte
64K byte
4K byte
10K byte
96K byte
4K byte
10K byte
128K byte
5K byte
32K byte 4K byte
128K byte 10K byte
10K byteM30610ECFS 128K byte 100D0
10K byte
4K byte
100P6S-A
100P6S-A 100P6Q-A 100P6S-A
100P6S-A
100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A
100P6S-A
Mask ROM version
One-time PROM version
EPROM version (Note)
External ROM version
Apr. 1999
6
Description
Type No. M 3 0 6 1 2 M 4 – X X X F P
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Package type: FP : Package 100P6S-A GP : 100P6Q-A FS : 100D0
ROM No. Omitted for blank one-time PROM version and EPROM version
ROM capacity: 4 : 32K bytes A : 96K bytes 8 : 64K bytes C : 128K bytes
Memory type: M : Mask ROM version E : EPROM or one-time PROM version S : External ROM version
Figure 1.1.5. Type No., memory size, and package
Shows RAM capacity, pin count, etc (The value itself has no specific meaning)
M16C/61 Group
M16C Family
7
Pin Description
Pin Description
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin name
VCC, VSS
CNVSS
RESET XIN
XOUT
BYTE
AV
CC
AVSS
VREF
Signal name
Power supply input
CNV
SS
Reset input Clock input
Clock output
External data bus width select input
Analog power supply input
Analog power supply input
Reference voltage input
I/O type
Input
Input Input
Output
Input
Input
Function
Supply 2.7 to 5.5 V to the V
CC pin. Supply 0 V to the VSS pin.
This pin switches between processor modes. Connect it to the V
SS pin when operating in single-chip or memory expansion mode.
Connect it to the V
CC pin when in microprocessor mode.
A “L” on this input resets the microcomputer. These pins are provided for the main clock generating circuit.Connect
a ceramic resonator or crystal between the X use an externally derived clock, input it to the X X
OUT pin open.
IN and the XOUT pins. To
IN pin and leave the
This pin selects the width of an external data bus. A 16-bit width is selected when this input is “L”; an 8-bit width is selected when this input is “H”. This input must be fixed to either “H” or “L”. When operating in single-chip mode,connect this pin to V
SS.
This pin is a power supply input for the A-D converter. Connect this pin to V
CC.
This pin is a power supply input for the A-D converter. Connect this pin to V
SS.
This pin is a reference voltage input for the A-D converter.
P00 to P07
D0 to D7 P10 to P17
D8 to D15
P20 to P27
A0 to A7
A0/D0 to A
7/D7
A0, A1/D0 to A7/D6
P30 to P37 A8 to A15
A8/D7, A
9 to A15
P40 to P47
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
Input/output
Input/output Input/output
Input/output
Input/output Output Input/output
Output Input/output
Input/output Output
Input/output Output
Input/output
This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When used for input in single-chip mode, the port can be set to have or not have a pull-up resistor in units of four bits by software. In memory expansion and microprocessor modes, selection of the internal pull-resistor is not available.
When set as a separate bus, these pins input and output data (D
0–D7).
This is an 8-bit I/O port equivalent to P0.
When set as a separate bus, these pins input and output data
(D8–D15).
This is an 8-bit I/O port equivalent to P0. These pins output 8 low-order address bits (A
0–A7).
If the external bus is set as an 8-bit wide multiplexed bus, these pins input and output data (D (A
0–A7) separated in time by multiplexing.
0–D7) and output 8 low-order address bits
If the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (D in time by multiplexing. They also output address (A
0–D6) and output address (A1–A7) separated
0).
This is an 8-bit I/O port equivalent to P0. These pins output 8 middle-order address bits (A
8–A15).
If the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (D by multiplexing. They also output address (A
7) and output address (A8) separated in time 9–A15).
This is an 8-bit I/O port equivalent to P0.
CS
0 to CS3,
A
16 to A19
Output Output
These pins output CS0–CS3 signals and A16–A19. CS0–CS3 are chip select signals used to specify an access space. A
16–A19 are 4 high-
order address bits.
8
Pin Description
Pin Description
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Signal name FunctionPin name I/O type
0 to P57
P5
WRL / WR, WRH / BHE, RD, BCLK, HLDA, HOLD,
ALE, RDY
P60 to P67
P70 to P77
I/O port P5 Input/output
Output Output Output Output Output Input
Output Input
I/O port P6
I/O port P7
Input/output
Input/output
This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in this port outputs a divide-by-8 or divide-by-32 clock of X the same frequency as X
CIN as selected by software.
IN or a clock of
Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE signals. WRL and WRH, and BHE and WR can be switched using software control. WRL, WRH, and RD selected With a 16-bit external data bus, data is written to even addresses when the WRL signal is “L” and to the odd addresses when the WRH signal is “L”. Data is read when RD is “L”. WR, BHE, and RD selected Data is written when WR is “L”. Data is read when RD is “L”. Odd addresses are accessed when BHE is “L”. Use this mode when using an 8-bit external data bus. While the input level at the HOLD pin is “L”, the microcomputer is placed in the hold state. While in the hold state, HLDA outputs a “L” level. ALE is used to latch the address. While the input level of the RDY pin is “L”, the microcomputer is in the ready state.
This is an 8-bit I/O port equivalent to P0. When used for input in single­chip, memory expansion, and microprocessor modes, the port can be set to have or not have a pull-up resistor in units of four bits by software. Pins in this port also function as UART0 and UART1 I/O pins as selected by software.
This is an 8-bit I/O port equivalent to P6 (P7 open-drain output). Pins in this port also function as timer A
0 and P71 are N channel
0–A3 or
UART2 I/O pins as selected by software.
P8
0 to P84,
P8
6,
P87,
5
P8
P90 to P97
P100 to P107
I/O port P8
I/O port P8
I/O port P9
I/O port P10
5
Input/output Input/output
Input/output Input
Input/output
Input/output
P80 to P84, P86, and P87 are I/O ports with the same functions as P6. Using software, they can be made to function as the I/O pins for timer A4 and the input pins for external interrupts. P8
6 and P87 can be set
using software to function as the I/O pins for a sub clock generation circuit. In this case, connect a quartz oscillator between P8 pin) and P8
7 (XCIN pin). P85 is an input-only port that also functions
6 (XCOUT
for NMI. The NMI interrupt is generated when the input at this pin changes from “H” to “L”. The NMI function cannot be cancelled using software. The pull-up cannot be set for this pin.
This is an 8-bit I/O port equivalent to P6. Pins in this port also function as Timer B0–B2 input pins, D-A converter output pins, A-D converter extended input pins, or A-D trigger input pins as selected by software.
This is an 8-bit I/O port equivalent to P6. Pins in this port also function as A-D converter input pins. Furthermore, P10
4–P107 also function as
input pins for the key input interrupt function.
9
Mitsubishi microcomputers
A
A
M16C / 61 Group

Memory

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Operation of Functional Blocks

The M16C/61 group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also included are peripheral units such as timers, serial I/O, D-A converter, DMAC, CRC calculation circuit, A-D converter, and I/O ports. The following explains each unit.
Memory
Figure 1.4.1 is a memory map of the M16C/61 group. The address space extends the 1M bytes from address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30612M4A-XXXFP, there is 32K bytes of internal ROM from F800016 to FFFFF16. The vector table for fixed interrupts such as the reset and NMI are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts for details. From 0040016 up is RAM. For example, in the M30612M4A-XXXFP, 4K bytes of internal RAM is mapped to the space from 0040016 to 013FF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated. The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for periph­eral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Any part of the SFR area that is not occupied is reserved and cannot be used for other purposes. The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps. In memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be used. For example, in the M30612M4A-XXXFP, the following spaces cannot be used.
• The space between 0140016 and 03FFF16
• The space between D000016 and F7FFF16 (When external area do not expand in memory expansion
mode) Do not expand the external area in single chip mode. A part of internal memory cannot be used depending on MCU.
_______
Type No. Address YYYYY M30610M8A M30610MAA M30610MCA/EC M30612M4A/E4 M30612M8A M30612MAA M30612MCA
Address XXXXX
02BFF 02BFF 02BFF 013FF 013FF 013FF 017FF
Figure 1.4.1. Memory map
10
00000
16
00400
XXXXX
04000
16
F0000 E8000 E0000
F8000
F0000 E8000 E0000
16
16
D0000
16 16 16 16 16 16
16
YYYYY
FFFFF
Note 1: During memory expansion and microprocessor modes, can not be used. Note 2: When external area do not expand in memory expansion mode.
16 16 16 16 16 16 16 16
SFR area
For details, see Figure
1.7.1 and Figure 1.7.2
16
Internal RAM area
16
Internal reserved
area (Note 1)
AAA
External area
AAA
Internal reserved
area (Note 2)
16
Internal ROM area
16
FFE00
FFFDC
FFFFF
16
Special page
vector table
16
Undefined instruction
BRK instruction
Address match
Single step
Watchdog timer
16
Overflow
DBC NMI
Reset
Mitsubishi microcomputers
A
M16C / 61 Group
CPU
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Central Processing Unit (CPU)

The CPU has a total of 13 registers shown in Figure 1.5.1. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks.
R0
R1
R2
R3
A0
A1
FB
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
b15
b15
b15
b15
b15
b15
b15
b8 b7 b0
H
b8 b7 b0
H
L
b19
L
PC
b0
Program counter
Data
b0
registers
INTB
b19
H
b0
L
Interrupt table register
b0
b0
b15
USP
b15
ISP
b0
User stack pointer
b0
Interrupt stack pointer
Address
b0
b0
registers
Frame base registers
SB
FLG
b15
b15
b0
Static base register
b0
Flag register
IPL
CDZSBOIU
Note: These registers consist of two register banks.
Figure 1.5.1. Central processing unit register
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32-bit data registers (R2R0/R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
11
Mitsubishi microcomputers
M16C / 61 Group
CPU
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config­ured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.5.2 shows the flag register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt. When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt. An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0” when the interrupt is acknowledged.
“1”
when an arithmetic operation resulted in a negative value; otherwise, cleared to
“0”
.
12
Mitsubishi microcomputers
M16C / 61 Group
CPU
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected when this flag is “1”. This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
IPL
b0b15
Flag register (FLG)
CDZSBOIU
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Figure 1.5.2. Flag register (FLG)
13
Mitsubishi microcomputers
M16C / 61 Group

Reset

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset. (See “Software Reset” for details of software resets.) This section explains on hardware resets. When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H” level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. Figure 1.6.1 shows the example reset circuit. Figure 1.6.2 shows the reset sequence.
RESET
Example when V
V
CC
Figure 1.6.1. Example reset circuit
X
IN
More than 20 cycles are needed
Microprocessor
mode BYTE = “H”
RESET
BCLK
Address
RD
BCLK 24cycles
CC
= 5V
5V
V
CC
0V
5V
RESET
0V
4.0V
0.8V
.
Content of reset vector
FFFFC
16
FFFFD
16
FFFFE
16
WR
CS0
Microprocessor
mode BYTE = “L”
Address
RD
WR
CS0
Single chip
mode
Address
Figure 1.6.2. Reset sequence
14
FFFFC
FFFFC
16
16
FFFFE
FFFFE
16
Content of reset vector
16
Content of reset vector
Reset
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.6.1 shows the statuses of the other pins while the RESET pin level is “L”. Figure 1.6.3 shows the
____________
internal status of the microcomputer immediately after the reset is cancelled.
Table 1.6.1. Pin status when RESET pin level is “L”
____________
Status
Pin name
P0
P1 P2, P3, P4 P44 P45 to P47 P50 P51 P52 P53
0 to P43
CNVSS = VSS
Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating)
BYTE = VSS BYTE = VCC Data input (floating) Data input (floating) Address output (undefined) CS0 output (“H” level is output) Input port (floating)
WR output (“H” level is output) BHE output (undefined) RD output (“H” level is output) BCLK output
CNVSS = VCC
Data input (floating)
Input port (floating) Address output (undefined) CS0 output (“H” level is output) Input port (floating) WR output (“H” level is output) BHE output (undefined) RD output (“H” level is output) BCLK output
P54
P55 P56 P57
P6, P7, P80 to P84,
6, P87, P9, P10
P8
Input port (floating)
Input port (floating) Input port (floating) Input port (floating)
Input port (floating)
HLDA output (The output value depends on the input to the HOLD pin)
HOLD input (floating) ALE output (“L” level is output) RDY input (floating)
Input port (floating) Input port (floating)
HLDA output (The output value depends on the input to the HOLD pin)
HOLD input (floating) ALE output (“L” level is output) RDY input (floating)
15
Reset
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Processor mode register 0 (Note) (2) Processor mode register 1 (3) System clock control register 0 (4) System clock control register 1 (5) Chip select control register (6) Address match interrupt enable register (7) Protect register (8) Watchdog timer control register (9) Address match interrupt register 0
(10)Address match interrupt register 1
(11)DMA0 control register (12)DMA1 control register
Bus collision detection interrupt control
(13)
register
(14)DMA0 interrupt control register (15)DMA1 interrupt control register (16)Key input interrupt control register (17)A-D conversion interrupt control register (18)UART2 transmit interrupt control register (19)UART2 receive interrupt control register (20)UART0 transmit interrupt control register (21)UART0 receive interrupt control register (22)UART1 transmit interrupt control register (23)UART1 receive interrupt control register (24)Timer A0 interrupt control register (25)Timer A1 interrupt control register (26)Timer A2 interrupt control register (27)Timer A3 interrupt control register (28)Timer A4 interrupt control register (29)Timer B0 interrupt control register (30)Timer B1 interrupt control register (31)Timer B2 interrupt control register (32)INT0 interrupt control register (33)INT1 interrupt control register (34)INT2 interrupt control register (35)UART2 transmit/receive mode register (36)UART2 transmit/receive control register 0 (37)UART2 transmit/receive control register 1 (38)Count start flag (39)
One-shot start flag(40) Trigger select flag
(41)
Up-down flag(42)
(0004 (0005 (0006 (0007 (0008 (0009 (000A (000F (0010 (0011 (0012 (0014 (0015 (0016 (002C (003C (004A (004B (004C (004D (004E (004F (0050 (0051 (0052 (0053 (0054 (0055 (0056 (0057 (0058 (0059 (005A (005B (005C (005D (005E (005F (0378 (037C (037D (0380 (0381 (0382 (0383 (0384
16)···
16)···
00
16)···
0000100
1
16)···
00010000
16)···
00000010
16)···
16)···
16)···
00?0????
16)···
16)···
16)···
16)···
16)···
16)···
16)···
0000?00
0
16)···
00000?00
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···Clock prescaler reset flag
0
16)···
0
000000
16)···
16)···
00 00 00
16
00
0016 0016
0 0016 0016
0
?
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 000
? 000
? 000 0016
0016
0016 0016
0
0
0
0 0 0
0 0 0
0 0 0
00000001 01000000
Timer A0 mode register(43)
0
Timer A1 mode register(44) Timer A2 mode register
(45)
Timer A3 mode register(46)
(47) 0 0
Timer B0 mode register(48) Timer B1 mode register(49) Timer B2 mode register(50) UART0 transmit/receive mode register(51) UART0 transmit/receive control register 0(52) UART0 transmit/receive control register 1(53) UART1 transmit/receive mode register(54) UART1 transmit/receive control register 0(55) UART1 transmit/receive control register 1(56) UART transmit/receive control register 2(57) DMA0 cause select register(58) DMA1 cause select register(59) A-D control register 2(60) A-D control register 0(61) A-D control register 1(62) D-A control register(63) Port P0 direction register(64) Port P1 direction register(65) Port P2 direction register(66) Port P3 direction register(67) Port P4 direction register(68) Port P5 direction register(69) Port P6 direction register(70) Port P7 direction register(71) Port P8 direction register(72) Port P9 direction register(73) Port P10 direction register(74) Pull-up control register 0(75) Pull-up control register 1(76) Pull-up control register 2(77) Data registers (R0/R1/R2/R3)(78) Address registers (A0/A1)(79) Frame base register (FB)(80) Interrupt table register (INTB)(81) User stack pointer (USP)(82) Interrupt stack pointer (ISP)(83) Static base register (SB)(84)
(85)
Flag register (FLG)
x : Nothing is mapped to this bit
? : Undefined
(0396 (0397 (0398 (0399 (039A (039B (039C (039D (03A0 (03A4 (03A5
(03A8 (03AC (03AD
(03B0
(03B8 (03BA
(03D4
(03D6
(03D7 (03DC
(03E2
(03E3
(03E6
(03E7 (03EA (03EB (03EE
(03EF
(03F2
(03F3
(03F6 (03FC (03FD
(03FE
16)···
16)···
16)···
16)···
16)···Timer A4 mode register
16)···
0
0? 0000
16)···
00? 0000
16)···
00? 0000
16)···
16)···
000 1000
16)···
000 0010
16)···
16)···
000 1000
16)···
000 0010
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
16)···
000000
0
0000 000 0???0
00 00000
000016 000016 000016
0000016
000016 000016 000016 000016
0016 0016 0016 0016 0016
0016 0 0 0016 0 0
0016 0016
0
0016 0016 0016 0016 0016 0016 0016 0016 0016 0016
0016 0016 0016 0016 0016
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Note: When the V
CC level is applied to the CNVSS pin, it is 0316 at a reset.
Figure 1.6.3. Device's internal status after a reset is cleared
16
SFR
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
000016 000116 000216 000316 000416
Processor mode register 0 (PM0)
000516
Processor mode register 1(PM1)
000616
System clock control register 0 (CM0)
000716
System clock control register 1 (CM1)
000816
Chip select control register (CSR)
000916
Address match interrupt enable register (AIER)
000A16
Protect register (PRCR)
000B16 000C16 000D16 000E16
Watchdog timer start register (WDTS)
000F16
Watchdog timer control register (WDC)
001016 001116
Address match interrupt register 0 (RMAD0)
001216 001316 001416 001516
Address match interrupt register 1 (RMAD1)
001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16
002016
DMA0 source pointer (SAR0)
002116 002216 002316 002416
DMA0 destination pointer (DAR0)
002516 002616 002716 002816
DMA0 transfer counter (TCR0)
002916 002A16 002B16 002C16
DMA0 control register (DM0CON)
002D16 002E16 002F16 003016
DMA1 source pointer (SAR1)
003116 003216 003316 003416
DMA1 destination pointer (DAR1)
003516 003616 003716 003816
DMA1 transfer counter (TCR1)
003916 003A16 003B16 003C16
DMA1 control register (DM1CON)
003D16 003E16 003F16
004016 004116 004216 004316 004416 004516 004616 004716 004816 004916
Bus collision detection interrupt control register (BCNIC)
004A16
DMA0 interrupt control register (DM0IC)
004B16
DMA1 interrupt control register (DM1IC)
004C16
Key input interrupt control register (KUPIC)
004D16
A-D conversion interrupt control register (ADIC)
004E16
UART2 transmit interrupt control register (S2TIC)
004F16
UART2 re c e ive in terru p t c o n trol re g iste r (S 2 RIC)
005016
UART0 transmit interrupt control register (S0TIC)
005116
UART0 re c e ive in terru p t c o n trol re g iste r (S 0 RIC)
005216
UART1 transmit interrupt control register (S1TIC)
005316
UART1 re c e ive in terru p t c o n trol re g iste r (S 1 RIC)
005416
Timer A0 interrupt control register (TA0IC)
005516
Timer A1 interrupt control register (TA1IC)
005616
Timer A2 interrupt control register (TA2IC)
005716
Timer A3 interrupt control register (TA3IC)
005816
Timer A4 interrupt control register (TA4IC)
005916
Timer B0 interrupt control register (TB0IC)
005A16
Timer B1 interrupt control register (TB1IC)
005B16
Timer B2 interrupt control register (TB2IC)
005C16
INT0 interrupt control register (INT0IC)
005D16
INT1 interrupt control register (INT1IC)
005E16
INT2 interrupt control register (INT2IC)
005F16
036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816
UART2 transmit/receive mode register (U2MR)
037916
UART2 bit rate generator (U2BRG)
037A16
UART2 transmit buffer register (U2TB)
037B16 037C16
UART2 transmit/receive control register 0 (U2C0)
037D16
UART2 transmit/receive control register 1 (U2C1)
037E16
UART2 receive buffer register (U2RB)
037F16
Figure 1.7.1. Location of peripheral unit control registers
17
SFR
0380
16
Count start flag (TABSR)
0381
16
Clock prescaler reset flag (CPSRF)
0382
16
One-shot start flag (ONSF)
0383
16
Trigger select register (TRGSR)
0384
16
Up-down flag (UDF)
0385
16
0386
16
Timer A0 (TA0)
0387
16
0388
16
Timer A1 (TA1)
0389
16
038A
16
Timer A2 (TA2)
038B
16
038C
16
Timer A3 (TA3)
038D
16
038E
16
Timer A4 (TA4)
038F
16
0390
16
Timer B0 (TB0)
0391
16
0392
16
Timer B1 (TB1)
0393
16
0394
16
Timer B2 (TB2)
0395
16
0396
16
Timer A0 mode register (TA0MR)
0397
16
Timer A1 mode register (TA1MR)
0398
16
Timer A2 mode register (TA2MR)
0399
16
Timer A3 mode register (TA3MR)
039A
16
Timer A4 mode register (TA4MR)
039B
16
Timer B0 mode register (TB0MR)
039C
16
Timer B1 mode register (TB1MR)
039D
16
Timer B2 mode register (TB2MR)
039E
16
039F
16
03A0
16
UART0 transmit/receive mode register (U0MR)
03A1
16
UART0 bit rate generator (U0BRG)
03A2
16
UART0 transmit buffer register (U0TB)
03A3
16
03A4
16
UART0 transmit/receive control register 0 (U0C0)
03A5
16
UART0 transmit/receive control register 1 (U0C1)
03A6
16
UART0 receive buffer register (U0RB)
03A7
16
03A8
16
UART1 transmit/receive mode register (U1MR)
03A9
16
UART1 bit rate generator (U1BRG)
03AA
16
UART1 transmit buffer register (U1TB)
03AB
16
03AC
16
UART1 transmit/receive control register 0 (U1C0)
03AD
16
UART1 transmit/receive control register 1 (U1C1)
03AE
16
UART1 receive buffer register (U1RB)
03AF
16
03B0
16
UART transmit/receive control register 2 (UCON)
03B1
16
03B2
16
03B3
16
03B4
16
03B5
16
03B6
16
03B7
16
03B8
16
DMA0 cause select register (DM0SL)
03B9
16
03BA
16
DMA1 cause select register (DM1SL)
03BB
16
03BC
16
CRC data register (CRCD)
03BD
16
03BE
16
CRC input register (CRCIN)
03BF
16
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
03C0
16
A-D register 0 (AD0)
03C1
16
03C2
16
A-D register 1 (AD1)
03C3
16
03C4
16
A-D register 2 (AD2)
03C5
16
03C6
16
A-D register 3 (AD3)
03C7
16
03C8
16
A-D register 4 (AD4)
03C9
16
03CA
16
A-D register 5 (AD5)
03CB
16
03CC
16
A-D register 6 (AD6)
03CD
16
03CE
16
A-D register 7 (AD7)
03CF
16
03D0
16
03D1
16
03D2
16
03D3
16
03D4
16
A-D control register 2 (ADCON2)
03D5
16
03D6
16
A-D control register 0 (ADCON0)
03D7
16
A-D control register 1 (ADCON1)
03D8
16
D-A register 0 (DA0)
03D9
16
03DA
16
D-A register 1 (DA1)
03DB
16
03DC
16
D-A control register (DACON)
03DD
16
03DE
16
03DF
16
03E0
16
Port P0 (P0)
03E1
16
Port P1 (P1)
03E2
16
Port P0 direction register (PD0)
03E3
16
Port P1 direction register (PD1)
03E4
16
Port P2 (P2)
03E5
16
Port P3 (P3)
03E6
16
Port P2 direction register (PD2)
03E7
16
Port P3 direction register (PD3)
03E8
16
Port P4 (P4)
03E9
16
Port P5 (P5)
03EA
16
Port P4 direction register (PD4)
03EB
16
Port P5 direction register (PD5)
03EC
16
Port P6 (P6)
03ED
16
Port P7 (P7)
03EE
16
Port P6 direction register (PD6)
03EF
16
Port P7 direction register (PD7)
03F0
16
Port P8 (P8)
03F1
16
Port P9 (P9)
03F2
16
Port P8 direction register (PD8)
03F3
16
Port P9 direction register (PD9)
03F4
16
Port P10 (P10)
03F5
16
03F6
16
Port P10 direction register (PD10)
03F7
16
03F8
16
03F9
16
03FA
16
03FB
16
03FC
16
Pull-up control register 0 (PUR0)
03FD
16
Pull-up control register 1 (PUR1)
03FE
16
Pull-up control register 2 (PUR2)
03FF
16
Mitsubishi microcomputers
M16C / 61 Group
Figure 1.7.2. Location of peripheral unit control registers
18
Mitsubishi microcomputers
M16C / 61 Group

Software Reset

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal RAM are preserved.

Processor Mode

(1) Types of Processor Mode
One of three processor modes can be selected: single-chip mode, memory expansion mode, and micro­processor mode. The functions of some pins, the memory map, and the access space differ according to the selected processor mode.
• Single-chip mode
In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be accessed. Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal peripheral functions.
• Memory expansion mode
In memory expansion mode, external memory can be accessed in addition to the internal memory space (SFR, internal RAM, and internal ROM). In this mode, some of the pins function as the address bus, the data bus, and as control signals. The number of pins assigned to these functions depends on the bus and register settings. (See “Bus Settings” for details.)
• Microprocessor mode
In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. The internal ROM area cannot be accessed. In this mode, some of the pins function as the address bus, the data bus, and as control signals. The number of pins assigned to these functions depends on the bus and register settings. (See “Bus Settings” for details.)
(2) Setting Processor Modes
The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address
000416). Do not set the processor mode bits to “102”. Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore, never change the processor mode bits when changing the contents of other bits. Also do not attempt to shift to or from the microprocessor mode within the program stored in the internal ROM area.
• Applying VSS to CNVSS pin
The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode is selected by writing “012” to the processor mode is selected bits.
• Applying VCC to CNVSS pin
The microcomputer starts to operate in microprocessor mode after being reset. Figure 1.8.1 shows the processor mode register 0 and 1. Figure 1.9.1 shows the memory maps appli­cable for each of the modes.
19
Processor Mode
Processor mode register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset PM0 0004
16
00
16
(Note 2)
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
WR
PM00
PM01
PM02
PM03
PM04
PM05
PM06
PM07
Bit name FunctionBit symbol
Processor mode bit
R/W mode select bit
Software reset bit
Multiplexed bus space select bit
Port P40 to P43 function select bit (Note 3)
BCLK output disable bit
b1 b0
0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Inhibited 1 1: Microprocessor mode
0 : RD,BHE,WR 1 : RD,WRH,WRL
The device is reset when this bit is set to “1”. The value of this bit is “0” when read.
b5 b4
0 0 : Multiplexed bus is not used 0 1 : Allocated to CS2 space 1 0 : Allocated to CS1 space 1 1 : Allocated to entire space (Note4)
0 : Address output 1 : Port function (Address is not output)
0 : BCLK is output 1 : BCLK is not output (Pin is left floating)
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new
values to this register.
Note 2: If the V
CC
reset is 03
voltage is applied to the CNVSS, the value of this register when
16.
(PM00 and PM01 both are set to “1”.) Note 3: Valid in microprocessor and memory expansion modes. Note 4: If the entire space is of multiplexed bus in memory expansion mode, choose
an 8-bit width.The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select.
Processor mode register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol Address When reset PM1 0005
0
Bit name FunctionBit symbol
Reserved bit
Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Reserved bit
PM16
PM17
External memory area expansion bit (Note 2)
Wait bit
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing
new values to this register.
Note 2: When this bit is set to “1” in memory expansion mode, M30612M4A/E4
provides the means of using part of internal reserved area as an external area. Set this bit to “0” except M30612M4A/E4. Set this bit to “0” in single chip mode.
Figure 1.8.1. Processor mode register 0 and 1
16
00XXXXX0
2
Must always be set to “0”
Must always be set to “0”
0 : Do not expand 1 : Expand
0 : No wait state 1 : Wait state inserted
WR
20
Processor Mode
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
00000
16
0040016
XXXXX16
0400016
D000016
YYYYY16
FFFFF16
Type No.
M30610M8A
M30610MCA/EC M30612M4A/E4 M30612M8A M30612MAA M30612MCA
Single-chip mode
SFR area
Internal RAM
area
Inhibited
Internal ROM area (Note 2)
Address
16
XXXXX
Address
YYYYY F0000 E80001602BFF16M30610MAA E00001602BFF16 F8000 F0000 E8000 E000016017FF16
Memory expansion mode
SFR area
Internal RAM
area
Internally
reserved area
External area
Internally reserved
area (Note 1)
Internal ROM
area
External area : Accessing this area allows the user to
16
1602BFF16
16013FF16 16013FF16
16013FF16
Note 1: This area becomes external area when PM16 (external
memory area expansion bit ) = “1” in M30612M4A/E4. Set “0” except M30612M4A/E4.
Note 2: Set “0” to PM16 (external memory area expansion bit)
in single chip mode.
Microprocessor mode
SFR area
Internal RAM
area
Internally
reserved area
External area
access a device connected externally to the microcomputer.
Figure 1.9.1. Memory maps in each processor mode
21
Mitsubishi microcomputers
M16C / 61 Group

Bus Settings

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Settings
The BYTE pin and bits 4 to 6 of the processor mode register 0 (address 000416) are used to change the bus settings. Table 1.10.1 shows the factors used to change the bus settings.
Table 1.10.1. Factors for switching bus settings
Bus setting Switching factor Switching external address bus width Bit 6 of processor mode register 0 Switching external data bus width BYTE pin Switching between separate and multiplex bus Bits 4 and 5 of processor mode register 0
(1) Selecting external address bus width
The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K bytes address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register 0 is set to “1”, the external address bus width is set to 16 bits, and P2 and P3 become part of the address bus. P40 to P43 can be used as programmable I/O ports. When bit 6 of processor mode register 0 is set to “0”, the external address bus width is set to 20 bits, and P2, P3, and P40 to P43 become part of the address bus.
(2) Selecting external data bus width
The external data bus width can be set to 8 or 16 bits. (Note, however, that only the separate bus can be set.) When the BYTE pin is “L”, the bus width is set to 16 bits; when “H”, it is set to 8 bits. (The internal bus width is permanently set to 16 bits.) While operating, fix the BYTE pin either to “H” or to “L”.
(3) Selecting separate/multiplex bus
The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0.
• Separate bus
In this mode, the data and address are input and output separately. The data bus can be set using the BYTE pin to be 8 or 16 bits. When the BYTE pin is “H”, the data bus is set to 8 bits and P0 functions as the data bus and P1 as a programmable I/O port. When the BYTE pin is “L”, the data bus is set to 16 bits and P0 and P1 are both used for the data bus. When the separate bus is used for access, a software wait can be selected.
• Multiplex bus
In this mode, data and address I/O are time multiplexed. With an 8-bit data bus selected (BYTE pin = “H”), the 8 bits from D0 to D7 are multiplexed with A0 to A7. With a 16-bit data bus selected (BYTE pin = “L”), the 8 bits from D0 to D7 are multiplexed with A1 to A8. D8 to D15 are not multiplexed. In this case, the external devices connected to the multiplexed bus are mapped to the microcomputer’s even addresses (every 2nd address). To access these external de­vices, access the even addresses as bytes. The ALE signal latches the address. It is output from P56. Before using the multiplex bus for access, be sure to insert a software wait. If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width. The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select.
22
Bus Settings
P00 to P0
7
I/O port Data bus Data bus Data bus Data bus I/O port
Either CS1 or CS2 is for multiplexed bus and others are for separate bus
(separate bus)
multiplexed
bus for the
entire space
Single-chip
mode
Memory expansion mode/microprocessor modes
Memory
expansion mode
Data bus width BYTE pin level
Port P40 to P4
3
function select bit = 0
“01”, “10” “00”
“11” (Note 1)
8 bit
“H”
8 bits
“H”
16 bits
“L”
8 bits
“H”
16 bits
“L”
Note 1: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width.
The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode.
The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select. Note 2: Address bus when in separate bus mode.
Processor mode
Multiplexed bus space select bit
CS (chip select) or programmable I/O port
(For details, refer to “Bus control”)
Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK
(For details, refer to “Bus control”)
Port P40 to P4
3
function select bit = 1
P1
0
to P1
7
I/O port I/O port Data bus I/O port Data bus I/O port
P2
1
to P2
7
I/O port
Address bus Address bus
Address bus Address bus Address bus
/data bus
(Note 2)
/data bus
(Note 2)
/data bus
P2
0
I/O port
Address bus
Address bus Address bus Address bus Address bus
/data bus
(Note 2)
/data bus
P3
0
I/O port Address bus
Address bus
Address bus Address bus A8/D
7
/data bus
(Note 2)
P31 to P3
7
I/O port Address bus Address bus Address bus Address bus I/O port
P4
0
to P4
3
I/O port I/O port I/O port /O port I/O port I/O port
P4
0
to P4
3
I/O port Address bus Address bus Address bus Address bus I/O port
P4
4
to P4
7
I/O port
P5
0
to P5
3
I/O port
P5
4
I/O port HLDA HLDA HLDA HLDA HLDA
P5
5
I/O port HOLD HOLD HOLD HOLD HOLD
P5
6
I/O port ALE ALE ALE ALE ALE
P5
7
I/O port RDY RDY RDY RDY RDY
Table 1.10.2. Pin functions for each processor mode
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
23
Mitsubishi microcomputers
M16C / 61 Group

Bus Control

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
The following explains the signals required for accessing external devices and software waits. The signals required for accessing the external devices are valid when the processor mode is set to memory expansion mode and microprocessor mode. The software waits are valid in all processor modes.
(1) Address bus/data bus
The address bus consists of the 20 pins A0 to A19 for accessing the 1M bytes of address space. The data bus consists of the pins for data I/O. When the BYTE pin is “H”, the 8 ports D0 to D7 function as the data bus. When BYTE is “L”, the 16 ports D0 to D15 function as the data bus. Both the address and data bus retain their previous states when internal ROM or RAM is accessed. Also, when a change is made from single-chip mode to memory expansion mode, the value of the address bus is undefined until external memory is accessed.
(2) Chip select signal
The chip select signal is output using the same pins as P4 4 to P47. Bits 0 to 3 of the chip select control register (address 000816) set each pin to function as a port or to output the chip select signal. The chip select control register is valid in memory expansion mode and microprocessor mode. In single-chip mode, P44 to P47 function as programmable I/O ports regardless of the value in the chip select control register. In microprocessor mode, only CS0 outputs the chip select signal after the reset state has been cancelled.
_______ _______ _______ _______
CS1 to CS3 function as input ports. Therefore, when using CS1 to CS3, external pull-up resistors are required. Figure 1.11.1 shows the chip select control register. The chip select signal can be used to split the external area into as many as four blocks. Table 1.11.1 shows the external memory areas specified using the chip select signal.
_______
Table 1.11.1. External areas specified by the chip select signals
Chip select
CS0 CS1
CS2 CS3
Memory expansion mode Microprocessor mode
30000
16
to CFFFF16(640K)
30000
16
to F7FFF 2800016 to 2FFFF 08000
16
to 27FFF16(128K)
16
04000
to 07FFF
16 16
16
Specified address range
(800K)
(Note)
(32K)
(16K)
30000 28000
08000 04000
16
to FFFFF16(832K)
16
to 2FFFF16(32K)
16
to 27FFF16(128K)
16
to 07FFF
16
(16K)
Note: When PM16 (External memory area expansion bit) = “1”. (Only M30612M4A/E4 is valid.)
Chip select control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset CSR 0008
Bit symbol
CS0 CS1 CS2 CS3 CS0W CS1W CS2W CS3W
Bit name
CS0 output enable bit CS1 output enable bit CS2 output enable bit CS3 output enable bit
CS0 wait bit CS1 wait bit CS2 wait bit CS3 wait bit
16
01
16
0 : Chip select output disabled
(Normal port pin)
1 : Chip select output enabled
0 : Wait state inserted 1 : No wait state
Function
R
W
Figure 1.11.1. Chip select control register
24
Mitsubishi microcomputers
M16C / 61 Group
Bus Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Read/write signals
With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 000416) select the combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE pin = “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0 (address 000416) to “0”.) Tables 1.11.2 and 1.11.3 show the operation of these signals. After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected. When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the processor mode register 0 (address 000416) has been set (Note).
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
_____ ________ ______ _____ ________ _________
_____ ______ _______
_____ ______ ________
_____ _________ _________
Table 1.11.2. Operation of RD, WRL, and WRH signals
_____ ________ _________
Data bus width
16-bit
(BYTE = “L”)
L H H H
_____ ______ ________
H
L
H
L
WRHWRLRD
H H
L L
Read data Write 1 byte of data to even address Write 1 byte of data to odd address Write data to both even and odd addresses
Status of external data bus
Table 1.11.3. Operation of RD, WR, and BHE signals
Data bus width A0
16-bit
(BYTE = “L”)
RD
BHEWR
HLL
LHL
HLH
LHH
H H
HLLL
LHLL
8-bit
(BYTE = “H”)
HL H / L
LH H / L
Not used Not used
Write 1 byte of data to odd address
Read 1 byte of data from odd address L L
Write 1 byte of data to even address
Read 1 byte of data from even address
Write data to both even and odd addresses Read data from both even and odd addresses Write 1 byte of data Read 1 byte of data
Status of external data bus
(4) ALE signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the ALE signal falls.
When BYTE pin = “H”
ALE
D
0/A0
to D7/A
A8 to A
7
19
Address Data (Note 1)
Address (Note 2)
Note 1: Floating when reading. Note 2: When multiplexed bus for the entire space is selected, these are I/O ports.
Figure 1.11.2. ALE signal and address/data bus
When BYTE pin = “L”
ALE
0/A1
to D7/A
D
A9 to A
0
A
8
19
Address Data (Note 1)
Address
Address
25
Mitsubishi microcomputers
M16C / 61 Group
Bus Control
________
(5) The RDY signal
________
RDY is a signal that facilitates access to an external device that requires long access time. As shown in Figure 1.11.3, if an “L” is being input to the RDY at the BCLK falling edge, the bus turns to the wait state.
________
If an “H” is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state. Table
1.11.4 shows the state of the microcomputer with the bus in the wait state, and Figure 1.11.3 shows an example in which the RD signal is prolonged by the RDY signal.
________
____ ________
The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the chip select control register (address 000816) are set to “0”. The RDY signal is invalid when setting “1” to all bits 4 to 7 of the chip select control register (address 000816), but the RDY pin should be treated as properly as in non-using.
Table 1.11.4. Microcomputer status in ready state (Note)
Item Status
Oscillation On
___ _____
R/W signal, address bus, data bus, CS
__________
ALE signal, HLDA, programmable I/O ports Internal peripheral circuits On
________
Note: The RDY signal cannot be received immediately prior to a software wait.
________
Maintain status when RDY signal received
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
________
________
________
In an instance of separate bus
BCLK
RD
CS
i
(i=0 to 3)
RDY
Accept timing of RDY signal
In an instance of multiplexed bus
BCLK
RD
CS
i
(i=0 to 3)
RDY
: Wait using RDY signal
: Wait using software
tsu(RDY - BCLK)
tsu(RDY - BCLK)
Accept timing of RDY signal
Figure 1.11.3. Example of RD signal extended by RDY signal
_____ ________
26
Mitsubishi microcomputers
M16C / 61 Group
Bus Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(6) Hold signal
The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L” to
__________
the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status
__________ __________
is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table 1.11.5 shows the microcomputer status in the hold state.
__________
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence.
__________
HOLD > DMAC > CPU
Figure 1.11.4. Bus-using priorities
Table 1.11.5. Microcomputer status in hold state
Item Status
Oscillation ON
___ _____ _______
R/W signal, address bus, data bus, CS, BHE Floating Programmable I/O ports P0, P1, P2, P3, P4, P5 Floating
__________
HLDA Output “L” Internal peripheral circuits ON (but watchdog timer stops) ALE signal Undefined
P6, P7, P8, P9, P10 Maintains status when hold signal is received
(7) External bus status when the internal area is accessed
Table 1.11.6 shows the external bus status when the internal area is accessed.
Table 1.11.6. External bus status when the internal area is accessed
Item SFR accessed Internal ROM/RAM accessed Address bus Address output Maintain status before accessed
address of external area
Data bus When read Floating Floating
When write Output data Undefined RD, WR, WRL, WRH RD, WR, WRL, WRH output Output "H" BHE BHE output Maintain status before accessed
status of external area CS Output "H" Output "H" ALE Output "L" Output "L"
27
Mitsubishi microcomputers
M16C / 61 Group
Bus Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(8) BCLK output
The user can choose the BCLK output by use of bit 7 of processor mode register 0 (000416) (Note). When set to “1”, the output floating.
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
(9) Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
000516) (Note) and bits 4 to 7 of the chip select control register (address 000816). A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle. When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been reset, this bit defaults to “0”. When cycles), regardless of the contents of bits 4 to 7 of the chip select control register to the recommended operating conditions (main clock input oscillation frequency) of the electric character­istics.
However, when the user is using the RDY signal, the relevant bit in the chip select control register’s bits 4 to 7 must be set to “0”. When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for each of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register
_______ _______
correspond to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed in one BCLK cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bits default to “0” after the microcomputer has been reset. The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also, insert a software wait if using the multiplex bus to access the external memory area. Table 1.11.7 shows the software wait and bus cycles. Figure 1.11.5 shows example bus timing when using software waits.
set to “1”, a wait is applied to all memory areas (two or three BCLK
. Set this bit after referring
________
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to “1”.
Table 1.11.7. Software waits and bus cycles
Area Bus status Wait bit
SFR
Internal
ROM/RAM
Separate bus
External
memory
area
Note: When using the RDY signal, always set to “0”.
Separate bus Separate bus
Multiplex bus 0 0 3 BCLK cycles Multiplex bus
Invalid Invalid 2 BCLK cycles
0 Invalid 1 BCLK cycle
0 1 1 BCLK cycle 0 0 2 BCLK cycles
1 0 (Note) 2 BCLK cycles
1 3 BCLK cycles0 (Note)
Bits 4 to 7 of chip select
control register
Invalid1 2 BCLK cycles
Bus cycle
28
Bus Control
Mitsubishi microcomputers
M16C / 61 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
< Separate bus (no wait) >
BCLK
Write signal
Read signal
Data bus
Address bus
Chip select
< Separate bus (with wait) >
BCLK
Write signal
Bus cycle
Address
Bus cycle
Output
Input
Address
Read signal
Data bus
Address bus
Chip select
< Multiplexed bus >
Write signal
Read signal
Address bus
Address bus/ Data bus
BCLK
ALE
Address
Address
Bus cycle
Address
Data output
Output
Address
Input
Address
Address
Input
Chip select
Figure 1.11.5. Typical bus timings using software wait
29
Mitsubishi microcomputers
M16C / 61 Group

Clock Generating Circuit

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units.
Table 1.12.1. Main clock and sub-clock generating circuits
Main clock generating circuit Sub-clock generating circuit
Use of clock • CPU’s operating clock source • CPU’s operating clock source
• Internal peripheral units’ • Timer A/B’s count clock
operating clock source source Usable oscillator Ceramic or crystal oscillator Crystal oscillator Pins to connect oscillator XIN, XOUT XCIN, XCOUT Oscillation stop/restart function Available Available Oscillator status immediately after reset Other Externally derived clock can be input
Oscillating Stopped

Example of oscillator circuit

Figure 1.12.1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Figure 1.12.2 shows some examples of sub-clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Circuit constants in Figures 1.12.1 and 1.12.2 vary with each oscillator used. Use the values recommended by the manufacturer of your oscillator.
Microcomputer
(Built-in feedback resistor)
X
IN
C
IN
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between X and X
OUT
X
OUT
(Note) R
d
C
OUT
following the instruction.
Figure 1.12.1. Examples of main clock
Microcomputer
(Built-in feedback resistor)
X
IN
Externally derived clock
Vcc Vss
X
OUT
Open
IN
Microcomputer
(Built-in feedback resistor)
X
CIN
C
CIN
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between X and X
COUT
X
COUT
(Note) R
Cd
C
COUT
following the instruction.
Figure 1.12.2. Examples of sub-clock
30
Microcomputer
(Built-in feedback resistor)
X
CIN
Externally derived clock
Vcc Vss
X
COUT
Open
CIN
Loading...
+ 167 hidden pages
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use