Mitsubishi M2V64S30DTP-8L, M2V64S30DTP-8, M2V64S30DTP-7L, M2V64S30DTP-7, M2V64S30DTP-6L Datasheet
...
MITSUBISHI LSIs
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x
1,048,576
-WORD x 16-BIT)
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
FEATURES
ITEM
M2V64S20/30/40DTP
-7
-8
Icc1
Icc6
Active to Precharge Command Period
(Min.)
(Single Bank)
Self Refresh Current
(Max.)
50ns
20ns
6ns
1mA
10ns
V64S20D
V64S30D
-6
45ns
20ns
5.4
ns
1mA
70mA
70mA
80mA
70mA
70mA
80mA
75mA
75mA
85mA
SDRAM (Rev.3.2)
Feb.'00
(4-BANK x 4,194,304-WORD x 4-BIT)
64M Synchronous DRAM
PRELIMINARY
Some of contents are described for general products and are
subject to change without notice.
DESCRIPTION
M2V64S20DTP is a 4-bank x 4,194,304-word x 4-bit,
M2V64S30DTP is a 4-bank x 2,097,152-word x 8-bit,
M2V64S40DTP is a 4-bank x 1,048,576-word x 16-bit,
synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge
of CLK. M2V64S20DTP, M2V64S30DTP and M2V64S40DTP achieve very high speed data rate up
to 133MHz for -6, and are suitable for main memory or graphic memory in computer systems.
tCLK
tRAS
tRCD
tAC
tRC
Clock Cycle Time (Min.)
Row to Column Delay (Min.)
Access Time from CLK (Max.) (CL=3)
Ref /Active Command Period (Min.)
7.5ns
67.5ns
10ns
70ns
50ns
20ns
6ns
70ns
Operation Current (Max.)
V64S40D
- Single 3.3v±0.3V power supply
- Max. Clock frequency -6:133MHz<3-3-3>, -7:100MHz<2-2-2>, -8:100MHz<3-2-2>
- Fully Synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0 & BA1 (Bank Address)
- /CAS latency- 2 and 3 (programmable)
- Burst length- 1, 2, 4, 8 and full page (programmable)
- Burst type- sequential and interleave (programmable)
- Byte Control- DQML and DQMU for M2V64S40DTP
- Random column access
- Auto precharge and All bank precharge controlled by A10
- Auto refresh and Self refresh
- 4096 refresh cycles every 64ms
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
1mA
MITSUBISHI ELECTRIC
1
MITSUBISHI LSIs
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x
1,048,576
-WORD x 16-BIT)
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
CLK
: Master Clock
CKE
: Clock Enable
/CS
: Chip Select
/RAS
: Row Address Strobe
/CAS
: Column Address Strobe
/WE
: Write Enable
DQ0-15
: Data I/O
DQM
: Output Disable/ Write Mask
A0-11
: Address Input
BA0,1
: Bank Address
Vdd
: Power Supply
VddQ
: Power Supply for Output
Vss
: Ground
VssQ
: Ground for Output
SDRAM (Rev.3.2)
Feb.'00
PIN CONFIGURATION (TOP VIEW)
(4-BANK x 4,194,304-WORD x 4-BIT)
64M Synchronous DRAM
M2V64S20DTP
M2V64S30DTP
M2V64S40DTP
PIN CONFIGURATION
(TOP VIEW)
Vdd
NC
VddQ
NC
DQ0
VssQ
NC
NC
VddQ
NC
DQ1
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)
A0
A1
A2
A3
Vdd
Vdd
DQ0
VddQ
NC
DQ1
VssQ
NC
DQ2
VddQ
NC
DQ3
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)
A0
A1
A2
A3
Vdd
Vdd
DQ0
VddQ
DQ1
DQ2
VssQ
DQ3
DQ4
VddQ
DQ5
DQ6
VssQ
DQ7
Vdd
DQML
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)
A0
A1
A2
A3
Vdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23 32
24 31
25 30
26 29
27 28
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Vss
DQ15
VssQ
DQ14
DQ13
VddQ
DQ12
DQ11
VssQ
DQ10
DQ9
VddQ
DQ8
Vss
NC
DQMU
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
Vss
DQ7
VssQ
NC
DQ6
VddQ
NC
DQ5
VssQ
NC
DQ4
VddQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
Vss
NC
VssQ
NC
DQ3
VddQ
NC
NC
VssQ
NC
DQ2
VddQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
MITSUBISHI ELECTRIC
2
MITSUBISHI LSIs
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x
1,048,576
-WORD x 16-BIT)
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
Process Generation
Density
Mitsubishi DRAM
TP: TSOP(II)
D : 5th gen.
SDRAM (Rev.3.2)
Feb.'00
(4-BANK x 4,194,304-WORD x 4-BIT)
64M Synchronous DRAM
BLOCK DIAGRAM
Memory Array
4096 x512 x8
Cell Array
Bank #0
Mode
Register
Address Buffer
Memory Array
4096 x512 x8
Cell Array
Bank #1
DQ0-7
I/O Buffer
Memory Array
4096 x512 x8
Cell Array
Control Circuitry
Bank #2
Control Signal Buffer
Memory Array
4096 x512 x8
Cell Array
Bank #3
A0-11
Note : This figure shows the M2V64S30DTP.
The M2V64S20DTP configration is 4096x1024x4 of cell array and DQ 0-3.
The M2V64S40DTP configration is 4096x256x16 of cell array and DQ 0-15.
Type Designation Code
M2 V 64 S 3 0 TP -8
D
BA0,1
Clock Buffer
CLK CKE
Access Item
Package Type
Function
Organization
Synchronous DRAM
Interface
/CS
These rules are only applied to the Synchronous DRAM family.
/RAS
/CAS
-6 : 7.5ns (PC133 3-3-3),
-7 : 10ns (PC100 2-2-2),
-8 : 10ns (PC100 3-2-2)
Reserved for Future Use
2 : x4, 3 : x8, 4 : x16
64 : 64Mbit
V : LVTTL
/WE
DQM
MITSUBISHI ELECTRIC
3
MITSUBISHI LSIs
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x
1,048,576
-WORD x 16-BIT)
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
PIN FUNCTION
A10 is also used to indicate precharge option. When A10 is high at a
DQM(U, L)(x16)
SDRAM (Rev.3.2)
Feb.'00
(4-BANK x 4,194,304-WORD x 4-BIT)
64M Synchronous DRAM
CLK Input
CKE Input
/CS Input
/RAS, /CAS, /WE Input Combination of /RAS, /CAS, /WE defines basic commands.
A0-11 Input
BA0,1 Input
Master Clock:
All other inputs are referenced to the rising edge of CLK.
Clock Enable:
CKE controls internal clock. When CKE is low, internal clock for the
following cycle is ceased. CKE is also used to select auto /
selfrefresh. After self refresh mode is started, CKE becomes
asynchronous input. Self refresh is maintained as long as CKE is low.
Chip Select:
When /CS is high, any command means No Operation.
A0-11 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-11. The Column Address is
specified by A0-9 (x4) / A0-8 (x8) / A0-7 (x16).
read / write command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
Bank Address:
BA0,1 specifies one of four banks to which a command is applied.
BA0,1 must be set with ACT, PRE, READ, WRITE commands.
DQ0-3(x4),
DQ0-7(x8),
DQ0-15(x16)
DQM(x4,x8),
Vdd, Vss Power Supply Power Supply for the memory array and peripheral circuitry.
VddQ, VssQ Power Supply VddQ and VssQ are supplied to the Output Buffers only.
Input / Output
Input
Data In and Data out are referenced to the rising edge of CLK.
Din Mask and Output Disable:
When DQM(U, L) is high in burst write, Din for the current cycle is
masked. When DQM(U, L) is high in burst read, Dout is disabled at
the next but one cycle.
MITSUBISHI ELECTRIC
4
MITSUBISHI LSIs
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x
1,048,576
-WORD x 16-BIT)
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
BASIC FUNCTIONS
truth table.
precharge,
READA
)
(auto-precharge,
WRITEA
).
/write operation. When A10 =H at this command, all banks are deactivated (precharge all,
PREA
).
command, the banks are precharged automatically.
(4-BANK x 4,194,304-WORD x 4-BIT)
SDRAM (Rev.3.2)
Feb.'00
64M Synchronous DRAM
The M2V64S20, 30 and 40DTP provides basic functions, bank (row) activate, burst read and write, bank
(row) precharge, and auto and self refresh. Each command is defined by control signals of /RAS, /CAS and
/WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option,
and precharge option, respectively. To know the detailed definition of commands, please see the command
CLK
/CS
/RAS
/CAS
/WE
CKE
A10
Chip Select : L=select, H=deselect
Command
Command
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command
define basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address are generated internally. After this
MITSUBISHI ELECTRIC
5
MITSUBISHI LSIs
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x
1,048,576
-WORD x 16-BIT)
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
SDRAM (Rev.3.2)
Feb.'00
COMMAND TRUTH TABLE
COMMAND MNEMONIC
Deselect DESEL H X H X X X X X X X
CKE
n-1
CKE
n
(4-BANK x 4,194,304-WORD x 4-BIT)
64M Synchronous DRAM
/CS /RAS /CAS /WE BA0,1 A11 A10 A0-9
No Operation
Row Address Entry &
Bank Activate
Single Bank Precharge
Precharge All Banks
Column Address Entry
& Write
Column Address Entry &
Write with Auto-Precharge
Column Address Entry
& Read
Column Address Entry &
Read with Auto-Precharge
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit REFSX
NOP H X L H H H X X X X
ACT
PRE
PREA
WRITE
WRITEA
READ
READA
REFA
REFS
H X L L H H V V V V
H X L L H L V X L X
H X L L H L X H X
H X L H L L V V L V
H X L H L L V V H V
H X L H L H V V L V
H X L H L H V V H V
H H L L L H X X X X
H L L L L H X X X X
L H H X X X X X X X
L H L H H H X X X X
X
Burst Terminate TBST H X L H H L X X X X
Mode Register Set MRS
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. A7-A9 =0, A0-A6 =Mode Address
H X L L L L L L L V*1
MITSUBISHI ELECTRIC
6
MITSUBISHI LSIs
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x
1,048,576
-WORD x 16-BIT)
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
FUNCTION TRUTH TABLE
SDRAM (Rev.3.2)
Feb.'00
Current State /CS /RAS /CAS /WE Address Command Action
(4-BANK x 4,194,304-WORD x 4-BIT)
64M Synchronous DRAM
IDLE
ROW ACTIVE
H X X X X DESEL NOP
L H H H X NOP NOP
L H H L X TBST ILLEGAL*2
L H L X BA, CA, A10
L L H H BA, RA ACT Bank Active, Latch RA
L L H L BA, A10
L L L H X REFA Auto-Refresh*5
L L L L
H X X X X DESEL NOP
L H H H X NOP NOP
L H H L X TBST NOP
Op-Code,
Mode-Add
READ &
WRITE
PRE &
PREA
MRS Mode Register Set*5
ILLEGAL*2
NOP*4
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA ACT Bank Active / ILLEGAL*2
L L H L BA, A10
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
READ &
READA
WRITE &
WRITEA
PRE &
PREA
MRS ILLEGAL
Begin Read, Latch CA, Determine
Auto-Precharge
Begin Write, Latch CA, Determine
Auto-Precharge
Precharge / Precharge All
MITSUBISHI ELECTRIC
7
MITSUBISHI LSIs
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x
1,048,576
-WORD x 16-BIT)
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
FUNCTION TRUTH TABLE (continued)
Terminate Burst, Latch CA, Begin New
PRE &
PRE &
SDRAM (Rev.3.2)
Feb.'00
Current State /CS /RAS /CAS /WE Address Command Action
(4-BANK x 4,194,304-WORD x 4-BIT)
64M Synchronous DRAM
READ
WRITE
H X X X X DESEL NOP (Continue Burst to END)
L H H H X NOP NOP (Continue Burst to END)
L H H L X TBST Terminate Burst
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA ACT Bank Active / ILLEGAL*2
L L H L BA, A10
L L L H X REFA ILLEGAL
L L L L
H X X X X DESEL
L H H H X NOP NOP (Continue Burst to END)
Op-Code,
Mode-Add
READ
/READA
WRITE &
WRITEA
PREA
MRS ILLEGAL
Read, Determine Auto-Precharge*3
Terminate Burst, Latch CA, Begin
Write, Determine Auto-Precharge*3
Terminate Burst, Precharge
NOP (Continue Burst to END)
L H H L X TBST Terminate Burst
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA ACT Bank Active / ILLEGAL*2
L L H L BA, A10
L L L H X REFA ILLEGAL
L L L L MRS ILLEGAL
Op-Code,
Mode-Add
READ &
READA
WRITE &
WRITEA
PREA
Terminate Burst, Latch CA, Begin
Read, Determine Auto-Precharge*3
Terminate Burst, Latch CA,Begin
Write, Determine Auto-Precharge*3
Terminate Burst, Precharge
MITSUBISHI ELECTRIC
8
MITSUBISHI LSIs
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x
1,048,576
-WORD x 16-BIT)
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
FUNCTION TRUTH TABLE (continued)
READ &
WRITE &
PRE &
WRITE &
PRE &
SDRAM (Rev.3.2)
Feb.'00
Current State /CS /RAS /CAS /WE Address Command Action
(4-BANK x 4,194,304-WORD x 4-BIT)
64M Synchronous DRAM
READ with
AUTO
PRECHARGE
WRITE with
AUTO
PRECHARGE
H X X X X DESEL NOP (Continue Burst to END)
L H H H X NOP NOP (Continue Burst to END)
L H H L X TBST ILLEGAL
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA ACT Bank Active / ILLEGAL*2
L L H L BA, A10
L L L H X REFA ILLEGAL
L L L L
H X X X X DESEL NOP (Continue Burst to END)
L H H H X NOP NOP (Continue Burst to END)
Op-Code,
Mode-Add
READA
WRITEA
PREA
MRS ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL*2
L H H L X TBST ILLEGAL
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA ACT Bank Active / ILLEGAL*2
L L H L BA, A10
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
READ &
READA
WRITEA
PREA
MRS ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL*2
MITSUBISHI ELECTRIC
9
MITSUBISHI LSIs
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x
1,048,576
-WORD x 16-BIT)
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
FUNCTION TRUTH TABLE (continued)
SDRAM (Rev.3.2)
Feb.'00
Current State /CS /RAS /CAS /WE Address Command Action
(4-BANK x 4,194,304-WORD x 4-BIT)
64M Synchronous DRAM
PRE -
CHARGING
ROW
ACTIVATING
H X X X X DESEL NOP (Idle after tRP)
L H H H X NOP NOP (Idle after tRP)
L H H L X TBST ILLEGAL*2
L H L X BA, CA, A10
L L H H BA, RA ACT ILLEGAL*2
L L H L BA, A10
L L L H X REFA ILLEGAL
L L L L
H X X X X DESEL NOP (Row Active after tRCD)
L H H H X NOP NOP (Row Active after tRCD)
L H H L X TBST ILLEGAL*2
Op-Code,
Mode-Add
READ &
WRITE
PRE &
PREA
MRS ILLEGAL
ILLEGAL*2
NOP*4 (Idle after tRP)
L H L X BA, CA, A10
L L H H BA, RA ACT ILLEGAL*2
L L H L BA, A10
L L L H X REFA ILLEGAL
Op-Code,
L L L L
Mode-Add
READ &
WRITE
PRE &
PREA
MRS ILLEGAL
ILLEGAL*2
ILLEGAL*2
MITSUBISHI ELECTRIC
10
MITSUBISHI LSIs
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x
1,048,576
-WORD x 16-BIT)
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
FUNCTION TRUTH TABLE (continued)
READ &
SDRAM (Rev.3.2)
Feb.'00
Current State /CS /RAS /CAS /WE Address Command Action
(4-BANK x 4,194,304-WORD x 4-BIT)
64M Synchronous DRAM
WRITE
RECOVERING
REFRESHING H X X X X DESEL NOP (Idle after tRC)
H X X X
L H H H
L H H L
L H L X
L L H H
L L H L
L L L H
L L L L
L H H H X NOP NOP (Idle after tRC)
L H H L X TBST ILLEGAL
X
X NOP NOP
X TBST
BA, CA, A10
BA, RA ACT
BA, A10
X REFA ILLEGAL
Op-Code,
Mode-Add
DESEL
READ &
WRITE
PRE &
PREA
MRS
NOP
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
ILLEGAL
L H L X BA, CA, A10
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
WRITE
PRE &
PREA
MRS ILLEGAL
ILLEGAL
ILLEGAL
MITSUBISHI ELECTRIC
11
MITSUBISHI LSIs
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x
1,048,576
-WORD x 16-BIT)
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
PRE &
FUNCTION TRUTH TABLE (continued)
SDRAM (Rev.3.2)
Feb.'00
Current State /CS /RAS /CAS /WE Address Command Action
(4-BANK x 4,194,304-WORD x 4-BIT)
64M Synchronous DRAM
MODE
REGISTER
SETTING
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on
the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
H X X X X DESEL NOP (Idle after tRSC)
L H H H X NOP NOP (Idle after tRSC)
L H H L X TBST ILLEGAL
L H L X BA, CA, A10
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10
L L L H X REFA ILLEGAL
L L L L
Op-Code,
Mode-Add
READ &
WRITE
PREA
MRS ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
MITSUBISHI ELECTRIC
12
MITSUBISHI LSIs
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x
1,048,576
-WORD x 16-BIT)
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
FUNCTION TRUTH TABLE for CKE
SDRAM (Rev.3.2)
Feb.'00
(4-BANK x 4,194,304-WORD x 4-BIT)
64M Synchronous DRAM
Current State
SELF-
REFRESH*1
POWER
DOWN
ALL BANKS
IDLE*2
CKE
CKE
n-1
H X X X X X X INVALID
L H H X X X X Exit Self-Refresh (Idle after tRC)
L H L H H H X Exit Self-Refresh (Idle after tRC)
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
L L X X X X X NOP (Maintain Self-Refresh)
H X X X X X X INVALID
L H X X X X X Exit Power Down to Idle
L L X X X X X NOP (Maintain Power Down)
H H X X X X X Refer to Function Truth Table
H L L L L H X Enter Self-Refresh
H L H X X X X Enter Power Down
H L L H H H X Enter Power Down
/CS /RAS /CAS /WE Add Action
n
H L L H H L X ILLEGAL
H L L H L X X ILLEGAL
H L L L X X X ILLEGAL
L X X X X X X Refer to Current State =Power Down
ANY STATE
other than
listed above
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum
setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
H H X X X X X Refer to Function Truth Table
H L X X X X X Begin CLK Suspend at Next Cycle*3
L H X X X X X Exit CLK Suspend at Next Cycle*3
L L X X X X X Maintain CLK Suspend
MITSUBISHI ELECTRIC
13
MITSUBISHI LSIs
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x
1,048,576
-WORD x 16-BIT)
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
SIMPLIFIED STATE DIAGRAM
REGISTER
ACTIVE
TERM
SDRAM (Rev.3.2)
Feb.'00
(4-BANK x 4,194,304-WORD x 4-BIT)
64M Synchronous DRAM
SELF
REFRESH
REFS
REFSX
WRITE
SUSPEND
MODE
SET
CLK
SUSPEND
CKEL
CKEH
MRS
IDLE
ACT
CKEL
CKEH
REFA
REFRESH
CKEL
CKEH
POWER
DOWN
ROW
TERM
WRITE
WRITEA
WRITE READ
WRITE
READA
READ
READ
AUTO
CKEL
CKEH
READ
SUSPEND
WRITEA
WRITEA
SUSPEND
POWER
APPLIED
CKEL
WRITEA
CKEH
POWER
ON
WRITEA READA
PRE
PRE PRE
PRE
PRE
CHARGE
MITSUBISHI ELECTRIC
READA
READA
CKEL
CKEH
READA
SUSPEND
Automatic Sequence
Command Sequence
14
MITSUBISHI LSIs
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x
1,048,576
-WORD x 16-BIT)
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
POWER ON SEQUENCE
MODE REGISTER
idle state. After tRSC from a MRS command, the
(4-BANK x 4,194,304-WORD x 4-BIT)
SDRAM (Rev.3.2)
Feb.'00
64M Synchronous DRAM
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the
inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
Burst Length, Burst Type, /CAS Latency and Write Mode can be
programmed by setting the mode register (MRS). The mode register
stores these data until the next MRS command, which may be issued
when both banks are in
SDRAM is ready for new command.
BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 0 0 WM 0 0 LTMODE BT BL
LATENCY
MODE
Write
Mode
CL /CAS LATENCY
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Burst Write
0
Single Write
1
R
R
2
3
R
R
R
R
BURST
LENGTH
BURST
TYPE
CLK
/CS
/RAS
/CAS
/WE
BA0,1 A11-A0
BL BT=0 BT=1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
1
2
4
8
R
R
R
Full Page
SEQUENTIAL
INTERLEAVED
V
1
2
4
8
R
R
R
R
R: Reserved for Future Use
MITSUBISHI ELECTRIC
15
MITSUBISHI LSIs
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x
1,048,576
-WORD x 16-BIT)
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
SDRAM (Rev.3.2)
Feb.'00
CLK
Command
Read
(4-BANK x 4,194,304-WORD x 4-BIT)
64M Synchronous DRAM
Write
Address
DQ
CL= 3
BL= 4
Initial Address BL
A2 A1 A0
0 0 0
0 0 1
0 1 0
0 1 1
8
1 0 0
Y
Q0 Q1 Q2 Q3 D0 D1 D2 D3
/CAS Latency
Burst Length Burst Length
Burst Type
Column Addressing
Sequential Interleaved
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
Y
1 0 1
1 1 0
1 1 1
- 0 0
- 0 1
- 1 0
- 1 1
- - 0
- - 1
5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
7 0 1 2
0 1 2 3
1 2 3 0
4
2 3 0 1
3 0
0 1
2
1 0
3 4 5 6 3 2 1 0
1 2
7 6 5 4
0 1 2 3
1 0 3 2
2 3 0 1
3 2
0 1
1 0
1 0
MITSUBISHI ELECTRIC
16
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