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M2V28S40TP-7
Datasheet
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Mitsubishi M2V28S30TP-8L, M2V28S30TP-8, M2V28S30TP-7L, M2V28S40TP-8L, M2V28S40TP-8 Datasheet

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MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
DESCRIPTION
FEATURES
ITEM
M2V28S20/30/40TP
-7
-8
Icc1
Icc6
Active to Precharge Command Period
(Min.)
(Single Bank)
Self Refresh Current
(Max.)
50ns
20ns
6ns
2mA
V28S30
V28S40
-6
45ns
20ns
2mA
130mA
120mA
120
mA
120mA
115mA
115mA
Jun. '99
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
PRELIMINARY
Some of contents are described for general products and are subject to change without notice.
M2V28S20TP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL interface and M2V28S30TP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40TP is organized as 4-bank x 2,097,152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.
M2V28S20TP,M2V28S30TP,M2V28S40TP achieves very high speed data rates up to 133MHz, and is suitable for main memory or graphic memory in computer systems.
tCLK tRAS
tRCD tAC
tRC
Clock Cycle Time (Min.)
Row to Column Delay (Min.) Access Time from CLK (Max.) (CL=3)
Ref/Active Command Period (Min.)
V28S20
Operation Current (Max.)
7.5ns
5.4ns
67.5ns
10ns
70ns
10ns 50ns 20ns
6ns
70ns
-
- Single 3.3V ±0.3V power supply
- Max. Clock frequency -6:PC133<3-3-3> / -7:PC100<2-2-2> / -8:PC100<3-2-2>
- PC133(-6) supports x4/x8 only. And does not support Low-Power (L) version.
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (M2V28S40TP)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 4096 refresh cycles /64ms
- LVTTL Interface
- Package M2V28S20TP/30TP/40TP
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
135mA
135mA
2mA
1
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
Revision History
1.0
Jun. '99
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
Rev.
Description
- Add PC133 Specification.
2
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
CLK
: Master Clock
CKE
: Clock Enable
/CS
: Chip Select
/RAS
: Row Address Strobe
/CAS
: Column Address Strobe
/WE
: Write Enable
DQ0-15
: Data I/O
DQM
: Output Disable/ Write Mask
A0-11
: Address Input
BA0,1
: Bank Address
Vdd
: Power Supply
VddQ
: Power Supply for Output
Vss
: Ground
VssQ
: Ground for Output
M2V28S20TP-6,-7,-8
Jun. '99
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
PIN CONFIGURATION (TOP VIEW)
128M Synchronous DRAM
M2V28S20TP
M2V28S30TP
M2V28S40TP
PIN CONFIGURATION
(TOP VIEW)
Vdd NC VddQ NC DQ0 VssQ NC NC
VddQ NC DQ1 VssQ NC Vdd NC /WE /CAS /RAS /CS
BA0(A13) BA1(A12) A10(AP) A0 A1 A2 A3 Vdd
Vdd DQ0 VddQ NC DQ1 VssQ NC DQ2
VddQ NC DQ3 VssQ NC Vdd NC /WE /CAS /RAS /CS
BA0(A13) BA1(A12) A10(AP) A0 A1 A2 A3 Vdd
Vdd DQ0 VddQ DQ1 DQ2 VssQ DQ3 DQ4
VddQ DQ5 DQ6 VssQ DQ7 Vdd DQML /WE /CAS /RAS /CS
BA0(A13) BA1(A12) A10(AP) A0 A1 A2 A3 Vdd
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19
20 21 22
23 32 24 31
25 30 26 29 27 28
54 53 52 51 50 49 48 47
46 45 44 43 42 41 40 39 38 37 36
35 34 33
Vss DQ15 VssQ DQ14 DQ13 VddQ DQ12 DQ11
VssQ DQ10 DQ9 VddQ DQ8 Vss NC DQMU CLK CKE NC
A11 A9 A8 A7 A6 A5 A4 Vss
Vss DQ7 VssQ NC DQ6 VddQ NC DQ5
VssQ NC DQ4 VddQ NC Vss NC DQM CLK CKE NC
A11 A9 A8 A7 A6 A5 A4 Vss
Vss NC VssQ NC DQ3 VddQ NC NC
VssQ NC DQ2 VddQ NC Vss NC DQM CLK CKE NC
A11 A9 A8 A7 A6 A5 A4 Vss
3
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
Jun. '99
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
BLOCK DIAGRAM
Memory Array
4096 x1024 x8
Cell Array
Bank #0
Register
Address Buffer
Mode
Memory Array
4096 x1024 x8
Cell Array
Bank #1
DQ0-7
I/O Buffer
Memory Array
4096 x1024 x8
Cell Array
Control Circuitry
Bank #2
Control Signal Buffer
Memory Array
4096 x1024 x8
Cell Array
Bank #3
A0-11
Note : This figure shows the M2V28S30TP.
The M2V28S20TP configration is 4096x2048x4 of cell array and DQ 0-3. The M2V28S40TP configration is 4096x512x16 of cell array and DQ 0-15.
Type Designation Code
M2 V 28 S 3 0 TP -8
BA0,1
Clock Buffer
CLK CKE
Access Item -6 : 7.5ns (PC133/3-3-3),
-7 : 10ns(PC100/2-2-2),
Package Type TP : TSOP(II) Process Generation Blank : 1st gen. Function 0 : Random Column Organization 2: x4, 3: x8, 4: x16
Synchronous DRAM
Density 28 : 128Mbit Interface V : LVTTL Mitsubishi DRAM
/CS /RAS
These rules are only applied to the Synchronous DRAM family.
/CAS
-8 : 10ns(PC100/3-2-2)
/WE
DQM
4
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
PIN FUNCTION
following cycle is ceased. CKE is also used to select auto /
Jun. '99
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
CLK Input
CKE Input
/CS Input
/RAS, /CAS, /WE Input Combination of /RAS, /CAS, /WE defines basic commands.
A0-11 Input
BA0,1 Input
Master Clock: All other inputs are referenced to the rising edge of CLK.
Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the
selfrefresh. After self refresh mode is started, CKE becomes synchronous input. Self refresh is maintained as long as CKE is low.
Chip Select: When /CS is high, any command means No Operation.
A0-11 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-11. The Column Address is specified by A0-9,11 (x4) / A0-9 (x8) / A0-8 (x16). A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged.
Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
DQ0-7 Input / Output
DQM Input
Vdd, Vss Power Supply Power Supply for the memory array and peripheral circuitry.
VddQ, VssQ Power Supply VddQ and VssQ are supplied to the Output Buffers only.
Data In and Data out are referenced to the rising edge of CLK. Din Mask / Output Disable:
When DQM is high in burst write, Din for the current cycle is masked. When DQM is high in burst read, Dout is disabled at the next but one cycle.
5
MITSUBISHI LSIs
128M Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev. 1.0E)
Jun. '99
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
BASIC FUNCTIONS
The M2V28S30TP provides basic functions, bank (row) activate, burst read / write, bank
(row) precharge, and auto / self refresh.
Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively.
To know the detailed definition of commands, please see the command truth table.
CLK
/CS Chip Select : L=select, H=deselect /RAS Command /CAS
/WE Command
CKE Refresh Option @ refresh command
A10 Precharge Option @ precharge or read/write command
Command
define basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data
appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-precharge, READA).
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to
be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates
burst read / write operation. When A10 =H at this command, all banks are deactivated (precharge all,
PREA ). Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are
generated internally. After this command, the banks are precharged automatically.
6
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
M2V28S20TP-6,-7,-8
Jun. '99
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
COMMAND TRUTH TABLE
COMMAND MNEMONIC
Deselect DESEL H X H X X X X X X X
CKE
n-1
CKE
n
128M Synchronous DRAM
/CS /RAS /CAS /WE BA0,1 A11 A10 A0-9
No Operation
Row Address Entry &
Bank Activate
Single Bank Precharge
Precharge All Banks
Column Address Entry
& Write
Column Address Entry &
Write with Auto-Precharge
Column Address Entry
& Read
Column Address Entry &
Read with Auto-Precharge
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit REFSX
NOP H X L H H H X X X X
ACT
PRE
PREA
WRITE
WRITEA
READ
READA
REFA
REFS
H X L L H H V V V V
H X L L H L V X L X
H X L L H L X H X
H X L H L L V V L V
H X L H L L V V H V
H X L H L H V V L V
H X L H L H V V H V
H H L L L H X X X X
H L L L L H X X X X
L H H X X X X X X X
L H L H H H X X X X
X
Mode Register Set MRS
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. A7-A9 =0, A0-A6 =Mode Address
H X L L L L L L L V*1
7
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
FUNCTION TRUTH TABLE
M2V28S20TP-6,-7,-8
Jun. '99
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
Current State /CS /RAS /CAS /WE Address Command Action
128M Synchronous DRAM
IDLE
ROW ACTIVE
H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA TBST ILLEGAL*2
L H L X BA, CA, A10
L L H H BA, RA ACT Bank Active, Latch RA
L L H L BA, A10
L L L H X REFA Auto-Refresh*5
L L L L
H X X X X DESEL NOP
L H H H X NOP NOP
L H H L BA TBST NOP
Op-Code, Mode-Add
READ / WRITE
PRE /
PREA
MRS Mode Register Set*5
ILLEGAL*2
NOP*4
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA ACT Bank Active / ILLEGAL*2
L L H L BA, A10
L L L H X REFA ILLEGAL
L L L L
Op-Code, Mode-Add
READ / READA
WRITE /
WRITEA
PRE /
PREA
MRS ILLEGAL
Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge
Precharge / Precharge All
8
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
FUNCTION TRUTH TABLE (continued)
M2V28S20TP-6,-7,-8
Jun. '99
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
Current State /CS /RAS /CAS /WE Address Command Action
128M Synchronous DRAM
READ
WRITE
H X X X X DESEL NOP (Continue Burst to END)
L H H H X NOP NOP (Continue Burst to END)
L H H L BA TBST Terminate Burst
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA ACT Bank Active / ILLEGAL*2
L L H L BA, A10
L L L H X REFA ILLEGAL
L L L L
H X X X X DESEL
L H H H X NOP NOP (Continue Burst to END)
Op-Code, Mode-Add
READ
/READA WRITE /
WRITEA
PRE /
PREA
MRS ILLEGAL
Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge*3
Terminate Burst, Latch CA, Begin Write, Determine Auto-Precharge*3
Terminate Burst, Precharge
NOP (Continue Burst to END)
L H H L BA TBST Terminate Burst
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA ACT Bank Active / ILLEGAL*2
L L H L BA, A10
L L L H X REFA ILLEGAL
L L L L MRS ILLEGAL
Op-Code, Mode-Add
READ /
READA WRITE / WRITEA
PRE /
PREA
Terminate Burst, Latch CA, Begin Read, Determine Auto-Precharge*3 Terminate Burst, Latch CA,Begin Write, Determine Auto-Precharge*3
Terminate Burst, Precharge
9
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
FUNCTION TRUTH TABLE (continued)
M2V28S20TP-6,-7,-8
Jun. '99
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
Current State /CS /RAS /CAS /WE Address Command Action
128M Synchronous DRAM
READ with
AUTO
PRECHARGE
WRITE with
AUTO
PRECHARGE
H X X X X DESEL NOP (Continue Burst to END)
L H H H X NOP NOP (Continue Burst to END)
L H H L BA TBST ILLEGAL
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA ACT Bank Active / ILLEGAL*2
L L H L BA, A10
L L L H X REFA ILLEGAL
L L L L
H X X X X DESEL NOP (Continue Burst to END)
L H H H X NOP NOP (Continue Burst to END)
Op-Code, Mode-Add
READ /
READA
WRITE /
WRITEA
PRE /
PREA
MRS ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL*2
L H H L BA TBST ILLEGAL
L H L H BA, CA, A10
L H L L BA, CA, A10
L L H H BA, RA ACT Bank Active / ILLEGAL*2
L L H L BA, A10
L L L H X REFA ILLEGAL
L L L L
Op-Code, Mode-Add
READ /
READA
WRITE /
WRITEA
PRE /
PREA
MRS ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL*2
10
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
FUNCTION TRUTH TABLE (continued)
M2V28S20TP-6,-7,-8
Jun. '99
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
Current State /CS /RAS /CAS /WE Address Command Action
128M Synchronous DRAM
PRE -
CHARGING
ROW
ACTIVATING
H X X X X DESEL NOP (Idle after tRP)
L H H H X NOP NOP (Idle after tRP)
L H H L BA TBST ILLEGAL*2
L H L X BA, CA, A10
L L H H BA, RA ACT ILLEGAL*2
L L H L BA, A10
L L L H X REFA ILLEGAL
L L L L
H X X X X DESEL NOP (Row Active after tRCD)
L H H H X NOP NOP (Row Active after tRCD)
L H H L BA TBST ILLEGAL*2
Op-Code, Mode-Add
READ / WRITE
PRE /
PREA
MRS ILLEGAL
ILLEGAL*2
NOP*4 (Idle after tRP)
L H L X BA, CA, A10
L L H H BA, RA ACT ILLEGAL*2
L L H L BA, A10
L L L H X REFA ILLEGAL
Op-Code,
L L L L
Mode-Add
READ /
WRITE
PRE / PREA
MRS ILLEGAL
ILLEGAL*2
ILLEGAL*2
11
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
FUNCTION TRUTH TABLE (continued)
M2V28S20TP-6,-7,-8
Jun. '99
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
Current State /CS /RAS /CAS /WE Address Command Action
128M Synchronous DRAM
WRITE
RECOVERING
REFRESHING H X X X X DESEL NOP (Idle after tRC)
H X X X
L H H H
L H H L
L H L X
L L H H
L L H L
L L L H X REFA ILLEGAL
L L L L
L H H H X NOP NOP (Idle after tRC)
L H H L BA TBST ILLEGAL
X
X NOP NOP
BA TBST
BA, CA, A10
BA, RA ACT
BA, A10
Op-Code, Mode-Add
DESEL
READ / WRITE
PRE / PREA
MRS
NOP
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
ILLEGAL
L H L X BA, CA, A10
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10
L L L H X REFA ILLEGAL
L L L L
Op-Code, Mode-Add
READ / WRITE
PRE / PREA
MRS ILLEGAL
ILLEGAL
ILLEGAL
12
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
FUNCTION TRUTH TABLE (continued)
M2V28S20TP-6,-7,-8
Jun. '99
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
Current State /CS /RAS /CAS /WE Address Command Action
128M Synchronous DRAM
MODE
REGISTER
SETTING
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
H X X X X DESEL NOP (Idle after tRSC)
L H H H X NOP NOP (Idle after tRSC)
L H H L BA TBST ILLEGAL
L H L X BA, CA, A10
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10
L L L H X REFA ILLEGAL
L L L L
Op-Code, Mode-Add
READ / WRITE
PRE / PREA
MRS ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
13
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
FUNCTION TRUTH TABLE for CKE
Jun. '99
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
Current State
SELF-
REFRESH*1
POWER
DOWN
ALL BANKS
IDLE*2
CKE
CKE
n-1
H X X X X X X INVALID L H H X X X X Exit Self-Refresh (Idle after tRC) L H L H H H X Exit Self-Refresh (Idle after tRC) L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP (Maintain Self-Refresh) H X X X X X X INVALID L H X X X X X Exit Power Down to Idle L L X X X X X NOP (Maintain Power Down) H H X X X X X Refer to Function Truth Table H L L L L H X Enter Self-Refresh H L H X X X X Enter Power Down H L L H H H X Enter Power Down
/CS /RAS /CAS /WE Add Action
n
H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Refer to Current State =Power Down
ANY STATE
other than
listed above
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
H H X X X X X Refer to Function Truth Table H L X X X X X Begin CLK Suspend at Next Cycle*3 L H X X X X X Exit CLK Suspend at Next Cycle*3 L L X X X X X Maintain CLK Suspend
14
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
SIMPLIFIED STATE DIAGRAM
Jun. '99
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
REFS
REFSX
128M Synchronous DRAM
SELF
REFRESH
WRITE
SUSPEND
MODE
REGISTER
SET
CLK
SUSPEND
CKEL
WRITE READ
CKEH
MRS
CKEH
WRITE
CKEL
ACTIVE
WRITEA
WRITE
IDLE
ACT
ROW
READ
CKEH
READA
REFA
CKEL
READ
AUTO
REFRESH
POWER
DOWN
CKEH
CKEL
READ
SUSPEND
READA
READA
CKEL
CKEH
READA
SUSPEND
WRITEA
SUSPEND
POWER APPLIED
WRITEA
CKEL
CKEH
POWER
ON
WRITEA
PRE
WRITEA READA
PRE
PRE PRE
PRE
CHARGE
Automatic Sequence Command Sequence
15
MITSUBISHI LSIs
128M Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev. 1.0E)
Jun. '99
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when all banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0BA1BA0
0 0 0 0 0 LTMODE BT BL00
LATENCY
MODE
CL
0 0 0 0 0 1
0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
/CAS LATENCY
R R
2 3 R R R R
BURST
LENGTH
BURST
TYPE
CLK /CS /RAS /CAS /WE
BA0,1 A11-A0
BL
0 0 0 0 0 1 0 1 0 0 1 1 1 0 0
1 0 1 1 1 0 1 1 1
0
SEQUENTIAL
1
INTERLEAVED
V
BT= 0 BT= 1
1 2 4 8 R
R R
FP
1 2 4 8 R
R R R
R: Reserved for Future Use
16
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
Jun. '99
CLK
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
Command
Address
DQ
CL= 3 BL= 4
Initial Address BL
A2 A1 A0
0 0 0 0 0 1 0 1 0 0 1 1 1 0 0
Read
Y
Q0 Q1 Q2 Q3
/CAS Latency Burst Length Burst Length
Burst Type
Column Addressing
Sequential Interleaved 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
8
4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
Write
Y
D0 D1 D2 D3
1 0 1 1 1 0 1 1 1
- 0 0
- 0 1
- 1 0
- 1 1
- - 0
- - 1
5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 7 0 1 2 0 1 2 3 1 2 3 0
4
2 3 0 1 3 0 0 1
2
1 0
3 4 5 6 3 2 1 0
1 2
7 6 5 4 0 1 2 3 1 0 3 2
2 3 0 1 3 2 0 1 1 0
1 0
17
MITSUBISHI LSIs
128M Synchronous DRAM
MITSUBISHI ELECTRIC
Xb
Xb
Xb
Xb
Xb
Xb
OPERATIONAL DESCRIPTION
SDRAM (Rev. 1.0E)
Jun. '99
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
BANK ACTIVATE
The SDRAM has four independent banks. Each bank is activated by the ACT command with the bank addresses (BA0,1). A row is indicated by the row addresses A0-11. The minimum activation interval between one bank and the other bank is tRRD. Maximum 2 ACT commands are allowed within tRC , although the number of banks which are active concurrently is not limited.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the precharge all command (PREA, PRE + A10=H) is available to deactivate them at the same time. After tRP from the precharge, an ACT command to the same bank can be issued.
CLK
Command
A0-9
A10
A11 Xa
BA0,1
DQ
READ
After tRCD from the bank activation, a READ command can be issued. 1st output data is
Bank Activation and Precharge All (BL=4, CL=3)
2 ACT command / tRCmin
ACT
tRRD
Xa
tRCD
Xa
00
ACT
01
READ
Y
0
00
tRCmin
tRAS
PRE
tRP
1
Qa0 Qa1 Qa2 Qa3
Precharge all
ACT
01
available after the /CAS Latency from the READ, followed by (BL -1) consecutive data when the Burst Length is BL. The start address is specified by A0-A9,A11(x4), A0-9(X8), A0-8(X16) , and the address sequence of burst data is defined by the Burst Type. A READ command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous output data by interleaving the multiple banks. When A10 is high at a READ command, the auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at BL after READA. (Need to keep tRAS min.) The next ACT command can be issued after (BL + tRP) from the previous READA.
18
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
Xa
Xa
Xa
Jun. '99
CLK
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
Multi Bank Interleaving READ (BL=4, CL=3)
128M Synchronous DRAM
Command
A0-9
A10
A11
BA0,1
DQ
CLK
Command
A0-9
ACT
tRCD
Xa
Xa
Xa Xb
00
READ
Y
0
00
ACT
Xb
Xb
10
/CAS latency
READ
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
Burst Length
READ with Auto-Precharge (BL=4, CL=3)
BL + tRP
ACT
tRCD tRP
READ
BL
Y
10
PRE
Y
0
0
00
ACT
Xa
A10
1
A11
BA0,1
00
00
DQ
READ Auto-Precharge Timing (BL=4)
CLK
Command ACT READ
CL=3
CL=2
DQ
DQ
Xa
Xa
00
Qa0 Qa1 Qa2 Qa3
Internal precharge start
BL
Qa1 Qa2 Qa3Qa0
Qa1 Qa2 Qa3Qa0
Internal Precharge Start Timing
19
MITSUBISHI LSIs
128M Synchronous DRAM
MITSUBISHI ELECTRIC
Xa
Xa
Xa
Xa
Xa
SDRAM (Rev. 1.0E)
Jun. '99
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set at the same cycle as the WRITE. Following (BL -1) data are written into the RAM, when the Burst Length is BL. The start address is specified by A0-A9,A11(x4), A0-9(X8), A0-8(X16) and the address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous input data by interleaving the multiple banks. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, the autoprecharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge begins at tWR after the last input data cycle. (Need to keep tRAS min.) The next ACT command can be issued after tRP from the internal precharge timing.
Multi Bank Interleaving WRITE (BL=4)
CLK
Command
A0-9
A10
A11
BA0,1
DQ
CLK
Command
A0-9
ACT
00
ACT
Xa
Write
tRCD tRCD
ACT
Y
Xb
0 0
Xb
Xb 0
00
10
Da0
Da1 Da2 Da3 Db0 Db1 Db2 Db3
Write
Y
10
WRITE with Auto-Precharge (BL=4)
Write
tRCD
Y
tWR
PRE
0
0
00
PRE
0
10
ACT
tRP
Xa
A10
A11
BA0,1
DQ
Xa
Xa Xa
00
1
00
Da0 Da1 Da2 Da3
Internal precharge starts
Xa
00
20
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
M2V28S20TP-6,-7,-8
Jun. '99
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
BURST INTERRUPTION [ Read Interrupted by Read ]
Burst read operation can be interrupted by new read of any bank. Random column access is
allowed READ to READ interval is minimum 1 CLK..
Read Interrupted by Read (BL=4, CL=3)
CLK
128M Synchronous DRAM
Command
A0-9
A10
A11
BA0,1
DQ
READ READ READ READ
Yi
Yj Yk Yl
0 00 0
00 1000 01
Qai0 Qaj1 Qbk0 Qbk1Qaj0 Qbk2 Qal0 Qal1 Qal2 Qal3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled automatically 1 cycle after WRITE assertion.
Read Interrupted by Write (BL=4, CL=3)
CLK
Command
A0-9
A10
A11
BA0,1
DQM
Q
D
READ
Yi
0
00
Qai0
DQM control Write control
Write
Yj
0
00
Daj0 Daj1 Daj2 Daj3
21
MITSUBISHI LSIs
128M Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev. 1.0E)
Jun. '99
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge of the same bank . READ to PRE interval is minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. As a result, READ to PRE interval determines valid data length to be output. The figure below shows examples of BL=4.
Read Interrupted by Precharge (BL=4)
CLK
CL=3
CL=2
Command
DQ
Command
DQ
Command
DQ
Command
DQ
Command
DQ
READ
READ
READ
READ
READ PRE
PRE
PRE
Q0 Q1 Q2
Q0
PRE
Q0 Q1 Q2
Q0
Q1
Q0
PRE
Q1
Command
DQ
READ PRE
Q0
22
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
M2V28S20TP-6,-7,-8
Jun. '99
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any bank. Random column access is
allowed. WRITE to WRITE interval is minimum 1 CLK.
Write Interrupted by Write (BL=4)
CLK
128M Synchronous DRAM
Command
A0-9
A10
A11
BA0,1
DQ
Write
Write
Yi
Yj
0
0
00
00
Dai0 Daj0 Daj1 Dbk0
Write
Yk
10
0
Dbk1 Dbk2
Write
Yl
0
00
Dal0 Dal1 Dal2 Dal3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=3)
CLK
Command
A0-9
A10
A11
BA0,1
DQM
DQ
Write
Yi
0
00
READ
Yj
0
00
Qaj0
Qaj1Dai0 Dbk0 Dbk1
Write
Yk
0
10
READ
Yl
0
00
23
Qal0
MITSUBISHI LSIs
128M Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev. 1.0E)
Jun. '99
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank. Random column
access is allowed. Write recovery time (tWR) is required from the last data to PRE command.
Write Interrupted by Precharge (BL=4)
CLK
Command
A0-9
A10
A11
BA0,1
DQM
DQ
Write
tWR tRP
Yi
0
00
Dai0 Dai1 Dai2
PRE
0
00
ACT
Xb
Xb
Xb
00
24
MITSUBISHI LSIs
128M Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev. 1.0E)
Jun. '99
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H)
command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 128Mbit memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto-refresh, all banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum tRC. Any command must not be supplied to the device before tRC from the REFA command.
Auto-Refresh
CLK
/CS
/RAS
/CAS
/WE
CKE
A0-11
BA0,1
Auto Refresh on All Banks
NOP or DESELECT
minimum tRC
Auto Refresh on All Banks
25
MITSUBISHI LSIs
128M Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev. 1.0E)
Jun. '99
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enabled input ,all other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE (REFSX) for longer than tSRX. After tRC from REFSX all banks are in the idle state and a new command can be issued, but DESEL or NOP commands must be asserted till then.
Self-Refresh
CLK
Stable CLK
/CS
NOP
/RAS
/CAS
/WE
CKE
A0-11
BA0,1
Self Refresh Entry
tSRX
Self Refresh Exit
new command
X
00
minimum tRC +1 CLOCK for recovery
26
MITSUBISHI LSIs
128M Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev. 1.0E)
Jun. '99
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
CLK SUSPEND
CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle. A command at the suspended cycle is ignored.
ext.CLK
CKE
CLK
CKE
Command
CKE
Command
CLK
int.CLK
PRE
ACT
Power Down by CKE
Standby Power Down
NOP NOP NOP NOP NOP NOP
NOP
Active Power Down
NOP NOP NOP NOP NOP NOP
NOP
DQ Suspend by CKE
CKE
Command
DQ
Write
D0
READ
Q0 Q1 Q2 Q3D1 D2 D3
27
MITSUBISHI LSIs
128M Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev. 1.0E)
Jun. '99
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
DQM CONTROL
DQM is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, DQM masks input data word by word. DQM to write mask latency is 0. During reads, DQM forces output to Hi-Z word by word. DQM to output Hi-Z latency is 2.
DQM Function
CLK
Command
DQM
DQ
Write
D0 D2 D3
masked by DQM=H
READ
Q0 Q1 Q3
disabled by DQM=H
28
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
CAPACITANCE
VO
M2V28S20TP-6,-7,-8
Jun. '99
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
ABSOLUTE MAXIMUM RATINGS
128M Synchronous DRAM
Symbol Parameter
Vdd
VddQ
VI
IO
Pd Topr Tstg
Supply Voltage Supply Voltage for Output Input Voltage
Output Voltage -0.5 - 4.6 Output Current 50
Power Dissipation Operating Temperature Storage Temperature
Conditions Ratings Unit with respect to Vss with respect to VssQ with respect to Vss with respect to VssQ
Ta = 25ºC
RECOMMENDED OPERATING CONDITIONS
(Ta=0 – 70ºC, unless otherwise noted )
Symbol
Vdd
Vss
VddQ Supply Voltage for Output 3.0
VssQ
VIH*1
VIL*2
Parameter
Supply Voltage Supply Voltage
Supply Voltage for Output High-level Input Voltage all inputs
Low-level Input Voltage all inputs
Min.
3.0
2.0
-0.3
-0.5 - 4.6
-0.5 - 4.6
-0.5 - 4.6
1000 mW 0 - 70
-65 - 150
Limits
Typ. Max.
3.3
0
0
0
3.3 0
VddQ +0.3
V V V V
mA
ºC ºC
Unit
3.6 V 0 V
3.6 V 0 V
V
0.8 V
NOTES)
1. VIH(max)=5.5V for pulse width less than 10ns.
2. VIL(min)=-1.0V for pulse width less than 10ns.
(Ta=0 – 70ºC, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted )
Symbol
CI(A) CI(C) CI(K)
CI/O Input Capacitance, I/O pin
Input Capacitance, address pin Input Capacitance, contorl pin
Input Capacitance, CLK pin
Parameter
Test Condition
@ 1MHz
1.4V bias 200mV swing Vcc=3.3V
Limits (min.)
2.5
2.5
2.5
4.0
Limits (max.)
-6 (PC133) -7/-8(PC100)
3.8
3.8
3.5
6.5
5.0
5.0
4.0
6.5
29
Unit
pF pF pF
pF
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
I
M2V28S20TP-6,-7,-8
Jun. '99
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 – 70ºC, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted )
128M Synchronous DRAM
operating current
tRC=min, tCLK =min, BL=1 , CL=3
precharge standby current in Non Power down mode
/CS > Vcc -0.2V
precharge standby current in Power down mode
/CS > Vcc -0.2V
active standby current
burst current
All Bank Active tCLK = min BL=4, CL=3
ITEM
single bank operation
tCLK = 15ns CKE = H VIH > Vcc - 0.2V VIL < 0.2V
CLK = L & CKE = H VIH > Vcc - 0.2V VIL < 0.2V all input signals are fixed.
tCLK = 15ns CKE = L
CLK = L CKE = L
CKE = H, tCLK=15ns
CKE = H, CLK=L
Symbol
Icc1
Icc2N
Icc2NS
Icc2P
Icc2PS
Icc3N 40 Icc3NS
Icc4
Organi­zation
x4 x8
x16
x4/x8/x16
x4/x8/x16 *1mA
x4/x8/x16
x4/x8/x16 *1mA
x4/x8/x16 40 x4/x8/x16
x4 x8
x16
Limits (max.)
-6 120 115 115 130
-
25
2
1
35
185
200
-
-7
120 135
1515
40
140 150
160
120
135
2
140 150
160
Unit
mA
mA
mA
mA
mA
Note
*1
*1
*1
*1
*1
-8
2525
15
2
11
3535
auto-refresh current
self-refresh current
tRC=min, tCLK=min
CKE < 0.2V
Icc5
Icc6
x4/x8/x16
x4/x8/x16
NOTE)
1. Icc(max) is specified at the output open condition.
2. Low Power version. (-7L,-8L only)
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 – 70ºC, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted )
Symbol
VOH (DC)
VOL (DC) IOZ
I
High-Level Output Voltage (DC) Low-level Output Voltage (DC) Off-state Output Current
Input Current
Parameter Test Conditions
IOH=-2mA IOL= 2mA
Q floating VO=0 -- VddQ VIH = 0 -- VddQ +0.3V
200
200
Min.
2.4
-10
-10 10
Limits
200
22
0.80.8- mA
Max.
0.4 10
mA
*1 *1mA2
*1,2
unit
V V
µA µA
30
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
tWR
Self-refresh Exit time
M2V28S20TP-6,-7,-8
Jun. '99
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
AC TIMING REQUIREMENTS
(Ta=0 – 70ºC, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted ) Input Pulse Levels: 0.8V – 2.0V Input Timing Measurement Level: 1.4V
Min.
10
-6 Max.
Symbol
tCLK
CLK cycle time
Parameter
CL=2 10
128M Synchronous DRAM
Limits
Min.
-7 Max.
Min.
13
-8 Max.
Unit
ns
CL=3
tCH CLK High pulse width 3 3 ns
tCL CLK Low pulse width 3 3 ns
tT
tIS tIH Input Hold time (all inputs) 1 1 ns
tRC Row Cycle time 70 70 ns
tRCD Row to Column Delay 20 20 ns
tRAS Row Active time 50
tRP Row Precharge time 20 20 ns
tRRD
tRSC tSRX tPDE
tREF Refresh Interval time
Transition time of CLK Input Setup time (all inputs)
Write Recovery time 20 20 ns Act to Act Delay time Mode Register Set Cycle time
Power Down Exit time
7.5
2.5
2.5 1
1.5
0.8
67.5 20 45 20
15 15 15
7.5
7.5
10
100K
64
10
1 2 2 ns
20 20 ns 20 20 ns 10 10
10
100K
64 64
10 ns
1
50
10 ns 10 ns
10
100K
ms
ns
ns
CLK
DQ
1.4V
1.4V
Any AC timing is referenced to the input signal passing through 1.4V.
31
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
V
OUT
CLK
M2V28S20TP-6,-7,-8
Jun. '99
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
SWITCHING CHARACTERISTICS
(Ta=0 – 70ºC, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted )
Limits
Symbol Parameter
tAC
tOH Output Hold time from CLK
tOLZ
tOHZ
Access time from CLK
Delay time, output low­impedance from CLK
Delay time, output high­impedance from CLK
CL=2 CL=3
CL=2 CL=3
-6
Min. Max.
6
5.4
3
2.7
0
2.7
5.4
Min.
3 3
0
3
128M Synchronous DRAM
-7 Max. Min. Max.
6 7 6 6
6
-8
3 3 ns
0
3 6 ns
Unit
ns ns ns
ns
Note
*1
NOTE)
1. If clock rising time is longer than 1ns, (tr /2–0.5ns) should be added to the parameter.
Output Load Condition
50pF
DQ
Output Timing Measurement Reference Point
CLK
tOLZ
1.4V
1.4V
1.4V
DQ
tAC
tOH
tOHZ
1.4V
32
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
Burst Write (single bank) @BL=4
CKE
CLK
Jun. '99
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
/CS
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
tRC
128M Synchronous DRAM
/RAS
/CAS
/WE
DQM
A0-8
A10
tRAS
tRCD
tWR
X
X
Y
tRP
tRCD
X
X
Y
A9,11
BA0,1
DQ
X
0
ACT#0 WRITE#0 PRE#0 ACT#0 WRITE#0
0 0
D0 D0 D0 D0
X
0
Italic parameter indicates minimum case
0
D0 D0 D0 D0
33
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
/RAS
/CAS
CKE
CLK
DQM
Jun. '99
Burst Write (multi bank) @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
/CS
tRRD
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
tRC
tRAS
tRP
128M Synchronous DRAM
tRRD
/WE
A0-8
A10
A9,11
tRCD
tWR
X
X
X
Y
X
X
X
Y
tWR
tRCD
X
X
X
Y
X
X
X
BA0,1
DQ
0
ACT#0 WRITE#0 PRE#0 ACT#0 WRITE#0
0 1
1
D0 D0 D0 D0
ACT#1 WRITE#1 PRE#1
0
D1 D1 D1 D1
Italic parameter indicates minimum case
0
1
2
ACT#2
0
D0 D0 D0 D0
34
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
CKE
CLK
Jun. '99
Burst Read (single bank) @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
/CS
/RAS
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
tRC
tRAS tRP
128M Synchronous DRAM
/CAS
/WE
DQM
A0-8
A10
A9,11
tRCD
DQM read latency =2
X
X
X
Y
tRCD
X
X
X
Y
BA0,1
DQ
0
ACT#0 READ#0 PRE#0 ACT#0 READ#0
0 0
CL=3
Q0 Q0 Q0 Q0
READ to PRE ³BL allows full data out
Italic parameter indicates minimum case
0
0
35
Q0 Q0
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
/RAS
/CAS
CKE
CLK
DQM
Jun. '99
Burst Read (multiple bank) @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
/CS
tRRD
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
tRC
tRAS tRP
128M Synchronous DRAM
tRRD
/WE
A0-8
A10
A9,11
tRCD
DQM read latency =2
X
X
X
Y
X
X
X
Y
tRCD
X
X
X
Y
X
X
X
BA0,1
DQ
0
ACT#0
0 0
1
CL=3
READ#0
ACT#1
1
CL=3
Q0 Q0 Q0 Q0
PRE#0 ACT#0 READ#0
READ#1 PRE#1 ACT#2
Italic parameter indicates minimum case
0
Q1 Q1 Q1 Q1
0
21
36
Q0
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
CKE
CLK
Jun. '99
Burst Write (multi bank) with Auto-Precharge @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
/CS
tRRD
/RAS
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
tRC
128M Synchronous DRAM
tRRD
/CAS
/WE
DQM
A0-8
A10
A9,11
tRCD
BL-1+ tWR + tRP
BL-1+ tWR + tRP
X
X
X
Y
X
X
X
Y X
tRCD
Y
X
X
tRCD
X
X
X
Y
BA0,1
DQ
0
ACT#0 WRITE#0 with
ACT#1 WRITE#1 with
0 1
1
D0 D0 D0 D0
AutoPrecharge
0
D1 D1 D1 D1
ACT#0 WRITE#0
AutoPrecharge
Italic parameter indicates minimum case
0
1
D0 D0 D0 D0
ACT#1 WRITE#1
37
1
D1
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
/RAS
/CAS
CKE
CLK
DQM
Jun. '99
Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
/CS
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
tRC
128M Synchronous DRAM
/WE
A0-8
A10
X
X
tRRD
tRCD
tRRD
tRCD
BL+tRP
DQM read latency =2
Y
X
X
Y
BL+tRP
X
X
Y
tRCD
X
X
Y
A9,11
BA0,1
DQ
X
0
ACT#0 READ#0 with
ACT#1
X
0
1
Auto-Precharge
CL=3
1
CL=3
Q0 Q0 Q0 Q0
READ#1 with Auto-Precharge
X
0
Q1 Q1 Q1 Q1
ACT#0 READ#0
Italic parameter indicates minimum case
0
X
1
CL=3
Q0
ACT#1
1
Q0
38
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
CKE
CLK
Jun. '99
Page Mode Burst Write (multi bank) @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
/CS
tRRD
/RAS
tRCD
/CAS
/WE
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
DQM
A0-8
A10
A9,11
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0 WRITE#0
Y
X
X
X
0 0
1
D0 D0 D0 D0
ACT#1
Y Y
D0 D0 D0 D0 D0 D0 D0
WRITE#0
Y
1
D1 D1 D1 D1
WRITE#1
Italic parameter indicates minimum case
0
39
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
CKE
CLK
Jun. '99
Page Mode Burst Read (multi bank) @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
/CS
tRRD
/RAS
/CAS
/WE
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
tRCD
128M Synchronous DRAM
DQM
A0-8
A10
A9,11
BA0,1
DQ
DQM read latency=2
X
X
X
0
ACT#0 READ#0 READ#0
Y
X
X
X
0 0
1
CL=3 CL=3 CL=3
ACT#1
Y Y
Q0 Q0 Q0
Q0
READ#0
Y
1
Q0 Q0 Q0 Q0
READ#1
Italic parameter indicates minimum case
0
Q1 Q1 Q1 Q1
40
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
Write Interrupted by Write / Read @BL=4
/RAS
/CAS
CKE
CLK
DQM
Jun. '99
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
/CS
tRRD
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
/WE
A0-8
A10
A9,11
tRCD
X
X
X
Y
X
X
X
tCCD
Y Y
Y
Y
BA0,1
DQ
0
ACT#0 WRITE#0
ACT#1
Burst Write can be interrupted by Write or Read of any active bank.
0
1
D0 D0 D0 D0
0 0 0
D0 D0 D1 D1 Q0 Q0 Q0
WRITE#0 READ#0
WRITE#0
1
CL=3
WRITE#1
Italic parameter indicates minimum case
Q0
41
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
CKE
CLK
Jun. '99
Read Interrupted by Read / Write @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
/CS
tRRD
/RAS
/CAS
/WE
tRCD
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
DQM
A0-8
A10
A9,11
BA0,1
DQ
DQM read latency=2
X
X
X
0
ACT#0 READ#0 WRITE#0
ACT#1
Burst Read can be interrupted by Read or Write of any active bank.
Y
X
X
X
0 0
1
Y Y
Y
0
Q0 Q0 Q0
Q0
READ#0 READ#0
READ#0
Y
1
READ#1
Y
0
Q0 Q0 Q1 Q1
blank to prevent bus contention
0
Q0 D0 D0
Italic parameter indicates minimum case
42
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
/RAS
/CAS
CKE
CLK
DQM
Jun. '99
Write Interrupted by Precharge @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
/CS
tRRD
/WE
tRCD
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
A0-8
A10
A9,11
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0
ACT#1
Y
X
X
X
0
1
D0 D0 D0 D0
Burst Write is not interrupted by Precharge of the other bank.
Y
0
1
PRE#1
Burst Write is interrupted by Precharge of the same bank.
Italic parameter indicates minimum case
1 1
D1 D1 D1 D1 D1
PRE#0
WRITE#1
X
X
X
1
ACT#1 WRITE#1
Y
43
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
CKE
CLK
Jun. '99
Read Interrupted by Precharge @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
/CS
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
/RAS
/CAS
/WE
DQM
A0-8
A10
X
X
tRRD
tRCD
tRP
tRCD
DQM read latency=2
Y
X
X
Y
X
X
Y
A9,11
BA0,1
DQ
X
0
ACT#0 READ#0
X
1
0
ACT#1
Burst Read is not interrupted by Precharge of the other bank.
1
Q0 Q0 Q0
Q0
READ#1 ACT#1 READ#1
0
PRE#0
X
1
Q1 Q1
PRE#1
Burst Read is interrupted by Precharge of the same bank.
Italic parameter indicates minimum case
1
1
44
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
Mode Register Setting
CKE
CLK
Jun. '99
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
/CS
/RAS
/CAS
/WE
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
tRC
tRSC
128M Synchronous DRAM
tRCD
DQM
A0-8
A10
A9,11
BA0,1
DQ
Auto-Ref (last of 8 cycles)
M
0
Mode Register Setting
X
X
X
0
ACT#0 WRITE#0
Italic parameter indicates minimum case
Y
0
D0
D0 D0 D0
45
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
CKE
CLK
Jun. '99
Auto-Refresh @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
/CS
/RAS
/CAS
/WE
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
tRC
128M Synchronous DRAM
tRCD
DQM
A0-8
A10
A9,11
BA0,1
DQ
Auto-Refresh Before Auto-Refresh,
all banks must be idle state.
X
X
X
0
ACT#0 WRITE#0 After tRC from Auto-Refresh,
all banks are idle state.
Italic parameter indicates minimum case
Y
0
D0
D0 D0 D0
46
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
Self-Refresh
CKE
CLK
DQM
Jun. '99
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
/CS
/RAS
/CAS
/WE
A0-8
CLK can be stopped
tSRX
CKE must be low to maintain Self-Refresh
tRC
X
A10
A9,11
BA0,1
DQ
Self-Refresh Entry
Before Self-Refresh Entry, all banks must be idle state.
X
X
0
Self-Refresh Exit ACT#0
After tRC from Self-Refresh Exit, all banks are idle state.
Italic parameter indicates minimum case
47
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
CKE
CLK
Jun. '99
DQM Write Mask @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
/CS
/RAS
tRCD
/CAS
/WE
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
DQM
A0-8
A10
A9,11
BA0,1
DQ
X
X
X
0
ACT#0 WRITE#0 WRITE#0 WRITE#0
Y
0 0
D0 D0 D0 D0
Y
Y
0
masked
D0 D0 D0
Italic parameter indicates minimum case
masked
48
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
/RAS
/CAS
CKE
CLK
DQM
Jun. '99
DQM Read Mask @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
/CS
/WE
tRCD
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
A0-8
A10
A9,11
BA0,1
DQ
DQM read latency=2
X
X
X
0
ACT#0 READ#0 READ#0 READ#0
Y
0 0
Y
Q0 Q0 Q0 Q0
Y
0
masked
masked
Q0 Q0 Q0
Italic parameter indicates minimum case
49
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
/RAS
/CAS
CKE
CLK
DQM
Jun. '99
Power Down
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
/CS
/WE
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
A0-8
A10
A9,11
BA0,1
DQ
Standby Power Down
CKE latency=1
X
X
X
0
Precharge All ACT#0
Active Power Down
Italic parameter indicates minimum case
50
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
MITSUBISHI ELECTRIC
CLK Suspend @BL=4 CL=3
CKE
CLK
Jun. '99
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
/CS
/RAS
tRCD
/CAS
/WE
M2V28S20TP-6,-7,-8 M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
DQM
A0-8
A10
A9,11
BA0,1
DQ
CKE latency=1 CKE latency=1
X
X
X
0
ACT#0 WRITE#0 READ#0
Y
0 0
D0 D0 D0D0
Y
Q0 Q0 Q0 Q0
CLK suspendedCLK suspended
Italic parameter indicates minimum case
51
MITSUBISHI LSIs
128M Synchronous DRAM
MITSUBISHI ELECTRIC
Keep safety first in your circuit designs!
Notes regarding these materials
SDRAM (Rev. 1.0E)
M2V28S20TP-6,-7,-8
Jun. '99
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable,but there is always the possibility that trouble may occur with them. Trouble with semiconductors consideration to safety when making your circuit designs,with appropriate measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
1.These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application;they do not convey any license under any intellectual property rights,or any other rights,belonging to Mitsubishi Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third­party's rights,originating in the use of any product data,diagrams,charts or circuit application examples contained in these materials.
3.All information contained in these materials,including product data, diagrams and charts,represent information on products at the time of publication of these materials,and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubish Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein.
4.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for special applications, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
5.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
6.If these products or technologies are subject the Japanese export control restrictions,they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
52
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