(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
PRELIMINARY
Some of contents are described for general products and are
subject to change without notice.
M2V28S20ATP is organized as 4-bank x 8,388,608-word x 4-bit Synchronous DRAM with LVTTL
interface and M2V28S30ATP is organized as 4-bank x 4,194,304-word x 8-bit and M2V28S40ATP is organized
as 4-bank x 2,097,152-word x 16-bit. All inputs and outputs are referenced to the rising edge of CLK.
M2V28S20ATP,M2V28S30ATP,M2V28S40ATP achieves very high speed data rates up to 133MHz,
and is suitable for main memory or graphic memory in computer systems.
FEATURES
M2V28S20/30/40ATP
tCLK
tRAS
tRCD
tAC
tRC
Clock Cycle Time(Min.)
Row to Column Delay(Min.)
Access Time from CLK(Max.) (CL=3)
Ref/Active Command Period(Min.)
Operation Current(Max.)
V28S20
V28S40
7.5ns
5.4ns
67.5ns
100mA 95mA 95mA
110mA100mA
10ns
6ns
70ns
120mA
10ns
50ns
20ns
6ns
70ns
100mA
120mA
2mA
- Single 3.3V ±0.3V power supply
- Max. Clock frequency -6:PC133<3-3-3> / -7:PC100<2-2-2> / -8:PC100<3-2-2>
- Fully synchronous operation referenced to clock rising edge
- 4-bank operation controlled by BA0,BA1(Bank Address)
- /CAS latency- 2/3 (programmable)
- Burst length- 1/2/4/8/FP (programmable)
- Burst type- Sequential and interleave burst (programmable)
- Byte Control- DQML and DQMU (M2V28S40ATP)
- Random column access
- Auto precharge / All bank precharge controlled by A10
- Auto and self refresh
- 4096 refresh cycles /64ms
- LVTTL Interface
- Package
M2V28S20ATP/30ATP/40ATP
400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
1
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
CLK
: Master Clock
CKE
: Clock Enable
/RAS
: Row Address Strobe
DQ0-15
: Data I/O
DQM
: Output Disable/ Write Mask
A0-11
: Address Input
BA0,1
: Bank Address
VddQ
: Power Supply for Output
Nov. '99
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L
PIN CONFIGURATION (TOP VIEW)
128M Synchronous DRAM
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
M2V28S20ATP
M2V28S30ATP
M2V28S40ATP
PIN CONFIGURATION
(TOP VIEW)
Vdd
NC
VddQ
NC
DQ0
VssQ
NC
NC
VddQ
NC
DQ1
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)
A0
A1
A2
A3
Vdd
Vdd
DQ0
VddQ
NC
DQ1
VssQ
NC
DQ2
VddQ
NC
DQ3
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)
A0
A1
A2
A3
Vdd
Vdd
DQ0
VddQ
DQ1
DQ2
VssQ
DQ3
DQ4
VddQ
DQ5
DQ6
VssQ
DQ7
Vdd
DQML
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)
A0
A1
A2
A3
Vdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
2332
2431
2530
2629
2728
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Vss
DQ15
VssQ
DQ14
DQ13
VddQ
DQ12
DQ11
VssQ
DQ10
DQ9
VddQ
DQ8
Vss
NC
DQMU
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
Vss
DQ7
VssQ
NC
DQ6
VddQ
NC
DQ5
VssQ
NC
DQ4
VddQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
Vss
NC
VssQ
NC
DQ3
VddQ
NC
NC
VssQ
NC
DQ2
VddQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
2
/CS: Chip Select
/CAS: Column Address Strobe
/WE: Write Enable
MITSUBISHI ELECTRIC
Vdd: Power Supply
Vss: Ground
VssQ: Ground for Output
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
Mitsubishi DRAM
Nov. '99
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L
128M Synchronous DRAM
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
BLOCK DIAGRAM
Memory Array
4096 x1024 x8
Cell Array
Bank #0
Mode
Register
Address Buffer
Memory Array
4096 x1024 x8
Cell Array
Bank #1
DQ0-7
I/O Buffer
Memory Array
4096 x1024 x8
Cell Array
Control Circuitry
Bank #2
Control Signal Buffer
Memory Array
4096 x1024 x8
Cell Array
Bank #3
A0-11
Note : This figure shows the M2V28S30ATP.
The M2V28S20ATP configration is 4096x2048x4 of cell array and DQ 0-3.
The M2V28S40ATP configration is 4096x512x16 of cell array and DQ 0-15.
Type Designation Code
M2 V 28 S 3 0 A TP -8
BA0,1
Clock Buffer
CLKCKE
Access Item
Package Type
Process Generation
Function
Organization2: x4, 3: x8, 4: x16
Synchronous DRAM
Density 28 : 128Mbit
Interface V : LVTTL
/CS
These rules are only applied to the Synchronous DRAM family.
/RAS
/CAS
-6 : 7.5ns (PC133/3-3-3),
-7 : 10ns(PC100/2-2-2),
-8 : 10ns(PC100/3-2-2)
TP : TSOP(II)
A : 2nd. gen.
0 : Random Column
/WE
DQM
3
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
PIN FUNCTION
following cycle is ceased. CKE is also used to select auto /
Nov. '99
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L
128M Synchronous DRAM
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
CLKInput
CKEInput
/CSInput
/RAS, /CAS, /WEInputCombination of /RAS, /CAS, /WE defines basic commands.
A0-11Input
BA0,1Input
Master Clock:
All other inputs are referenced to the rising edge of CLK.
Clock Enable:
CKE controls internal clock. When CKE is low, internal clock for the
selfrefresh. After self refresh mode is started, CKE becomes
synchronous input. Self refresh is maintained as long as CKE is low.
Chip Select:
When /CS is high, any command means No Operation.
A0-11 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-11. The Column Address is
specified by A0-9,11 (x4) / A0-9 (x8) / A0-8 (x16).
A10 is also used to indicate precharge option. When A10 is high at a
read / write command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
Bank Address:
BA0,1 specifies one of four banks to which a command is applied.
BA0,1 must be set with ACT, PRE, READ, WRITE commands.
DQ0-7Input / Output
DQMInput
Vdd, VssPower SupplyPower Supply for the memory array and peripheral circuitry.
VddQ, VssQPower SupplyVddQ and VssQ are supplied to the Output Buffers only.
Data In and Data out are referenced to the rising edge of CLK.
Din Mask / Output Disable:
When DQM is high in burst write, Din for the current cycle is masked.
When DQM is high in burst read, Dout is disabled at the next but one
cycle.
4
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
128M Synchronous DRAM
To know the detailed definition of commands, please see the command truth table.
SDRAM (Rev. 1.0E)
Nov. '99
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
BASIC FUNCTIONS
The M2V28S30ATP provides basic functions, bank (row) activate, burst read / write, bank
(row) precharge, and auto / self refresh.
Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In
addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option,
respectively.
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on
the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
HXXXXDESELNOP (Idle after tRSC)
LHHHXNOPNOP (Idle after tRSC)
LHHLBATBSTILLEGAL
LHLXBA, CA, A10
LLHHBA, RAACTILLEGAL
LLHLBA, A10
LLLHXREFAILLEGAL
LLLL
Op-Code,
Mode-Add
READ /
WRITE
PRE /
PREA
MRSILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
12
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
FUNCTION TRUTH TABLE for CKE
/WE
Nov. '99
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L
128M Synchronous DRAM
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
Current State
SELF-
REFRESH*1
POWER
DOWN
ALL BANKS
IDLE*2
CKE
CKE
n-1
HXXXXXXINVALID
LHHXXXXExit Self-Refresh (Idle after tRC)
LHLHHHXExit Self-Refresh (Idle after tRC)
LHLHHLXILLEGAL
LHLHLXXILLEGAL
LHLLXXXILLEGAL
LLXXXXXNOP (Maintain Self-Refresh)
HXXXXXXINVALID
LHXXXXXExit Power Down to Idle
LLXXXXXNOP (Maintain Power Down)
HHXXXXXRefer to Function Truth Table
HLLLLHXEnter Self-Refresh
HLHXXXXEnter Power Down
HLLHHHXEnter Power Down
/CS/RAS /CAS
n
AddAction
HLLHHLXILLEGAL
HLLHLXXILLEGAL
HLLLXXXILLEGAL
LXXXXXXRefer to Current State =Power Down
ANY STATE
other than
listed above
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum
setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
HHXXXXXRefer to Function Truth Table
HLXXXXXBegin CLK Suspend at Next Cycle*3
LHXXXXXExit CLK Suspend at Next Cycle*3
LLXXXXXMaintain CLK Suspend
13
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
SIMPLIFIED STATE DIAGRAM
Nov. '99
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L
SELF
REFRESH
REFS
REFSX
128M Synchronous DRAM
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
WRITE
SUSPEND
MODE
REGISTER
SET
CLK
SUSPEND
CKEL
WRITEREAD
CKEH
WRITEA
MRS
CKEH
WRITE
CKEL
ACTIVE
WRITEA
WRITE
IDLE
ACT
ROW
READ
CKEH
READA
REFA
CKEL
READ
AUTO
REFRESH
POWER
DOWN
READA
CKEL
CKEH
READ
SUSPEND
WRITEA
SUSPEND
POWER
APPLIED
CKEL
CKEH
POWER
14
WRITEA
ON
WRITEAREADA
PRE
PREPRE
PRE
PRE
CHARGE
MITSUBISHI ELECTRIC
READA
CKEL
CKEH
READA
SUSPEND
Automatic Sequence
Command Sequence
MITSUBISHI LSIs
128M Synchronous DRAM
SDRAM (Rev. 1.0E)
Nov. '99
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a
SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at
the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200µs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be
programmed by setting the mode register (MRS). The mode
register stores these data until the next MRS command, which
may be issued when all banks are in idle state. After tRSC
from a MRS command, the SDRAM is ready for new
command.
A11 A10 A9A8A7 A6A5A4 A3A2A1 A0BA1BA0
00000LTMODEBTBL00
LATENCY
MODE
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
/CAS LATENCY
R
R
2
3
R
R
R
R
BURST
LENGTH
BURST
TYPE
CLK
/CS
/RAS
/CAS
/WE
BA0,1 A11-A0
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
SEQUENTIAL
INTERLEAVED
1
V
BT= 0BT= 1
1
2
4
8
R
R
R
FP
1
2
4
8
R
R
R
R
15
R: Reserved for Future Use
MITSUBISHI ELECTRIC
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
Nov. '99
CLK
M2V28S20ATP -6,-6L,-7,-7L,-8,-8L
M2V28S30ATP -6,-6L,-7,-7L,-8,-8L
M2V28S40ATP -6,-6L,-7,-7L,-8,-8L
128M Synchronous DRAM
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)