MITEL ACE9030IW, ACE9030FP2Q, ACE9030FP2N, ACE9030FP1Q, ACE9030FP1N Datasheet

...

ACE9030 is a combined radio interface circuit and twin

synthesiser, intended for use in a cellular telephone.

The radio interface section contains circuits to monitor and control levels such as transmit power in the telephone, circuits to demodulate the frequency modulated signal to audio, and a crystal oscillator with a frequency multiplier.

The Main synthesiser has normal and fractional-N modes both with optional speed-up to select the desired channel. The Auxiliary synthesiser is used for the transmit-receive offset and for modulation.

Both sections are controlled by a serial bus and have software selected power saving modes for battery economy. The circuit techniques used have been chosen to minimise external components and at the same time give very high performance.

Fig.1 Pin connections - top view

ORDERING INFORMATION

Industrial temperature range TQFP 64 lead 10 x 10 mm, 0·5 mm pitch

ACE9030M/IW/FP1N - shipped in trays and dry packed ACE9030M/IW/FP1Q - tape & reel and dry packed

TQFP 64 lead 7 x 7 mm, 0·4 mm pitch

ACE9030M/IW/FP2N - shipped in trays and dry packed ACE9030M/IW/FP2Q - tape & reel and dry packed

APPLICATIONS

■ AMPS and TACS Cellular Telephone

■ Two-way Radio Systems

RELATED PRODUCTS

ACE9030 is part of the following chipset:

■ ACE9020 Receiver and Transmitter Interface

■ ACE9040 Audio Processor

■ ACE9050 System Controller and Data Modem

VP64 FP64

FEATURES

■ Low Power Low Voltage (3·6 to 5·0 V) Operation

■ Serial Bus Controlled Power Down Modes

■ Simple Programming Format

■ Reference Crystal Oscillator

■ Frequency Multiplier for LO2 Signal

■ 8·064 MHz Output for External Microcontroller

■ Main Synthesiser with Fractional-N Option

■ Auxiliary Synthesiser

■ Main Synthesiser Speed-up Options

■ FM Discriminator for 450 kHz or 455 kHz I.F. Signal

■ Radio System Control Interface

■ Part of the ACE Integrated Cellular Phone Chipset

■ TQFP 64 pin 0·4 mm and 0·5 mm pitch packages

Note: Pin 1 is identified by moulded spot and by coding orientation

DOUT5

DOUT6

DOUT7

FIAB

FIA

VDDSA

VSSSA

FIMB

FIM

VSSD

PDI

PDP

RSMA

DECOUP

RSC

VDDD

DOUT0 VDDX DOUT1 VDDA VSSA LO2 ADC1 ADC3A ADC3B ADC5 DOUT8 DAC2 DAC1 DOUT2 CIN1 CIN2

MODMP

MODMIN

TEST

PDA

VDDSUB

DOUT3 DOUT4 AMPP2 AMPN2

DAC3 AMPP1 AMPN1

AMP01 ADC2A ADC2B

ADC4

AMP02

RXCD

LATCHC

LATCHB

DATA

AFCOUT

AUDIO

AFCIN

IREF

VSSL

VDDL

CLK8

C8B

VDDSUB2

ACE9030

Fig. 2 ACE9030 Simplified Block Diagram

POLLING

ADC

BUS

INTERFACE

LOCK

DETECT

TWIN

SYNTHESISER

DIGITAL

OUTPUTS

CRYSTAL

MULTIPLIER

CRYSTAL

OSCILLATOR

8 MHz

PLL

TRIMMING

DACs

AFC

MIXER

AMP &

LIMITER

AUDIO

DEMOD.

−

L.F . AMPS

ACE9030

Radio Interface and Twin Synthesiser

Supersedes February 1997 edition, DS4288 - 1.4 DS4288 - 2.0 January 1998

ACE9030

Fig.3 ACE9030 Block diagram

−

MAIN SYNTHESISER

with FRACTIONAL-N

SERIAL BUS INPUT

REGISTERS (SYTHS)

SERIAL BUS I/O TO RADIO INTERFACE

BAND-GAP

REFERENCE

LOCK

DETECT

AUXILIARY

SYNTHESISER

REFERENCE

DIVIDER

FILTER

DEFINE

LEVELS

DATA & CONTROL

DEMOD

MIXER

TEST

SEL.

MULT x3, x5

VDDL VSSL

SWITCHES

ADC1

INPUT SCANNER

8 Bit A to D Converter

DEMULTIPLEXER

REGISTERS

SELECTOR

VREF

RXCD VDDX

DOUT0 DOUT1 DOUT2 DOUT3

DOUT4 DOUT5

DOUT6

DOUT8

AUDIO

BP AFCOUT

DAC1

DAC2

VSSD

VDDD

MODMN

MODMP

PDI

PDP

RSMA

RSC

DAC3

DAC2

DAC1

BIAS

GEN.

PDA

DOUT7

AMPO2

AMPO1

VSSL

VDDL

IREF

VSSA

VDDA

LEVEL SENSE

AMPP1

OSC8

PLL.

AMPN1

AMPP2

ADC2A

AMPN2

ADC1

ADC2B ADC3A

ADC4 ADC5

ADC3B

CRYSTAL

OSC.

AFCIN

C8B

CLK8

LO2

CIN2

CIN1

LATCHB

VDDSUB2

VDDSUB

DECOUP

VDDSA VSSSA

FIM

FIMB

DATA

LATCHC

TEST

FIA

FIAB

ACE9030

PIN DESCRIPTIONS

The relevant supplies (VDD) and grounds (VSS) for each circuit function are listed. All VDD and VSS pins should be used.

Pin No. Name Description VDD VSS

1 AMPO2 LF amplifier 2 output. VDDA VSSA 2 RXCD Receive carrier detect (ADC1 comparator) output. VDDL VSSL 3 LATCHC Synthesiser programme enable input. VDDL VSSL 4 LATCHB Radio interface programme enable input. VDDL VSSL 5 DATA Serial data; programming input, results output. VDDL VSSL 6 CL Clock input for programming bus and for I.F. sampling. VDDL VSSL 7 AFCOUT Output from AFC amplifier after sampling. VDDL VSSL 8 AUDIO Output from f.m. discriminator after filtering. VDDA VSSA

9 BP Feedback input to audio bandpass filter. VDDA VSSA 10 AFCIN Input to AFC amplifier and f.m. discriminator. VDDL VSSL 11 IREF Bias current input for radio interface, connect setting resistor to ground. – VSSA 12 VSSL Ground for radio interface logic. – – 13 VDDL Power supply to radio interface logic. – – 14 CLK8 Output clock at 8·064 MHz, locked to crystal. VDDL VSSL 15 C8B 8·064 MHz oscillator charge pump output and control voltage input. VDDA VSSA 16 VDDSUB2 Second connection for clean positive supply to bias substrate. VDDA VSSA 17 CIN2 Connection for crystal oscillator. VDDL VSSL 18 CIN1 Connection for crystal oscillator. VDDL VSSL 19 DOUT2 Digital control output 2. VDDL VSSL 20 DAC1 Analog control output 1. VDDA VSSA 21 DAC2 Analog control output 2. VDDA VSSA 22 DOUT8 Digital control output 8. VDDA VSSA 23 ADC5 Analog to digital converter input 5. VDDA VSSA 24 ADC3B Analog to digital converter input 3B. VDDA VSSA 25 ADC3A Analog to digital converter input 3A. VDDA VSSA 26 ADC1 Analog to digital converter input 1. VDDA VSSA 27 LO2 Output from crystal frequency multiplier. VDDA VSSA 28 VSSA Ground for radio interface analog parts. – – 29 VDDA Power supply to radio interface analog parts. – – 30 DOUT1 Digital control output 1. VDDX – 31 VDDX Power supply to DOUT1 and DOUT2 switches. – – 32 DOUT0 Digital control output 0. VDDX – 33 VDDD Power supply to synthesisers, except input buffers and the bandgap. – – 34 RSC Fractional-N compensation bias current, resistor to ground. – VSSSA 35 DECOUP Bandgap reference decoupling capacitor connection. VDDSA VSSSA 36 RSMA Bias current for synthesiser charge pumps, resistor to ground. – VSSSA 37 PDP Main synthesiser proportional charge pump output. VDDD VSSD 38 PDI Main synthesiser integral charge pump output. VDDD VSSD 39 VSSD Ground for synthesisers, except input buffers and the bandgap. – – 40 FIM Main synthesiser positive input from prescaler. VDDSA VSSSA 41 FIMB Main synthesiser negative input from prescaler. VDDSA VSSSA 42 VSSSA Ground for FIM and FIA input buffers and the bandgap. – – 43 VDDSA Power for FIM and FIA input buffers and the bandgap. – – 44 FIA Auxiliary synthesiser positive input from VCO. VDDSA VSSSA 45 FIAB Auxiliary synthesiser negative input from VCO. VDDSA VSSSA 46 DOUT7 Digital control output 7. VDDD VSSD 47 DOUT6 Digital control output 6. VDDD VSSD 48 DOUT5 Digital control output 5. VDDD VSSD 49 MODMP Modulus control output to prescaler - positive sense. VDDD VSSD 50 MODMN Modulus control output to prescaler - negative sense. VDDD VSSD 51 TEST Test input and output for synthesisers. VDDD VSSD 52 PDA Auxiliary synthesiser charge pump output. VDDD VSSD 53 VDDSUB Clean positive supply to bias substrate. – – 54 DOUT3 Digital control output 3. VDDL VSSL 55 DOUT4 Digital control output 4. VDDL VSSL 56 AMPP2 LF amplifier 2 positive input. VDDA VSSA 57 AMPN2 LF amplifier 2 negative input. VDDA VSSA 58 DAC3 Analog control output 3. VDDL VSSL 59 AMPP1 LF amplifier 1 positive input. VDDA VSSA 60 AMPN1 LF amplifier 1 negative input. VDDA VSSA 61 AMPO1 LF amplifier 1 output. VDDA VSSA 62 ADC2A Analog to digital converter input 2A. VDDA VSSA 63 ADC2B Analog to digital converter input 2B. VDDA VSSA 64 ADC4 Analog to digital converter input 4. VDDA VSSA

ACE9030

Fig.4 Typical VDD local decoupling networks without series resistors

Fig.5 Typical VDD local decoupling networks with series resistors

ABSOLUTE MAXIMUM RATINGS

Supply voltage from ground – 0·3 V to + 6·0 V (any V

to any VSS) Supply voltage difference – 0·3 V to + 0·3 V (any V

to any other VDD) Input voltage V

– 0·3 V to VDD + 0·3 V (any input pin to its local VSS and VDD) Output voltage V

– 0·3 V to VDD + 0·3 V (any output pin to its local V

and VDD) Storage temperature – 55 °C to + 150 °C Operating temperature – 40 °C to + 85 °C

tions V

DDSUB

and V

DDSUB2

must be the most positive of all VDD’s at all times including during power on and off ramping. As the current taken through these V

’s is significantly less than through the other VDD’s this requirement can be easily met by directly connecting all V

pins to a common point on the circuit board but with the decoupling capacitors distributed to minimise cross-talk caused by common mode currents. If low value series resistors are to be included in the V

connections, with decoupling capacitors by the ACE9030 pins to further reduce interference, the V

DDSUB

and V

DDSUB2

pins should not have such a resistor in order to guarantee that their voltage is not slowed down at power-on. Power switches to DOUT0 and DOUT1 are supplied from V

DDX

and are specified

for a total current of up to 40 mA so any resistor in the V

DDX

connection must be very low, around 1Ω, in order to avoid excessive voltage drop; it is recommended that this supply has no series resistor. These two methods are shown in circuit diagrams, figures 4 and 5. In both circuits the main V

must

also have good decoupling.

These are not the operating conditions, but are the absolute limits which if exceeded even momentarily may cause permanent damage. To ensure sustained correct operation the device should be used within the limits given under Electrical Characteristics.

To avoid any possibility of latch-up the substrate connec-

Main VDD

VDDSUB VDDSUB2 VDDL VDDA VDDX VDDD VDDSA

Main VDD

No Resistor No Resistor

Very Small

ACE9030

Parameter Min. Typ. Max. Unit Conditions Power supply

Supply current, Radio Interface: Sleep mode 2.3 2·7 mA XO, OSC8 on Fully operating (excluding I

DDX

) 7 mA (see Note 1)

Supply current, Synthesisers: V

=5V f

REF

= 10 MHz

Main and Auxiliary ON 5 mA f

MAIN

= 10 MHz

Main ON and Auxiliary in Standby 3.7 mA f

AUX

= 10 MHz Main in Standby and Auxiliary ON 3 mA (see Note 2) Main and Auxiliary in Standby, with Bandgap off 100 µA Supply current, Synthesisers: f

REF

= 15 MHz Main and Auxiliary ON 3 mA f

MAIN

= 16 MHz

Main ON and Auxiliary in Standby 2 mA f

AUX

= 90 MHz Main in Standby and Auxiliary ON 2 mA (see Note 2) Main and Auxiliary in Standby 100 µA

Input and output signals

Logic input HIGH (LATCHC, LATCHB, DATA, CL, and TEST) 0·7 x V

VDD + 0·3 V Logic input LOW (LATCHC, LATCHB, DATA, CL, and TEST) – 0·3 + 0·8 V Input capacitance (signal pins) 10 pF Pin voltage Input leakage (signal pins) 1 µAVSS to V

Logic output HIGH (RXCD, DATA, AFCOUT, VDD – 0·5 V TEST and DOUT2, 3 and 4) External load: Logic output LOW (RXCD, DATA, AFCOUT, 0·4 V 20 kΩ & 30 pF TEST and DOUT2, 3 and 4) Output ON level, DOUT0 and DOUT1 V

DDX

– 0·2 V IOH = 20 mA. Output HIGH level, DOUT5, 6 and 7 2·3 2·9 V IOH = 80 µA Output LOW level, DOUT5, 6 and 7 0·3 V IOL = 0.2 µA Trimmed output level ON, DOUT8 3·35 3·55 V IOH = 135 to 400 µA. Level difference, DOUT8 ON – ADC reference – 5 + 15 mV Output level OFF, DOUT8 0.4 V MODMP, MODMN output HIGH VDD/2 + 0·35 VDD/2 + 1·0 V IOH = 10 µA MODMP, MODMN output LOW VDD/2 – 1·0 VDD/2 – 0·35 V IOL = – 10 µA Input Schmitt Hysteresis, pins CL, LATCHB, 0·3 V LATCHC, DATA. Analog circuits bias resistor on I

REF

68 kΩ VDD @ 3·75 V

100 kΩ V

@ 4·85 V

ELECTRICAL CHARACTERISTICS

These characteristics apply over these ranges of conditions (unless otherwise stated):

AMB

= – 40 °C to + 85 °C, VDD = + 3·6 to + 5·0 V, GND ref. = V

D.C. Characteristics

Notes

1. The sleep current is specified with the crystal oscillator (XO) and the OSC8 oscillator and PLL running as these are normally needed to provide the clock to the system controller.

2. The terms f

REF

, f

MAIN

, and f

AUX

refer to the frequencies of the Reference inputs (Crystal oscillator, pins CIN1 and CIN2), the Main synthesiser

inputs (pins FIM and FIMB) and the Auxiliary synthesiser inputs (pins FIA and FIAB) respectively.

ACE9030

Parameter Min. Typ. Max. Unit Conditions

Synthesiser charge pump current

Current setting resistor R

SMA

19 39 78 kΩ Note 3

Current setting resistor R

19 39 78 kΩ Note 3

External capacitance on pin R

SMA

5 pF Ensures stable

External capacitance on pin R

5 pF bias current.

Bias current I

RSMA

(nominally 1·25V / R

SMA

) 28·8 32 35·2 µAR

SMA

= 39 kΩ

Bias current I

RSC

(nominally 1·25V / RSC) 28·8 32 35·2 µARSC = 39 kΩ Iprop(0) scaling accuracy, pin PDP –10 +10 % @ 200 µA. Note 4 Iprop(1) scaling accuracy, pin PDP –10 +10 % @ 800 µA. Note 4 Iint scaling accuracy, pin PDI –10 +10 % @ 4 mA. Note 4 Icomp(0) scaling accuracy, pin PDP –10 +10 % @ ACC x 0·2 µA

Note 4

Icomp(1) scaling accuracy, pin PDP –10 +10 % @ ACC x 0·8 µA

Note 4

Icomp(2) scaling accuracy, pin PDI –10 +10 % @ ACC x 4 µA

Note 4 Iauxil scaling accuracy, pin PDA –5 +5 % @ 256 µA. Note 4 Auxiliary Charge Pump, –10 +10 % Note 5 Up or Down I

AUX

current variation Main Charge Pumps, –10 +10 % Note 6 Up or Down I

MAIN

or I

INTEGRAL

current variation Iprop(0) or Iprop(1) setting from PDP pin 1·0 mA Iint setting from PDI pin 5 mA Icomp(0) or Icomp(1) setting from PDP pin 12 µA Icomp(2) setting from PDI pin 180 µA Iauxil setting from PDA pin 512 µA

ELECTRICAL CHARACTERISTICS

These characteristics apply over these ranges of conditions (unless otherwise stated):

AMB

= – 40 °C to + 85 °C, VDD= + 3·6 to + 5·0 V, GND ref. = V

D.C. Characteristics (continued)

Notes

3. The circuit is defined with resistors R

SMA

and RSC connected from pins RSMA and RSC to V

SSSA

but in most practical applications all VSS pins

will be connected to a ground plane so R

SMA

and RSC should then also be connected to this ground plane.

4. The charge pump currents are specified to this accuracy when the relevant output pin is at a potential of VDD/2 and with R

SMA

= 39 kΩ, CN = 200, L= 1, K = 5, RSC = 19 kΩ. The nominal value is set by external resistors and by programming registers, as defined in Table 6. Tolerances in the internal Bandgap voltage and bias circuits are within the limits given for I

RSMA

and I

RSC

, the scaling accuracy of the multiplying DAC’s

is within these limits given for Iprop(0), Iprop(1), Iint, Icomp(0), Icomp(1), Icomp(2), and auxil.

5. The Auxiliary charge pump output voltage is referred to as V

PDA

and the output current I

AUX

is the Up or Down current measured when

PDA

= VDD/2. The conditions for the variation limits for the Up current are: either I

AUX

= 128 or 256 µA and 0 < V

PDA

< VDD – 0·5 V

or I

AUX

= 512 µA and 0 < V

PDA

< VDD – 0·65 V The conditions for the variation limits for the Down current are: either I

AUX

= 128 or 256 µA and 0·5 V < V

PDA

< V

or I

AUX

= 512 µA and 0·65 V < V

PDA

< V

6. The Main charge pump output voltage at pin PDP is referred to as V

PDP

and at pin PDI as V

PDI.

The output currents I

MAIN

and I

INTEGRAL

are the

up or down current Iprop(0), Iprop(1) or Iint measured when V

PDP

or V

DPI

= VDD/2.

The conditions for the variation limits for the Up current are :

MAIN

= 100 to 1000 µA or I

INTEGRAL

= 1 to 5 mA and 0 < V

PDP

< VDD – 0·45 V

The conditions for the variation limits for the Down current are:

MAIN

= 100 to 1000 µA or I

INTEGRAL

= 1 to 5 mA and 0·45 V < V

PDP

< V

ACE9030

Parameter Min. Typ. Max. Unit Conditions CONTROL BUS

Clock rate CL input 1008 kHz Clock duty cycle CL input 40 50 60 % tDS, input data set-up time 80 ns See Fig. 7 tDH, input data hold time 80 ns See Fig. 7 t

CWL

, t

CWH

, CL input pulse width (to bus logic) 400 600 ns See Fig. 7 tCL, delay time, clock to latch 440 ns See Fig. 7 tLW, latch pulse high time 230 ns See Fig. 7 tLH, delay time, latch to clock 220 ns See Fig. 7 t

DSO

, output data set-up time 80 ns See Fig. 8

DHO

, output data hold time 80 ns See Fig. 8 tZS, DATA line available to ACE9030 80 1200 ns See Fig. 8 tZH, DATA line released by ACE9030 80 1200 ns See Fig. 8 t

, delay from received message to 4 4 cycles See Figs. 8 and 10 transmitted response of CL Rise and Fall times, all digital inputs: 50 ns

DIGITAL OUTPUTS

DOUT0 and 1 On time to V

– 0·2 V 100 µs 100 nF load and from DOUT0 and 1 Off time to > 1 MΩ 100 µs LATCHB rising edge DOUT5, 6 and 7 rise and fall times 10 µs 30 pF load and to D.C. DOUT8 rise and fall time 10 µs specification noise

A to D CONVERTER

Lowest transition, 0000 0000 to 0000 0001 0·07 0·15 0·23 V Bandgap multiplier Highest transition, 1111 1110 to 1111 1111 3·35 3·45 3·55 V correctly trimmed ADC conversion time (20 cycles of CL) 20 µs CL = 1008 kHz Input scanning rate (CL ÷ 40) 25·2 kHz CL = 1008 kHz Integral Non-linearity – 1 + 1 LSB Differential Non-linearity – 0·8 + 0·8 LSB Power supply sensitivity 3 LSB/0.3V 0 to 10 kHz

CRYSTAL OSCILLATOR

Start-up time of crystal oscillator 5 ms Crystal effective series resistance (ESR) 25 Ω Power dissipation in crystal 50 150 µW

D to A CONVERTERS

Full scale output level, DAC1, DAC2 & DAC3 3·35 3·45 3·55 V Bandgap multiplier Zero scale output level, DAC1 1·0 1·2 V trimmed to nominal Zero scale output level, DAC2 & DAC3 0·3 0·5 V reference voltage Integral Non-linearity – 1 + 1 LSB Differential Non-linearity – 0·5 + 0·5 LSB Output wideband and clock noise: 50 Hz to 1·1 MHz, flat integration 3 mV

rms

Power supply rejection ratio 30 dB 50 Hz to 25 kHz. Settling time to within 10% of end of step 6 µs DAC1 and DAC2 (DAC3 with external 15 kΩ resistor) 10 pF load Output load capacitance, DAC1 and DAC2 100 nF Output load capacitance, DAC3 30 pF To guarantee stability Internal series resistor, DAC1 and DAC2 7 15 40 kΩ DAC3 output current, sink or source 1·0 mA

ELECTRICAL CHARACTERISTICS

These characteristics apply over these ranges of conditions (unless otherwise stated):

AMB

= – 40 °C to + 85 °C, VDD= + 3·6 to + 5·0 V, GND ref. = V

A.C. Characteristics

ACE9030

ELECTRICAL CHARACTERISTICS

These characteristics apply over these ranges of conditions (unless otherwise stated):

AMB

= – 40 °C to + 85 °C, all VDD= + 3·6 to + 5·0 V, GND ref. = V

A.C. Characteristics (continued)

Note

7. AUDIO signal quality is measured with feedback components as shown in figure 18 and with 500 mV peak to peak input to AFCIN. Discriminator gain is set with D = 3 and M = 40 and VDD = 3·75 V and a crystal at 14·85 MHz. SINAD is defined as the ratio of wanted signal to all unwanted output, measured simultaneously with filters. The hum and noise figure is defined as the ratio of output power at AUDIO when AFCIN is unmodulated to the output power when AFCIN is driven as specified above.

Parameter Min. Typ. Max. Unit Conditions LOW FREQUENCY AMPLIFIERS (1 and 2)

Voltage Gain 1200 2800 Input Offset 10 20 mV Open loop input resistance 1 MΩ Open loop output resistance 8 kΩ Unity Gain bandwidth 2 MHz Input bias current, inverting input 200 nA Power supply rejection at 120 Hz, 10 kHz 40 50 dB Output voltage maximum V

DDA

– 0·2 V 10 kΩ to 6ND

Output voltage maximum, as a comparator V

DDA

– 0·1 V 10 kΩ to 6ND Output voltage minimum level 0·2 V 10 kΩ to 6ND Output voltage minimum level 0·1 V 10 kΩ to 6ND Common mode input range (LF1 1) V

SSA

2.5 V

Common mode input range (LF1 2) V

SSA

DDA

Output slew rate 0.15 0.25 V/µs Output load capacitance 30 pF

8 MHz OSCILLATOR and PLL

OSC8 centre frequency 8·064 MHz OSC8 VCO sensitivity 25

MHz/V

OSC8 charge pump output current 50 µA CLK8 output load, resistive: 15 25 100 kΩ capacitive: 15 25 30 pF CLK8 output amplitude 0·8 1·0 2·4 V

pk-pk

CLK8 total output jitter 500 Hz 0 - 3 kHz Start-up time at power-on, to default settings 15 ms With a loop filter as

described in fig. 17 Lock time to within 125 ppm, after reprogramming set-ups 15 ms

AFCIN F.M. DISCRIMINATOR and AFC

AFCIN input signal level 0·05 2·5 V

pk-pk

AFCIN input impedance, resistive: 50 kΩ capacitive: 10 pF Input frequency 400 500 kHz Input signal to integrated noise ratio 10 dB I.F. ± 15 kHz. Input Schmitt Hysteresis 8 mV AUDIO signal SINAD, psophometric, note 7 40 45 dB 1 kHz tone at 3 kHz AUDIO signal hum and noise, note 7 – 46 dB peak deviation on AUDIO output signal level, note 7 195 260 mV

rms

AFCIN input at I.F. AFCOUT load 30 pF AFCOUT duty cycle 37 63 % AFCOUT rise and fall times 75 ns

ACE9030

ELECTRICAL CHARACTERISTICS

These characteristics apply over these ranges of conditions (unless otherwise stated):

AMB

= – 40 °C to + 85 °C, all VDD= + 3·6 to + 5·0 V, GND ref. = V

A.C. Characteristics (continued)

Note

8. To simplify single ended drive there is a resistor between FIA and FIAB and another between FIM and FIMB. In this mode the inputs should drive FIA or FIM with D.C. coupling and the other inputs FIAB and FIMB should be decoupled to ground by external capacitors.

Parameter Min. Typ. Max. Unit Conditions LO2 Multiplier

Amplitude 235 500 mV

rms

Circuit as in fig. 15, Reference frequency content of output -10.5 dBc 2nd, 4th harmonic content of output -13.5 dBc 5th harmonic of output -15 dBc 6th and higher harmonics in output -20 dBc

SYNTHESISERS Reference divider

Reference divider input frequency 5 30 MHz Drive level into CIN1 from external oscillator 400 mV

pk-pk

With crystal oscillator

powered down CIN1 input capacitance 10 pF CIN1 input resistance 10 kΩ

Auxiliary synthesiser

FIA input frequency 10 135 MHz May be a sinewave Rise and fall times of inputs 10 ns Timing Skew between FIA and FIAB ± 2 ns See Fig. 6

or ± 10% signal Both maxima

period must be met

FIA, FIAB differential signal level with both 180 mV

pk-pk

Each input, 5 to 50 & sides driven 99 to 135 MHz

100 mV

pk-pk

Each input,

50 to 99 MHz FIA single input drive level with FIAB 360 mV

pk-pk

One input, 5 to 50 & decoupled to V

99 to 135 MHz

200 mV

pk-pk

One input,

50 to 99 MHz FIA, FIAB common mode range VDD – 1·7 VDD – 0·7 V VDD = 3.6V FIA, FIAB common mode range 2.8 VDD – 0·85 V VDD = 5V FIA, FIAB input capacitance 10 pF FIA, FIAB differential input resistance 10 kΩ Note 8 Auxiliary Synthesiser comparison frequency 2 MHz

Main Synthesiser

FIM input frequency 4 20 MHz Rise and fall times of inputs 50 ns FIM - FIMB Timing Skew ± 2 ns See Fig. 6

or ± 10% signal Both maxima

period must be met

FIM, FIMB differential signal level 100 mV

pk-pk

Each input, with both sides driven. 4 to 20 MHz FIM single input drive level 200 1000 mV

pk-pk

One input, with FIMB decoupled to V

4 to 20 MHz FIM, FIMB common mode range VDD – 1·7 VDD – 0·7 V VDD =3.6V FIM, FIMB common mode range 2·8 VDD – 0·85 V VDD =5V FIM, FIMB input capacitance 10 pF FIM, FIMB differential input resistance 10 kΩ Note 8 Delay FIM rising to MODMP/MODMN changing 30 ns Main Synthesiser comparison frequency 2 MHz

ACE9030

Fig. 6 Synthesiser Inputs

Fig. 7 Control Bus input timing

Fig. 8 Control Bus output timing

TIMING WAVEFORMS

SIGNAL PERIOD

PEAK to PEAK

AMPLITUDE

FIM or FIA

FIMB or FIAB

TIMING SKEW

DATA D2

D1 D0

LATCHB or LATCHC

CWL

CWH

DHO

DSO

234

28 29

MSB

LSB

OUTPUT FROM ACE9030

DATA UNDEFINED

INTO ACE9030

DATA

DATA OUTPUT DRIVE FROM ACE9030

LATCHB

ACE9030

FUNCTIONAL DESCRIPTION - CONTROL BUS

The functions of the ACE9030 fall into two separate

groups, the Radio Interface and the Synthesisers.

The common control bus splits the input strings differently for these two sections so this bus operation is described first as an introduction to the available features.

All functions are controlled by a serial bus; DATA is a bidirectional data line, to input all control data and to output the results of measurements in the Radio Interface section, CL is the clock, and LATCHB and LATCHC are the latch signals at the end of each control word for either the Radio Interface or the Synthesiser section respectively.

CL is a continuously running clock at typically 1·008 MHz, and all incoming and output data are latched on rising edges of this clock. The controller should clock data in and out on falling clock edges. For bus control purposes the frequency of

CL may be widely varied and this clock does not need to be continuous, however, the sampled I.F. signal AFCOUT, the Polling ADC, and the Lock Detect Filter also use CL as the sampling clock. In systems where any of these are required the clock CL is constrained to be 1·008 MHz and to be continuous.

To ensure clean initialisation the clock CL should give at least 8 cycles before the power-up command and similarly to set the control logic to known states there should be 8 cycles of CL after a power-down command.

During normal operation there should be at least 30 cycles of CL between latch pulses, 24 for the data bits (see figures 9,10 & 11) plus 6 extra. This minimum becomes 36 cycles if the extended synthesiser programming command (A2) is used.

Radio Interface Bus - Receive

Fig.9 Radio Interface receive bus timing

The received data is split into three bytes, where DATA1 normally contains a value to be loaded into a destination set by DATA2 and DATA3. When a command does not need to put any information into byte DATA1 a preamble xx1010xx is recommended to fill this byte. It is possible to set-up several features in one bus operation and to allow this the decoding only acts on single or selected bits; the others are given as “x” in the block descriptions. Two bits of DATA2 also set the type of command, with four options:

DATA2 DATA2 Type of Comment

bit 7 bit 6 Command

0 0 SLEEP No reply 0 1 NORMAL Send requested data 1 0 SET-UP No reply 1 1 TEST No reply

and the CLK8 output driver will be active, and are used to clock the microcontroller. To reduce the supply current to its minimum in Sleep the synthesisers must also be powered down, by a Word D message with DA and DM both set HIGH as described under Synthesiser Bus - Receive Only. During Sleep all set-up values are retained unless changed by a Setup command. The exit from Sleep is by any Normal command.

Normal commands will end Sleep mode but are primarily used to change the operating mode of the cellular terminal or to request ADC data. The ACE9030 will output data onto the serial bus after a Normal command.

Set-up commands are used to adjust various operating parameters but can also initiate a logic restart if DATA3 bits 1 and 0 are both “1” so for routine changes of set-ups these bits should always be 00.

Test mode is included only for use during chip manufacture.

Sleep mode is selected to put the cellular terminal into a very low power state for when it is “Off” and neither waiting for, nor setting up a call. In Sleep only the crystal and 8·064 MHz oscillators, DAC1 and DAC2, the OSC8 phase locked loop,

The Sleep Command - DATA2 bits 7, 6 = 00

DATA1 DATA2 DATA3

xx1010xx 00xxxxxx xxxxxxxx

DATA

LATCHB

DATA1 DATA2 DATA3

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

ACE9030

Summary of Normal Commands - DATA2 bits 7, 6 = 01

Normal commands are always a request for data; the ADC registers to be read are defined by Y1 and Y0 in DATA3. A normal

command will also end Sleep mode.

BIT EFFECT when at 0 EFFECT when at 1

DATA2:

7 With DATA2:6 defines command type 6 - With DATA2:7 defines command type 5 Discriminator powered down Discriminator active. 4 - Load Lock threshold register from DATA1:7-1 3 DAC3 powered down DAC3 active 2 - Load DOUT7-0 from DATA1:7-0 1 - Load DAC3 from DATA1:7-0 0 Not used Not used

DATA3:

7 Not used Not used 6 LO2 multiplier powered down LO2 multiplier active 5 Set DOUT8 to OFF Set DOUT8 to ON, to output the ADC reference voltage 4 - Load ADC1 comparator from DATA1:7-0 3 - Load DAC1 from DATA1:7-0 2 - Load DAC2 from DATA1:7-0 1 Y1 Decode with DATA3:0 for Polling ADC register read 0 Y0 Decode with DATA3:1 for Polling ADC register read

BIT EFFECT when at 0 EFFECT when at 1

DATA2:

7 - With DATA2:6 defines command type 6 With DATA2:7 defines command type 5 Not used Not used 4 - Set OSC8 VCO range from DATA1:5-0 3 - Set OSC8 VCO offset from DATA1:5-0 2 Select input A for ADC3 Select input B for ADC3 1 Select input A for ADC2 Select input B for ADC2 0 OSC8 off OSC8 on

DATA3:

7 Crystal oscillator off Crystal oscillator on 6 Bandgap off - use external reference Bandgap on 5 - Set discriminator divisors from DATA1:7,6

and lock detect period from DATA1:5

and OSC8 divisors from DATA1:2-0 4 - Set bandgap trim from DATA1:7-0 3 Not used Not used 2 Not used Not used 1 - Do a restart if both DATA3 bits 1 and 0 are at 1 0 - Do a restart if both DATA3 bits 1 and 0 are at 1

Summary of Set-up Commands - DATA2 bits 7, 6 = 10

+ 27 hidden pages