MAINTENANCE & ADJUSTMENT
Circuit Theory
The concept of PLL system frequency synthesization is not of recent development, however, it has not been a long age since the digital theory has been couplet with the PLL synthesization technology. Although details of the PLL theory is somewhat complicated and not within the scope of this brochure, we hereby provide the fundamental theory of it.
PLL Circuitry. PLL is an abbreviation of the phase-locked loop which is fundamentary composed of a closed loop feedback circuit. The feedback components is the balance of frequency drifts and PLL circuit acts to cancel it out. To detect out the frequency drift of the PLL output, a fixed reference oscillator (10KHZ, 1/1024 divided down from 10.240MHZ) is compared constantly with the input frequency (10KHZ). The input frequency is obtained by dividing the VCO frequency. A functional block diagram is provided below under “PLL Circuit” for the easier understanding.
Fvco = f off-set + Nfr
Where, fvco = VCO frequency, N = programming code for divider output, fr = reference frequency step, 0.01MHZ.
i.e. At channel #1 in band A, and AM band corresponding N code is 91.
TRANSMITTER
Fvco = 14.300 + 91x0.01 = 15.210MHZ
Since the mixer output is determined by two factors-the off-set frequency output (dependent on band selector switch) and the VCO output, the mixer output contains the subtracted frequencies of 0.91 to 2.25MHZ. These frequencies appear in pin #2 of IC803 through C105, and divided by the programmable divider in IC803 down to 10KHZ which is compared with another 10KHZ signal obtained from the reference oscillator (10.240MHZ).
The VCO output is mixed with TR402—TR407 through band-pass filters L43 and L44 i.e.
PLL CIRCUIT
RECEIVER
Alignment Procedure
1 – Measurement Condition |
|
1) reference temperature |
25°C |
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