Page 1
5
Table of Contents
4
3
2
1
Page
01
D D
02
03
04
05
06
07
08
09
Title
TABLE OF CONTENTS
Build Options
BLOCK DIAGRAM
CLOCK DISTRIBUTION
SIGNAL & RESET MAP
POWER FLOW 1 of 3
POWER FLOW 2 of 3
POWER FLOW 3 of 3
I2C MAP
CPU(1)_Disp,Type-C,MISC
11
C C
12
13
CPU(2)_LPDDR
CPU(3)_ICL POWER1_DDR_VCCSTG
CPU(4)_ICL_POWER2_VCCIN
Page
31
32
33
34
35
36
37
38
39
40
41
42
43
Title
Power/Volume Button Debug
Sensors
Debug Conn
SAM_1_PWR_ADC_Debug
SAM_2
X
Level Shifters
TPM
Temp Sensor
REALTEK ALC3269C-GRT CODEC
Headphone/Speaker Connector
Audio Smart Amp
X
Page
61
62
63
64
65
66
67
68
69
70
71
72
73
Title
X
+1.8VSB & Load SW
CHARGER
+5V Load SW
+3P3V Load SW
VCCIN Coontroller
VCCIN DRMOS
VCCINAUX Controller
VCCINAUX DRMOS
SL1 PWR/ BATT CONN.10
SL1 SIGNALS
+3P3V_HPD/LCD backlight
X
14
15
16
17
18
19
20
21
B B
22
23
24
25
26
27
28
CPU(5)_GND
CPU(6)_CFG_RESERVED
LPDDR3(1)_MEMORY DOWN
LPDDR3(2)_MEMORY DOWN
SFF
Mechanical Parts
PCH(1)_SD,HDA,RTC, CLK
PCH(2)_CLK,SMB,LPC, SPI
PCH(3)_SYS PWR CONTR
PCH(4)_CSI,eMMC,CNVi
PCH(5)_PCIE,USB
PCH(6)_CPU,GPIO,MISC
PCH(7)_POWER
PCH(8)_VCCIN_AUX_Decoupling
Power Monitor
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
M.2 SSD Connector
USB A 3.0 Port
DP Dongle Control
X
uSD Card B2B
X
Wi-Fi_BT
X
X
X
Camera Front/IR Connector
VA and VCCRTC
+VCCSTG
eDP connector
Silego Controller
74
75
76
77
78
80
81
82
KBTP Connector
X
X
USB Type-C Port
X
USB Type-C PD79
X
X
X
29
30
A A
Type-C Debug
Touch Con & Key
59
60
+5VSB & +3P3VSB
+1P2V_DUAL&++0P6V_DDR_VDDQ
DBG_S - Replace with board short for MP
CAD Note:
Property: BUILD-OPT
DNP = Do Not Place
5
DBG_R - Replace with lower cost component for MP
DBG_N - Install for Non-Debug Builds
DBG_D - Remove from BOM (Depopulate) for MP
DBG_T - Used for Telemetry in MP as needed
DBG_TS - Used for Telemetry in MP as needed. This part needs to be
replaced with a short if telemetry is not needed.
4
3
<Variant Name>
<Variant Name>
<Variant Name>
Table of Contents
Table of Contents
Title:
Title:
Title:
Engineer:
Engineer:
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Table of Contents
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
1 82Tuesday, May 21, 2019
1 82Tuesday, May 21, 2019
1
1 82Tuesday, May 21, 2019
<RevCode>
<RevCode>
<RevCode>
Page 2
5
D D
4
3
2
1
C C
B B
A A
Build Options
Build Options
Build Options
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
1
1.00
1.00
1.00
2 82Tuesday, May 21, 2019
2 82Tuesday, May 21, 2019
2 82Tuesday, May 21, 2019
CAD Note:
Defaults: Footprint SMD 0201, Cap tmp Coeff X5R, 1% resistors
5
4
3
Title:
Title:
Title:
Engineer:
Engineer:
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Page 3
5
4
3
2
1
LAST UPDATE - Oct 25 2018
D D
EDAN-A
Dragonfly
Debug connector
Multiple MB
interfaces
IR Camera
IR
OV7251
LED
MIPI
Power Monitors
MIPI MIPI
RTS5849D-GR ISP
Firefly
USB-C
conn
Type C Debug
Multiple MB
interfaces
Chimera
SSD M.2
128GB, 256GB
C C
512GB, 1TB
LPDDR4X x32
LPDDR3 x32
LPDDR3 x32
LPDDR3 x32
8,16,32 GB
128-bit (32b x 4) – 2 Chl -64 bit each
I2C
4x PCIe
USB2
USB2
USB2
I2C
PCIe
DDR
Front RGB Camera
OV9734
MIPI
ALS
TCS3430
Chimera FPC
I2C
SPI
HDA
PDM
USB3
USB2
TPM
Nuvoton
NationZ
I2C
SPI
Chimera FPC
I2C
HD Audio
Digital
Mic
Digital
Mic
USB3.1
USB2
SPI ROM
ALC 3300
Codec
PDM
16MB
R
ALC1304M
L
AMP
Analog audio combo jack
Right
Left
USB A Port
Block Diagram 1.6
USB3
USB2
CNVi
USB3.1
USB2
DP
DP
SL40
PWR_SL
Wifi
CNVi
Harrison Peak
Thermal
Sensors
Hall
Sensor
BU52072
Chimera
LCD
13.5"
15"
eDP
CONN
I2C
eDP
NTRIG G5
SPI
I2C
eDP
SPI
Ice Lake
U 4+2
IO
IOx
Backlight
Controller
AND
PWM_EN
PWM
BT
Greenpak
B B
KBTP CONN
Battery
Connector
IOx
GPIO
UART
16Mb SPI
Flash
I2C
SPI
I2C
SAM
eSPI
UART
PWM
eSPI
UART
FAN
I2C
SML1
USBC
USB2
I2C
8Mb SPI
Flash
USBC
PD Controller
Retimer
SPI
USB2
USBC
CC1/CC2
TCP_VBUS
USB C Port
BQ25713
+5VSB
SPI
8Mb SPI
Flash
LEGEND
Edan-A specific
Common to Foxburg
I2C
VBAT
VBATI2C
Battery
Charger
VBAT
EXT_DC_IN
Charging
FET’s
A A
Fuel
Gauge
5
2S3P batt
49.4 WHr
PWR_SL
IMVP9
4
3
VCCIN
AUX
ROP
Power
Debug feature
BLOCK DIAGRAM
BLOCK DIAGRAM
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A1
A1
A1
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
1
Title:
Engineer:
Engineer:
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
BLOCK DIAGRAM
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
3 82Tuesday, May 21, 2019
3 82Tuesday, May 21, 2019
3 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 4
5
D D
4
3
2
1
C C
B B
A A
<Variant Name>
<Variant Name>
<Variant Name>
CLCOK DISTRIBUTION
CLCOK DISTRIBUTION
Title:
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
Engineer:
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
CLCOK DISTRIBUTION
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
4 82Tuesday, May 21, 2019
4 82Tuesday, May 21, 2019
1
4 82Tuesday, May 21, 2019
2.89.6
2.89.6
2.89.6
Page 5
5
SIGNAL & RESET MAP
4
3
2
1
Last Update - Feb 13 2018
D D
Battery
+VDD_BATA_PACK
SL1_PWR_GOOD
SL1
PWR_SL1_F
SW
Switch
(Diode)
1-1
+V_ALWAYS_ON
TCP0_VBUS_PWR_GOOD
USB-C
+VBUS_P0_CONN
TCP1_VBUS_PWR_GOOD
USB-C
C C
+VBUS_P1_CONN
SAM_SL1_PWR_EN
TCP0_LS_EN_N
TCP1_LS_EN_N
LS
LS
CHG_BATDRV_A
LS
FET
SW
SW
EXT_DC_IN
Step Down
LDO
Charging
circuit
& Switch
+3P3VSB
+5VSB
+5VSB2
1-2
+VSYS
+1P8VSB
10
1P8VSB_PG
+VCCIN_AUX
11
VCCIN_AUX_READY
+VNN_BYP
12
+V1P05_BYP_EN
+1P8V_DDR_VDD1
+V1P05_BYP
+1P1V_DDR_VDD2
B B
+3P3VAS
2
+VCC_RTC
Silego
1 of 2
Power
Button
6
SUS_PWRGD
+1P8VAS
3P3VA_EN
PWRBTN#_1V8
VSUS_ON
13
VCCIN_AUX_PG
17
SLP_S4_DRV#
19
SLP_S3_DRV#
3 4
LDO
+1P8V_SAM
5
7
SAM
LPC
15
SAM_PCH_PWRBT N#
14
RSMRST#
8
PCH_DPWROK
9
SLP_SUS#
23
PM_PCH_PWROK
24
SYS_PWROK
21
VCCST_PWRGD
PWRBTN#
RSMRST#
DSW_PWROK
SLP_SUS#
PCH_PWROK
SYS_PWROK
VCCST_PWRGD
Intel
PCH
16
18
SLP_S3#
SLP_S4#
PLTRST#
SLP_S4#
SLP_S3#
25
PLTRST#
SAM
TPM
SSD/M.2
PLTRST_BUF#
AND Gate
Buffer
Silego
2 of 2
+1P1V_DDR_PG
3P3V/5V
3P3V_SSD_M2
ML_3P3V_PWR_FUSE (MDP)
OD
page 75
+3P3V_SSD
Power On Sequence
20
ALL_SYS_PWRGD
1
VRDY
3
EN
22
VRM_PWRGD
2
A A
VCCIN
5
4
25
<Core Design>
<Core Design>
<Core Design>
SIGNAL&RESET MAP
SIGNAL&RESET MAP
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
Date: Sheet of
Title:
Engineer:
Engineer:
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
1
SIGNAL&RESET MAP
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
5 82Tuesday, May 21, 2019
5 82Tuesday, May 21, 2019
5 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 6
5
4
3
2
1
LAST UPDATE - Sept 13 2018
EDAN/HOOK Power Flow EV1
D D
C C
B B
A A
<Core Design>
<Core Design>
<Core Design>
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A1
A1
A1
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
Title:
Engineer:
Engineer:
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
POWER FLOW (1 OF 3)
POWER FLOW (1 OF 3)
POWER FLOW (1 OF 3)
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
1.00
1.00
1.00
6 82Tuesday, May 21, 2019
6 82Tuesday, May 21, 2019
6 82Tuesday, May 21, 2019
Page 7
5
4
3
2
1
LAST UPDATE - SEPT. 13 2018
D D
C C
B B
A A
<Core Design>
<Core Design>
<Core Design>
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A1
A1
A1
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
Title:
Engineer:
Engineer:
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
POWER FLOW (2 OF 3)
POWER FLOW (2 OF 3)
POWER FLOW (2 OF 3)
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
1.00
1.00
1.00
7 82Tuesday, May 21, 2019
7 82Tuesday, May 21, 2019
7 82Tuesday, May 21, 2019
Page 8
5
4
3
2
1
LAST UPDATE - SEPT. 13 2018
D D
C C
B B
A A
<Core Design>
<Core Design>
<Core Design>
POWER FLOW (3 OF 3)
POWER FLOW (3 OF 3)
Title:
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
Engineer:
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
POWER FLOW (3 OF 3)
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
8 82Tuesday, May 21, 2019
8 82Tuesday, May 21, 2019
1
8 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 9
5
4
3
2
1
LAST UPDATE - APR.2018 (OUTDATED)
D D
C C
B B
A A
09. I2C MAP
09. I2C MAP
09. I2C MAP
Title:
Title:
Title:
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
Engineer:
Engineer:
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A1
A1
A1
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
1.00
1.00
1.00
9 82Tuesday, May 21, 2019
9 82Tuesday, May 21, 2019
9 82Tuesday, May 21, 2019
Page 10
5
4
3
2
1
+VCCST_CPU
U1003
5
VCC
4
PCB1001
D D
ALL
H_PROCHOT#[26,63,66,76]
C C
SAM_PROCHOT[35]
Q1001
SOT-VMT3_1P2XP8XP55_P4MM-1
U1002
H_PROCHOT#
B B
TBT_LSX0_TXD[77]
TBT_LSX0_RXD[77]
I2O
1
NC1
74AUP1G07GX
+3P3VSB
R1011
100K
ALL
HIGH: JTAG ODT ENABLED
Pull up or down straps required
DDP1 I2C/TBT LSX #0/BSSB-LS#0 VCC
GPP_E19/DDP1_CTRLDATA
0 1.8V
1
3.3V
DDP2 I2C/TBT LSX #1/BSSB-LS#1 VCC
A A
GPP_E21/DDP2_CTRLDATA
0 1.8V
1
3.3V
TOP
Bottom
M1098028-005
R1001
330
Added terminatio n when PECI trans is DNP
Intel recommend ed 200-400 Ohm PD
R1037
100
0402S_P4
G
DBG_PMODE[18,29]
+VCCST_CPU
5
VCC
4
3
GND
+1P8VSB
R1042
75K
DNP
GPP_E6
R1091
20K
eSPI Flash Sharing Mode
+VCCSTG_TERM
R1008
1K
0201S_P28-W 35
H_PROCHOT#
D
R1023 49.9
R1022 49.9
0201S_P28-W35
0201S_P28-W35
S
+1P8VSB
R1039
10K
C1009
0.1u 10V
H_PROCHOT_1P8V# [33,34]
eDP
mDP
+3P3V_PANEL_EN_R[65]
SLDP_CTRL_CLK[46]
SLDP_CTRL_DATA[46]
LOW: 1.8V FOR BSSB SINGAL THROUGH LS
EDP_HPD[57]
SL1_DP_HPD[71]
R1017 100K
GPP_H2
0 DEFAULT Master Attached
1
Slave Attached
R1002 499
0201S_P28-W 35
C1008 47pDNP
0201S_P33
EDP_TX0_DN[57]
EDP_TX0_DP[57]
EDP_TX1_DN[57]
EDP_TX1_DP[57]
EDP_TX2_DN[57]
EDP_TX2_DP[57]
EDP_TX3_DN[57]
EDP_TX3_DP[57]
EDP_AUX_DN[57]
EDP_AUX_DP[57]
PCH_SERIRQ[38]
+VCCST_CPU
R1016
49.9
0201S_P28-W 35
H_PROCHOT#_R
PROC_POPIRCOMP
PCH_OPIRCOMP
DBG_PMODE
SAM_PCH_PW RBTN#[22,37]
R1010
DNP
1K
PCIE_SSD_PERST#[44]
R1015 15
R1034 0
R1014 0
R1006 0
GPP_E17 reserved for GPU_EVENT# for SB
R1033 1M
+3P3VSB
PCH_VDD_PANEL_EN[30,65]
PCH_LCD_BKLT_EN[34,72]
PCH_BKLT_CTRL_PW M[72]
BB_FORCE_PW R[77,79]
R1007 1K
DNP
GPP_E22_SERIRQ
GPP_E23_3P3_PNL
EDP_DISP_UTIL
DNP
R1019
0
GPP_E6[18]
DP_RCOMP
TP_CATERR#_R [ 76]
GPP_E3[18]
GPP_E7[18]
R10430
R1040
49.9K
0201S_P28-W 35
R1003
150
I2O
1
NC1
3
GND
74AUP1G07GX
+VCCST_CPU
R1020
1K
0201S_P28-W 35
H_THERMTRIP#[58]
TP_CATERR#_R
PM_THRMTRIP#
PCH_PW RBTN#
GPP_H2
Y5
Y3
Y1
Y2
V2
V1
V3
V5
W4
W3
AE3
AE5
AE2
AE1
AC5
AC3
AC1
AC2
AD3
AD4
DP15
DJ17
DL40
DP42
DL17
DK17
DN17
DP17
DK34
DL34
DN33
DL33
DW11
CV42
CV39
CY43
CR41
CT41
DV14
DN21
DL19
DU19
J3
D2
R2
J4
CD5
PECI
C3
E3
CJ41
DU3
A14
B14
INT. PU
DL15
DV11
DT11
CR38
CR39
DT12
INT. PD
DJ38
DL38
U1001A
DDIA_TXN_0
DDIA_TXP_0
DDIA_TXN_1
DDIA_TXP_1
DDIA_TXN_2
DDIA_TXP_2
DDIA_TXN_3
DDIA_TXP_3
DDIA_AUX
DDIA_AUX_P
DDIB_TXN_0
DDIB_TXP_0
DDIB_TXN_1
DDIB_TXP_1
DDIB_TXN_2
DDIB_TXP_2
DDIB_TXN_3
DDIB_TXP_3
DDIB_AUX
DDIB_AUX_P
GPP_E22/DDPA_CTRLCLK/PCIE_LNK_DOWN
GPP_E23/DDPA_CTRLDATA/BK4/SBK4
GPP_H16/DDPB_CTRLCLK
GPP_H17/DDPB_CTRLDATA
GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD
GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD
GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD
GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD
GPP_D9/ISH_SPI_CS_N/DDP3_CTRLCLK/GSPI2_CS0_N/TBT_LSX2_TXD
GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/GSPI2_CLK/TBT_LSX2_RXD
GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/GSPI2_MISO/TBT_LSX3_TXD
GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/GSPI2_MOSI/TBT_LSX3_RXD
GPP_E14/DPPE_HPDA/DISP_MISCA
GPP_A18/DDSP_HPDB/DISP_MISCB
GPP_A19/DDSP_HPD1/DISP_MISC1
GPP_A20/DDSP_HPD2/DISP_MISC2
GPP_A14/USB_OC1_N/DDSP_HPD3/DISP_MISC3
GPP_A15/USB_OC2_N/DDSP_HPD4/DISP_MISC4
GPP_E17
EDP_VDDEN
EDP_BKLTEN
EDP_BKLTCTL
RSVD_1
DISP_UTILS
DISP_RCOMP
M1042225-001
R1018 0
U1001D
CATERR
PECI
PROCHOT
THRMTRIP
PROC_POPIRCOMP
PCH_OPIRCOMP
RSVD_A14
RSVD_B14
DBG_PMODE
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
GPP_E6
GPP_H2/CNV_BT_I2S_SDO
GPP_H19/TIME_SYNC0
M1042225-001
C1001
0.1u 6.3V
0201S_P28-W 35
4 OF 19
+1P8VSB
R1012
10K
PM_THRMTRIP#
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST
PCH_TRST
PCH_TCK
PCH_TDI
PCH_TDO
PCH_TMS
PCH_JTAGX
PROC_PRDY
PROC_PREQ
1 OF 19
PCH_CATERR#_1V8 [33,34 ]
+VCCSTG_TERM +3P3VSB
R1021
5.1
DBG_D
D
Q1002
DBG_D
P3
K5
K3
P4
N1
N5
R5
K1
K2
N3
N2
P6
M6
G
+VCCSTG_TERM
S
GPP_A17/DISP_MISCC
R1038 100
R1004 49.9
TCP0_TX_N0
TCP0_TX_P0
TCP0_TX_N1
TCP0_TX_P1
TCP0_TXRX_N0
TCP0_TXRX_P0
TCP0_TXRX_N1
TCP0_TXRX_P1
TCP0_AUX
TCP0_AUX_P
TCP1_TX_N0
TCP1_TX_P0
TCP1_TX_N1
TCP1_TX_P1
TCP1_TXRX_N0
TCP1_TXRX_P0
TCP1_TXRX_N1
TCP1_TXRX_P1
TCP1_AUX
TCP1_AUX_P
TCP2_TX_N0
TCP2_TX_P0
TCP2_TX_N1
TCP2_TX_P1
TCP2_TXRX_N0
TCP2_TXRX_P0
TCP2_TXRX_N1
TCP2_TXRX_P1
TCP2_AUX
TCP2_AUX_P
TCP3_TX_N0
TCP3_TX_P0
TCP3_TX_N1
TCP3_TX_P1
TCP3_TXRX_N0
TCP3_TXRX_P0
TCP3_TXRX_N1
TCP3_TXRX_P1
TCP3_AUX
TCP3_AUX_P
TC_RCOMP
TC_RCOMP_P
GPP_A21
GPP_A22
DBG_D
R1013 100K
DNP
SAM_SOC_JTAG_T RST# [35]
XDP_TCK [18,76]
XDP_TDI [18,76]
XDP_TDO [18,76]
XDP_TMS [18,76]
XDP_TRST# [18,76]
PROC_PRDY# [18]
PROC_PREQ# [18]
R1005 49.9
BB5
BB6
AV6
AV5
BH2
BH1
BF1
BF2
AY5
AY6
AR5
AR6
AL5
AL3
BD2
BD1
BB1
BB2
AN3
AN5
BF6
BF5
BJ5
BJ6
BL1
BL2
BM2
BM1
BG6
BG5
BP6
BP5
BV5
BV6
BR1
BR2
BT2
BT1
BT6
BT5
TCRCOMP_DN
AY1
TCRCOMP_DP
AY2
CT38
CV43
CV41
R1009
150
TP1001
EDP_I2C_INT [57,76]
+VCCSTG_TERM
100
R1028
R1027 49.9
R1030 1K
DNP
R1026 49.9
PCH_TRST# [18,76]
PCH_JTAG_TCK [ 18,76]
PCH_JTAG_TDI [18,76]
PCH_JTAG_TDO [18,76]
PCH_JTAG_TMS [18,76]
PCH_JTAGX [18, 76]
DNP
R1029
49.9
0201S_P28-W 35
TBL1001
Table is not avaliable now.
TCP0_TX_N0 [77]
TCP0_TX_P0 [77]
TCP0_TX_N1 [77]
TCP0_TX_P1 [77]
TCP0_TXRX_N0 [77]
TCP0_TXRX_P0 [77]
TCP0_TXRX_N1 [77]
TCP0_TXRX_P1 [77]
TCP0_AUX_DN [77]
TCP0_AUX_DP [77]
SL_DATA0_DN [71]
SL_DATA0_DP [71]
SL_DATA2_DN [71]
SL_DATA2_DP [71]
SL_DATA1_DN [71]
SL_DATA1_DP [71]
SL_DATA3_DN [71]
SL_DATA3_DP [71]
SLDP_AUX_DN [46]
SLDP_AUX_DP [46]
USBA_EN [45]
USB-C
USB-C
SL40
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
W x H 437 x 328 mm
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
CPU(1)_Disp,Type-C,MISC
CPU(1)_Disp,Type-C,MISC
CPU(1)_Disp,Type-C,MISC
Title:
Title:
Title:
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
Engineer:
Engineer:
Engineer:
1
0.23
0.23
10 82Tuesday, May 21, 2019
10 82Tuesday, May 21, 2019
10 82Tuesday, May 21, 2019
0.23
Page 11
5
4
3
2
1
D D
C C
B B
M_A_0_DQ_[7:0][16]
M_A_1_DQ_[7:0][16]
M_A_2_DQ_[7:0][16]
M_A_3_DQ_[7:0][16]
M_B_0_DQ_[7:0][16]
M_B_1_DQ_[7:0][16]
M_B_2_DQ_[7:0][16]
M_B_3_DQ_[7:0][16]
M_A_0_DQ_0
M_A_0_DQ_1
M_A_0_DQ_2
M_A_0_DQ_3
M_A_0_DQ_4
M_A_0_DQ_5
M_A_0_DQ_6
M_A_0_DQ_7
M_A_1_DQ_0
M_A_1_DQ_1
M_A_1_DQ_2
M_A_1_DQ_3
M_A_1_DQ_4
M_A_1_DQ_5
M_A_1_DQ_6
M_A_1_DQ_7
M_A_2_DQ_0
M_A_2_DQ_1
M_A_2_DQ_2
M_A_2_DQ_3
M_A_2_DQ_4
M_A_2_DQ_5
M_A_2_DQ_6
M_A_2_DQ_7
M_A_3_DQ_0
M_A_3_DQ_1
M_A_3_DQ_2
M_A_3_DQ_3
M_A_3_DQ_4
M_A_3_DQ_5
M_A_3_DQ_6
M_A_3_DQ_7
M_B_0_DQ_0
M_B_0_DQ_1
M_B_0_DQ_2
M_B_0_DQ_3
M_B_0_DQ_4
M_B_0_DQ_5
M_B_0_DQ_6
M_B_0_DQ_7
M_B_1_DQ_0
M_B_1_DQ_1
M_B_1_DQ_2
M_B_1_DQ_3
M_B_1_DQ_4
M_B_1_DQ_5
M_B_1_DQ_6
M_B_1_DQ_7
M_B_2_DQ_0
M_B_2_DQ_1
M_B_2_DQ_2
M_B_2_DQ_3
M_B_2_DQ_4
M_B_2_DQ_5
M_B_2_DQ_6
M_B_2_DQ_7
M_B_3_DQ_0
M_B_3_DQ_1
M_B_3_DQ_2
M_B_3_DQ_3
M_B_3_DQ_4
M_B_3_DQ_5
M_B_3_DQ_6
M_B_3_DQ_7
U1001B
CA48
DDRA_DQ0_0/DDR0_DQ0_0/DDR0_DQ0_0
CA47
DDRA_DQ0_1/DDR0_DQ0_1/DDR0_DQ0_1
CA49
DDRA_DQ0_2/DDR0_DQ0_2/DDR0_DQ0_2
BV49
DDRA_DQ0_3/DDR0_DQ0_3/DDR0_DQ0_3
CA45
DDRA_DQ0_4/DDR0_DQ0_4/DDR0_DQ0_4
BV47
DDRA_DQ0_5/DDR0_DQ0_5/DDR0_DQ0_5
BV45
DDRA_DQ0_6/DDR0_DQ0_6/DDR0_DQ0_6
BV48
DDRA_DQ0_7/DDR0_DQ0_7/DDR0_DQ0_7
CC42
DDRA_DQ1_0/DDR0_DQ1_0/DDR1_DQ0_0
CC39
DDRA_DQ1_1/DDR0_DQ1_1/DDR1_DQ0_1
CC43
DDRA_DQ1_2/DDR0_DQ1_2/DDR1_DQ0_2
CE38
DDRA_DQ1_3/DDR0_DQ1_3/DDR1_DQ0_3
CC38
DDRA_DQ1_4/DDR0_DQ1_4/DDR1_DQ0_4
CE39
DDRA_DQ1_5/DDR0_DQ1_5/DDR1_DQ0_5
CE42
DDRA_DQ1_6/DDR0_DQ1_6/DDR1_DQ0_6
CE43
DDRA_DQ1_7/DDR0_DQ1_7/DDR1_DQ0_7
BT48
DDRA_DQ2_0/DDR0_DQ2_0/DDR0_DQ1_0
BT47
DDRA_DQ2_1/DDR0_DQ2_1/DDR0_DQ1_1
BT49
DDRA_DQ2_2/DDR0_DQ2_2/DDR0_DQ1_2
BN49
DDRA_DQ2_3/DDR0_DQ2_3/DDR0_DQ1_3
BT45
DDRA_DQ2_4/DDR0_DQ2_4/DDR0_DQ1_4
BN47
DDRA_DQ2_5/DDR0_DQ2_5/DDR0_DQ1_5
BN45
DDRA_DQ2_6/DDR0_DQ2_6/DDR0_DQ1_6
BN48
DDRA_DQ2_7/DDR0_DQ2_7/DDR0_DQ1_7
BV42
DDRA_DQ3_0/DDR0_DQ3_0/DDR1_DQ1_0
BV39
DDRA_DQ3_1/DDR0_DQ3_1/DDR1_DQ1_1
BV43
DDRA_DQ3_2/DDR0_DQ3_2/DDR1_DQ1_2
BW38
DDRA_DQ3_3/DDR0_DQ3_3/DDR1_DQ1_3
BV38
DDRA_DQ3_4/DDR0_DQ3_4/DDR1_DQ1_4
BW39
DDRA_DQ3_5/DDR0_DQ3_5/DDR1_DQ1_5
BW42
DDRA_DQ3_6/DDR0_DQ3_6/DDR1_DQ1_6
BW43
DDRA_DQ3_7/DDR0_DQ3_7/DDR1_DQ1_7
AY48
DDRB_DQ0_0/DDR0_DQ4_0/DDR0_DQ2_0
AY47
DDRB_DQ0_1/DDR0_DQ4_1/DDR0_DQ2_1
AY49
DDRB_DQ0_2/DDR0_DQ4_2/DDR0_DQ2_2
AU45
DDRB_DQ0_3/DDR0_DQ4_3/DDR0_DQ2_3
AY45
DDRB_DQ0_4/DDR0_DQ4_4/DDR0_DQ2_4
AU47
DDRB_DQ0_5/DDR0_DQ4_5/DDR0_DQ2_5
AU48
DDRB_DQ0_6/DDR0_DQ4_6/DDR0_DQ2_6
AU49
DDRB_DQ0_7/DDR0_DQ4_7/DDR0_DQ2_7
AY42
DDRB_DQ1_0/DDR0_DQ5_0/DDR1_DQ2_0
AY38
DDRB_DQ1_1/DDR0_DQ5_1/DDR1_DQ2_1
AY43
DDRB_DQ1_2/DDR0_DQ5_2/DDR1_DQ2_2
BB39
DDRB_DQ1_3/DDR0_DQ5_3/DDR1_DQ2_3
AY39
DDRB_DQ1_4/DDR0_DQ5_4/DDR1_DQ2_4
BB38
DDRB_DQ1_5/DDR0_DQ5_5/DDR1_DQ2_5
BB42
DDRB_DQ1_6/DDR0_DQ5_6/DDR1_DQ2_6
BB43
DDRB_DQ1_7/DDR0_DQ5_7/DDR1_DQ2_7
AR48
DDRB_DQ2_0/DDR0_DQ6_0/DDR0_DQ3_0
AR47
DDRB_DQ2_1/DDR0_DQ6_1/DDR0_DQ3_1
AR49
DDRB_DQ2_2/DDR0_DQ6_2/DDR0_DQ3_2
AM45
DDRB_DQ2_3/DDR0_DQ6_3/DDR0_DQ3_3
AR45
DDRB_DQ2_4/DDR0_DQ6_4/DDR0_DQ3_4
AM47
DDRB_DQ2_5/DDR0_DQ6_5/DDR0_DQ3_5
AM48
DDRB_DQ2_6/DDR0_DQ6_6/DDR0_DQ3_6
AM49
DDRB_DQ2_7/DDR0_DQ6_7/DDR0_DQ3_7
AT42
DDRB_DQ3_0/DDR0_DQ7_0/DDR1_DQ3_0
AT39
DDRB_DQ3_1/DDR0_DQ7_1/DDR1_DQ3_1
AR43
DDRB_DQ3_2/DDR0_DQ7_2/DDR1_DQ3_2
AT38
DDRB_DQ3_3/DDR0_DQ7_3/DDR1_DQ3_3
AR38
DDRB_DQ3_4/DDR0_DQ7_4/DDR1_DQ3_4
AR39
DDRB_DQ3_5/DDR0_DQ7_5/DDR1_DQ3_5
AR42
DDRB_DQ3_6/DDR0_DQ7_6/DDR1_DQ3_6
AT43
DDRB_DQ3_7/DDR0_DQ7_7/DDR1_DQ3_7
D47
DDR_RCOMP_0
E46
DDR_RCOMP_1
C47
DDR_RCOMP_2
M1042225-001
2 OF 19
DDRA_CLK_N/DDR0_CLK_N_0
DDRA_CLK_P/DDR0_CLK_P_0
DDRB_CLK_N/DDR0_CLK_N_1
DDRB_CLK_P/DDR0_CLK_P_1
DDRA_CKE0/DDR0_CKE0
DDRA_CKE1/NC
DDRB_CKE0/NC
DDRB_CKE1/DDR0_CKE1
DDRA_CS_0/DDR0_CS_N_0
DDRB_CS_1/DDR0_CS_N_1
DDRB_CA1/DDR0_MA15CAS
DDRB_CA3/DDR0_MA16RAS
DDRA_DQSN_0/DDR0_DQSN_0/DDR0_DQSN_0
DDRA_DQSP_0/DDR0_DQSP_0/DDR0_DQSP_0
DDRA_DQSN_1/DDR0_DQSN_1/DDR1_DQSN_0
DDRA_DQSP_1/DDR0_DQSP_1/DDR1_DQSP_0
DDRA_DQSN_2/DDR0_DQSN_2/DDR0_DQSN_1
DDRA_DQSP_2/DDR0_DQSP_2/DDR0_DQSP_1
DDRA_DQSN_3/DDR0_DQSN_3/DDR1_DQSN_1
DDRA_DQSP_3/DDR0_DQSP_3/DDR1_DQSP_1
DDRB_DQSN_0/DDR0_DQSN_4/DDR0_DQSN_2
DDRB_DQSP_0/DDR0_DQSP_4/DDR0_DQSP_2
DDRB_DQSN_1/DDR0_DQSN_5/DDR1_DQSN_2
DDRB_DQSP_1/DDR0_DQSP_5/DDR1_DQSP_2
DDRB_DQSN_2/DDR0_DQSN_6/DDR0_DQSN_3
DDRB_DQSP_2/DDR0_DQSP_6/DDR0_DQSP_3
DDRB_DQSN_3/DDR0_DQSN_7/DDR1_DQSN_3
DDRB_DQSP_3/DDR0_DQSP_7/DDR1_DQSP_3
DDRA_CS_1/NC
DDRB_CS_0/NC
DDRB_CA4/DDR0_BA0
NC/DDR0_BA1
DDRA_CA5/DDR0_BG0
NC/DDR0_BG1
NC/DDR0_MA0
NC/DDR0_MA1
DDRB_CA5/DDR0_MA2
NC/DDR0_MA3
NC/DDR0_MA4
DDRA_CA0/DDR0_MA5
DDRA_CA2/DDR0_MA6
DDRA_CA4/DDR0_MA7
DDRA_CA3/DDR0_MA8
DDRA_CA1/DDR0_MA9
NC/DDR0_MA10
NC/DDR0_MA11
NC/DDR0_MA12
DDRB_CA0/DDR0_MA13
DDRB_CA2/DDR0_MA14WE
NC/DDR0_ODT_0
NC/DDR0_ODT_1
NC/DDR0_PAR
NC/DDR0_ACT
NC/DDR0_ALERT
RSVD_M38
DDR0_VREF_CA
DDR1_VREF_CA
DDR_VTT_CTL
DRAM_RESET
BL48
BL47
BF42
BF43
BG49
BJ47
BF38
BF41
BM38
BM42
BP42
BG42
BM43
BG39
BB49
BD47
BB48
BL49
BG38
BL45
BJ46
BG48
BE45
BG45
BG47
BE47
BJ38
BB47
BE48
BM39
BG43
BJ42
BM41
BJ39
BB45
BY47
BY46
CC41
CE41
BR47
BR46
BV41
BW41
AV46
AV47
AY41
BB41
AN46
AN47
AR41
AT41
BF39
BE49
BD46
M38
C44
B45
M39
DK47
M_A_LP4_CLK_N [16]
M_A_LP4_CLK_P [16]
M_B_LP4_CLK_N [16]
M_B_LP4_CLK_P [16]
M_A_LP4_CKE0 [16]
M_A_LP4_CKE1 [16]
M_B_LP4_CKE0 [16]
M_B_LP4_CKE1 [16]
M_A_LP4_CS#0 [16]
M_A_LP4_CS#1 [16]
M_B_LP4_CS#0 [16]
M_B_LP4_CS#1 [16]
M_B_CA4
M_A_CA5
M_B_CA5
M_A_CA0
M_A_CA2
M_A_CA4
M_A_CA3
M_A_CA1
M_A_CA5
M_B_CA0
M_B_CA2
M_B_CA1
M_B_CA3
M_B_CA4
M_B_CA5
DDR0_ALERT#
DDR_VTT_CTRL
M_A_CA[5:0] [16]
M_B_CA[5:0] [16]
M_A_DQS_0_DN [16]
M_A_DQS_0_DP [16]
M_A_DQS_1_DN [16]
M_A_DQS_1_DP [16]
M_A_DQS_2_DN [16]
M_A_DQS_2_DP [16]
M_A_DQS_3_DN [16]
M_A_DQS_3_DP [16]
M_B_DQS_0_DN [16]
M_B_DQS_0_DP [16]
M_B_DQS_1_DN [16]
M_B_DQS_1_DP [16]
M_B_DQS_2_DN [16]
M_B_DQS_2_DP [16]
M_B_DQS_3_DN [16]
M_B_DQS_3_DP [16]
R1135 0
0201S_P28-W35
+1P1V_DDR_VDD2
M_C_1_DQ_[7:0][17]
M_C_2_DQ_[7:0][17]
M_C_3_DQ_[7:0][17]
M_D_1_DQ_[7:0][17]
DNP
R1117
10K
0201S_P28-W35
M_C_0_DQ_[7:0][17]
M_D_0_DQ_[7:0][17]
M_D_2_DQ_[7:0][17]
M_D_3_DQ_[7:0][17]
M_C_0_DQ_0
M_C_0_DQ_1
M_C_0_DQ_2
M_C_0_DQ_3
M_C_0_DQ_4
M_C_0_DQ_5
M_C_0_DQ_6
M_C_0_DQ_7
M_C_1_DQ_0
M_C_1_DQ_1
M_C_1_DQ_2
M_C_1_DQ_3
M_C_1_DQ_4
M_C_1_DQ_5
M_C_1_DQ_6
M_C_1_DQ_7
M_C_2_DQ_0
M_C_2_DQ_1
M_C_2_DQ_2
M_C_2_DQ_3
M_C_2_DQ_4
M_C_2_DQ_5
M_C_2_DQ_6
M_C_2_DQ_7
M_C_3_DQ_0
M_C_3_DQ_1
M_C_3_DQ_2
M_C_3_DQ_3
M_C_3_DQ_4
M_C_3_DQ_5
M_C_3_DQ_6
M_C_3_DQ_7
M_D_0_DQ_0
M_D_0_DQ_1
M_D_0_DQ_2
M_D_0_DQ_3
M_D_0_DQ_4
M_D_0_DQ_5
M_D_0_DQ_6
M_D_0_DQ_7
M_D_1_DQ_0
M_D_1_DQ_1
M_D_1_DQ_2
M_D_1_DQ_3
M_D_1_DQ_4
M_D_1_DQ_5
M_D_1_DQ_6
M_D_1_DQ_7
M_D_2_DQ_0
M_D_2_DQ_1
M_D_2_DQ_2
M_D_2_DQ_3
M_D_2_DQ_4
M_D_2_DQ_5
M_D_2_DQ_6
M_D_2_DQ_7
M_D_3_DQ_0
M_D_3_DQ_1
M_D_3_DQ_2
M_D_3_DQ_3
M_D_3_DQ_4
M_D_3_DQ_5
M_D_3_DQ_6
M_D_3_DQ_7
U1001C
AK48
DDRC_DQ0_0/DDR1_DQ0_0/DDR0_DQ4_0
AK45
DDRC_DQ0_1/DDR1_DQ0_1/DDR0_DQ4_1
AK49
DDRC_DQ0_2/DDR1_DQ0_2/DDR0_DQ4_2
AG47
DDRC_DQ0_3/DDR1_DQ0_3/DDR0_DQ4_3
AK47
DDRC_DQ0_4/DDR1_DQ0_4/DDR0_DQ4_4
AG45
DDRC_DQ0_5/DDR1_DQ0_5/DDR0_DQ4_5
AG48
DDRC_DQ0_6/DDR1_DQ0_6/DDR0_DQ4_6
AG49
DDRC_DQ0_7/DDR1_DQ0_7/DDR0_DQ4_7
AJ38
DDRC_DQ1_0/DDR1_DQ1_0/DDR1_DQ4_0
AL39
DDRC_DQ1_1/DDR1_DQ1_1/DDR1_DQ4_1
AJ39
DDRC_DQ1_2/DDR1_DQ1_2/DDR1_DQ4_2
AL43
DDRC_DQ1_3/DDR1_DQ1_3/DDR1_DQ4_3
AL38
DDRC_DQ1_4/DDR1_DQ1_4/DDR1_DQ4_4
AJ42
DDRC_DQ1_5/DDR1_DQ1_5/DDR1_DQ4_5
AL42
DDRC_DQ1_6/DDR1_DQ1_6/DDR1_DQ4_6
AJ43
DDRC_DQ1_7/DDR1_DQ1_7/DDR1_DQ4_7
AB49
DDRC_DQ2_0/DDR1_DQ2_0/DDR0_DQ5_0
AB48
DDRC_DQ2_1/DDR1_DQ2_1/DDR0_DQ5_1
AE49
DDRC_DQ2_2/DDR1_DQ2_2/DDR0_DQ5_2
AE47
DDRC_DQ2_3/DDR1_DQ2_3/DDR0_DQ5_3
AE48
DDRC_DQ2_4/DDR1_DQ2_4/DDR0_DQ5_4
AB47
DDRC_DQ2_5/DDR1_DQ2_5/DDR0_DQ5_5
AB45
DDRC_DQ2_6/DDR1_DQ2_6/DDR0_DQ5_6
AE45
DDRC_DQ2_7/DDR1_DQ2_7/DDR0_DQ5_7
AD38
DDRC_DQ3_0/DDR1_DQ3_0/DDR1_DQ5_0
AD39
DDRC_DQ3_1/DDR1_DQ3_1/DDR1_DQ5_1
AE39
DDRC_DQ3_2/DDR1_DQ3_2/DDR1_DQ5_2
AE43
DDRC_DQ3_3/DDR1_DQ3_3/DDR1_DQ5_3
AE38
DDRC_DQ3_4/DDR1_DQ3_4/DDR1_DQ5_4
AD43
DDRC_DQ3_5/DDR1_DQ3_5/DDR1_DQ5_5
AD42
DDRC_DQ3_6/DDR1_DQ3_6/DDR1_DQ5_6
AE42
DDRC_DQ3_7/DDR1_DQ3_7/DDR1_DQ5_7
J48
DDRD_DQ0_0/DDR1_DQ4_0/DDR0_DQ6_0
J45
DDRD_DQ0_1/DDR1_DQ4_1/DDR0_DQ6_1
J49
DDRD_DQ0_2/DDR1_DQ4_2/DDR0_DQ6_2
G47
DDRD_DQ0_3/DDR1_DQ4_3/DDR0_DQ6_3
J47
DDRD_DQ0_4/DDR1_DQ4_4/DDR0_DQ6_4
G45
DDRD_DQ0_5/DDR1_DQ4_5/DDR0_DQ6_5
G48
DDRD_DQ0_6/DDR1_DQ4_6/DDR0_DQ6_6
E48
DDRD_DQ0_7/DDR1_DQ4_7/DDR0_DQ6_7
J38
DDRD_DQ1_0/DDR1_DQ5_0/DDR1_DQ6_0
G39
DDRD_DQ1_1/DDR1_DQ5_1/DDR1_DQ6_1
G38
DDRD_DQ1_2/DDR1_DQ5_2/DDR1_DQ6_2
G42
DDRD_DQ1_3/DDR1_DQ5_3/DDR1_DQ6_3
J39
DDRD_DQ1_4/DDR1_DQ5_4/DDR1_DQ6_4
J42
DDRD_DQ1_5/DDR1_DQ5_5/DDR1_DQ6_5
G43
DDRD_DQ1_6/DDR1_DQ5_6/DDR1_DQ6_6
J43
DDRD_DQ1_7/DDR1_DQ5_7/DDR1_DQ6_7
B43
DDRD_DQ2_0/DDR1_DQ6_0/DDR0_DQ7_0
D43
DDRD_DQ2_1/DDR1_DQ6_1/DDR0_DQ7_1
A43
DDRD_DQ2_2/DDR1_DQ6_2/DDR0_DQ7_2
C40
DDRD_DQ2_3/DDR1_DQ6_3/DDR0_DQ7_3
C43
DDRD_DQ2_4/DDR1_DQ6_4/DDR0_DQ7_4
D40
DDRD_DQ2_5/DDR1_DQ6_5/DDR0_DQ7_5
B40
DDRD_DQ2_6/DDR1_DQ6_6/DDR0_DQ7_6
A40
DDRD_DQ2_7/DDR1_DQ6_7/DDR0_DQ7_7
B35
DDRD_DQ3_0/DDR1_DQ7_0/DDR1_DQ7_0
D35
DDRD_DQ3_1/DDR1_DQ7_1/DDR1_DQ7_1
A35
DDRD_DQ3_2/DDR1_DQ7_2/DDR1_DQ7_2
D38
DDRD_DQ3_3/DDR1_DQ7_3/DDR1_DQ7_3
C35
DDRD_DQ3_4/DDR1_DQ7_4/DDR1_DQ7_4
C38
DDRD_DQ3_5/DDR1_DQ7_5/DDR1_DQ7_5
B38
DDRD_DQ3_6/DDR1_DQ7_6/DDR1_DQ7_6
A38
DDRD_DQ3_7/DDR1_DQ7_7/DDR1_DQ7_7
M1042225-001
3 OF 19
DDRC_CLK_N/DDR1_CLK_N_0
DDRC_CLK_P/DDR1_CLK_P_0
DDRD_CLK_N/DDR1_CLK_N_1
DDRD_CLK_P/DDR1_CLK_P_1
DDRC_CKE0/DDR1_CKE0
DDRC_CKE1/NC
DDRD_CKE0/NC
DDRD_CKE1/DDR1_CKE1
DDRC_CS_0/DDR1_CS_N_0
DDRC_CS_1/NC
DDRD_CS_0/NC
DDRD_CS_1/DDR1_CS_N_1
DDRD_CA4/DDR1_BA0
DDRC_CA5/DDR1_BG0
DDRD_CA5/DDR1_MA2
DDRC_CA0/DDR1_MA5
DDRC_CA2/DDR1_MA6
DDRC_CA4/DDR1_MA7
DDRC_CA3/DDR1_MA8
DDRC_CA1/DDR1_MA9
NC/DDR1_MA10
NC/DDR1_MA11
NC/DDR1_MA12
DDRD_CA0/DDR1_MA13
DDRD_CA2/DDR1_MA14WE
DDRD_CA1/DDR1_MA15CAS
DDRD_CA3/DDR1_MA16RAS
NC/DDR1_ODT_0
NC/DDR1_ODT_1
DDRC_DQSN_0/DDR1_DQSN_0/DDR0_DQSN_4
DDRC_DQSP_0/DDR1_DQSP_0/DDR0_DQSP_4
DDRC_DQSN_1/DDR1_DQSN_1/DDR1_DQSN_4
DDRC_DQSP_1/DDR1_DQSP_1/DDR1_DQSP_4
DDRC_DQSN_2/DDR1_DQSN_2/DDR0_DQSN_5
DDRC_DQSP_2/DDR1_DQSP_2/DDR0_DQSP_5
DDRC_DQSN_3/DDR1_DQSN_3/DDR1_DQSN_5
DDRC_DQSP_3/DDR1_DQSP_3/DDR1_DQSP_5
DDRD_DQSN_0/DDR1_DQSN_4/DDR0_DQSN_6
DDRD_DQSP_0/DDR1_DQSP_4/DDR0_DQSP_6
DDRD_DQSN_1/DDR1_DQSN_5/DDR1_DQSN_6
DDRD_DQSP_1/DDR1_DQSP_5/DDR1_DQSP_6
DDRD_DQSN_2/DDR1_DQSN_6/DDR0_DQSN_7
DDRD_DQSP_2/DDR1_DQSP_6/DDR0_DQSP_7
DDRD_DQSN_3/DDR1_DQSN_7/DDR1_DQSN_7
DDRD_DQSP_3/DDR1_DQSP_7/DDR1_DQSP_7
NC/DDR1_ALERT
NC/DDR1_BA1
NC/DDR1_BG1
NC/DDR1_MA0
NC/DDR1_MA1
NC/DDR1_MA3
NC/DDR1_MA4
NC/DDR1_PAR
NC/DDR1_ACT
Y48
Y47
M43
M42
U45
V46
M41
P43
V42
V39
Y39
T39
T38
T42
R45
N47
P42
Y49
U48
Y45
U47
R49
U49
M47
M45
R47
P39
N46
R48
Y41
V41
Y42
V47
V43
V38
AH46
AH47
AJ41
AL41
AC47
AC46
AE41
AD41
H47
H46
G41
J41
C42
D42
D36
C36
P38
M48
M49
M_C_LP4_CLK_N [17]
M_C_LP4_CLK_P [17]
M_D_LP4_CLK_N [17]
M_D_LP4_CLK_P [17]
M_C_LP4_CKE0 [17]
M_C_LP4_CKE1 [17]
M_D_LP4_CKE0 [17]
M_D_LP4_CKE1 [17]
M_C_LP4_CS#0 [17]
M_C_LP4_CS#1 [17]
M_D_LP4_CS#0 [17]
M_D_LP4_CS#1 [17]
M_D_CA4
M_C_CA5
M_D_CA5
M_C_CA0
M_C_CA2
M_C_CA4
M_C_CA3
M_C_CA1
M_C_CA5
M_D_CA0
M_D_CA2
M_D_CA1
M_D_CA3
M_D_CA4
M_D_CA5
DDR1_ALERT#
M_C_DQS_0_DN [ 17]
M_C_DQS_0_DP [17]
M_C_DQS_1_DN [ 17]
M_C_DQS_1_DP [17]
M_C_DQS_2_DN [ 17]
M_C_DQS_2_DP [17]
M_C_DQS_3_DN [ 17]
M_C_DQS_3_DP [17]
M_D_DQS_0_DN [ 17]
M_D_DQS_0_DP [17]
M_D_DQS_1_DN [ 17]
M_D_DQS_1_DP [17]
M_D_DQS_2_DN [ 17]
M_D_DQS_2_DP [17]
M_D_DQS_3_DN [ 17]
M_D_DQS_3_DP [17]
R1136 0
0201S_P28-W35
M_C_CA[5:0] [17]
M_D_CA[5:0] [17]
R1103
R1105
100
5
R1102
100
470
DRAM_RESET_N_R
4
R1101
0
3
DRAM_RESET# [16,17]
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
W x H 512 x 331 mm
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
CPU(2)_LPDDR4
CPU(2)_LPDDR4
CPU(2)_LPDDR4
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
1
1.00
1.00
11 82Tuesday, May 21, 2019
11 82Tuesday, May 21, 2019
11 82Tuesday, May 21, 2019
1.00
100 R1104
Use Seperated Via To GND
A A
Page 12
5
4
3
2
1
+VCCSTG_OUT
D D
+VCCSTG +VCCST_CPU
C C
C1204
1u
6.3V
0201S_P35-W35
+VCCSTG_TERM
+VCCSTG_OUT
R1201
0
5%
1/10W
0603S_P6-W95
+VCCSTG_OUT_LGC
+1P1V_DDR_VDD2
AA37
AG36
AJ36
AL36
AL49
AN36
AP37
AR36
AR37
AT36
AT49
AA49
AV36
AW37
AY36
BA37
BA49
BB36
BD36
BE37
BF36
BF37
AB36
BF49
BG36
BJ36
BL37
BM49
BN37
BP38
CB1
BY1
F33
G33
E5
U1001M
M1042225-001
VDDQ_1
13 OF 19
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
VDDQ_27
VDDQ_28
VDDQ_29
VDDQ_30
VCCST
VCCSTG
VCCSTG_OUT_F33
VCCSTG_OUT_G33
VCCSTG_OUT_LGC
VCCSTG_OUT_R35
VCCSTG_OUT_V34
VCCSTG_OUT_T34
VCCSTG_OUT_U35
VCCSTG_OUT_AB34
VDDQ_31
VDDQ_32
VDDQ_33
VDDQ_34
VDDQ_35
VDDQ_36
VDDQ_37
VDDQ_38
VDDQ_39
VDDQ_40
VDDQ_41
VDDQ_42
VDDQ_43
VDDQ_44
VDDQ_45
VDDQ_46
VDDQ_47
RSVD_2
RSVD_3
VCC1P8A_1
VCC1P8A_2
VCC1P8A_3
VCC1P8A_4
VCC1P8A_5
RSVD_W35
RSVD_AA35
RSVD_Y34
VCCPLL
VCCPLL_OC_1
VCCPLL_OC_2
VCCPLL_OC_3
VCCPLL_OC_4
VCCIO_OUT
+1P1V_DDR_VDD2
BP39
BR37
BT38
AC35
BU37
BU49
CA39
CB49
L38
L49
N36
T49
AC37
AD35
AD36
AE36
AF49
VCCIN_AUX0_R
A33
VCCIN_AUX1_R
B33
BG9
BJ9
BM9
BW1
BW2
R35
V34
T34
U35
AB34
W35
AA35
Y34
CD2
CG38
CG41
CG42
CG49
AD7
TP1201 SP_TP_SMDP58
TP1202 SP_TP_SMDP58
+VCC1P8A
+VCCSTG_OUT
+VCC1.05_OUT_SFR
+VCCPLL_OC
VCCIO_OUT [18]
B B
TOP SIDE BOTTOM SIDE TOP SIDE SOCKET
+1P1V_DDR_VDD2
C1211
22u
0603
20%
10V
+VCCSTG
A A
C1203
1u
0201S_P35-W35
6.3V
DNP
Place close to U1001M Place close to U1001M
C1220
22u
0603
20%
10V
C1247
1u
0201S_P35-W35
6.3V
5
C1228
22u
0603
20%
10V
DNP
+VCCST_CPU
C1205
1u
0201S_P35-W35
6.3V
DNP
+1P1V_DDR_VDD2
C1222
1u
6.3V
20%
0201
C1218
1u
6.3V
20%
0201
C1202
1u
6.3V C1252
0201S_P35-W35
C1206
1u
6.3V
20%
0201
C1238
1u
6.3V
20%
0201
C1233
1u
6.3V
20%
0201
C1207
1u
6.3V
20%
0201
C1250
1u
0201S_P35-W35
6.3V
DNP
4
C1221
1u
6.3V
20%
0201
C1208
1u
6.3V
20%
0201
C1249
1u
0201S_P35-W35
6.3V
+1P1V_DDR_VDD2 +1P1V_DDR_VDD2
C1253
1u
0201S_P35-W35
6.3V
C1214
10u
20%
6.3V
0402
C1254
1u
0201S_P35-W35
6.3V
DNP
C1224
10u
20%
6.3V
0402
1u
0201S_P35-W35
6.3V
3
C1251
1u
0201S_P35-W35
6.3V
DNP
DNP
C1213
10u
20%
6.3V
0402
C1225
10u
20%
6.3V
0402
DNP
+VCC1P8A+VCC1.05_OUT_FET+VCCPLL_OC+VCCSTG_OUT
C1248
10u
6.3V
0402S_P7-W70
Place close to U1001MPlace close to U1001MPlace close to U1001MPlace close to U1001M
DNP
C1215
10u
20%
6.3V
0402
C1201
22u
0603S_1-W100
20%
10V
DNP
2
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
W x H 437 x 328 mm
Date: Sheet of
Date: Sheet of
Date: Sheet of
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
CPU(3)_ICL_POWER1
CPU(3)_ICL_POWER1
CPU(3)_ICL_POWER1
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
12 82Tuesday, May 21, 2019
12 82Tuesday, May 21, 2019
1
12 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 13
5
4
3
2
1
+VCCIN
D D
TODO: Update rail
C C
SVID_ALERT#[66]
VIDSCLK[66]
VIDSOUT[66]
+VCCST_CPU
0201S_P28-W35
0201S_P28-W35
R1303 56
R1304 100
TP1303SP_TP_SMDP58
R130200201S_P28-W35
R130500201S_P28-W35
R130100201S_P28-W35
H_CPU_SVIDALERT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
A19
AC12
V13
W12
Y13
K29
K31
B19
B23
B27
B29
BN10
BP11
BP9
BR10
BT11
A21
BT9
BU10
BV36
BV9
BW10
BW36
BW9
BY10
C19
C23
A23
C27
C29
CA36
CA9
CB10
CC11
CC36
CC9
CD10
CE11
A24
CE34
CE35
CF10
CF33
CG11
CG34
CG35
CH10
J30
CJ11
A27
CJ34
U1001L
VCCIN_1
VCCIN_2
VCCIN_3
VCCIN_4
VCCIN_5
VCCIN_6
VCCIN_7
VCCIN_8
VCCIN_9
VCCIN_10
VCCIN_11
VCCIN_12
VCCIN_13
VCCIN_14
VCCIN_15
VCCIN_16
VCCIN_17
VCCIN_18
VCCIN_19
VCCIN_20
VCCIN_21
VCCIN_22
VCCIN_23
VCCIN_24
VCCIN_25
VCCIN_26
VCCIN_27
VCCIN_28
VCCIN_29
VCCIN_30
VCCIN_31
VCCIN_32
VCCIN_33
VCCIN_34
VCCIN_35
VCCIN_36
VCCIN_37
VCCIN_38
VCCIN_39
VCCIN_40
VCCIN_41
VCCIN_42
VCCIN_43
VCCIN_44
VCCIN_45
VCCIN_46
VCCIN_47
VCCIN_48
VCCIN_49
VCCIN_50
VCCIN_51
H1
VIDALERT
H2
VIDSCK
H3
VIDSOUT
M1042225-001
12 OF 19
VCCIN_100
VCCIN_101
VCCIN_102
VCCIN_103
VCCIN_104
VCCIN_SENSE
VSSIN_SENSE
VCCIN_52
VCCIN_53
VCCIN_54
VCCIN_55
VCCIN_56
VCCIN_57
VCCIN_58
VCCIN_59
VCCIN_60
VCCIN_61
VCCIN_62
VCCIN_63
VCCIN_64
VCCIN_65
VCCIN_66
VCCIN_67
VCCIN_68
VCCIN_69
VCCIN_70
VCCIN_71
VCCIN_72
VCCIN_73
VCCIN_74
VCCIN_75
VCCIN_76
VCCIN_77
VCCIN_78
VCCIN_79
VCCIN_80
VCCIN_81
VCCIN_82
VCCIN_83
VCCIN_84
VCCIN_85
VCCIN_86
VCCIN_87
VCCIN_88
VCCIN_89
VCCIN_90
VCCIN_91
VCCIN_92
VCCIN_93
VCCIN_94
VCCIN_95
VCCIN_96
VCCIN_97
VCCIN_98
VCCIN_99
CJ35
CK10
J32
CL34
CL35
CN34
CN35
CP33
CR34
A29
CR35
CT33
CT34
CT35
CU33
D19
D21
D23
D24
D27
AA12
D29
F19
F21
F23
F24
F27
F29
G1
G19
G23
AB1
G27
G29
H19
H23
H27
H29
J18
J20
J22
J23
AB13
J26
J28
K17
K19
K21
K23
K24
K27
M1
U1
F17
G17
+VCCIN
VCCIN_VIN_SENSE [66]
VCCIN_VSS_SENSE [66]
BACKSIDE CAP
+VCCIN
C1322
1u
6.3V
20%
0201
PRIMARY SIDE
+VCCIN
C1320
22u
0603
20%
10V
C1313
22u
0603
20%
10V
C1316
22u
0603
20%
10V
C1301
1u
6.3V
20%
0201
C1311
22u
0603
20%
10V
C1323
22u
0603
20%
10V
C1309
22u
0603
20%
10V
C1325
1u
6.3V
20%
0201
C1310
1u
6.3V
20%
0201
C1321
22u
0603
20%
10V
C1326
22u
0603
20%
10V
Place close as possible to A29
C1318
22u
0603
20%
10V
C1307
22u
0603
20%
10V
C1324
22u
0603
20%
10V
C1303
22u
0603
20%
10V
C1314
22u
0603
20%
10V
C1327
22u
0603
20%
DNP
10V
C1364
22u
0603
20%
10V
3
DNP
B B
A A
5
4
C1360
22u
0603
20%
10V
C1306
22u
0603
20%
10V
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
W x H 512 x 331 mm
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
CPU(4)_ICL_POWER2
CPU(4)_ICL_POWER2
CPU(4)_ICL_POWER2
Title:
Title:
Title:
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
Engineer:
Engineer:
Engineer:
1
1.00
1.00
13 82Tuesday, May 21, 2019
13 82Tuesday, May 21, 2019
13 82Tuesday, May 21, 2019
1.00
Page 14
5
4
3
2
1
BT3
BT39
BT41
BT42
BT43
BT7
BU45
BU47
BV1
BV11
BV2
BV3
BV7
BW3
BW37
BW5
BW6
BW7
BY37
BY45
BY49
C11
C13
C14
C17
C21
C24
C31
C34
C39
C48
C49
C6
CA3
CA38
CA41
CA42
CA43
CA7
CB37
CB45
CB47
CC3
CC7
CE37
CE45
CE49
CE9
CG37
CG39
CG43
CG45
CG47
CG9
CH3
CH5
CJ37
CJ42
CJ9
CK45
CK49
CK9
CL37
CL42
CL49
CM45
CM47
CM9
CN3
CN37
CN39
CN5
CP9
CR32
U1001P
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
M1042225-001
16 OF 19
3
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
CR37
CR45
CR49
CT37
CT39
CT42
CT9
CU45
CU47
CU49
CV3
CV34
CV35
CV5
CV9
CY41
CY45
CY49
CY9
D13
D17
D31
D44
D49
DA10
DA33
DA9
DB32
DB35
DB38
DB45
DB47
DB49
DC3
DC49
DC5
DC6
DD37
DD42
DE10
DE13
DE17
DE18
DE20
DE22
DE23
DE26
DE28
DE29
DE33
DE45
DE6
DF13
DF22
DF28
DF33
DF35
DF39
DG10
DG12
DG13
DG15
DG22
DG23
DG47
DG6
DH1
DH3
DH45
DH5
DJ19
DJ21
DJ27
DJ31
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
W x H 347 x 225 mm
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
U1001O
A11
VSS_1
A46
BB3
BB7
BD3
A48
BD5
BD6
BD7
BE1
BE2
BF3
A49
BF45
BF47
BF7
BG3
BG7
BJ1
BJ2
BJ3
BJ41
BJ43
BJ45
BJ49
BJ7
BM3
BM5
BM6
BM7
BP1
BP2
BP3
BP7
AB3
A17
AB5
AB6
A3
AE6
AF37
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
M1042225-001
BA45
BA47
BB11
D D
BC37
BD38
BD39
BD41
BD42
BD43
BD45
BD49
C C
B B
A A
BG41
BH37
AA45
BM11
BM45
BM47
AA47
BP43
BR45
BR49
AB11
AB38
AB39
AB41
AB42
AB43
AC45
AC49
AD10
AD11
AD34
AD37
15 OF 19
5
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
AF45
AF47
AG1
AG11
AG3
AG38
AG39
AG41
A31
AG42
AG43
AG5
AG9
AH2
AH37
AH45
AH49
AJ2
AJ3
A34
AK37
AL2
AL45
AL47
AL6
AM2
AM37
AN2
AN38
AN39
A36
AN41
AN42
AN43
AN45
AN49
AN6
AR1
AR11
AR2
AR3
A39
AR7
AR9
AT3
AT45
AT47
AT5
AT6
AT7
AU37
AV11
A42
AV3
AV38
AV39
AV41
AV42
AV43
AV45
AV49
AV7
AY3
A44
AY7
B17
B2
B21
B24
B3
B31
B48
BA1
BA2
4
U1001Q
DJ33
VSS_297
DJ36
VSS_298
DJ42
VSS_299
DK3
VSS_300
DK4
DK49
DL10
DL13
DL44
DL47
DM47
DN15
DN19
DN24
DN31
DN36
DN42
DP45
DR49
DT10
DT15
DT20
DT27
DT32
DT37
DT42
DT49
DU10
DU15
DU20
DU27
DU32
DU37
DU48
DU49
DV44
DV48
DW10
DW20
DW27
DW44
DW46
DW48
DW49
VSS_301
VSS_302
DK6
VSS_303
DK8
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
DT1
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
DT3
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
DT6
VSS_328
DT7
VSS_329
DT8
VSS_330
DU1
VSS_331
VSS_332
VSS_333
DU2
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
DU7
VSS_341
DV2
VSS_342
VSS_343
VSS_344
DV8
VSS_345
DW1
VSS_346
VSS_347
DW2
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
DW7
VSS_355
E11
VSS_356
E34
VSS_357
E36
VSS_358
E39
VSS_359
E42
VSS_360
E6
VSS_361
M1042225-001
<OrgName>
<OrgName>
<OrgName>
Custom
Custom
Custom
17 OF 19
VSS_362
VSS_363
VSS_364
VSS_365
VSS_366
VSS_367
VSS_368
VSS_369
VSS_370
VSS_371
VSS_372
VSS_373
VSS_374
VSS_375
VSS_376
VSS_377
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
VSS_383
VSS_384
VSS_385
VSS_386
VSS_387
VSS_388
VSS_389
VSS_390
VSS_391
VSS_392
VSS_393
VSS_394
VSS_395
VSS_396
VSS_397
VSS_398
VSS_399
VSS_400
VSS_401
VSS_402
VSS_403
VSS_404
VSS_405
VSS_406
VSS_407
VSS_408
VSS_409
VSS_410
VSS_411
VSS_412
VSS_413
VSS_414
VSS_415
VSS_416
VSS_417
VSS_418
VSS_419
VSS_420
VSS_421
VSS_422
VSS_423
VSS_424
VSS_425
VSS_426
VSS_427
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
F11
F31
F45
F47
F8
G21
G24
G3
G31
G36
G49
G5
H17
H21
H24
H31
H33
H36
H45
H49
J10
J13
J16
J36
J6
K11
K33
K8
L36
L39
L41
L42
L43
L45
L47
M10
M3
M36
M5
N45
N49
P11
P41
P8
R3
R37
T11
T36
T41
T43
T45
T47
U3
U37
U5
V11
V36
V45
V49
V9
W37
Y36
Y38
Y43
Y9
DE15
CPU(5)_GND
CPU(5)_GND
CPU(5)_GND
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
14 82Tuesday, May 21, 2019
14 82Tuesday, May 21, 2019
14 82Tuesday, May 21, 2019
1
1.00
1.00
1.00
Page 15
5
4
3
2
1
CFG4
0
Default
1
D D
C C
B B
enable eDP
Disable eDP
TP1519
TP1520
TP1521
R1507 49.9
0201S_P28-W35
TP1528
TP1529
TP1518SP_TP_SMDP58
TP1514SP_TP_SMDP58
Place outside of thermal module
TP1516
U1001S
CFG0[18]
CFG1[18]
CFG2[18]
CFG3[18]
CFG4[18]
CFG5[18]
CFG6[18]
CFG7[18]
CFG16
CFG17[18]
CFG18
CFG_RCOMP
BPM_N_2
BPM_N_3
CFG8
CFG9
CFG10
BPM_N_0
BPM_N_1
AG6
AE7
AG7
AD9
AE9
AB9
AJ6
AB7
V10
AJ5
Y10
AJ7
AB10
AL7
AL9
AJ9
V6
V7
Y6
Y7
AD6
T9
T7
T10
T6
BJ11
BL10
AV1
AT2
AT1
AU1
AU2
AV2
DP3
DT2
AR10
AP10
BP36
BM36
J15
K15
C5
D4
A5
R1502
0
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_RCOMP
BPM_N_0
BPM_N_1
BPM_N_2
BPM_N_3
RSVD_68
RSVD_69
RSVD_TP_AV1
RSVD_TP_AT2
RSVD_TP_AT1
RSVD_TP_AU1
RSVD_TP_AU2
RSVD_TP_AV2
RSVD_83
RSVD_84
RSVD_85
RSVD_87
RSVD_86
RSVD_88
VSS_430
VSS_431
SKTOCC
RSVD_D4
RSVD_70
M1042225-001
19 OF 19
RSVD_TP_1
RSVD_TP_2
RSVD_60
RSVD_61
RSVD_TP_CT32
RSVD_TP_CV32
RSVD_G15
RSVD_F15
RSVD_TP_BW11
RSVD_TP_CA11
VSS_428
VSS_429
RSVD_58
RSVD_59
RSVD_71
RSVD_72
RSVD_65
RSVD_66
RSVD_TP_DV6
RSVD_TP_DW6
RSVD_TP_DP2
RSVD_TP_DP1
RSVD_TP_DW4
RSVD_TP_DV4
RSVD_TP_R1
RSVD_TP_DW3
RSVD_TP_DV3
RSVD_TP_DH49
RSVD_TP_DL8
VSS_432
RSVD_TP_P10
TP_3
TP_4
TP_1
TP_2
A47
B47
C1
E1
CT32
CV32
G15
F15
BW11
CA11
C16
A16
C2
A4
DP5
DR5
D14
E16
DV6
DW6
DP2
DP1
DW4
DV4
CM33
DB10
R1
DW3
DV3
DH49
DL8
DW47
DV47
DU47
P10
TP1501
FIVR_VLOAD_TCSS
CFG4
N34
AK10
BT36
AH10
BC10
CH33
CJ32
AM10
BH10
J34
Y11
L34
AJ11
CG32
CK33
BP41
AL11
BG11
AN11
M13
M34
DU42
DW42
D33
L13
K13
U1001R
RSVD_TP_N34
RSVD_TP_AK10
RSVD_7
RSVD_TP_AH10
RSVD_TP_BC10
RSVD_TP_CH33
RSVD_12
RSVD_TP_AM10
RSVD_TP_BH10
RSVD_TP_J34
RSVD_9
RSVD_10
RSVD_17
RSVD_21
RSVD_22
RSVD_20
RSVD_23
RSVD_24
RSVD_16
RSVD_18
RSVD_19
RSVD_42
RSVD_43
RSVD_44
RSVD_45
RSVD_47
M1042225-001
R1501
1K
0201S_P28-W35
18 OF 19
CFG16
CFG18
RSVD_TP_DA11
RSVD_TP_CL32
RSVD_TP_CN32
RSVD_32
RSVD_33
RSVD_34
IST_TP_0
IST_TP_1
IST_TRIG_0
IST_TRIG_1
PCH_IST_TP0
PCH_IST_TP1
RSVD_27
RSVD_28
VCCIN_AUX_OUT
RSVD_35
RSVD_46
RSVD_48
RSVD_49
RSVD_50
RSVD_51
RSVD_52
RSVD_53
RSVD_54
RSVD_36
RSVD_37
RSVD_38
RSVD_39
RSVD_40
RSVD_41
R1503 49.9
DA11
CL32
CN32
CY35
DB37
DF37
BF11
BD11
BE10
BF10
CW33
CY32
CY37
CV37
C33
G34
H34
DJ34
DK31
DK15
CP3
CP5
AN9
AN7
AF10
AE11
H5
D1
DJ40
DK40
R1504 49.9
A A
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
W x H 367 x 237 mm
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
CPU(6)_CFG,RESERVED
CPU(6)_CFG,RESERVED
CPU(6)_CFG,RESERVED
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
15 82Tuesday, May 21, 2019
15 82Tuesday, May 21, 2019
15 82Tuesday, May 21, 2019
1
1.00
1.00
1.00
Page 16
5
4
3
2
1
M_A_2_DQ_[7:0][11]
M_A_3_DQ_[7:0][11]
D D
+0P6V_DDR_VDDQ
1%
1%
R1601 240
R1602 240
M_A_CA[5:0][11]
C C
B B
A A
+1P1V_DDR_VDD2
LPDDR4X ODT_CA is not used.
M_A_2_DQ_4
M_A_2_DQ_1
M_A_2_DQ_7
M_A_2_DQ_6
M_A_2_DQ_3
M_A_2_DQ_5
M_A_2_DQ_2 M_A_0_DQ_4
M_A_2_DQ_0
M_A_3_DQ_2
M_A_3_DQ_0
M_A_3_DQ_1
M_A_3_DQ_4
M_A_3_DQ_3
M_A_3_DQ_5
M_A_3_DQ_6
M_A_3_DQ_7
M_A_DQS_2_DP[11]
M_A_DQS_2_DN[11]
M_A_DQS_3_DP[11]
M_A_DQS_3_DN[11]
GND GND
ZQ0_1601
ZQ1_1601
M_A_LP4_CKE0[11]
M_A_LP4_CKE1[11]
M_A_LP4_CS#0[11]
M_A_LP4_CS#1[11]
M_A_LP4_CLK_P[11]
M_A_LP4_CLK_N[11]
M_A_CA0
M_A_CA1
M_A_CA2
M_A_CA3
M_A_CA4
M_A_CA5
R1606 0
+1P8V_DDR_VDD1
+1P1V_DDR_VDD2
+0P6V_DDR_VDDQ
GND
U1601
B2
DQ0_A
C2
DQ1_A
E2
DQ2_A
F2
DQ3_A
F4
DQ4_A
E4
DQ5_A
C4
DQ6_A
B4
DQ7_A
B11
DQ8_A
C11
DQ9_A
E11
DQ10_A
F11
DQ11_A
F9
DQ12_A
E9
DQ13_A
C9
DQ14_A
B9
DQ15_A
D3
DQS0_A_t
E3
DQS0_A_c
D10
DQS1_A_t
E10
DQS1_A_c
C3
DMI0_A
C10
DMI1_A
A5
ZQ0
A8
NC/ZQ1
J4
CKE0_A
J5
NC/CKE1_A
H4
CS0_A
H3
NC/CS1_A
J8
CK_A_t
J9
CK_A_c
H2
CA0_A
J2
CA1_A
H9
CA2_A
H10
CA3_A
H11
CA4_A
J11
CA5_A
G2
ODT_CA_A
A1
DNU_A1
A2
DNU_A2
A11
DNU_A11
A12
DNU_A12
B1
DNU_B1
B12
DNU_B12
G11
NC_G11
K5
NC_K5
K8
NC_K8
F1
VDD1_F1
F12
VDD1_F12
G4
VDD1_G4
G9
VDD1_G9
A4
VDD2_A4
A9
VDD2_A9
F5
VDD2_F5
F8
VDD2_F8
H1
VDD2_H1
H5
VDD2_H5
H8
VDD2_H8
H12
VDD2_H12
K1
VDD2_K1
K3
VDD2_K3
K10
VDD2_K10
K12
VDD2_K12
B3
VDDQ_B3
B5
VDDQ_B5
B8
VDDQ_B8
B10
VDDQ_B10
D1
VDDQ_D1
D5
VDDQ_D5
D8
VDDQ_D8
D12
VDDQ_D12
F3
VDDQ_F3
F10
VDDQ_F10
A10
VSS_A10
A3
VSS_A3
C1
VSS_C1
C12
VSS_C12
C5
VSS_C5
C8
VSS_C8
D11
VSS_D11
D2
VSS_D2
D4
VSS_D4
D9
VSS_D9
E1
VSS_E1
E12
VSS_E12
E5
VSS_E5
E8
VSS_E8
G12
VSS_G12
G1
VSS_G1
G10
VSS_G10
G3
VSS_G3
G5
VSS_G5
G8
VSS_G8
J1
VSS_J1
J10
VSS_J10
J12
VSS_J12
J3
VSS_J3
K11
VSS_K11
K2
VSS_K2
K4
VSS_K4
K9
VSS_K9
32GB
BGA200_15P1X10P1X1_P65XP8-2
TBL1601
DQS0_B_t
DQS0_B_c
DQS1_B_t
DQS1_B_c
RESET_n
CKE1_B/NC
CS1_B/NC
ODT_CA_B
DNU_AA1
DNU_AA12
DNU_AB1
DNU_AB2
DNU_AB11
DNU_AB12
VDD1_T4
VDD1_T9
VDD1_U1
VDD1_U12
VDD2_N1
VDD2_N3
VDD2_N10
VDD2_N12
VDD2_R1
VDD2_R5
VDD2_R8
VDD2_R12
VDD2_U5
VDD2_U8
VDD2_AB4
VDD2_AB9
VDDQ_U3
VDDQ_U10
VDDQ_W1
VDDQ_W5
VDDQ_W8
VDDQ_W12
VDDQ_AA3
VDDQ_AA5
VDDQ_AA8
VDDQ_AA10
VSS_N11
VSS_P10
VSS_P12
VSS_T10
VSS_T12
VSS_V12
VSS_W2
VSS_W4
VSS_W9
VSS_W11
VSS_Y12
VSS_AB10
VSS_AB3
VSS_AB5
VSS_AB8
DQ0_B
DQ1_B
DQ2_B
DQ3_B
DQ4_B
DQ5_B
DQ6_B
DQ7_B
DQ8_B
DQ9_B
DQ10_B
DQ11_B
DQ12_B
DQ13_B
DQ14_B
DQ15_B
DMI0_B
DMI1_B
CKE0_B
CS0_B
CK_B_t
CK_B_c
CA0_B
CA1_B
CA2_B
CA3_B
CA4_B
CA5_B
NC_N5
NC_N8
VSS_N2
VSS_N4
VSS_N9
VSS_P1
VSS_P3
VSS_T1
VSS_T3
VSS_T5
VSS_T8
VSS_V1
VSS_V5
VSS_V8
VSS_Y1
VSS_Y5
VSS_Y8
AA2
Y2
V2
U2
U4
V4
Y4
AA4
AA11
Y11
V11
U11
U9
V9
Y9
AA9
W3
V3
W10
V10
Y3
Y10
T11
P4
P5
R4
R3
P8
P9
R2
P2
R9
R10
R11
P11
T2
N5
N8
AA1
AA12
AB1
AB2
AB11
AB12
T4
T9
U1
U12
N1
N3
N10
N12
R1
R5
R8
R12
U5
U8
AB4
AB9
U3
U10
W1
W5
W8
W12
AA3
AA5
AA8
AA10
N2
N4
N9
N11
P1
P3
P10
P12
T1
T3
T5
T8
T10
T12
V1
V5
V8
V12
W2
W4
W9
W11
Y1
Y5
Y8
Y12
AB10
AB3
AB5
AB8
M_A_0_DQ_1
M_A_0_DQ_0
M_A_0_DQ_2
M_A_0_DQ_7
M_A_0_DQ_3
M_A_0_DQ_5
M_A_0_DQ_6
M_A_1_DQ_7
M_A_1_DQ_3
M_A_1_DQ_2
M_A_1_DQ_0
M_A_1_DQ_4
M_A_1_DQ_1
M_A_1_DQ_6
M_A_1_DQ_5
DRAM_RESET#
C1615 0.1u
10VDNP
M_A_LP4_CKE0
M_A_LP4_CKE1
M_A_LP4_CS#0
M_A_LP4_CS#1
M_A_LP4_CLK_P
M_A_LP4_CLK_N
M_A_CA0
M_A_CA1
M_A_CA2
M_A_CA3
M_A_CA4
M_A_CA5
R1605 0
+1P8V_DDR_VDD1
+1P1V_DDR_VDD2
+0P6V_DDR_VDDQ
GND
M_A_DQS_0_DP [11]
M_A_DQS_0_DN [11]
M_A_DQS_1_DP [11]
M_A_DQS_1_DN [11]
DRAM_RESET# [11,17]
GND
+1P1V_DDR_VDD2
M_A_0_DQ_[7:0] [11]
M_A_1_DQ_[7:0] [11]
M_B_2_DQ_[7:0][11]
M_B_3_DQ_[7:0][11]
+0P6V_DDR_VDDQ
1%
1%
R1603 240
R1604 240
M_B_CA[5:0][11]
+1P1V_DDR_VDD2 +1P1V_DDR_VDD2
M_B_2_DQ_4
M_B_2_DQ_1
M_B_2_DQ_6
M_B_2_DQ_5
M_B_2_DQ_7
M_B_2_DQ_3
M_B_2_DQ_2
M_B_2_DQ_0
M_B_3_DQ_2
M_B_3_DQ_6
M_B_3_DQ_5
M_B_3_DQ_4
M_B_3_DQ_3
M_B_3_DQ_1
M_B_3_DQ_0
M_B_3_DQ_7
M_B_DQS_2_DP[11]
M_B_DQS_2_DN[11]
M_B_DQS_3_DP[11]
M_B_DQS_3_DN[11]
GND
M_B_LP4_CKE0[11]
M_B_LP4_CKE1[11]
M_B_LP4_CS#0[11]
M_B_LP4_CS#1[11]
M_B_LP4_CLK_P[11]
M_B_LP4_CLK_N[11]
R1607 0
+1P8V_DDR_VDD1
+1P1V_DDR_VDD2
+0P6V_DDR_VDDQ
ZQ0_1602
ZQ1_1602
M_B_CA0
M_B_CA1
M_B_CA2
M_B_CA3
M_B_CA4
M_B_CA5
GND
U1602
B2
DQ0_A
C2
DQ1_A
E2
DQ2_A
F2
DQ3_A
F4
DQ4_A
E4
DQ5_A
C4
DQ6_A
B4
DQ7_A
B11
DQ8_A
C11
DQ9_A
E11
DQ10_A
F11
DQ11_A
F9
DQ12_A
E9
DQ13_A
C9
DQ14_A
B9
DQ15_A
D3
DQS0_A_t
E3
DQS0_A_c
D10
DQS1_A_t
E10
DQS1_A_c
C3
DMI0_A
C10
DMI1_A
A5
ZQ0
A8
NC/ZQ1
J4
CKE0_A
J5
NC/CKE1_A
H4
CS0_A
H3
NC/CS1_A
J8
CK_A_t
J9
CK_A_c
H2
CA0_A
J2
CA1_A
H9
CA2_A
H10
CA3_A
H11
CA4_A
J11
CA5_A
G2
ODT_CA_A
A1
DNU_A1
A2
DNU_A2
A11
DNU_A11
A12
DNU_A12
B1
DNU_B1
B12
DNU_B12
G11
NC_G11
K5
NC_K5
K8
NC_K8
F1
VDD1_F1
F12
VDD1_F12
G4
VDD1_G4
G9
VDD1_G9
A4
VDD2_A4
A9
VDD2_A9
F5
VDD2_F5
F8
VDD2_F8
H1
VDD2_H1
H5
VDD2_H5
H8
VDD2_H8
H12
VDD2_H12
K1
VDD2_K1
K3
VDD2_K3
K10
VDD2_K10
K12
VDD2_K12
B3
VDDQ_B3
B5
VDDQ_B5
B8
VDDQ_B8
B10
VDDQ_B10
D1
VDDQ_D1
D5
VDDQ_D5
D8
VDDQ_D8
D12
VDDQ_D12
F3
VDDQ_F3
F10
VDDQ_F10
A10
VSS_A10
A3
VSS_A3
C1
VSS_C1
C12
VSS_C12
C5
VSS_C5
C8
VSS_C8
D11
VSS_D11
D2
VSS_D2
D4
VSS_D4
D9
VSS_D9
E1
VSS_E1
E12
VSS_E12
E5
VSS_E5
E8
VSS_E8
G12
VSS_G12
G1
VSS_G1
G10
VSS_G10
G3
VSS_G3
G5
VSS_G5
G8
VSS_G8
J1
VSS_J1
J10
VSS_J10
J12
VSS_J12
J3
VSS_J3
K11
VSS_K11
K2
VSS_K2
K4
VSS_K4
K9
VSS_K9
32GB
BGA200_15P1X10P1X1_P65XP8-2
TBL1601
DQS0_B_t
DQS0_B_c
DQS1_B_t
DQS1_B_c
RESET_n
CKE1_B/NC
CS1_B/NC
ODT_CA_B
DNU_AA1
DNU_AA12
DNU_AB1
DNU_AB2
DNU_AB11
DNU_AB12
VDD1_T4
VDD1_T9
VDD1_U1
VDD1_U12
VDD2_N1
VDD2_N3
VDD2_N10
VDD2_N12
VDD2_R1
VDD2_R5
VDD2_R8
VDD2_R12
VDD2_U5
VDD2_U8
VDD2_AB4
VDD2_AB9
VDDQ_U3
VDDQ_U10
VDDQ_W1
VDDQ_W5
VDDQ_W8
VDDQ_W12
VDDQ_AA3
VDDQ_AA5
VDDQ_AA8
VDDQ_AA10
VSS_N11
VSS_P10
VSS_P12
VSS_T10
VSS_T12
VSS_V12
VSS_W2
VSS_W4
VSS_W9
VSS_W11
VSS_Y12
VSS_AB10
VSS_AB3
VSS_AB5
VSS_AB8
DQ0_B
DQ1_B
DQ2_B
DQ3_B
DQ4_B
DQ5_B
DQ6_B
DQ7_B
DQ8_B
DQ9_B
DQ10_B
DQ11_B
DQ12_B
DQ13_B
DQ14_B
DQ15_B
DMI0_B
DMI1_B
CKE0_B
CS0_B
CK_B_t
CK_B_c
CA0_B
CA1_B
CA2_B
CA3_B
CA4_B
CA5_B
NC_N5
NC_N8
VSS_N2
VSS_N4
VSS_N9
VSS_P1
VSS_P3
VSS_T1
VSS_T3
VSS_T5
VSS_T8
VSS_V1
VSS_V5
VSS_V8
VSS_Y1
VSS_Y5
VSS_Y8
AA2
Y2
V2
U2
U4
V4
Y4
AA4
AA11
Y11
V11
U11
U9
V9
Y9
AA9
W3
V3
W10
V10
Y3
Y10
T11
P4
P5
R4
R3
P8
P9
R2
P2
R9
R10
R11
P11
T2
N5
N8
AA1
AA12
AB1
AB2
AB11
AB12
T4
T9
U1
U12
N1
N3
N10
N12
R1
R5
R8
R12
U5
U8
AB4
AB9
U3
U10
W1
W5
W8
W12
AA3
AA5
AA8
AA10
N2
N4
N9
N11
P1
P3
P10
P12
T1
T3
T5
T8
T10
T12
V1
V5
V8
V12
W2
W4
W9
W11
Y1
Y5
Y8
Y12
AB10
AB3
AB5
AB8
M_B_1_DQ_5
M_B_1_DQ_6
M_B_1_DQ_0
M_B_1_DQ_2
M_B_1_DQ_1
M_B_1_DQ_4
M_B_1_DQ_7
M_B_1_DQ_3
M_B_0_DQ_4
M_B_0_DQ_1
M_B_0_DQ_6
M_B_0_DQ_5
M_B_0_DQ_7
M_B_0_DQ_3
M_B_0_DQ_2
M_B_0_DQ_0
DRAM_RESET#
C1608 0.1u
M_B_LP4_CKE0
M_B_LP4_CKE1
M_B_LP4_CS#0
M_B_LP4_CS#1
M_B_LP4_CLK_P
M_B_LP4_CLK_N
M_B_CA0
M_B_CA1
M_B_CA2
M_B_CA3
M_B_CA4
M_B_CA5
R1608 0
+1P8V_DDR_VDD1
+1P1V_DDR_VDD2
+0P6V_DDR_VDDQ
GND
M_B_DQS_1_DP [11]
M_B_DQS_1_DN [11]
M_B_DQS_0_DP [11]
M_B_DQS_0_DN [11]
GND
10VDNP
GND
M_B_1_DQ_[7:0] [11]
M_B_0_DQ_[7:0] [11]
Performance S cheme, excep t 0402 10uF, 0201 1uF
+1P1V_DDR_VDD2
0402S_P7-W70
GND
+1P1V_DDR_VDD2
GND
+0P6V_DDR_VDDQ
0402S_P7-W70
GND
+0P6V_DDR_VDDQ +0P6V_DDR_VDDQ
GND GND
+1P8V_DDR_VDD1
0402S_P7-W70
GND
+1P8V_DDR_VDD1 +1P8V_DDR_VDD1
GND GND
Evenly distri buted
across all 4 DRAMs
C1613
10u
6.3V
C1614
1u
6.3V
C1631
10u
6.3V
0402S_P7-W70
6 caps per DR AM, 2 per lo ng
edge, 1 per s hort edge
C1612
1u
6.3V
0402S_P7-W70
C1640
1u
6.3V
C1618
10u
6.3V
Performance S cheme, excep t 0402 10uF, 0201 1uF
Evenly distri buted
across all 4 DRAMs
0402S_P7-W70
C1633
1u
10V
C1627
10u
6.3V
C1620
10u
6.3V
C1606
1u
10V
C1634
10u
6.3V
0402S_P7-W70
4 caps per DR AM, 2 per lo ng
edge, 1 per s hort edge
C1639
1u
10V
Performance S cheme, excep t 0402 10uF, 0201 1uF
Evenly distri buted
across all 4 DRAMs
0402S_P7-W70
C1625
1u
10V
C1617
10u
6.3V
C1632
10u
6.3V
C1603
1u
10V
C1609
10u
6.3V
0402S_P7-W70
4 caps per DR AM, 2 per lo ng
edge, 1 per s hort edge
C1637
1u
10V
VDD2 Decoupling
C1623
1u
6.3V
C1605
10u
6.3V
0402S_P7-W70
C1643
1u
6.3V
C1630
10u
6.3V
0402S_P7-W70
C1619
1u
6.3V
VDDQ Decoupling
C1638
10u
6.3V
0402S_P7-W70
C1607
1u
10V
C1616
10u
6.3V
0402S_P7-W70
VDD1 Decoupling
C1644
10u
6.3V
0402S_P7-W70
C1604
1u
10V
C1635
10u
6.3V
0402S_P7-W70
+1P1V_DDR_VDD2
C1645
1u
6.3V
GND
C1628
1u
10V
C1621
1u
10V
6 caps per DR AM, 2 per lo ng
edge, 1 per s hort edge
C1611
1u
6.3V
C1624
1u
10V
C1622
1u
10V
C1610
1u
6.3V
C1629
1u
10V
C1601
1u
10V
C1636
1u
6.3V
4 caps per DR AM, 2 per lo ng
edge, 1 per s hort edge
C1642
1u
10V
4 caps per DR AM, 2 per lo ng
edge, 1 per s hort edge
C1641
1u
10V
C1626
1u
6.3V
C1602
1u
10V
LPDDR4X(1)_MEMORY DOWN
LPDDR4X(1)_MEMORY DOWN
LPDDR4X(1)_MEMORY DOWN
Title:
Title:
Title:
<OrgAddr1>
<OrgAddr1>
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
W x H 602 x 390 mm
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
1
<OrgAddr1>
1.00
1.00
16 82Tuesday, May 21, 2019
16 82Tuesday, May 21, 2019
16 82Tuesday, May 21, 2019
1.00
Page 17
5
4
3
2
1
M_C_1_DQ_[7:0][11]
M_C_0_DQ_[7:0][11]
D D
+0P6V_DDR_VDDQ
1%
1%
240
R1702 240
R1701
M_C_CA[5:0][11]
C C
B B
A A
+1P1V_DDR_VDD2
M_C_1_DQ_4
M_C_1_DQ_1
M_C_1_DQ_7
M_C_1_DQ_0
M_C_1_DQ_2
M_C_1_DQ_5
M_C_1_DQ_3
M_C_1_DQ_6
M_C_0_DQ_0
M_C_0_DQ_2
M_C_0_DQ_5
M_C_0_DQ_7
M_C_0_DQ_3
M_C_0_DQ_6
M_C_0_DQ_4
M_C_0_DQ_1
M_C_DQS_1_DP[11]
M_C_DQS_1_DN[11] M_C_DQS_3_DN [11]
M_C_DQS_0_DP[11]
M_C_DQS_0_DN[11]
GND GND
ZQ0_1701 DRAM_RESET# DRAM_RESET#
ZQ1_1701
M_C_LP4_CKE0[11]
M_C_LP4_CKE1[11]
M_C_LP4_CS#0[11]
M_C_LP4_CS#1[11]
M_C_LP4_CLK_P[11]
M_C_LP4_CLK_N[11]
M_C_CA0
M_C_CA1
M_C_CA2
M_C_CA3
M_C_CA4
M_C_CA5
R1707 0
+1P8V_DDR_VDD1
+1P1V_DDR_VDD2
+0P6V_DDR_VDDQ
5
U1701
B2
DQ0_A
C2
DQ1_A
E2
DQ2_A
F2
DQ3_A
F4
DQ4_A
E4
DQ5_A
C4
DQ6_A
B4
DQ7_A
B11
DQ8_A
C11
DQ9_A
E11
DQ10_A
F11
DQ11_A
F9
DQ12_A
E9
DQ13_A
C9
DQ14_A
B9
DQ15_A
D3
DQS0_A_t
E3
DQS0_A_c
D10
DQS1_A_t
E10
DQS1_A_c
C3
DMI0_A
C10
DMI1_A
A5
ZQ0
A8
NC/ZQ1
J4
CKE0_A
J5
NC/CKE1_A
H4
CS0_A
H3
NC/CS1_A
J8
CK_A_t
J9
CK_A_c
H2
CA0_A
J2
CA1_A
H9
CA2_A
H10
CA3_A
H11
CA4_A
J11
CA5_A
G2
ODT_CA_A
A1
DNU_A1
A2
DNU_A2
A11
DNU_A11
A12
DNU_A12
B1
DNU_B1
B12
DNU_B12
G11
NC_G11
K5
NC_K5
K8
NC_K8
F1
VDD1_F1
F12
VDD1_F12
G4
VDD1_G4
G9
VDD1_G9
A4
VDD2_A4
A9
VDD2_A9
F5
VDD2_F5
F8
VDD2_F8
H1
VDD2_H1
H5
VDD2_H5
H8
VDD2_H8
H12
VDD2_H12
K1
VDD2_K1
K3
VDD2_K3
K10
VDD2_K10
K12
VDD2_K12
B3
VDDQ_B3
B5
VDDQ_B5
B8
VDDQ_B8
B10
VDDQ_B10
D1
VDDQ_D1
D5
VDDQ_D5
D8
VDDQ_D8
D12
VDDQ_D12
F3
VDDQ_F3
F10
VDDQ_F10
A10
VSS_A10
A3
VSS_A3
C1
VSS_C1
C12
VSS_C12
C5
VSS_C5
C8
VSS_C8
D11
VSS_D11
D2
VSS_D2
D4
VSS_D4
D9
VSS_D9
E1
VSS_E1
E12
VSS_E12
E5
VSS_E5
E8
VSS_E8
G12
VSS_G12
G1
VSS_G1
G10
VSS_G10
G3
VSS_G3
G5
VSS_G5
G8
VSS_G8
J1
VSS_J1
J10
VSS_J10
J12
VSS_J12
J3
VSS_J3
K11
VSS_K11
K2
VSS_K2
K4
VSS_K4
K9
VSS_K9
32GB
BGA200_15P1X10P1X1_P65XP8-2
TBL1601
DQS0_B_t
DQS0_B_c
DQS1_B_t
DQS1_B_c
RESET_n
CKE1_B/NC
CS1_B/NC
ODT_CA_B
DNU_AA1
DNU_AA12
DNU_AB1
DNU_AB2
DNU_AB11
DNU_AB12
VDD1_T4
VDD1_T9
VDD1_U1
VDD1_U12
VDD2_N1
VDD2_N3
VDD2_N10
VDD2_N12
VDD2_R1
VDD2_R5
VDD2_R8
VDD2_R12
VDD2_U5
VDD2_U8
VDD2_AB4
VDD2_AB9
VDDQ_U3
VDDQ_U10
VDDQ_W1
VDDQ_W5
VDDQ_W8
VDDQ_W12
VDDQ_AA3
VDDQ_AA5
VDDQ_AA8
VDDQ_AA10
VSS_N11
VSS_P10
VSS_P12
VSS_T10
VSS_T12
VSS_V12
VSS_W11
VSS_Y12
VSS_AB10
VSS_AB3
VSS_AB5
VSS_AB8
DQ0_B
DQ1_B
DQ2_B
DQ3_B
DQ4_B
DQ5_B
DQ6_B
DQ7_B
DQ8_B
DQ9_B
DQ10_B
DQ11_B
DQ12_B
DQ13_B
DQ14_B
DQ15_B
DMI0_B
DMI1_B
CKE0_B
CS0_B
CK_B_t
CK_B_c
CA0_B
CA1_B
CA2_B
CA3_B
CA4_B
CA5_B
NC_N5
NC_N8
VSS_N2
VSS_N4
VSS_N9
VSS_P1
VSS_P3
VSS_T1
VSS_T3
VSS_T5
VSS_T8
VSS_V1
VSS_V5
VSS_V8
VSS_W2
VSS_W4
VSS_W9
VSS_Y1
VSS_Y5
VSS_Y8
AA2
Y2
V2
U2
U4
V4
Y4
AA4
AA11
Y11
V11
U11
U9
V9
Y9
AA9
W3
V3
W10
V10
Y3
Y10
T11
P4
P5
R4
R3
P8
P9
R2
P2
R9
R10
R11
P11
T2
N5
N8
AA1
AA12
AB1
AB2
AB11
AB12
T4
T9
U1
U12
N1
N3
N10
N12
R1
R5
R8
R12
U5
U8
AB4
AB9
U3
U10
W1
W5
W8
W12
AA3
AA5
AA8
AA10
N2
N4
N9
N11
P1
P3
P10
P12
T1
T3
T5
T8
T10
T12
V1
V5
V8
V12
W2
W4
W9
W11
Y1
Y5
Y8
Y12
AB10
AB3
AB5
AB8
M_C_3_DQ_7
M_C_3_DQ_3
M_C_3_DQ_5
M_C_3_DQ_6
M_C_3_DQ_0
M_C_3_DQ_1
M_C_3_DQ_2
M_C_3_DQ_4
M_C_2_DQ_7
M_C_2_DQ_3
M_C_2_DQ_0
M_C_2_DQ_5
M_C_2_DQ_1
M_C_2_DQ_6
M_C_2_DQ_4
M_C_2_DQ_2
M_C_DQS_3_DP [11]
M_C_DQS_2_DP [11]
M_C_DQS_2_DN [11]
C1729 0.1u
M_C_LP4_CKE0
M_C_LP4_CKE1
M_C_LP4_CS#0
M_C_LP4_CS#1
M_C_LP4_CLK_P
M_C_LP4_CLK_N
M_C_CA0
M_C_CA1
M_C_CA2
M_C_CA3
M_C_CA4
M_C_CA5
10VDNP
R1705 0
+1P8V_DDR_VDD1
+1P1V_DDR_VDD2
+0P6V_DDR_VDDQ
GND GND GNDGND
M_C_3_DQ_[7:0] [11] M_D_3_DQ_[7:0] [11]
M_C_2_DQ_[7:0] [11]
DRAM_RESET# [11,16]
GND
+1P1V_DDR_VDD2
4
M_D_1_DQ_[7:0][11]
M_D_0_DQ_[7:0][11]
+0P6V_DDR_VDDQ
1%
R1704 240
R1703 240
1%
M_D_LP4_CLK_P[11]
M_D_LP4_CLK_N[11]
M_D_CA[5:0][11]
+1P1V_DDR_VDD2
+1P8V_DDR_VDD1
+1P1V_DDR_VDD2
M_D_1_DQ_3
M_D_1_DQ_6
M_D_1_DQ_7
M_D_1_DQ_4
M_D_1_DQ_0
M_D_1_DQ_5
M_D_1_DQ_1
M_D_1_DQ_2
M_D_0_DQ_2
M_D_0_DQ_0
M_D_0_DQ_5
M_D_0_DQ_3
M_D_0_DQ_7
M_D_0_DQ_6
M_D_0_DQ_4
M_D_0_DQ_1
M_D_DQS_1_DP[11]
M_D_DQS_1_DN[11]
M_D_DQS_0_DP[11]
M_D_DQS_0_DN[11]
M_D_LP4_CKE0[11]
M_D_LP4_CKE1[11]
M_D_LP4_CS#0[11]
M_D_LP4_CS#1[11]
R1708 0
+0P6V_DDR_VDDQ
ZQ0_1702
ZQ1_1702
M_D_CA0
M_D_CA1
M_D_CA2
M_D_CA3
M_D_CA4
M_D_CA5
U1702
B2
DQ0_A
C2
DQ1_A
E2
DQ2_A
F2
DQ3_A
F4
DQ4_A
E4
DQ5_A
C4
DQ6_A
B4
DQ7_A
B11
DQ8_A
C11
DQ9_A
E11
DQ10_A
F11
DQ11_A
F9
DQ12_A
E9
DQ13_A
C9
DQ14_A
B9
DQ15_A
D3
DQS0_A_t
E3
DQS0_A_c
D10
DQS1_A_t
E10
DQS1_A_c
C3
DMI0_A
C10
DMI1_A
A5
ZQ0
A8
NC/ZQ1
J4
CKE0_A
J5
NC/CKE1_A
H4
CS0_A
H3
NC/CS1_A
J8
CK_A_t
J9
CK_A_c
H2
CA0_A
J2
CA1_A
H9
CA2_A
H10
CA3_A
H11
CA4_A
J11
CA5_A
G2
ODT_CA_A
A1
DNU_A1
A2
DNU_A2
A11
DNU_A11
A12
DNU_A12
B1
DNU_B1
B12
DNU_B12
G11
NC_G11
K5
NC_K5
K8
NC_K8
F1
VDD1_F1
F12
VDD1_F12
G4
VDD1_G4
G9
VDD1_G9
A4
VDD2_A4
A9
VDD2_A9
F5
VDD2_F5
F8
VDD2_F8
H1
VDD2_H1
H5
VDD2_H5
H8
VDD2_H8
H12
VDD2_H12
K1
VDD2_K1
K3
VDD2_K3
K10
VDD2_K10
K12
VDD2_K12
B3
VDDQ_B3
B5
VDDQ_B5
B8
VDDQ_B8
B10
VDDQ_B10
D1
VDDQ_D1
D5
VDDQ_D5
D8
VDDQ_D8
D12
VDDQ_D12
F3
VDDQ_F3
F10
VDDQ_F10
A10
VSS_A10
A3
VSS_A3
C1
VSS_C1
C12
VSS_C12
C5
VSS_C5
C8
VSS_C8
D11
VSS_D11
D2
VSS_D2
D4
VSS_D4
D9
VSS_D9
E1
VSS_E1
E12
VSS_E12
E5
VSS_E5
E8
VSS_E8
G12
VSS_G12
G1
VSS_G1
G10
VSS_G10
G3
VSS_G3
G5
VSS_G5
G8
VSS_G8
J1
VSS_J1
J10
VSS_J10
J12
VSS_J12
J3
VSS_J3
K11
VSS_K11
K2
VSS_K2
K4
VSS_K4
K9
VSS_K9
32GB
BGA200_15P1X10P1X1_P65XP8-2
TBL1601
DQS0_B_t
DQS0_B_c
DQS1_B_t
DQS1_B_c
RESET_n
CKE1_B/NC
CS1_B/NC
ODT_CA_B
DNU_AA1
DNU_AA12
DNU_AB1
DNU_AB2
DNU_AB11
DNU_AB12
VDD1_T4
VDD1_T9
VDD1_U1
VDD1_U12
VDD2_N1
VDD2_N3
VDD2_N10
VDD2_N12
VDD2_R1
VDD2_R5
VDD2_R8
VDD2_R12
VDD2_U5
VDD2_U8
VDD2_AB4
VDD2_AB9
VDDQ_U3
VDDQ_U10
VDDQ_W1
VDDQ_W5
VDDQ_W8
VDDQ_W12
VDDQ_AA3
VDDQ_AA5
VDDQ_AA8
VDDQ_AA10
VSS_N11
VSS_P10
VSS_P12
VSS_T10
VSS_T12
VSS_V12
VSS_W11
VSS_Y12
VSS_AB10
VSS_AB3
VSS_AB5
VSS_AB8
3
DQ0_B
DQ1_B
DQ2_B
DQ3_B
DQ4_B
DQ5_B
DQ6_B
DQ7_B
DQ8_B
DQ9_B
DQ10_B
DQ11_B
DQ12_B
DQ13_B
DQ14_B
DQ15_B
DMI0_B
DMI1_B
CKE0_B
CS0_B
CK_B_t
CK_B_c
CA0_B
CA1_B
CA2_B
CA3_B
CA4_B
CA5_B
NC_N5
NC_N8
VSS_N2
VSS_N4
VSS_N9
VSS_P1
VSS_P3
VSS_T1
VSS_T3
VSS_T5
VSS_T8
VSS_V1
VSS_V5
VSS_V8
VSS_W2
VSS_W4
VSS_W9
VSS_Y1
VSS_Y5
VSS_Y8
AA2
Y2
V2
U2
U4
V4
Y4
AA4
AA11
Y11
V11
U11
U9
V9
Y9
AA9
W3
V3
W10
V10
Y3
Y10
T11
P4
P5
R4
R3
P8
P9
R2
P2
R9
R10
R11
P11
T2
N5
N8
AA1
AA12
AB1
AB2
AB11
AB12
T4
T9
U1
U12
N1
N3
N10
N12
R1
R5
R8
R12
U5
U8
AB4
AB9
U3
U10
W1
W5
W8
W12
AA3
AA5
AA8
AA10
N2
N4
N9
N11
P1
P3
P10
P12
T1
T3
T5
T8
T10
T12
V1
V5
V8
V12
W2
W4
W9
W11
Y1
Y5
Y8
Y12
AB10
AB3
AB5
AB8
M_D_3_DQ_1
M_D_3_DQ_2
M_D_3_DQ_0
M_D_3_DQ_4
M_D_3_DQ_3
M_D_3_DQ_5
M_D_3_DQ_6
M_D_3_DQ_7
M_D_2_DQ_1
M_D_2_DQ_4
M_D_2_DQ_7
M_D_2_DQ_5
M_D_2_DQ_3
M_D_2_DQ_6
M_D_2_DQ_0
M_D_2_DQ_2
M_D_LP4_CKE0
M_D_LP4_CKE1
M_D_LP4_CS#0
M_D_LP4_CS#1
M_D_LP4_CLK_P
M_D_LP4_CLK_N
M_D_CA0
M_D_CA1
M_D_CA2
M_D_CA3
M_D_CA4
M_D_CA5
R1706 0
+1P8V_DDR_VDD1
+1P1V_DDR_VDD2
+0P6V_DDR_VDDQ
M_D_DQS_3_DP [11]
M_D_DQS_3_DN [11]
M_D_DQS_2_DP [11]
M_D_DQS_2_DN [11]
GNDGND
GND
10VDNP
+1P1V_DDR_VDD2
M_D_2_DQ_[7:0] [11]
+1P1V_DDR_VDD2
C1710
1u
10V
GND
C1724
1u
10V
GND
C1730
1u
10V
GND
Performance Scheme, except 0201 1uF
6 caps per DRAM, 2 per long
edge, 1 per short edge
C1727
C1717
C1725
1u
10V
1u
10V
1u
10V
Performance Scheme, except 0201 1uF
4 caps per DRAM, 2 per long
edge, 1 per short edge
C1714
1u
10V
C1711
1u
10V
C1706
1u
10V
Performance Scheme, except 0201 1uF
4 caps per DRAM, 2 per long
edge, 1 per short edge
C1704
1u
10V
C1722
1u
10V
C1718
1u
10V
2
VDD2 Decoupling
+1P1V_DDR_VDD2
C1703
1u
10V
C1705
1u
10V
GND
C1713
1u
10V
VDDQ Decoupling
+0P6V_DDR_VDDQ+0P6V_DDR_VDDQ
C1721
1u
10V
GND
VDD1 Decoupling
+1P8V_DDR_VDD1+1P8V_DDR_VDD1
C1728
1u
10V
GND
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
W x H 572 x 370 mm
6 caps per DRAM, 2 per long
edge, 1 per short edge
C1726
C1708
1u
10V
C1712
1u
10V
C1702
1u
10V
C1720
1u
10V
C1707
1u
10VC1723 0.1u
C1719
1u
10V
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
1
1u
10V
4 caps per DRAM, 2 per long
edge, 1 per short edge
C1701
1u
10V
4 caps per DRAM, 2 per long
edge, 1 per short edge
C1716
1u
10V
<OrgName>
<OrgName>
<OrgName>
Custom
Custom
Custom
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
C1715
C1709
1u
1u
10V
10V
LPDDR4X(2)_MEMORY DOWN
LPDDR4X(2)_MEMORY DOWN
LPDDR4X(2)_MEMORY DOWN
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
1.00
1.00
17 82Tuesday, May 21, 2019
17 82Tuesday, May 21, 2019
17 82Tuesday, May 21, 2019
1.00
Page 18
5
Pin
Pin
VISA,
4
USB2_DN 5 6 USB3_TX_DN
VBUS 7 8 GND
10
12
14
16
18
20
22
24
26
28
32
34
36
38
42
44
48
50
52
54
58
D D
4
3
2
1
+5VSB
+1P8VSB +3P3VSB
J1801
RECEPTACLE
1
1
3
3
5
5
7
7
9
9
SAM_PD_SCL[29,33,35,79]
SAM_PD_SDA[29,33,35,79]
GPP_E5[24]
GPP_E6[10]
GPP_E7[10]
C C
GPP_E8[21]
+VCC1.05_OUT_FET
R1805 0
V1P05A_DEBUG
CFG17[15]
PROC_PRDY#[10]
XDP_SPI0_IO2[21,34]
XDP_PRESENT#[34,56]
PCH_JTAG_TCK[10,76]
PCH_JTAG_TCK_MUX[29]
CFG0[15,18]
CFG1[15]
CFG2[15]
CFG3[15]
CFG4[15]
CFG5[15]
CFG6[15]
CFG7[15]
R1824 0
R1814 0
DBG_D
R1836 0
MIPI60_PRESENT2
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
R18070
R18320
DNP
USB BSSB is moved from SFF to USBC debug.
MIPI60_TCLK
MIPI60_TDI
MIPI60_TRST_N
MIPI60_TMS
MIPI60_TDO
MIPI60_DRRESET_N
V1P05A_CPU
SPI0_MOSI_XDP_R
MIPI60_HOOK2
MIPI60_SMCMIPI60_TCLK1
GPP_E0 [24]
GPP_E1 [21]
GPP_E2 [21]
GPP_E3 [10]
R18030
R18301K
R18200
R18080
R18160
R18290
R18060
R18150
0
R1819
R18280
R18171K
R18110
R18020
DNP
GPP_E4 [24]
RSMRST# [22,37]
+VCC1.05_OUT_FET
XDP_TCK [10,76]
XDP_TDI [10,76]
DBG_PMODE [10,29]
XDP_TRST# [10,76]
XDP_TMS [10,76]
XDP_TDO [10,76]
PCH_SYS_RST# [22,33]
PROC_PREQ# [10]
VCCIO_OUT [12]
SPI0_MOSI_XDP [21]
CFG0 [15,18]
XDP_PCH_PWRBTN# [22]
PWRBTN#_1V8 [31,33,34]
Better R1822/1826/1809/1818 put at PCH side.
GND
B B
Signal
GND 1
USB2_DP 3
VBUS 9
I2C_SCL 11
I2C_SDA 13
GND 15
MIPI60_FN13 17
MIPI60_FN14 19
MIPI60_FN15 21
MIPI60_FN_CLK2 23
GND 25
I2C_2_SCL 27
+V1.05A_VREF_DEBUG 2 9
MIPI60_NOA_STB0_DP 3 1
GND 33
MIPI60_PRDY_N 35
MIPI60_PRESENT1_N 37
MIPI60_OVERRIDE 3 9
A A
MIPI60_NOA0_N 41
MIPI60_NOA1_N 43
MIPI60_NOA2_N 45
MIPI60_NOA3_N 47
MIPI60_NOA4_N 49
MIPI60_NOA5_N 51
MIPI60_NOA6_N 53
MIPI60_NOA7_N 55
MIPI60_TCLK1 57
GND 59
# Interface
PCH-
USB,I2C
CPU-VISA
# Signal
2 GND
USB3_TX_DP
USB3_RX_DP
USB3_RX_DN
GND
+V3P3A_PCH_VREF_TRACE
MIPI60_FN8
MIPI60_FN9
MIPI60_FN10
MIPI60_FN11
MIPI60_FN12
PM_RSMRST_N*
30 GND
MIPI60_TCLK
MIPI60_TDI
DBG_PMODE_MIPI60_RST_R_N
MIPI60_TRST_N
40 MIPI60_TMS
MIPI60_TDO
MIPI60_DBRESET_N
46 I2C_2_SDA
MIPI60_PREQ_N
+V1.05A_CPU_VREF_TRACE
GND
SPI0_MOSI_SYS_PWROK_MIPI60
MIPI60_HOOK2_CPU_BOOT_STAL
56
L
SMC_ONOFF_MIPI60_N
60 GND
5
4
DBG_D
3
GND
0.1u
C1803
0.1u
C1801
0.1u
GNDGNDGND
2
DBG_DC1802
DBG_D
DBG_D
DBG_D
R18310
R18130
R18210
R18100
R18230
R18340
R18350
R18330
R18370
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
W x H 392 x 254 mm
PCH_JTAGX [10,76]
PCH_JTAG_TDI [10,76]
PCH_TRST# [10,76]
PCH_JTAG_TMS [10,76]
PCH_JTAG_TDO [10,76]
PCH_JTAG_TDI_MUX [29]
PCH_JTAG_TMS_MUX [29]
PCH_JTAG_TDO_MUX [29]
XDP_TCK_MUX [29]
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
SFF
SFF
SFF
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
18 82Tuesday, May 21, 2019
18 82Tuesday, May 21, 2019
1
18 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 19
5
D D
4
3
2
1
C C
B B
A A
Title:
Title:
Title:
<OrgAddr1>
<OrgAddr1>
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
W x H 372 x 241 mm
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
<OrgAddr1>
19 82Tuesday, May 21, 2019
19 82Tuesday, May 21, 2019
19 82Tuesday, May 21, 2019
1
1.00
1.00
1.00
Page 20
5
4
3
2
R2001 10M
1
U1001J
CJ3
CLKOUT_PCIE_N0
CJ5
CLKOUT_PCIE_P0
DK33
GPP_D5/SRCCLKREQ0
CL2
CLKOUT_PCIE_N1
CL1
D D
M.2 SSD
C C
M2_PCIECLK_N[44]
M2_PCIECLK_P[44]
M2_PCIECLK_REQ#[44]
CLKOUT_PCIE_P1
DN34
GPP_D6/SRCCLKREQ1
CL3
CLKOUT_PCIE_N2
CL5
CLKOUT_PCIE_P2
DP34
GPP_D7/SRCCLKREQ2
CK3
CLKOUT_PCIE_N3
CK4
CLKOUT_PCIE_P3
DP36
GPP_D8/SRCCLKREQ3
CJ2
CLKOUT_PCIE_N4
CJ1
CLKOUT_PCIE_P4
DN40
GPP_H10/SRCCLKREQ4
M1042225-001
10 OF 19
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
GPP_H11/SRCCLKREQ5
RTCX1
RTCX2
RTCRST
SRTCRST
GPD8/SUSCLK
XTAL_IN
XTAL_OUT
XCLK_BIASREF
CF5
CF3
DP40
DL48
DL49
DT47
DK46
DF49
DW8
DU8
DU6
RTC_X1
RTC_X2
RTC_RST#
SRTC_SRST#
XTAL_38P4M_IN
XTAL_38P4M_OUT
XCLK_BIASREF
R2022
60.4
TP2001
R2014 0
R2035 200K
R2013
0
R2083 0
C2007
10p 50V
NEEDS 38.4MHZ CRYSTAL
SUSCLK [50]
Y2001 38.4MHz
3 1
GND
24
R2007
0
R2005 0
C2001
15p 25V
5%
R2012
0
C2006
10p 50V
CTAL_1
1 2
X2001
R2021
71.5K
C2003
32.768KHZ
+VCC_RTC
R2002
2.2u10V
XTAL2_3P3X1P6XP9_2P5
71.5K
C2004
10V
C2002
15p 25V
5%
2.2u
R2004
0
D
Q2002
S
G
TP2004
RTCRST_CTRL_FET
100K
0
R2081
R2084
RTCRST_CTRL [35]
DNP
R2009 1K
HDA_SDO_R pin has internal pull-up
MHDA_BCLK[40]
MHDA_SYNC[40]
MHDA_SDOUT[40]
MHDA_SDIN[40]
TS_IRQ_1V8#[30]
B B
MODEM_CLKREQ[33,50]
10K
R2006
R2053 0
R2020 0
R2054 0
HDA_RST#
R2011
75K
DNP
R2008 33
R2010 0
ISP_FW_LOCK#[54]
C2009 2p
C2010 2p
C2008 2p
CNV_RF_RESET#[33,50]
+1P8VSB
HDA_BCLK_R
HDA_SYNC_R
HDA_SDO_R
INT. PD
TS_IRQ#_R
U1001G
CY46
GPP_R0/HDA_BCLK/I2S0_SCLK
CV49
GPP_R1/HDA_SYNC/I2S0_SFRM
CY47
GPP_R2/HDA_SDO/I2S0_TXD
CV45
GPP_R3/HDA_SDI0/I2S0_RXD
DA47
GPP_R4/HDA_RST
DP33
GPP_D19/I2S_MCLK
DC45
GPP_A23/I2S1_SCLK
DA49
GPP_R5/HDA_SDI1/I2S1_SFRM
DA45
GPP_R6/I2S1_TXD
DA48
GPP_R7/I2S1_RXD
CT49
GPP_A7/I2S2_SCLK
CT48
GPP_A8/I2S2_SFRM/CNV_RF_RESET
CV47
GPP_A10/I2S2_RXD
CT47
GPP_A9/I2S2_TXD/MODEM_CLKREQ
CY39
GPP_S0/SNDW1_CLK
CY38
GPP_S1/SNDW1_DATA
DB39
GPP_S2/SNDW2_CLK
DD38
GPP_S3/SNDW2_DATA
DF38
GPP_S4/SNDW3_CLK/DMIC_CLK1
DD39
GPP_S5/SNDW3_DATA/DMIC_DATA1
M1042225-001
7 OF 19
SD3.0
GPP_H1/SD_PWR_EN_N/CNV_BT_I2S_SDO
GPP_S7/SNDW4_DATA/DMIC_DATA0
AUDIO
GPP_H0/CNV_BT_I2S_SDO
GPP_S6/SNDW4_CLK/DMIC_CLK0
GPP_G6/SD_CLK
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G0/SD_CMD
GPP_G7/SD_WP
GPP_G5/SD_CD
SD3_RCOMP
SNDW_RCOMP
CE46
CC48
CC49
CC47
CF45
CC45
CF49
CE47
DK38
DG38
CJ43
DG36
DG34
CV38
SD_RCOMP
SNDW_RCOMP
TP2003
R2003
200
0201S_P26
R2080
200
0201S_P26
GPP_R2/HDA_SDO
A A
0 Enable Flash Security
Default
1
5
Disable Flash Security
PCH(1)_SD,HDA,RTC,CLK
PCH(1)_SD,HDA,RTC,CLK
Title:
Title:
Title:
Engineer:
Engineer:
Size Project Nam e Rev
Size Project Nam e Rev
Size Project Nam e Rev
Custom
Custom
Custom
W x H 417 x 270mm
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
PCH(1)_SD,HDA,RTC,CLK
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
20 82Tuesday, May 21, 2019
20 82Tuesday, May 21, 2019
1
20 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 21
5
XDP_SPI0_IO2[18,34]
SPI0_MOSI_XDP[18]
1K
R2109 33
R2101 33
R2105 33
R2112 0
R2134
1K
SPI_CLK_PCH
SPI_MOSI_PCH
SPI_MISO_PCH
SPI_WP_IO2
SPI_HOLD#_IO3
SPI_CS#0_R
SPI_CS#2_R
R2151 75K
SPI_CLK[38]
SPI_MOSI[38]
SPI_MISO[38]
D D
SPI_TPM_CS#[38]
TS_SPI_CLK[30]
TS_SPI_MOSI[30]
TS_SPI_MISO[30]
GPP_E1[18]
GPP_E2[18]
TS_SPI_CS#[30]
R2141 5.1
R2154 5.1
R2155 5.1
R2133
R2158 0
R2113
R2132
75K
75K
TS_SPI_CLK_R
TS_SPI_MOSI_R
TS_SPI_MISO_R
TS_SPI_CS#_R
GPP_E8[ 18]
+1P8VSB
R2123
75K
U1001E
DB42
SPI0_CLK
DD43
SPI0_MOSI
DF43
SPI0_MISO
DF42
SPI0_IO2
DD41
SPI0_IO3
DB43
SPI0_CS0
DF41
SPI0_CS1
DB41
SPI0_CS2
DV16
GPP_E11/SPI1_CLK/BK1/SBK1
DT16
GPP_E13/SPI1_MOSI/BK3/SBK3
DU18
GPP_E12/SPI1_MISO/BK2/SBK2
DT18
GPP_E1/SPI1_IO2
DW18
GPP_E2/SPI1_IO3
DW16
GPP_E10/SPI1_CS_N/BK0/SBK0
DU16
GPP_E8/SATALED_N/SPI1_CS1
DV19
CL_CLK
DW19
CL_DATA
DT19
CL_RST
M1042225-001
4
5 OF 19
SPI 0
SPI 1
MLINK
1
SMBUS
SML 0
GPP_C6/SML1CLK/SUSWARN_N/SUSPWRDNACK
SML1
eSPI
7bit i2c
Address
0x4D
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT
GPP_C7/SML1DATA/SUSACK
GPP_A5/ESPI_CLK
GPP_A0/ESPI_IO0
GPP_A1/ESPI_IO1
GPP_A2/ESPI_IO2
GPP_A3/ESPI_IO3
GPP_A4/ESPI_CS
GPP_A6/ESPI_RESET
R2114
DK27
DP24
DL24
DK24
DJ24
DP22
DN22
DL22
CR47
CN45
CN48
CN49
CN47
CT45
CR46
0
INT. PD
INT. PD
SML0CLK
SML0DAT
DEPROM_PROG [ 57]
R2102
1K
DNP
0201S_P28-W35
0201S_P28-W35
ME_CRYPTO_EN
EN_ESPI
3
R2103
R2107
1K
1K
DNP
0201S_P28-W35
R2142 49.9
10
R2143
10
R2119
10
R2118
10
R2129
0
R2140
0201S_P28-W35
R2110
1K
R2104
1K
0201S_P28-W35
ESPI_CLK [ 35]
ESPI_IO_0 [35]
ESPI_IO_1 [35]
ESPI_IO_2 [35]
ESPI_IO_3 [35]
ESPI_CS# [ 35]
R2150
75K
+3P3VSB
R2106
1K
0201S_P28-W35
R2117
R2115
1K
1K
DNP
DNP
Customer or Enterprise mode detection
R2111
1K
PD_I2C2_SCL [77,79]
PD_I2C2_SDA [77,79]
ESPI_RST# [35 ]
TP2128
SP_TP_SMDP58
2
1
C C
+1P8VSB
R2121
1K
ALL
UEFI_SPI1_CLK
UEFI_SPI_IO0
UEFI_SPI_IO1
UEFI_SPI_IO2
UEFI_SPI_IO3
B B
UEFI_SPI_CS#
Populate for production only
SPI_CLK_R1[76]
SPI_MOSI_R1[76]
SPI_MISO_R1[76]
SPI_WP_IO2_R 1[ 76]
SPI_HOLD#_IO3_R1[76]
SPI_CS#0_R[76]
R2127
R2128
R2146
R2130
R2147
R2149
0 DBG_N
0 DBG_N
0 DBG_N
0 DBG_N
0 DBG_N
0 DBG_N
R2120
1K
DNP
C2111
0.1u
0201
SPI_CLK = 20/33/50Mhz
UEFI SPI ROM
U2102
8
VCC
6
CLK
1
CS
4
GND
9
MPAD
W25R128J WPIQ
SPI_CLK_R1
SPI_MOSI_R1
SPI_MISO_R1
SPI_WP_IO2_R 1
SPI_HOLD#_IO3_R1
+1P8VSB
5
IO0
2
IO1
3
IO2
7
IO3
DBG_D
U2103
TS3A27518EZQSR
BGA24_5X5_3P1X3P1X1_P5
A1
COM1
COM2
COM3
COM4
COM5
COM6
N.C.
NC1
NC2
NC3
NC4
NC5
NC6
EN#
GND
NO1
NO2
NO3
NO4
NO5
NO6
V+
IN1
IN2
B1
C1
D1
E1
D2
A3
B3
A2
A4
B5
C5
A5
R2138 15
R2137 15
R2145 15
R2144 33
R2108 33
R2122
1K
DNP
C2110
0.1u
10V
DBG_D
SPI1_WP#_DBG
SPI1_HOLD#_DBG
+1P8VSB
R2148
1K
DBG_D
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_WP_IO2
SPI_HOLD#_IO3
SPI_CS#0_R
R2124
1K
DBG_D
+1P8VSB
R2125
100K
0201
DNP
R2126
2K
DBG_D
IN1/IN2 = L => COM to NC
IN1/IN2 = H => NC to COM
SAM_UEFIROM_SPI_CLK [34]
SAM_UEFIROM_SPI_MO SI [ 34]
SAM_UEFIROM_SPI_MISO [34]
SAM_UEFIROM_SPI_CS# [35]
SAM_UEFIROM_EN [35,76]
Needs to strap SPI0_IO2, SPI0_IO3 high
GPP_C2/SMBALERT#
0 Disable ME crypto TLS
Default
1
Enable ME crypto TLS
GPP_C5/SMLALERT#
0 Enable eSPI
Default
1
Disable eSPI
+1P8VSB
C2
C4
B4
D3
C3
E2
E3
E4
D5
D4
E5
A A
PCH(2)_CLK,SMB,LPC,SPI
PCH(2)_CLK,SMB,LPC,SPI
PCH(2)_CLK,SMB,LPC,SPI
Title:
Title:
Title:
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
Engineer:
Engineer:
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A2
A2
A2
W x H 417 x 270mm
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
1
1.00
1.00
21 82Tuesday, May 21, 2019
21 82Tuesday, May 21, 2019
21 82Tuesday, May 21, 2019
1.00
Page 22
5
+1P8VSUS_ORG
Level Shift Should be Able to Remove
Only 3.3V connected to TPM
C2202
0.1u
10V
PLT_RST_BUF#[33,34,38,44]
D D
PCH_SYS_RST#[18,33]
RSMRST#[18,37]
R2224
49.9K
If switch to 1.8V SPI IO, Then change
U2202
74AUP1G08GX
5
VCC
4
Y
3
GND
Note:
Place C2204
next to U2202.2
R2223 0DNP
PLTRST#[58]
+3P3VSB
R2239 0
0201S_P28-W35
2
A
1
B
R2225
10K
0201S_P28-W35
C2204
100p
PM_RSMRST_R
Level shifter needed for connection to SAM
R2208
75K
ALL
4
SLP_SUS#[34,62]
TP2217
SLP_S4#[33,34,60]
SLP_S3#[22,33,34,58]
SLP_A#[33,34]
SLP_S0#[33,34]
TP2202
TP2221
TP2220
+VCC_RTC
Fastboot <140mS need
diode connected
to both VCCRTC
and 3P3VDSW.
TP2208
TP2218
R2258 33
R2267 33
R2264 33
R2265 33
R2263 33
PCH_DPWROK_R
SYS_PWROK_R
R22561M
C2201
0.1u
DNP
TP2203
TP2219
INPUT3VSEL_STRAP
INTRUDER#
R2206
100K
SLP_SUS#_R
SLP_S5#_R
SLP_S4#_R
SLP_S3#_R
SLP_A#_R
SLP_S0#_R
SLP_WLAN#
SLP_LAN#
PLTRST#
DM49
DF45
DC48
DF47
DH47
CL45
DE49
DN48
DG49
DK19
CM49
DR48
DN47
DP19
DN49
DR47
3
U1001K
SLP_SUS
GPD10/SLP_S5
GPD5/SLP_S4
GPD4/SLP_S3
GPD6/SLP_A
GPP_B12/SLP_S0
GPD9/SPL_WLAN
SLP_LAN
RSMRST
SYS_RESET
GPP_B13/PLTRST
DSW_PWROK
PCH_PWROK
SYS_PWROK
INPUT3VSEL
INTRUDER
M1042225-001
11 OF 19
GPD3/PWRBTN
GPD1/ACPRESENT
GPD0/BATLOW
GPP_B11/PMCALERT
GPP_H3/SX_EXIT_HOLDOFF_N/CNV_BT_I2S_SDO
GPP_H18/CPU_C10_GATE
WAKE
GPD11/LANPHYPC/DSWLDO_MON
GPD_2/LAN_WAKE
VCCST_OVERRIDE
VCCST_PWRGD
VCCSTPWRGOOD_TCSS
PROCPWRGD
GPD7
CY42
DE46
BATLOW#_R
DH48
CL39
R2211 0
DU40
DG40
DL45
DE47
DF48
VCCST_OVERRIDE
CE4
VCCST_PWRGD_R
CF2
VCCST_PWRGD_TCSS
CE3
CF1
PROCPWRGD
INT. PD
DC47
2
R221210K
R225920K
LANPHYPC
R2202
R2232 0
R222610K
+3P3VSB
TP2216
R225760.4
TP2211
TP2201
BB_PERST# [77]
10K
XDP_PCH_PWRBTN# [18]
SAM_PCH_PWRBTN# [10,37]
+3P3VSB
PD_BB_I2C2_INT# [77,79]
CPU_C10_GATE# [33,56,60,62]
+3P3VSB
VCCST_PWRGD [58]
R2262 0
1
SAM_PCH_ACPRESENT [37]
10K
R2268
R2251
49.9K
C C
R2260 0
R2261 0
R2255
100K
R2228 100
0201S_P28-W35
SYS_PWROK[37]
SLP_S3#[22,33,34,58]
PM_PCH_PWROK[35]
B B
0201S_P28-W35
R2252 100K
U2203
1
2
VCC
A
B
GND
SN74LV1T08DCKR
0201S_P28-W35
+3P3VSB
5
PM_PCH_PWROK_R
4
O
3
C2203
470p
0201S_P33
25V
0201
C2205
0.1u 10V
VCCST_OVERRIDE
SLP_S0#
CPU_C10_GATE#
SLP_A#
SLP_S3#
SLP_S4#
SLP_SUS#
R2204
75K
PCH Signal Glitch Free Implementation Requirements
R2209
75K
VCCDSW 3V SELECT STRAP
R2203
75K
R2207
75K
R2201
75K
R2216
75K
DNP
R2217
75K
+3P3VSB +1P8VSB
R2218
100K
SLP_S0#
PDG Table 6-113 states 100k PU for
3.3V and 75k PU for 1.8V. Adding DNP
options for 1.8V and DNP options for
75k PD
R2219
75K
DNP
INPUT3VSEL
0 3.3V
1
PCH_DPWROK[37]
A A
R2235 0
0201S_P28-W35
R2253 100K
0201S_P28-W35
5
PCH_DPWROK_R
4
3.0V
3
PCH(3)_SYS PWR CONTR
PCH(3)_SYS PWR CONTR
Title:
Title:
Title:
Engineer:
Engineer:
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
PCH(3)_SYS PWR CONTR
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
22 82Tuesday, May 21, 2019
22 82Tuesday, May 21, 2019
1
22 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 23
5
Please place testpoints at back of SoC and as close as possible.
D D
C C
1%
R2322100 0201
B B
PCH_DEBUG_GPP_H23[33]
TP2303
CSI2_COMP
4
U1001I
D12
CSI_E_CLK
C12
CSI_E_CLK_P
B12
CSI_E_DN_0
A12
CSI_E_DP_0
G13
CSI_E_DN_1
F13
CSI_E_DP_1
K10
CSI_F_CLK
L10
CSI_F_CLK_P
L8
CSI_F_DN_0
M8
CSI_F_DP_0
M11
CSI_F_DN_1
L11
CSI_F_DP_1
D9
CSI_D_CLK
C9
CSI_D_CLK_P
A7
CSI_D_DN_0
B7
CSI_D_DP_0
B9
CSI_D_DN_1
A9
CSI_D_DP_1
D7
CSI_D_DN_2/CSI_C_DN_0
C7
CSI_D_DP_2/CSI_C_DP_0
D8
CSI_D_DN_3/CSI_C_CLK
C8
CSI_D_DP_3/CSI_C_CLK_P
G11
CSI_H_CLK
J11
CSI_H_CLK_P
F6
CSI_H_DN_0
G6
CSI_H_DP_0
G10
CSI_H_DN_1
F10
CSI_H_DP_1
G8
CSI_H_DN_2/CSI_G_DN_0
J8
CSI_H_DP_2/CSI_G_DP_0
K6
CSI_H_DN_3/CSI_G_CLK
L6
CSI_H_DP_3/CSI_G_CLK_P
B4
CSI_RCOMP
DT34
GPP_D4/IMGCLKOUT0
DP38
GPP_H20/IMGCLKOUT1
DK36
GPP_H21/IMGCLKOUT2
DL36
GPP_H22/IMGCLKOUT3
DN38
GPP_H23/IMGCLKOUT4
M1042225-001
9 OF 19
CSI2 eMMC
CNVi
GPP_F1/CNV_BRI_RSP/UART0_RXD
GPP_F3/CNV_RGI_RSP/UART0_CTS
3
GPP_F8/EMMC_DATA0
GPP_F9/EMMC_DATA1
GPP_F10/EMMC_DATA2
GPP_F11/EMMC_DATA3
GPP_F12/EMMC_DATA4
GPP_F13/EMMC_DATA5
GPP_F14/EMMC_DATA6
GPP_F15/EMMC_DATA7
GPP_F7/EMMC_CMD
GPP_F16/EMMC_RCLK
GPP_F17/EMMC_CLK
GPP_F18/EMMC_RESET
EMMC_RCOMP
CNV_WT_D0N
CNV_WT_D0P
CNV_WT_D1N
CNV_WT_D1P
CNV_WT_CLKN
CNV_WT_CLKP
CNV_WR_D0N
CNV_WR_D0P
CNV_WR_D1N
CNV_WR_D1P
CNV_WR_CLKN
CNV_WR_CLKP
CNV_WT_RCOMP
GPP_F2/CNV_RGI_DT/UART0_TXD
GPP_F0/CNV_BRI_DT/UART0_RTS
GPP_F4/CNV_RF_RESET
GPP_F6/CNV_PA_BLANKING
GPP_F19/A4WP_PRESENT
GPP_F5/MODEM_CLKREQ
Camino
GPP_F8 is PCH_SAM_INT
GPP_F9 is PCH_SAM_DGPU_STS
DP27
GPP_F9_PCH_SAM_INT2
DU30
DT30
DT29
DV30
DU29
DW30
DW29
DV28
DW28
DN27
DT28
EMMC_RCOMP_R
DU28
DV45
DU45
DU44
DT44
DL42
DK42
DP44
DN44
DG42
DG44
DK44
DJ44
DT45
CNV_BRI_RSP_R
DL29
CNVI_EN_STRAP
DP31
DL31
DN29
DJ29
DP29
DL27
DK29
38.4MHZ_STRAPE
INT. PD
CNV_RGI_RSP_R
R2319
R2306
R2317
R2312
R2310
R2316
R2311
R2323 150
R2327 22
R2303 22
R2304 22
R2328 22
R2309
75K
DNP
0
0
0
0
0
0
R2307 0DNP
R2308 0
200
2
SAM_PCH_RTC_WAKE [35]
PCH_SAM_INT2 [34]
SAM_PCH_INT [35]
SAM_PCH_BASE [35]
SAM_PCH_RSK [35]
SAM_PCH_LID_STATE [35]
PCH_SAM_INST_ON [34,72]
PCH_SAM_INT [34]
CNV_WT_D0_DN_D100 [50]
CNV_WT_D0_DP_D100 [50]
CNV_WT_D1_DN_D100 [50]
CNV_WT_D1_DP_D100 [50]
CNV_WT_CLK_DN_D100 [50]
CNV_WT_CLK_DP_D100 [50]
CNV_WR_D0_DN_D100 [50]
CNV_WR_D0_DP_D100 [50]
CNV_WR_D1_DN_D100 [50]
CNV_WR_D1_DP_D100 [50]
CNV_WR_CLK_DN_D100 [50]
CNV_WR_CLK_DP_D100 [50]
CNV_BRI_RSP [50]
CNV_RGI_DT [50]
CNV_BRI_DT [50]
CNV_RGI_RSP [50]
BIOS_REC
TP2301
R2339 49.9K
0201S_P28-W35
R2305 49.9K
R2337 49.9K
0201S_P28-W35
R2336 49.9K
0201S_P28-W35
R2335 49.9K
0201S_P28-W35
R2334 49.9K
0201S_P28-W35
R2331
SP_TP_SMDP58
1
SAM_PCH_RTC_WAKE
PCH_SAM_INT2
SAM_PCH_INT
SAM_PCH_BASE
SAM_PCH_RSK
SAM_PCH_LID_STATE
+1P8VSB
ALL
R2333
20K
0
0201S_P28-W35
R2332
49.9K
DNP
0201S_P28-W35
+1P8VSB +1P8VSB +1P8VSB +1P8VSB
DNP
0201S_P28-W35
R2302
10K
R2301
100K
CNVI_EN_STRAP 38.4MHZ_STRAPE
DNP
R2340
10K
0201S_P28-W35
DNP
R2341
20K
CNV_BRI_RSP_R CNV_RGI_RSP_R
0201S_P28-W35
DNP
R2342
20K
0201S_P28-W35
XTAL FREQUENCY SELECTION
GPP_F0
0 38.4MHZ
Default
1
24MHZ
CNVI ENABLE
GPP_F2
0 Integrated CNVi Enabled
Default
A A
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
W x H 422 x 273 mm
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
1
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
Integrated CNVi Disabled
PCH(4)_CSI,eMMC,CNVi,IDs
PCH(4)_CSI,eMMC,CNVi,IDs
PCH(4)_CSI,eMMC,CNVi,IDs
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
23 82Tuesday, May 21, 2019
23 82Tuesday, May 21, 2019
1
23 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 24
5
U1001H
CV7
D D
PCIE_SSD_RX0_DN[44]
PCIE_SSD_RX0_DP[44]
PCIE_SSD_TX0_DN[44]
PCIE_SSD_TX0_DP[44]
PCIE_SSD_RX1_DN[44]
PCIE_SSD_RX1_DP[44]
PCIE_SSD_TX1_DN[44]
PCIE_SSD_TX1_DP[44]
PCIE M.2 SSD
C C
B B
PCIE_SSD_RX2_DN[44]
PCIE_SSD_RX2_DP[44]
PCIE_SSD_TX2_DN[44]
PCIE_SSD_TX2_DP[44]
PCIE_SSD_RX3_DN[44]
PCIE_SSD_RX3_DP[44]
PCIE_SSD_TX3_DN[44]
PCIE_SSD_TX3_DP[44]
GPP_E0[18]
USBA_OVCUR#[45]
TP2402
TCP0_OC#[79]
GPP_E4[18]
TCON_VENDOR_ID[57,76]
GPP_E5[18]
BT_DISABLE#[33,50]
WLAN_DISABLE#[33,50]
PCIE_RCOMPN
R2401 100
0201S_P28-W35
PCIE_RCOMPP
PCIE7_RXN
CV6
PCIE7_RXP
DD3
PCIE7_TXN
DD5
PCIE7_TXP
CT6
PCIE8_RXN
CT7
PCIE8_RXP
DA3
PCIE8_TXN
DA5
PCIE8_TXP
CP7
PCIE9_RXN
CP6
PCIE9_RXP
DA2
PCIE9_TXN
DA1
PCIE9_TXP
CM7
PCIE10_RXN
CM6
PCIE10_RXP
CY3
PCIE10_TXN
CY4
PCIE10_TXP
CK7
PCIE11_RXN/SATA0_RXN
CK6
PCIE11_RXP/SATA0_RXP
CW2
PCIE11_TXN/SATA0_TXN
CW1
PCIE11_TXP/SATA0_TXP
CJ6
PCIE12_RXN/SATA1A_RXN
CJ7
PCIE12_RXP/SATA1A_RXP
CW5
PCIE12_TXN/SATA1A_TXN
CW3
PCIE12_TXP/SATA1A_TXP
CG7
PCIE13_RXN
CG6
PCIE13_RXP
CT3
PCIE13_TXN
CT5
PCIE13_TXP
CE6
PCIE14_RXN
CE7
PCIE14_RXP
CT2
PCIE14_TXN
CT1
PCIE14_TXP
CC5
PCIE15_RXN/SATA1B_RXN
CC6
PCIE15_RXP/SATA1B_RXP
CR3
PCIE15_TXN/SATA1B_TXN
CR4
PCIE15_TXP/SATA1B_TXP
CA6
PCIE16_RXN/SATA2_RXN
CA5
PCIE16_RXP/SATA2_RXP
CP1
PCIE16_TXN/SATA2_TXN
CP2
PCIE16_TXP/SATA2_TXP
DW12
GPP_E0/SATAXPCIE0/SATAGP0
CR42
GPP_A12/SATAXPCIE1/SATAGP1
CR43
GPP_A13/SATAXPCIE2/SATAGP2
DW14
GPP_E9/USB_OC0
CT43
GPP_A16/USB_OC3
DU12
GPP_E4/DEVSLP0
DU11
GPP_E5/DEVSLP1
CV48
GPP_A11/SATA_DEVSLP2
DT38
GPP_H12/M2_SKT2_CFG0
DW38
GPP_H13/M2_SKT2_CFG1
DV38
GPP_H14/M2_SKT2_CFG2
DU38
GPP_H15/M2_SKT2_CFG3
DN1
PCIE_RCOMPN
DN3
PCIE_RCOMPP
4
8 OF 19
PCIE1_RXN/USB31_1_RXN
PCIE1_RXP/USB31_1_RXP
PCIE1_TXN/USB31_1_TXN
PCIE1_TXP/USB31_1_TXP
PCIE2_RXN/USB31_2_RXN
PCIE2_RXP/USB31_2_RXP
PCIE2_TXN/USB31_2_TXN
PCIE2_TXP/USB31_2_TXP
PCIE3_RXN/USB31_3_RXN
PCIE3_RXP/USB31_3_RXP
PCIE3_TXN/USB31_3_TXN
PCIE3_TXP/USB31_3_TXP
PCIE4_RXN/USB31_4_RXN
PCIE4_RXP/USB31_4_RXP
PCIE4_TXN/USB31_4_TXN
PCIE4_TXP/USB31_4_TXP
PCIE5_RXN/USB31_5_RXN
PCIE5_RXP/USB31_5_RXP
PCIE5_TXN/USB31_5_TXN
PCIE5_TXP/USB31_5_TXP
PCIE6_RXN/USB31_6_RXN
PCIE6_RXP/USB31_6_RXP
PCIE6_TXN/USB31_6_TXN
PCIE6_TXP/USB31_6_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB_ID
USB_VBUSSENSE
USB2_COMP
UFS_RESET
DJ8
DJ6
DJ2
DJ1
DG9
DG7
DJ3
DJ5
DE7
DE9
DF3
DF5
DC7
DC9
DF2
DF1
DA6
DA7
DE4
DE3
CY7
CY6
DD1
DD2
DN8
DP8
DK11
DJ11
DP13
DN13
DK10
DJ10
DL5
DL3
DP11
DN11
DK13
DJ13
DN6
DP6
DL2
DL1
DP10
DN10
DL6
DL11
DN5
CD3
3
USB2_COMP
TP2401
USB3_SL1_RXN4 [71]
USB3_SL1_RXP4 [71]
USB3_SL1_TXN4 [71]
USB3_SL1_TXP4 [71]
USB3_USBA_RX_DN [45]
USB3_USBA_RX_DP [45]
USB3_USBA_TX_DN [45]
USB3_USBA_TX_DP [45]
USB2_SL1_DN [71]
USB2_SL1_DP [71]
USB2_USBA_DN [45]
USB2_USBA_DP [45]
USB2_TCP0_DN [77]
USB2_TCP0_DP [77]
CAM_USB_DM_SOC [54]
CAM_USB_DP_SOC [54]
R240510K
R240810K
R2402 113
2
USB3 SL40
USB3 TYPE A AND BSSB
USB2 SL40
USB2 USB-A PORT
USB2 USB-C PORT1
USB2 Camera
1
M1042225-001
A A
5
+1P8VSB
R2410 49.9K0201S_P28-W35
4
TCON_VENDOR_ID
PCH(5)_PCIE,USB
PCH(5)_PCIE,USB
Title:
Title:
Title:
Engineer:
Engineer:
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
3
2
W x H 412 x 267 mm
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
PCH(5)_PCIE,USB
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
24 82Tuesday, May 21, 2019
24 82Tuesday, May 21, 2019
1
24 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 25
5
4
3
2
1
SAM NEED DECIDE TO SET UEFI_TOP_SWAP HIGH OR LOW BEFORE ASSERT PCH_PWROK
SAM_PCH_TOP_SWAP[35]
R2518
100K
D D
No reboot strap
Low: Disable (Default)
High:Enable
PANEL_I2C_SDA[33,57]
PANEL_I2C_SCL[33,57]
C C
Removed connections from pins DK24 and DJ24 (page21)
Connecting them to page 25 PMI_I2C I2C1
0ohm straps refdes changed to match with page number
DNP
+1P8V_PANEL
SAMTX_PCHRX[29,33,34]
PCHTX_SAMRX[29,33,34]
ALL
ALL
PCHRTS_SAMCTS[29,33,34,76]
SAMRTS_PCHCTS[29,33,34,76]
R2598
R2597
RTD3_AUD_PWR_1P8[62]
RTD3_AUD_PWR_5P0[64]
0
0
PCH_SENSOR_I2C_SDA[54,76]
PCH_SENSOR_I2C_SCL[54,76]
VOL_UP#[31,33]
VOL_DOW N#[31,33]
PANEL_I2C_SDA_R
PANEL_I2C_SCL_R
R2584 2.2K
R2583 2.2K
PMI_I2C_SDA[28,33,76]
PMI_I2C_SCL[28,33,76]
0
PD_SML0_SCL[77]
PD_SML0_SDA[77]
R2501
0
R2502
+1P8VSB
TP2523
TP2518
U1001F
100K
R2533
R2536
100K
100K
100K
R2509
R2524
INT. PD
INT. PD
INT. PD
CH48
GPP_B16/GSPI0_CLK
CF48
GPP_B18/GSPI0_MOSI
CF47
GPP_B17/GSPI0_MISO
CH49
GPP_B15/GSPI0_CS0
CH47
GPP_B14/SPKR/TIME_SYNC1/GSPI0_CS1
CL47
GPP_B20/GSPI1_CLK
CK47
GPP_B22/GSPI1_MOSI
CK46
GPP_B21/GSPI1_MISO
CH45
GPP_B19/GSPI1_CS0
CL48
GPP_B23/SML1ALERT_N/PCHHOT_N/GSPI1_CS1
DP21
GPP_C8/UART0_RXD
DK21
GPP_C9/UART0_TXD
DL21
GPP_C10/UART0_RTS
DJ22
GPP_C11/UART0_CTS
DT22
GPP_C20/UART2_RXD
DW22
GPP_C21/UART2_TXD
DV22
GPP_C22/UART2_RTS
DU22
GPP_C23/UART2_CTS
DT24
GPP_C16/I2C0_SDA
DT23
GPP_C17/I2C0_SCL
DW23
GPP_C18/I2C1_SDA
DU23
GPP_C19/I2C1_SCL
DU41
GPP_H4/I2C2_SDA
DV41
GPP_H5/I2C2_SCL
DW41
GPP_H6/I2C3_SDA
DT41
GPP_H7/I2C3_SCL
DT40
GPP_H8/I2C4_SDA/CNV_MFUART2_RXD
DW40
GPP_H9/I2C4_SCL/CNV_MFUART2_TXD
M1042225-001
Should really be a space here in the symbol >
6 OF 19
GPP_D13/ISH_UART0_RXD
GPP_D15/ISH_UART0_RTS_N/GSPI2_CS1_N/IMGCLKOUT5
GPP_D16/ISH_UART0_CTS_N/CNV_WCEN
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS_N/ISH_UART1_RTS
GPP_C15/UART1_CTS_N/ISH_UART1_CTS
GPP_D14/ISH_UART0_TXD
GPP_B5/ISH_I2C0_SDA
GPP_B6/ISH_I2C0_SCL
GPP_B7/ISH_I2C1_SDA
GPP_B8/ISH_I2C1_SCL
GPP_B9/I2C5_SDA/ISH_I2C2_SDA
GPP_B10/I2C5_SCL/ISH_I2C2_SCL
GPP_D0/ISH_GP0
GPP_D1/ISH_GP1
GPP_D2/ISH_GP2
GPP_D3/ISH_GP3
GPP_D17/ISH_GP4
GPP_D18/ISH_GP5
GPP_E15/ISH_GP6
GPP_E16/ISH_GP7
DV33
DW33
DT33
DU33
DK22
DW24
DV24
DU24
CN43
CN42
CN41
CL43
CL41
CJ39
DU36
DV36
DW36
DT36
DU34
DW34
DT14
DU14
TPANEL_RST#_R
RTD3_CAM_PWREN_R
FLASH_PROTECT#_R
MEM_CONFIG
GPP_D3
R2511 0
R2517 1K
R2515 0
R2513 0
R2505 0
ACS_INT# [54]
TP2532
TP2501
ISH_SAM_INT [34]
-4mA sync
capability on
3.3V GPIO
R2599 0DBG_D
DBG_D
R2525
DBG_D
LED2501
ISH_DBG
Debug UART
+3P3VSB
1K
AK
RED
Red
TPANEL_RST# [30,33,35]
RTD3_TPANEL_PWR [62,64]
RTD3_CAM_PWREN [54,76]
FLASH_PROTECT# [30]
PCH_DBG_RX [29,33,76]
PCH_DBG_TX [29,33,76]
R2590 100K
+3P3VSB
R2589 100K
+1P8VSB
10K
DNP
R2537
MEM_CONFIG
B B
R2508 49.9K
R2572 49.9K
R2595 49.9K
R2559 49.9K
R2596 10K
R2592 49.9K
0201S_P28-W35
A A
CPUNSSC Clock Frequency
GPP_B23/SML1ALERT#/
ALL
LOW: A,B,C,D CHANNEL ENABLE
HIGH: A,C CHANNEL ENABLE
10K
R2526
0201S_P28-W35
0201S_P28-W35
0201S_P28-W35
0201S_P28-W35
0201S_P28-W35
DNP
ISH_SAM_INT
RTD3_AUD_PWR_1P8
RTD3_AUD_PWR_5P0
RTD3_TPANEL_PWR
TPANEL_RST#
RTD3_CAM_PWREN
PCHHOT#/GSPI1_CS1#
PCH(6)_CPU,GPIO,MISC
PCH(6)_CPU,GPIO,MISC
0 38.4MHz (crystal)
Default
1
19.2MHz (internal divider)
5
Title:
Title:
Title:
Engineer:
Engineer:
Size Project Nam e Rev
Size Project Nam e Rev
Size Project Nam e Rev
Custom
Custom
Custom
W x H 417 x 270mm
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
PCH(6)_CPU,GPIO,MISC
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
25 82Tuesday, May 21, 2019
25 82Tuesday, May 21, 2019
1
25 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 26
5
4
3
2
+3VSUS_ORG
1
Power rail can breakout with a 3.8mm width plane.
+VCCIN_AUX
Place near
DG26&DF23
DNP
C2620
1u
6.3V
0201S_P35-W35
DNP
C2634
1u
6.3V
0201S_P35-W35
1P8VSB need to come up after 3P3VSB
D D
C C
+3VSUS_ORG+1P8VSUS_ORG+1P8VSUS_ORG
B B
VCCIN_AUX_VIN_SENSE[69]
VCCIN_AUX_VSS_SENSE[69]
TP2602
TP2601
U1001N
AH1
VCCIN_AUX_AH1
AW10
VCCIN_AUX_AW 10
AY11
VCCIN_AUX_AY11
AY9
VCCIN_AUX_AY9
BA10
VCCIN_AUX_BA10
BB9
VCCIN_AUX_BB9
CH1
VCCIN_AUX_CH1
CK11
VCCIN_AUX_CK11
CL10
VCCIN_AUX_CL10
CM11
VCCIN_AUX_CM11
CN1
VCCIN_AUX_CN1
AJ1
VCCIN_AUX_AJ1
CN10
VCCIN_AUX_CN10
CP11
VCCIN_AUX_CP11
CR10
VCCIN_AUX_CR10
CT11
VCCIN_AUX_CT11
CU10
VCCIN_AUX_CU10
CV1
VCCIN_AUX_CV1
CV11
VCCIN_AUX_CV11
CW10
VCCIN_AUX_CW 10
CY11
VCCIN_AUX_CY11
DC1
VCCIN_AUX_DC1
AL1
VCCIN_AUX_AL1
P13
VCCIN_AUX_P13
R12
VCCIN_AUX_R12
T13
VCCIN_AUX_T13
U12
VCCIN_AUX_U12
DC11
VCCIN_AUX_DC11
DE12
VCCIN_AUX_DE12
DF12
VCCIN_AUX_DF12
AM1
VCCIN_AUX_AM1
AN1
VCCIN_AUX_AN1
AT11
VCCIN_AUX_AT11
AT9
VCCIN_AUX_AT9
AU10
VCCIN_AUX_AU10
AV9
VCCIN_AUX_AV9
BF9
VCCIN_AUX_VCCSENSE
BD9
VCCIN_AUX_VSSSENSE
DJ15
VCC_V1P05EXT_1P05
CY34
VCC_VNNEXT_1P05
DC33
VCCPRIM_3P3_1
DD35
VCCPRIM_1P8_1
DB34
VCCSPI
M1042225-001
14 OF 19
VCCPRIM_3P3_2
VCCPRIM_3P3_3
VCCPRIM_3P3_4
VCCPRIM_1P8_2
VCCPRIM_1P8_3
VCCPRIM_1P8_4
VCCPRIM_1P8_5
VCCPRIM_1P8_6
VCCPRIM_1P8_7
VCCPRIM_1P8_8
VCCPRIM_1P8_9
VCCLDOSTD_0P85
VCCA_CLKLDO_1P8
VCCDPHY_1P24
VCCDSW_1P05
VCC1P05_1
VCC1P05_2
VCC1P05_3
VCC1P05_OUT_PLL
VCCPRIM_1P05_1
VCCPRIM_1P05_2
VCCPRIM_1P05_3
VCCPRIM_1P05_4
VCCRTC
VCCDSW_3P3
VCCPGPPR
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
GPP_B2/VRALERT
DF23
DG26
DG28
DF15
DF17
DF18
DF20
DG17
DG18
DG20
DF34
PLACE NEAR DW37 WITHIN 3MM
FROM PACKAGE
C2654 2.2u 6.3V
DW37
DW15
DW32
DD34
BY2
CB2
CC1
CD1
DG31
DG29
DF29
DF31
DG33
DE31
DF26
CL38
CJ38
CN38
0201
Place cap within 3mm from package edge.
close as possible to pin DD34.
0.5A
+VCCPRIM_1P05
C2606
1u
6.3V
0201S_P35-W35
Place near
DG20
DNP
C2635
1u
0201S_P35-W35
+3VSUS_ORG
R2603
100K
6.3V
trace w 0.8mm
shield trace
C2603 4.7u
6.3V
0402
6.3V
C2604 1u
100k per reference schematic
10k per Calgary
0201
CORE_VID0 [69]
CORE_VID1 [69]
+1P8VSUS_ORG
C2621
1u
0201S_P35-W35
+VCC1.05_OUT_FET
6.3V
DNP
C2629
1u
6.3V
0201S_P35-W35
L2601 0.68uHDNP
R2650 0.01
0603S_P6-W100
R2601
0402
0
5%
C2653
47u
0603
R2602 0
0402S_P4
DNP
C2623
1u
6.3V
0201S_P35-W35
4.3A
DBG_S
+VCC_RTC
+1P8VSUS_ORG
+VCC1.05_OUT_SFR
connected to page 12 only
+3VSUS_ORG +1P8VSUS_ORG
+3VSUS_ORG
C2605
0.1u
10V
DNP
C2602
0.1u
10V
+VCC_RTC
C2601
1u
0201S_P35-W35
6.3V
DBG_TS
R2624 0.01
0402S_P5-W65
PMTP2605
SP-TP-C0P381
A A
5
PMTP2606
SP-TP-C0P381
4
+3P3VSB +3VSUS_ORG+1P8VSB +1P8VSUS_ORG
PMTP2607
SP-TP-C0P381
DBG_TS
R2612 0.01
0402S_P5-W65
PMTP2608
SP-TP-C0P381
Verify if PROCHOt# to be
used at PCH.
BC_PROCHOT# [79]
3
D2601
AK
RB520CS3002L
H_PROCHOT# [10,63,66,76]
2
Place near DE31
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
W x H 422 x 273 mm
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
Place near DG33
PCH(7)_POWER
PCH(7)_POWER
PCH(7)_POWER
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
26 82Tuesday, May 21, 2019
26 82Tuesday, May 21, 2019
1
26 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 27
5
4
3
2
1
+VCCIN_AUX
C2733
22u
D D
C C
0603
20%
10V
DNP
C2724
22u
0603
20%
10V
DNP
C2720
22u
0603
20%
10V
C2722
22u
0603
20%
10V
DNP
C2737
22u
0603
20%
10V
DNP
C2742
22u
0603
20%
10V
Primary Side Cap
C2735
22u
0603
20%
10V
DNP
C2753
22u
0603
20%
10V
C2755
22u
0603
20%
10V
C2706
22u
0603
20%
10V
DNP
C2707
22u
0603
20%
10V
C2715
22u
0603
20%
10V
DNP
C2725
22u
0603
20%
10V
B B
DNP
C2741
22u
0603
20%
10V
C2702
22u
0603
20%
10V
DNP
A A
PCH(8)_decoupling
PCH(8)_decoupling
Title:
Title:
Title:
Engineer:
Engineer:
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
W x H 377 x 244 mm
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
PCH(8)_decoupling
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
27 82Tuesday, May 21, 2019
27 82Tuesday, May 21, 2019
27 82Tuesday, May 21, 2019
1
1.00
1.00
1.00
Page 28
5
D D
+3P3VSB +3P3V_ PMI
R2801 0.1DBG_TS
4
3
2
1
+3P3V_PMI
Imax=0.0042A
+3P3V_PMI
2K
R2862
ALL
A3
A2
A1
B1
D1
C1
D3
D2
2K
R2863
ALL
U2813
IN1+
IN1-
IN2+
IN2-
IN3+
IN3-
IN4+
IN4-
A
MAX34417
DBG_T
+3P3V_PMI
VDD
SCL
SDA
PDN
SLOW
ADDR
GND
VIO
Ir*2 = 730uA
A4
B2
C4
D4
B3
C3
C2
B4
GND
Ir=12uA
PMI0_PDN_N
PMI0_ADDR
DBG_T
R2866
0
0201S_P28-W 35
GND
+3P3V_PMI
DBG_T
C2825
0.1u
0201S_P33-W 39
GND
DBG_T
R2856 10K
0201S_P28-W 35
10V
GND
Avila +5VSB while Carmel monitors PM_BLADE_IN+
PM_5VSB_IN+[5 9]
PM_5VSB_IN-[59]
PM_3P3VSB_IN+[59]
PM_3P3VSB_IN-[59]
PM_3P3V_SSD+[65]
PM_3P3V_SSD-[65]
+3P3V_PMI
PM_3P3V_W WAN+[65]
PM_3P3V_W WAN-[65]
D1
C1
D3
D2
A3
A2
A1
B1
U2802
IN1+
IN1-
IN2+
IN2-
IN3+
IN3-
IN4+
IN4-
B
MAX34417
DBG_T
VDD
VIO
SCL
SDA
PDN
SLOW
ADDR
GND
A4
B2
C4
D4
B3
C3
C2
B4
GNDGND
PMI1_PDN_N
PMI1_ADDR
DBG_T
R2864
499
0201S_P28-W 35
PMI1_I2C_SCL_ R [76]
PMI1_I2C_SDA_ R [76]
+3P3V_PMI
DBG_T
C2801
0.1u
10V
0201S_P33-W 39
GND
DBG_T
R2865 10K
0201S_P28-W 35
+3P3V_PMI
GND
DBG_T
R2874 0
0201S_P28-W 35
DBG_T
R2875 0
+3P3V_PMI
U2803
PM_VCCIN_IN+[67]
PM_VCCIN_IN-[67]
PM_1P1V_DDR_V DD2_IN+[60]
PM_1P1V_DDR_V DD2_IN-[60]
PM_3P3V_PANEL _IN+[65]
PM_3P3V_PANEL _IN-[6 5]
PM_BKLT_IN+[72]
PM_BKLT_IN-[72]
A3
IN1+
A2
IN1-
A1
IN2+
B1
IN2-
D1
IN3+
C1
IN3-
D3
IN4+
D2
IN4-
C
MAX34417
DBG_T
Address(7b) = 0x14
VDD
VIO
SCL
SDA
PDN
SLOW
ADDR
GND
A4
B2
C4
D4
B3
C3
C2
B4
PMI2_PDN_N
PMI2_ADDR
GNDGND
DBG_T
C2802
0.1u
0201S_P33-W 39
GND
DBG_T
R2867 10K
0201S_P28-W 35
DBG_T
R2850
931
0201S_P28-W 35
10V
GND
0201S_P28-W 35
+3P3V_PMI
PM_DBG_I2C_SCL [29]
to debug connector
PM_DBG_I2C_SDA [29]
MAX34417 VDD Average Supply Current
700uA PDNB=VIO and SLOW=GND
10uA PDNB=VIO and SLOW=VIO
2uA PDNB=GND
6x700uA=4.2mA
3.3Vx4.2mA=13.86mW
C C
ALL
R2854 0
ALL
R2855 0
Changed Build-opt to ALL for pull-ups and 0ohm
as Burnside Bridge is connected to the same I2C
Avila
+VSYS
while
Carmel
monitors
+3P3VAS
PMI_I2C_SCL[25,33,76 ]
PMI_I2C_SDA[25,33,76]
PM_VCCIN_AUX_IN+[69]
PM_VCCIN_AUX_IN-[6 9]
PM_+1P8V_SAM +[3 4]
PM_+1P8V_SAM -[34]
PM_VSYS+[63]
PM_VSYS-[63]
PM_1P8VSB_IN+[62]
PM_1P8VSB_IN-[6 2]
Address(7b) = 0x10 Address(7b) = 0x12
B B
Part B
5VSB
3P3 VSB
1P8 VSB
Part C
3P3 Panel
Display Backlight
3P3V SSD
3P3V WWAN
A A
Power Monitor
Power Monitor
Power Monitor
Title:
Title:
Title:
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
Engineer:
Engineer:
Size Proj ect Name Rev
Size Proj ect Name Rev
Size Proj ect Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
W x H 577 x 373 mm
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
1
1.00
1.00
28 82Tuesday, May 21, 2 019
28 82Tuesday, May 21, 2 019
28 82Tuesday, May 21, 2 019
1.00
Page 29
5
+3P3V_DEBUG
4
+3P3V_DEBUG+3P3VA
3
+3P3V_DEBUG
2
1
+3P3V_DEBUG
R2913 0 DBG_D
0603S_P6-W95
keep USB2 traces as short as possible between muxes
R2926 0DBG_D
R2918 0DBG_D
R2919 0DBG_D
R2927 0DBG_D
MUX0_EN#
R2920 0DBG_D
R2928 0DBG_D
R2921 0DBG_D Q2902
R2929 0DBG_D
USBC_MUX3[35]
R2909
100K
1%
0201
DBG_D
USBC_MUX2[35]
JTAG_TCK_R
PCH_DBG_TX_R
JTAG_TDI_R
PCH_DBG_RX_R
USBC_MUX2_SEL
USBC_MUX3_SEL
JTAG_TDO_R
PM_DBG_I2C_SCL_R
JTAG_TMS_R
PM_DBG_I2C_SDA_R
USBC_MUX2_SEL
USBC_MUX3_SEL
+3P3V_DEBUG
R2923
100K
1%
0201
DBG_D
D
G
Q2905
S
DBG_D
GND
R2903 0
R2910 0
U2902
7
IA0
6
IA1
5
IA2
4
IA3
13
IB0
14
IB1
15
IB2
16
IB3
2
EN
17
S0
3
S1
PI3USB14-AZHE
DBG_D
U2905
7
IA0
6
IA1
5
IA2
4
IA3
13
IB0
14
IB1
15
IB2
16
IB3
2
EN
17
S0
3
S1
PI3USB14-AZHE
DBG_D
0201S_P28-W35
0201S_P28-W35
DBG_D
DBG_D
USBC_MUX3
USBC_MUX2
USBC_MUX1
USBC_MUX0
U2910
1
2
SN74LV1T08DCKR
DBG_D
DBG_D
C2904
0.1u
10V
DBG_D
C2902
0.1u
10V
GND
GND
SAM_SWD_CLK[33,34,76]
PCH_JTAG_TCK_MUX[18]
PCH_DBG_TX[25,33,76]
SAM_SWD_DIO[33,34,76]
PCH_JTAG_TDI_MUX[18]
PCH_DBG_RX[25,33,76]
SAM_SWD_SWO[33,34,76]
PCH_JTAG_TDO_MUX[18]
PM_DBG_I2C_SCL[28]
SAM_RESET#[33,34,58,76]
PCH_JTAG_TMS_MUX[18]
PM_DBG_I2C_SDA[28]
SAM_DBG_MODE[29,58]
U2901
SAM_KIP_UART_TX_DBG[33,74]
D D
C C
B B
A A
SAM_KIP_UART_RX_DBG[33,74]
KIP_TRACE_SWO[74]
TS_TCK_1V8[30,33]
KIP_SWD_CLK[74,76]
SAMTX_PCHRX[25,33,34]
TS_TDI_1V8[30,33]
KIP_SWD_DIO[74]
PCHTX_SAMRX[25,33,34]
USBC_MUX0
USBC_MUX1
SAM_PD_SCL[18,33,35,79]
TS_TDO_1V8[30,33]
PCHRTS_SAMCTS[25,33,34,76]
TS_TMS_1V8[30,33]
SAM_KIP_RST#[35,74]
USBC_MUX0[35]
USBC_MUX1[35]
SAM_PD_SDA[18,33,35,79]
SAMRTS_PCHCTS[25,33,34,76]
7
IA0
6
IA1
5
IA2
4
IA3
13
IB0
14
IB1
15
IB2
16
IB3
2
EN
17
S0
3
S1
PI3USB14-AZHE
DBG_D
U2903
7
IA0
6
IA1
5
IA2
4
IA3
13
IB0
14
IB1
15
IB2
16
IB3
2
EN
17
S0
3
S1
PI3USB14-AZHE
DBG_D
MPAD
+3P3V_DEBUG
MPAD
VDD
YA
YB
NC_1
NC_2
NC_3
NC_4
NC_5
GND
VDD
YA
YB
NC_1
NC_2
NC_3
NC_4
NC_5
GND
20
8
12
1
9
11
18
19
10
21
GND
20
8
12
1
9
11
18
19
10
21
GND
C2901
0.1u
DBG_D
GND
VDD
YA
YB
NC_1
NC_2
NC_3
NC_4
NC_5
GND
MPAD
+3P3V_DEBUG
VDD
YA
YB
NC_1
NC_2
NC_3
NC_4
NC_5
GND
MPAD
VCC
A
B
O
GND
20
8
12
1
9
11
18
19
10
21
GND
C2905
20
8
12
1
9
11
18
19
10
21
5
4
3
U2911
1
2
SN74LV1T08DCKR
DBG_D
0.1u
10V
DBG_D
GND
C2908
0.1u
10V
DBG_D
GND
USBC_MUX3_SEL
VCC
A
B
GND
PD_SAM_DBG_ACC_MODE[37,79]
+3P3V_DEBUG
GND
5
USBC_MUX2_SEL
4
O
3
SAM_DBG_MODE[29,58]
DBG_D
TCP0_DBG0_A_DP [77]
TCP0_DBG1_A_DN [77]
TCP0_DBG2_B_DP [77]
TCP0_DBG3_B_DN [77]
+3P3V_DEBUG
R2901
100K
DBG_D
USBC_MUX3_SEL
C2907
0.1u
10V
DBG_D
GND
GND
G
DBG_D
R2907
100K
0201
MUX0_EN#[77]
U2906
5
VCC
R2904 0DBG_D
R2911 0DBG_D
+3P3V_DEBUG
C2909
0.1u
DBG_D
SN74LV1T02DCKR
GND
USBC_MUX3_SEL_INV USBC_MUX4_SEL
D
S
GND
USBC_MUX2_SEL
TCP0_BB_SBU1[29,77]
SAM_DBG_RX[33,34,71,76]
XDP_TCK_MUX[18]
TCP0_BB_SBU2[29,77]
SAM_DBG_TX[33,34,71,76]
DBG_PMODE[10,18]
TCP0_BB_SBU1[29,77] TCP0_SBU1 [29,77]
R2902 0
DBG_USB_EN
U2908
5
VCC
4
Y
3
GND
DBG_D
DFN5_P85XP85XP4_P48
2
1
1
A
2
B
U2909
74AUP1G08GX
VCC
A
B
GND
0201S_P28-W35
R2908 0DBG_N
R2906 0DBG_N
2
1
74LVC1G32GX
DBG_D
R2924 100K
5
4
Y
3
U2912
7
IA0
6
IA1
5
IA2
4
IA3
13
IB0
14
IB1
15
IB2
16
IB3
2
EN
17
S0
3
S1
PI3USB14-AZHE
DBG_D
R2905
1K
DBG_D
A
B
DBG_D
GND
4
Y
3
GND
DBG_USB_ENMUX0_EN#
SAM_MUX0_EN [35]
VDD
YA
YB
NC_1
NC_2
NC_3
NC_4
NC_5
GND
MPAD
TCP0_SBU2 [29,77]TCP0_BB_SBU2[29,77]
GND
GND
C2910
GND
+3P3V_DEBUG
20
8
12
1
9
11
18
19
10
21
C2906
0.1u
10V
DBG_D
GND
0.1u
DBG_D
C2903
0.1u
10V
DBG_D
GND
TCP0_SBU1 [29,77]
TCP0_SBU2 [29,77]
GND
Type-C Debug
Type-C Debug
Title:
Title:
R2917
100K
1%
0201
5
4
3
R2916
100K
1%
0201
DBG_D
R2915
100K
1%
0201
DBG_D
DBG_D
R2914
100K
1%
0201
DBG_D
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
GNDGNDGNDGND
2
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
W x H 377 x 244 mm
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Title:
Engineer:
Engineer:
Engineer:
Type-C Debug
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
29 82Tuesday, May 21, 2019
29 82Tuesday, May 21, 2019
29 82Tuesday, May 21, 2019
1
1.00
1.00
1.00
Page 30
5
4
3
2
1
TS_BOOST_HV_IN TS_HV_IN
TS_BOOST_HV_IN TS_HV_IN
TS_HV_IN
TS_HV_IN
TS_V1P0_TCH_DIG
C3019
10u6.3V
0603
TSGND_BOOST
L3002 4.7u H
C3057
10u 6.3V
0603
TSGND_BUCK
TS_V1P8A
MTP3036
MTP3012
MTP3020
MTP3002
TS_HV_IN
TS_V1P8A
TS_HV_IN
TS_HV_IN
TS_V1P0_TCH_SSI
TS_V1P8A
C3012
2.2u 25V
0402
2.2uH
L3003
2.0X1.6X1.0MM
0805
C3053
0.1u
0201
C3066
2.2u 25V
0402
C3068 4.7u 0402
C3054 2.2u 0402
C3059 0.1uFDNP
MTP3038
C3064 0.1uFDNP
C3043 0.1uFDNP
C3045 0.1uFDNP
TS_VDD_OK_H
TS_AY_RSTN_D
C3071
2.2u 25V
0402
C3018 0.1uFDNP
C3014 0.1uFDNP
C3013 0.1uFDNP
TS_VDD_OK_H
TS_AY_RSTN_D
TPANEL_RST#[25,33,35]
D D
+1P8VSB
R3011
100K
MTP3029
TS_IRQ_1V8#[20,30]
TS_TCK_1V8[29,33]
TS_TDI_1V8[29,33]
C C
R3014
200K
DNP
MTP3001
MTP3041
MTP3003
MTP3021
MTP3032
MTP3026
MTP3040
MTP3031
MTP3033
MTP3030
MTP3025
MTP3028
Q3003
D
NX3008NBKMB
D
G
G
S
S
TS_TDO_1V8[29,33]
TS_TMS_1V8[29,33]
+1P8V_TS +1P8V_TS
FLASH_PROTECT#
TPANEL_RST#
FLASH_PROTECT#
TS_TCK_1V8
TS_TMS_1V8
TS_TDO_1V8
TS_TDI_1V8
TS_SPI_CLK
TS_SPI_MISO
TS_SPI_MOSI
TS_SPI_CS#
TS_SPI_MOSI[21]
GPIO signals may toggle during boot
(see errata document). Please make
sure to implement the workaround
described in the errata
TS_SPI_MISO[21,30]
TS_SPI_CS#[21,30]
FLASH_PROTECT#[25,30]
R3016
10K
TS_TCK_1V8 TS_VDD_OK_H
TS_TDI_1V8
TS_TDO_1V8 TS_JTAG_TS_TDO_R TS_SCKL0 TS_SCKL TS_SCKL
TS_TMS_1V8
R3019
200K
XTAL,SM,48 MHZ,10 PPM,7 PF,2X1.6X0.45MM
The crystal and capacitors should be placed
as close as possible to the D5, with short and
symmetrical traces to the XI and XO pins
+1P8V_TS
TS_SPI_CLK
TS_SPI_CLK[21,30]
TS_SPI_MOSI
R3017 22.1
TS_IRQ_1V8 TPANEL_RST_N
R3015 1K
PANEL_VSYNCH[57]
R3013 22.1
TS_HOST_CLK TS_SD1 TS_SD1
(If Availible )
C3079
12p25V2%
MTP3027
MTP3023
FLASH_PROTECT# [25,30]
Not to be used for DEBUG build
Use MTP points on pg 31 instead
60 pin Drive Connector
B B
A A
50 pin Flex Breakout
J3002
2
112
4
H0
H2
H4
H6
H8
H10
H12
H14
H16
H18
H20
H22
H24
H26
H28
H30
H32
H34
H36
H38
H40
H42
H44
H46
H48
H50
5
334
6
556
8
778
9
10
9
10
12
111112
14
131314
16
151516
18
171718
20
191920
22
212122
24
232324
26
252526
28
272728
30
292930
32
313132
34
333334
36
353536
38
373738
40
393940
42
414142
44
434344
46
454546
48
474748
50
494950
52
515152
54
535354
56
555556
58
575758
60
595960
61
62
MT1
MT2
63
64
MT3
MT4
H0 to H47 are the horizontal sensor traces
V0 to V71 are the vertical sensor lines
TPANEL_RST_N
TS_V1P0_TCH_DIG +1P8V_TS
C3075 2.2u
6.3V
C3051 0.1uFDNP
TS_V1P0_TCH_SSI
C3007 2.2u
6.3V
C3046 0.1uFDNP
TS_SPI_CLK
TS_SPI_MOSI
TS_TOUCH_SPI_DO_R
TS_GPIO0
GTP3001
TS_FLASH_PROTECTn_GPI O_R
TP3002
TP3004
R3003 1K
TP3003
0201
TS_DLITE_XI
TS_DLITE_XO_R TS_SD4
R3018
0
ALL
0201
4
Y3001
TS_DLITE_XO TS_HV_IN
123
48MHz
C3063
12p25V2%
H1
H3
H5
H7
H9
H11
H13
H15
H17
H19
H21
H23
H25
H27
H29
H31
H33
H35
H37
H39
H41
H43
H45
H47
H49
H51
U3006
F2
SPI_CLK/I2C_SCL
F4
SPI_DI / I2C_SDA
F3
GPIO7 / SPI_DO
G1
GPIO6 / SPI_CS
D4
GPIO0
D3
GPIO1 / INT
D2
GPIO2 / IF_SEL
C1
GPIO3
C2
GPIO4
B1
GPIO5
H2
GPIO9
H1
GPIO10
G2
GPIO11
H5
TCK
H6
TDI
G6
TDO
F6
TMS
J3
CLK_IN
H11
XI
J11
XO
F10
CLK_SLCT
G5
FSCK
H3
FSDI
G4
FSDIO
H4
FSCS
DS-D5000-B064
TS_FLASH_CSn
+1P8V_TS
TS_FLASH_SCK
U3005
TS_FLASH_MISO
TS_FLASH_MOSI
SON9_4P1X4P1XP6_P8
1
CS
6
CK
5
SI/0
2
Q/1
3
WP/2
7
HLRS/3
MX25U1635FZUI
MTP3022
MTP3011
MTP3034
MTP3037
MTP3042
C3052 2.2u
6.3V
C3037 0.1uFDNP
C3073 10u
C3074 2.2u
6.3V
C3035 0.1uFDNP
B8
F11
G3
F5
RESERVED_GND[0]
RESERVED_GND[1]
VDE_F
RESERVED_GND[2]
VDE_H
VDD_SSI
RESERVED_GND[3]
RESERVED_GND[4]
VDD_CORE
RESERVED_GND[5]
RESERVED_GND[6]
RESERVED_GND[7]
RESERVED_GND[8]
RESERVED_GND[9]
GND1B9GND2
C3067
2.2u 6.3V
8
VCC
9
MTG
4
VSS
80 pin Sense Connector
V77
V75
V73
V71
V69
V67
V65
V63
V61
V59
V57
V55
V53
V51
V49
V47
V45
V43
V41
V39
V37
V35
V33
V31
V29
V27
V25
V23
V21
V19
V17
V15
V13
V11
V9
V7
V5
V3
V1
D6
B4
D5
C5
B5
C6
B6
C3
C4
B3
D8
RESERVED_NC[0]
J10
RESERVED_NC[1]
H10
RESERVED_NC[2]
J9
RESERVED_NC[3]
H9
RESERVED_NC[4]
J8
RESERVED_NC[5]
H8
RESERVED_NC[6]
VDD_OK_F
J2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
TS_AY_RSTN_D TS_VDD_OK_F
J1
RSTN_D
TS_VDD_OK_F TS_VDD_OK_H
J5
B2
RSTN
G10
SCKL
B10
SD0
B11
SD1
C9
SD2
C10
SD3
C11
SD4
C8
SD5
D9
SD6
D10
SD7
F8
SD8
G8
SD9
F9
SD10
G9
SD11
Special keepout made to isolate
buck and boost ground fr om system ground
+1P8V_TS TS_V1P8A
C304110u
0603
DNP
J3003
112
334
556
778
9910
111112
131314
151516
18
17
20
19
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
40
39
42
41
44
43
46
45
48
47
50
49
52
51
54
53
56
55
58
57
60
59
62
61
64
63
66
65
68
67
70
69
72
71
74
73
76
75
78
77
80
79
MP181MP2
MP484MP3
51338-0874
R3012 22.1
TS_SD0 TS_SD0
TS_SD2 TS_SD2
TS_SD3 TS_SD3
TS_SD5
TS_SD8
TS_SD9
TS_SD10
TS_SD11
R3002
0
C304710u
0603
DNP
V76
V74
V72
V70
V68
V66
V64
17
V62
19
V60
21
V58
23
V56
25
V54
27
V52
29
V50
31
V48
33
V46
35
V44
37
V42
39
V40
41
V38
43
V36
45
V34
47
V32
49
V30
51
V28
53
V26
55
V24
57
V22
59
V20
61
V18
63
V16
65
V14
67
V12
69
V10
71
V8
73
V6
75
V4
77
V2
79
V0
83
DNP
C302510u
0603
TS_V1P0_TCH_SSI
V1P8
Analog
80 pin Flex Breakout
4
MTP3024
R3001
4.99K
0402
MTP3035
+5V_TS
C3044
0.1uF
DNP
C3033
0.1uF
DNP
C3022
10u25V
0603
TSGND_BOOST
MTP3039
A K
PMEG4015EPK315
C3069
0.1uF
DNP
TS_HV_IN
TS_BOOST_HV_IN
TS_BOOST_HV_IN
1.4A
C3004 10u
0603
TSGND_BUCK
TS_AYALON1_LVDCDC_LX
TS_V1P0_TCH_SSI
C3011 0.1uFDNP
TS_V1P8A
C3032 2.2u 0402
C3062 0.033u
0201
C3031 0.033u
0201
TPANEL_RST_N
TS_AY_RSTN_D
TS_SCKLTS_SD6
TS_SD0TS_SD7
TS_SD4
TS_SD8
TS_HV_IN
C3040
0.1uF
DNP
TS_V1P0_TCH_SSI
C3050 2.2u 0402
C3061 2.2u 0402
C3010 2.2u 0402
C3056 0.033u 0201
C3078 0.033u 0201
TS_SCKL
TS_SD4
TS_SD5
TS_SD6
TS_SD7
TS_HV_IN
C3021
0.1uF
DNP
+1P8V_TS
C3042 2.2u 0402
C3006 2.2u 0402
C3008 2.2u 0402
C3038 10u 0603
C3058 0.033u 0201
C3055 0.033u 0201
TS_SCKL
TS_SD8
TS_SD9
TS_SD10
TS_SD11
D3001
1P8V_TS
+1P8V_TS
1P8V_TS
U3002
E3
HV_IN
A2
BOOST_HV_OUT
A1
BOOST_HV_IN
B1
BOOST_VSS
B8
BUCK_1V8_IN
A7
BUCK_VSS
A8
BUCK_OUT_FB
B7
BUCK_LX
D4
VDD_SSI
B5
LDO_1V0_OUT
J3
VDD_1V8_IN
C8
AVDD_IN
F3
AVDD_1V8_3
H3
AVDD_1V8_2
G3
AVDD_1V8_1
L5
VDE_H
B2
VDE_F
M6
RSTN_H
K5
RSTN_D
A3
VDD_OK_F
M5
VDD_OK_H
A6
SCLK
A5
A5_SSI_D0
B4
A5_SSI_D1
B3
A5_SSI_D2
A4
A5_SSI_D3
B6
GND
DS-A5048_82BGA
U3003
E3
HV_IN
A2
BOOST_HV_OUT
A1
BOOST_HV_IN
B1
BOOST_VSS
B8
BUCK_1V8_IN
A7
BUCK_VSS
A8
BUCK_OUT_FB
B7
BUCK_LX
D4
VDD_SSI
B5
LDO_1V0_OUT
J3
VDD_1V8_IN
C8
AVDD_IN
F3
AVDD_1V8_3
H3
AVDD_1V8_2
G3
AVDD_1V8_1
L5
VDE_H
B2
VDE_F
M6
RSTN_H
K5
RSTN_D
A3
VDD_OK_F
M5
VDD_OK_H
A6
SCLK
A5
A5_SSI_D0
B4
A5_SSI_D1
B3
A5_SSI_D2
A4
A5_SSI_D3
B6
GND
DS-A5048_82BGA
U3004
E3
HV_IN
A2
BOOST_HV_OUT
A1
BOOST_HV_IN
B1
BOOST_VSS
B8
BUCK_1V8_IN
A7
BUCK_VSS
A8
BUCK_OUT_FB
B7
BUCK_LX
D4
VDD_SSI
B5
LDO_1V0_OUT
J3
VDD_1V8_IN
C8
AVDD_IN
F3
AVDD_1V8_3
H3
AVDD_1V8_2
G3
AVDD_1V8_1
L5
VDE_H
B2
VDE_F
M6
RSTN_H
K5
RSTN_D
A3
VDD_OK_F
M5
VDD_OK_H
A6
SCLK
A5
A5_SSI_D0
B4
A5_SSI_D1
B3
A5_SSI_D2
A4
A5_SSI_D3
B6
GND
DS-A5048_82BGA
3
ANT_HV10
ANT_HV11
ANT_HV12
ANT_HV13
ANT_HV14
ANT_HV15
ANT_HV16
ANT_HV17
ANT_HV18
ANT_HV19
ANT_HV20
ANT_HV21
ANT_HV22
ANT_HV23
ANT_LV10
ANT_LV11
ANT_LV12
ANT_LV13
ANT_LV14
ANT_LV15
ANT_LV16
ANT_LV17
ANT_LV18
ANT_LV19
ANT_LV20
ANT_LV21
ANT_LV22
ANT_LV23
RESERVED_GND1
RESERVED_GND2
RESERVED_GND3
RESERVED_NC1
RESERVED_NC2
RESERVED_NC3
Add underfill
ANT_HV10
ANT_HV11
ANT_HV12
ANT_HV13
ANT_HV14
ANT_HV15
ANT_HV16
ANT_HV17
ANT_HV18
ANT_HV19
ANT_HV20
ANT_HV21
ANT_HV22
ANT_HV23
ANT_LV10
ANT_LV11
ANT_LV12
ANT_LV13
ANT_LV14
ANT_LV15
ANT_LV16
ANT_LV17
ANT_LV18
ANT_LV19
ANT_LV20
ANT_LV21
ANT_LV22
ANT_LV23
RESERVED_GND1
RESERVED_GND2
RESERVED_GND3
RESERVED_NC1
RESERVED_NC2
RESERVED_NC3
Add underfill
ANT_HV10
ANT_HV11
ANT_HV12
ANT_HV13
ANT_HV14
ANT_HV15
ANT_HV16
ANT_HV17
ANT_HV18
ANT_HV19
ANT_HV20
ANT_HV21
ANT_HV22
ANT_HV23
ANT_LV10
ANT_LV11
ANT_LV12
ANT_LV13
ANT_LV14
ANT_LV15
ANT_LV16
ANT_LV17
ANT_LV18
ANT_LV19
ANT_LV20
ANT_LV21
ANT_LV22
ANT_LV23
RESERVED_GND1
RESERVED_GND2
RESERVED_GND3
RESERVED_NC1
RESERVED_NC2
RESERVED_NC3
Add underfill
ANT_HV0
ANT_HV1
ANT_HV2
ANT_HV3
ANT_HV4
ANT_HV5
ANT_HV6
ANT_HV7
ANT_HV8
ANT_HV9
ANT_LV0
ANT_LV1
ANT_LV2
ANT_LV3
ANT_LV4
ANT_LV5
ANT_LV6
ANT_LV7
ANT_LV8
ANT_LV9
ANT_HV0
ANT_HV1
ANT_HV2
ANT_HV3
ANT_HV4
ANT_HV5
ANT_HV6
ANT_HV7
ANT_HV8
ANT_HV9
ANT_LV0
ANT_LV1
ANT_LV2
ANT_LV3
ANT_LV4
ANT_LV5
ANT_LV6
ANT_LV7
ANT_LV8
ANT_LV9
ANT_HV0
ANT_HV1
ANT_HV2
ANT_HV3
ANT_HV4
ANT_HV5
ANT_HV6
ANT_HV7
ANT_HV8
ANT_HV9
ANT_LV0
ANT_LV1
ANT_LV2
ANT_LV3
ANT_LV4
ANT_LV5
ANT_LV6
ANT_LV7
ANT_LV8
ANT_LV9
ATB
ATB
ATB
C1
C2
D1
D2
C3
D3
E2
E1
F2
F1
G2
G1
H2
H1
J2
J1
K2
K1
L2
L1
M2
M1
M3
L3
M8
M7
L8
L7
L6
K8
K7
K6
J8
J7
J6
H6
H7
H8
G6
G7
G8
F6
F7
F8
E7
E8
D7
D8
D5
D6
C6
K3
C5
C4
TS_AYALON0_ATB
C7
C1
C2
D1
D2
C3
D3
E2
E1
F2
F1
G2
G1
H2
H1
J2
J1
K2
K1
L2
L1
M2
M1
M3
L3
M8
M7
L8
L7
L6
K8
K7
K6
J8
J7
J6
H6
H7
H8
G6
G7
G8
F6
F7
F8
E7
E8
D7
D8
D5
D6
C6
K3
C5
C4
C7
C1
C2
D1
D2
C3
D3
E2
E1
F2
F1
G2
G1
H2
H1
J2
J1
K2
K1
L2
L1
M2
M1
M3
L3
M8
M7
L8
L7
L6
K8
K7
K6
J8
J7
J6
H6
H7
H8
G6
G7
G8
F6
F7
F8
E7
E8
D7
D8
D5
D6
C6
K3
C5
C4
TS_AYALON2_ATB
C7
H0
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
FC_AY0_HV16
FC_AY0_HV17
GND
V23
V22
V21
V20
V19
V18
V17
V16
V15
V14
V13
V12
V11
V10
V9
V8
V7
V6
V5
V4
V3
V2
V1
V0
H32
H33
H34
H35
H36
H37
H38
H39
H40
H41
H42
H43
H44
H45
H46
H47
H48
H49
H50
H51
FC_AY1_HV20
FC_AY1_HV21
V47
V46
V45
V44
V43
V42
V41
V40
V39
V38
V37
V36
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
V25
V24
TS_AYALON1_ATB
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
H31
FC_AY2_HV16
FC_AY2_HV17
V77
V76
V75
V74
V73
V72
V71
V70
V69
V68
V67
V66
V65
V64
V63
V62
V61
V60
V59
V58
V57
V56
V55
V54
V53
V52
V51
V50
V49
V48
NOTE: Place shorts close to Master AT rig.
JMP
W3002
C3081
C3030
220p
220p
GND
C3017
220p
GND GND
C3024
220p
GND GND
TP3005
TP3006
C3016
220p
JUMPER_0201_SHORTED_PADS
GND TSGND_BUCK TSGND_BOOST
C3080
220p
TP3007
JMP
W3001
+1P8V_TS
C3027
C3001
0.1u
10V
10u
0402S_P7-W70
GND
TS_SPI_CS#[21,30]
TS_SPI_MISO[21,30]
TS_IRQ_1V8#[20,30]
TS_SPI_CLK[21,30]
6.3V
0201S_P33-W39
GND
+1P8V_PANEL
R3005
100K
0201S_P28-W35
D
Q3002
PCH_VDD_PANEL_EN[10,65]
2
G
S
GND
+5V_TS
C3002
C3029
2.2u
6.3V
0.1u
0201S_P39-W39
GND
SPI Buffer
U3001
1A21Y
1
1OE
5
2A
4
2OE
9
3A
10
3OE
12
4A
13
4OE
7
GND
15
EPAD
74LVC125ABQ
GND
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
10V
0201S_P33-W39
GND
+1P8V_PANEL
C3003
0.1u 10V
0201S_P33-W39
14
A1
A1
A1
2Y
3Y
4Y
EDP_SPI_CS_R#
3
EDP_SPI_MISO_R
6
EDP_SPI_INT_R#
8
EDP_SPI_CLK_R
11
1
GND
R3009 33
R3008 33
R3010 33
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
R3007 33
Touch Con & Key
Touch Con & Key
Touch Con & Key
EDP_SPI_CS# [57]
EDP_SPI_MISO [57]
EDP_SPI_INT# [57]
EDP_SPI_CLK [57]
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
30 82Tuesday, May 21, 2019
30 82Tuesday, May 21, 2019
30 82Tuesday, May 21, 2019
1.00
1.00
1.00
VCC
Page 31
5
+3P3VAS_SIL
R3109
100K
0201S_P28-W35
D D
Uses Lynx Debug ATM
SW3103
DBG_D
12
N-O
34
GND
5
6
A1A2
D3102
V5.5MLA0402NR
GND
4
+1P8VA
R3104
100K
0201S_P28-W35
DNP
CDS2C05GTA
Power Button Filter
R3107
100
C3108
0.1u
GND
C3104
1000p
GND
3
DNP
D
SOTFL-3_1P3XP9XP55_P4
+1P8VA
R31050
Q3101
S
X865865-001
G
2
to silego
+1P8VA
R3108
100K
ALL
0201S_P28-W35
Prevent SAM IO leakage when sysoff
PWRBTN#_3V3 [58,74]
PWRBTN#_1V8 [18,33,34]
1
GND
C C
Uses Lynx Debug ATM
SW3101
DBG_D
12
N-O
34
GND
5
6
B B
GND
PWRBTN#_1V8_FILT [76]
+1P8VSB
R3103
4.7K
Volume Up Button Filter
R3101
100
A1A2
D3104
V5.5MLA0402NR
CDS2C05GTA
GND GND
VOL_UP#_FILT [76]
C3107
0.1u
GND
TP3101
TP3107
VOL_UP# [25,33]
C3103
1000p
+1P8VSB
R3102
4.7K
Volume Down Button Filter
R3106
Uses Lynx Debug ATM
A A
GND
SW3104
DBG_D
N-O
GND
5
6
12
34
5
A1A2
D3103
V5.5MLA0402NR
CDS2C05GTA
GND GNDGND
VOL_DOW N#_FILT [76]
100
C3105
0.1u
C3109
1000p
VOL_DOW N# [25,33]
4
Report errors to Steven
Button & Diagnostic Conn
Button & Diagnostic Conn
Button & Diagnostic Conn
Title:
Title:
Title:
<OrgAddr1>
<OrgAddr1>
Engineer:
Engineer:
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
3
2
WxH 422 x 273 mm
Engineer:
<OrgAddr1>
31 82Tuesday, May 21, 2019
31 82Tuesday, May 21, 2019
1
31 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 32
5
D D
4
3
2
1
C C
B B
A A
Cethera Sensor Connection
Cethera Sensor Connection
Cethera Sensor Connection
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A2
A2
A2
W x H 332 x 215 mm
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
1
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
1.00
1.00
32 82Tuesday, May 21, 2019
32 82Tuesday, May 21, 2019
32 82Tuesday, May 21, 2019
1.00
Page 33
5
SAM_SWD_CLK[29,34,76]
SAM_RESET#[29,34,58,76]
SAM_DBG_TX[29,34,71,76]
D D
SAM_KIP_UART_RX_DBG[29,74]
C C
FPC_DET_LOGIC_OVERRIDE#[58,76]
PCH_DBG_RX[25,29,76]
PCHTX_SAMRX[25,29,34]
TS_TCK_1V8[29,30]
TS_TDO_1V8[29,30]
IMVP_SCL_P[35,66]
PMI_I2C_SCL[25,28,76]
POWER_SMB_SDA[35,70]
VOL_UP#[25,31]
+3P3VSB
PCH_CATERR#_1V8[10,34]
CPU_C10_GATE#[22,56,60,62]
CNV_RF_RESET#[20,50]
PANEL_I2C_SCL[25,57]
PIO5_20[35,76]
RFU (LTE_UART_RX in Ca rmel DF) RFU (LTE_UART_TX in Ca rmel DF)
SLP_S4#[22,34,60] SLP_S3# [22,34,58]
PCH_SYS_RST#[18,22]
SAM_PD_SDA[18,29,35,79]
BT_DISABLE#[24,50]
SAM_SEN_SDA[35,39]
PLT_RST_BUF#[22,34,38,44]
SAM_LED1#[33,35]
+5VSB
+1P8VA
TP3307
TP3306
LTE_JTAG_TCK
LTE_JTAG_TDO
GND
4
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
2
4
6
8
J3302
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
MTG2
DBG_D
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
DEBUG CONN
63
65
67
69
MTG1
3
1
1
3
3
5
5
7
7
9
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
LTE_JTAG_TDI
LTE_JTAG_TMS
LTE_JTAG_SRST#
GND
SAM_SWD_DIO [29,34,76]
SAM_SWD_SWO [29,34,76]
TP3302
TP3305
SAM_DBG_RX [29,34,71,76]
PCH_DBG_TX [25,29,76]
SAMTX_PCHRX [25,29,34]
TS_TDI_1V8 [29,30]
TS_TMS_1V8 [29,30]
IMVP_SDA_P [35,66]
PMI_I2C_SDA [25,28,76]
POWER_SMB_SCL [35,70]
SAM_KIP_UART_TX_DBG [29,74]
BAT_SHUTDOWN# [58,70,76]
VOL_DOWN# [25,31]
SLP_A# [22,34]
PWRBTN#_1V8 [18,31,34]
SLP_S0# [22,34]
SAM_PD_SCL [18,29,35,79]
MODEM_CLKREQ [20,50]
PANEL_I2C_SDA [25,57]
WLAN_DISABLE# [24,50]
PIO5_21 [35,76]
SAM_SEN_SCL [35,39]
H_PROCHOT_1P8V# [10,34]
SAM_LED0# [33,35]
PCH_DEBUG_GPP_H23 [23]
+3P3VA
TPANEL_RST# [25,30,35]
TP3303 C3304
PCHRTS_SAMCTS [25,29,34,76]SAMRTS_PCHCTS
DBG_D
2
+3P3VSB +3P3VA
C3302
0.1u10V
0201
0201
DBG_D
C3301
0.1u10V
1.27mm
0.1u10V
0201
DBG_D
1
+5VSB +1P8VA
C3305
0.1u10V
0201
DBG_D
Orange
D3301
+3P3VA+3P3VA
R3302
1K
0201S_P28-W35
DBG_D
AK
<Core Design>
<Core Design>
<Core Design>
Debug Conn
Debug Conn
Title:
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
W x H 337 x 218 mm
2
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
Debug Conn
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
1
33 82Tuesday, May 21, 2019
33 82Tuesday, May 21, 2019
33 82Tuesday, May 21, 2019
1.00
1.00
1.00
B B
R3301
1K
0201S_P28-W35
DBG_D
LED_R_A LED_O_A
AK
D3302
Green
Heartbeat LED
A A
SAM_LED0#[33,35]
DBG_D
SAM_LED1#[33,35]
FW Debug LED
LED_1P1XP6XP6
DBG_D
LOW = LED ON
LOW = LED ON
5
4
3
Page 34
5
4
3
2
1
System
Aggregator
Module
D D
C341110u
VPP
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDDA
VBAT
VREFP
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSSA
DBG_T
DBG_TS
R3411 0.2
0603S_P6-W 100
D3402
N4
RB520CS3002L
E6
E8
F5
G5
J12
L6
L11
1V8_SAMA
N6
N11
P6
B3
D7
D8
E11
H5
J5
K7
L5
R3412
DBG_T
0
AK
TP3401
R3413
47
DBG_T
+1P8VA
PMTP3400
SP-TP-C0P381
32KHZ_XIN
32KHZ_XOUT
SAM_RESET#r
C3409
18p
18p
C3410
12
R3429
X3400
32.768KHZ
0
SAM_RESET#[29, 33,58,76]
D3401
RB520CS3002L
0201S_P33-W 39
C C
AK
C3419
0.1u
10V
R3400
10K
+1P8V_SAM
PMTP3401
SP-TP-C0P381
U3400D
L12
RTCXIN
K11
RTCXOUT
N13
RESETN
K4
XTALIN
J4
XTALOUT
LPC54S001JEV180 Rev 1B
PM_+1P8V_SAM+ [28]
PM_+1P8V_SAM- [28]
R3410
10
0201S_P28-W 35
C3426
2.2u
6.3V
0201S_P39-W39
C3412
0.1u
10V
0201S_P33-W 39
0201S_P33
C3425
0.01u
10V
VREFP
+1P8V_SAM
C3402
10u
6.3V
0402S_P7-W70
R3401
10
0201S_P28-W 35
+1P8VAS
C3403
2.2u
6.3V
0201S_P39-W39
C3401
1u
6.3V
0201S_P35-W35
C3405
C3413
0.01u
10V
0201S_P33
0201S_P33-W 39
C3404
0.1u
10V
0201S_P33-W 39
0.1u
10V
C3406
0.01u
10V
0201S_P33
C3407
C3414
0.01u
0.1u
10V
10V
0201S_P33
0201S_P33-W 39
C3408
C3415
0.1u
0.01u
10V
10V
0201S_P33
0201S_P33-W 39
C3417
C3416
0.1u
0.01u
10V
10V
0201S_P33
0201S_P33-W 39
C3420
C3418
0.01u
0.1u
10V
10V
0201S_P33
0201S_P33-W 39
C3421
0.1u
10V
0201S_P33
0201S_P33-W 39
C3427
0.01u
10V
C3428
0.1u
10V
0201S_P33-W 39
Configuration ID TBD
CFG_ID_THOS
CFG_ID_HUNS
CFG_ID_TENS
CFG_ID_ONES
ADC_RD_EN
TP3434
TP3435
TP3436
TP3437
TP3438
CFG_ID_THOS[ 35]
CFG_ID_HUNS[35]
TBL 3400
+1P8V_SAM +1P8V_SAM +1P8V_SAM +1P8V_SAM
R3404
R3402
2K
R3406
301
TBL3400
CFG_ID_THOS_EN
ADC_RD_EN[35 ,70]
R3403
2K
2K
R3407
R3408
402
121
TBL3400
TBL3400
CFG_ID_HUNS_EN
CFG_ID_TENS_EN
CFG_ID_EN
D
Q3401
SOTFL-3_1P3XP9XP55_P4
G
S
GND
CFG_ID_ONES_EN
R3405
2K
R3409
0
TBL3400
+1P8VA
C3422
1u 6.3V
OD PIN
OD PIN
R3434
47K
D6
A1
E9
A10
C8
E7
A5
H12
H10
G12
P2
M3
F11
E13
M4
E14
C14
C6
D13
C13
B12
N7
M7
K8
M13
M9
B13
A2
M5
L3
L4
L9
0201S_P35-W 35
U3400A
PIO0_0
PIO0_1
PIO0_2/TRST
PIO0_3/TCK
PIO0_4/TMS
PIO0_5/TDI
PIO0_6/TDO
PIO0_7
PIO0_8
PIO0_9
PIO0_10/ADC0_0
PIO0_11/ADC0_1
PIO0_12/ADC0_2
PIO0_13
PIO0_14
PIO0_15/ADC0_3
PIO0_16/ADC0_4
PIO0_17
PIO0_18
PIO0_19
PIO0_20
PIO0_21
PIO0_22
PIO0_23/ADC0_11
PIO0_24
PIO0_25
PIO0_26
PIO0_27
PIO0_28
PIO0_29
PIO0_30
PIO0_31/ADC0_5
LPC54S001JEV180 Rev 1B
DNP
GND
R3435
47K
SAM_PIO0_3
SAM_SW D_CLK
SAM_SW D_DIO
SAM_PIO0_2
SAM_PIO0_4_ISP0
SAM_PIO0_5_ISP1
SAM_PIO0_6_ISP2
PIO1_0/ADC0_6
R3426 100K
DNP
SAM_FLASH_EN[35]
PIO1_1
PIO1_2
PIO1_3
PIO1_4
PIO1_5
PIO1_6
PIO1_7
PIO1_8
PIO1_9
PIO1_10
PIO1_11
PIO1_12
PIO1_13
PIO1_14
PIO1_15
PIO1_16
PIO1_17
PIO1_18
PIO1_19
PIO1_20
PIO1_21
PIO1_22
PIO1_23
PIO1_24
PIO1_25
PIO1_26
PIO1_27
PIO1_28
PIO1_29
PIO1_30
PIO1_31
N3
K12
L14
J13
D4
E4
G4
N1
P8
K6
N9
B4
K9
G10
C12
A11
B7
N12
D1
L1
M1
N8
P11
M10
N14
M12
J10
F10
E12
C11
A8
C5
+1P8VA
R3424
R3425
R3436
47K
47K
B B
R3415
47K
SUS_PW RGD_5VSB[59]
TP3422
PIO0_4/5/6 used
for ISP Strap
SAM_SW D_SWO[29,33,76]
SAM_SW D_CLK[29,33,76]
SAM_SW D_DIO[29 ,33,76]
XDP_PRESENT#[18,56]
XDP_SPI0_IO2[18,21]
PCH_LCD_BKLT_EN[10,72]
VCCIN_AUX_PG[58,69]
PCH_SAM_INST_ON[23,72]
BATEN_PULSE[58,70]
THERMAL_MODULE _DET[39]
A A
H_PROCHOT_1P8V#[10,33]
THERMAL_MODULE_DET
LOW: AVC
HIGH: DELTA
FAN_TACH1[39]
SAM_PIO0_3[76]
SAM_PIO0_4_ISP0[76]
SAM_PIO0_5_ISP1[76]
SAM_PIO0_6_ISP2[76]
R3432 0
R3430 0
BAT_DET#[70]
CHRG_OK[63]
TP3415
5
47K
SLP_SUS#[22,62]
SLP_A#[22,33]
VRM_PW RGD[58,66]
CFG_ID_ONES
CFG_ID_TENS
BATEN_PULSE_SAM
PIO0_31_ADC_05
R3433
47K
SAM_PIO0_2
SAM_PIO0_3
R34200
SPIFI_CS#
SPIFI_io0
SPIFI_io1
SPIFI_Clk
SPIFI_io3
SPIFI_io2
FC10
PCH_UART_RXr
FC0
PCH_UART_TXr
PCH_UART_RTSr
PCH_UART_CTSr
PCH_CATERR#_1V8_SA M
DEBUG_RXr
FC1
DEBUG_TXr
PIO1_15_A11
PIO1_17
PIO1_18
KIP_UART_TX
KIP_UART_RX
FC4
U3402
NX3P1108UK
BGA4_2X2_P98XP98XP59_P5
A2
VOUT
VIN
B2
GND
EN
DNP
PIO1_0
PD_SAM_INT# [79]
R3428 10
R3422 10
SL1_PSU_DET [70,76]
SEN_HALL_INT#_N [54,76]
PWRBTN #_1V8 [18,31,33]
SUS_PW RGD [59]
PCH_SAM_INT [23]
PCH_SAM_INT2 [23]
4
A1
B1
C3430
0.1u
10V
GND
SAM_UEFIROM_SPI_MO SI [ 21]
SAM_UEFIROM_SPI_MISO [21]
SAM_UEFIROM_SPI_CLK [21]
TP3423
TP3408
TP3407
TP3404
R341610
R341710
R341810
R341910
R34270
R343110
R34370
TP3418
TP3419
TP3420
SLP_S0# [22,33]
SLP_S3# [22,33,58]
SLP_S4# [22,33,60]
+1P8VA
R3414
0
ALL
PCHTX_SAMRX [25,29,33]
SAMTX_PCHRX [25,29,33]
SAM_DBG_RX [29,33, 71,76]
SAM_DBG_TX [29,33,71,76]
TP3402
TP3403
R342310
SAM_KIP_UART_TX [74,76]
SAM_KIP_UART_RX [74]
TP3406
U3401
VCC8CS
SCLK
SI/SIO0
SO/SIO1
4
WP/SIO2
GND
9
NC/SIO3
MPAD
MX25U1635EZUI-10G
1
6
5
2
3
7
TP3430
PCH_CATERR#_1V8 [10,3 3]
TP3405
ISH_SAM_INT [25]SEN_HALL_INT#_S [54,76]
BLADE_UART_DBG_EN [74]
PD_SAM_DBG_ACC_M ODE_1V8 [37]
PLT_RST_BUF# [22,33,3 8,44]
SPIFI_Clk
SPIFI_io0
TP3428
TP3427
SAMRTS_PCHCTS [ 25,29,33,76]
PCHRTS_SAMCTS [ 25,29,33,76]
TP3409
TP3410
TP3411
TP3412
TP3413
TP3414
TP3429
SPIFI_io1
SPIFI_io3
SPIFI_io2
3
SPIFI_CS#
TP3432
+1P8VA
10K
R3421
TP3431
SAM Power, ADC, & Debug
SAM Power, ADC, & Debug
SAM Power, ADC, & Debug
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Proj ect Name Rev
Size Proj ect Name Rev
Size Proj ect Name Rev
A2
A2
A2
W x H 492 x 318 mm
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Title:
Engineer:
<OrgAddr1>
Engineer:
<OrgAddr1>
Engineer:
<OrgAddr1>
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
1
1.00
1.00
34 82Tuesday, May 21, 2019
34 82Tuesday, May 21, 2019
34 82Tuesday, May 21, 2019
1.00
Page 35
5
4
3
2
1
U3400B
FC3
P3
PIO2_0/ADC0_7
P4
PIO2_1/ADC0_8
C3
PIO2_2
B1
PIO2_3
D3
PIO2_4
C1
PIO2_5
F3
PIO2_6
J2
PIO2_7
F4
PIO2_8
K2
PIO2_9
P1
PIO2_10
K3
PIO2_11
M2
PIO2_12
P7
L7
M8
L8
P10
N10
P12
P13
L10
K10
M14
K14
J11
H11
H14
G13
G11
F12
D14
LPC54S001JEV180 Rev 1B
PIO2_13
PIO2_14
PIO2_15
PIO2_16
PIO2_17
PIO2_18
PIO2_19
PIO2_20
PIO2_21
PIO2_22
PIO2_23
PIO2_24
PIO2_25
PIO2_26
PIO2_27
PIO2_28
PIO2_29
PIO2_30
PIO2_31
FC5
PIO3_0
PIO3_1
PIO3_2
PIO3_3
PIO3_4
PIO3_5
PIO3_6
PIO3_7
PIO3_8
PIO3_9
PIO3_10
PIO3_11
PIO3_12
PIO3_13
PIO3_14
PIO3_15
PIO3_16
PIO3_17
PIO3_18
PIO3_19
PIO3_20
PIO3_21/ADC0_9
PIO3_22/ADC0_10
PIO3_23
PIO3_24
PIO3_25
PIO3_26
PIO3_27
PIO3_28
PIO3_29
PIO3_30
PIO3_31
TP3503
TP3501
PM_PCH_PWROK[22]
RSMRST_1v8#[37]
D D
SLP_S4_DRV#[58,60,62]
R3523
100K
0201S_P28-W35
POWER_SMB_SDA[33,70]
POWER_SMB_SCL[33,70]
C C
+1P8VA
R3501 2K
R3500 2K
TPANEL_RST#[25,30,33]
TP3508
SAM_KBTP_PWR_EN[64]
0201S_P28-W35
0201S_P28-W35
SAM_PROCHOT[10]
SYS_PWROK_1v8[37]
VCCRTC_RST[55]
VSUS_ON[59,62,69]
SL_UART_RX_1V8[37]
SL_UART_TX_1V8[37]
SAM_LCD_BKLT_EN[72]
SAM_VDD_PANEL_EN[65]
R35020
R35030
BAT_SDAr
BAT_SCLr
SAM_UEFIROM_SPI_CS#[21]
SAM_MUX0_EN[29]
PCH_DPWROK_1v8[37]
TP3505
TP3509
SAM_UEFIROM_EN[21,76]
R3533 499
R3532 499
PANEL_LOGO[57]
USBC_MUX0[29]
USBC_MUX1[29]
USBC_MUX2[29]
USBC_MUX3[29]
CFG_ID_HUNS[34]
CFG_ID_THOS[34]
SAM_BKLT_CTRL_PWM[72]
RTCRST_CTRL[20]
SAM_PWRBTN_1v8#[37]
SLP_S3_DRV#[58,65]
SL_UART_RXr
SL_UART_TXr
SAM_PIO2_24
SAM_PIO2_25
D12
D11
C10
A13
B11
B10
C9
B8
A7
C7
A3
B2
L2
H4
E3
D2
E1
K1
M6
J3
N2
P5
N5
C2
E2
P9
K5
P14
M11
L13
K13
J14
PD_SDAr
PD_SCLr
FC8
SAM_3P3V_PD_EN_R
SAM_PD_HRESET_R
OD PIN
OD PIN
FC2
ACPRESENT_SAM
R3526 0
FC9
TP3530
SAM_PCH_TOP_SWAP [25]
SAM_PCH_RTC_WAKE [23]
ESPI_RST# [21]
ESPI_CS# [21]
ESPI_IO_0 [21]
ESPI_IO_1 [21]
ESPI_CLK [21]
ESPI_IO_2 [21]
ESPI_IO_3 [21]
SAM_PCH_RSK [23]
SAM_PCH_LID_STATE [23]
EXT_VOLT_ADC_EN [63]
ADC_RD_EN [34,70]
FAN1_PWM_1v8 [37]
R3511 0
R3512 0
R3505 0
R3506 0
PIO3_23
PIO3_24
SAM_PIO3_27
SAM_PIO3_28
DNP
TP3528
TP3529
TP3525
SAM_FLASH_EN [34]
TP3514
IMVP_PROGRAM_ENABLE [66]
ACPRESENT_SAM [37]
TP3521
0201S_P28-W35
0201S_P28-W35
R3507 0
SAM_SOC_JTAG_TRST# [10]
TP3527
SAM_3P3V_PD_EN [79]
SAM_PD_HRESET [79]
+1P8VA
R3513
2K
R3514
2K
R3515 0
R3516 0
R3522 0
R3524 0
TP3526
SAM_KIP_RST# [29,74]
SAM_PD_SDA [18,29,33,79]
TP3511
SAM_PANEL_SDA [72]
SAM_PANEL_SCL [72]
SAM_PD_SCL [18,29,33,79]
SAM_LS_DIR1 [37]
C3501
0.01u
10V
0201S_P33
SAM_SEN_SDA [33,39]
SAM_SEN_SCL [33,39]
PSU_VOLT [63]
SL1_ADC [70]
C3502
0.01u
10V
0201S_P33
+1P8VA
R3508
10K
CHARGER_SDA[63]
B B
TP3516
MTP3518
A A
TP3517
TP3519
TP3520
IMVP_SDA_P[33,66]
IMVP_SCL_P[33,66]
+5V_FAN_EN[64]
CHARGER_SCL[63]
+5VSB_EN[59]
SAM_LS_DIR2[37]
SL1_RX_SEL#[70]
SAM_SL1_PWR_EN[63,79]
SL1_HPD2_EN#[72,76]
R3521 0
SAM_LED0#[33]
SAM_LED1#[33]
R3534 0
R3535 0
R3517 0
R3525 0
SAM_PIO4_8
IMVP_SDA_P_R
IMVP_SCL_P_R
+5V_FAN_EN_SAM
FC6
U3400C
H13
PIO4_0
G14
PIO4_1
F14
PIO4_2
F13
PIO4_3
D9
PIO4_4
E10
PIO4_5
D10
PIO4_6
A14
PIO4_7
B14
PIO4_8
A12
PIO4_9
B9
PIO4_10
A9
PIO4_11
A6
PIO4_12
B6
PIO4_13
B5
PIO4_14
A4
PIO4_15
C4
PIO4_16
LPC54S001JEV180 Rev 1B
PIO5_16
PIO5_17
PIO5_18
PIO5_19
PIO5_20
PIO5_21
PIO5_22
PIO5_23
PIO5_24
PIO5_25
PIO5_26
F2
PIO5_17
F1
G1
G2
G3
H1
FC7
H2
H3
SAM_PIO5_24
J1
E5
SAM_PIO5_26
D5
TP3510
SAM_PCH_INT [23]
SAM_PCH_BASE [23]
EXP_SDAr
EXP_SCLr
SL1_UART_LS_EN# [37]
TP3507
TP3504
TP3523
+1P8VA
R3518
2K
DNP
R3504
2K
DNP
R3519 0DNP
R3520 0DNP
+1P8VA
R3510
499K
TP3502
R3509
0
DNP
PIO5_20 [33,76]
PIO5_21 [33,76]
TP3506
KIP_LS_EN [74]
TDM_DET [54]
Title:
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
W x H 397 x 257 mm
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
SAM Buses
SAM Buses
SAM Buses
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
35 82Tuesday, May 21, 2019
35 82Tuesday, May 21, 2019
1
35 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 36
5
D D
4
3
2
1
C C
B B
A A
Blank
Blank
Blank
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A1
A1
A1
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
Title:
Engineer:
Engineer:
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
1.00
1.00
1.00
36 82Tuesday, May 21, 2019
36 82Tuesday, May 21, 2019
36 82Tuesday, May 21, 2019
Page 37
5
D D
SL_UART_TX_1V8[35] SAM_SL1_TX [70]
SL_UART_RX_1V8[35]
SAM_LS_DIR1[35]
SAM_LS_DIR2[35]
R3740 0
R3741 0
200K
R3706
DNP
200K
R3701
4
200K
R3702
200K
R3704
DNP
C3701
0.1u
10V
200K
R3705
DNP
+1P8VA
499K
R3700
3
SN74AVC2T245RSWR
VCCB
OE
GND
+3P3VA
6
5
B1
4
B2
2
3
C3700
1u
6.3V
U3700
7
VCCA
8
A1
9
A2
10
DIR1
1
DIR2
OE "HIGH" for hi-impedance both sides
R3719 0
R3720 0
2
SAM_SL1_RX [70]
1
SL1_UART_LS_EN#[35]
C C
+1P8VA
10K
+3P3VSB
R3718
10K
G
R3717
FAN1_PWM_1v8[35] FAN1_PWM [39]
B B
Series Rs to protec inputs in event SAM
drives signals HIGH and Silego IC is not powered
PCH_DPWROK_1v8[35] PCH_DPWROK [22]
SAM_PWRBTN_1v8#[35] SAM_PCH_PWRBTN# [10,22]
SYS_PWROK_1v8[35] SYS_PWROK [22]
ACPRESENT_SAM[35]
RSMRST_1v8#[35] RSMRST# [18,22]
R3731 1KALL
R3724 1KALL
R3728 1KALL
R3726 1KALL
R3729 1KALL
S
PCH_DPWROK_1v8_R
SAM_PWRBTN_1v8#_R
SYS_PWROK_1v8#
ACPRESENT_SAM_R
RSMRST_1V8#_R RSMRST#_R
D
R3716 0
Q3703
SOTFL-3_1P3XP9XP55_P4
R3721 0
U3713
3
A0
4
A1
5
A2
6
A3
2
B0
SLG4R42324
VDD
A0B0
GND
R3703
499K
DNP
+3P3VSB
C3713
0.1u
6.3V
1
11
Y0
10
Y1
9
Y2
8
Y3
12
7
GND
R3727 1K
SAM_PCH_ACPRESENT [22]
PD_SAM_DBG_ACC_MODE[29,79]
R3709 0
PD_SAM_DBG_ACC_MODE_1V8 [34]
GND
A A
20170908sjs1428
title is: SAM Level shifters
SAM Level Shifters
SAM Level Shifters
SAM Level Shifters
Title:
Title:
Title:
<OrgAddr1>
<OrgAddr1>
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
WxH 472 x 305mm
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
<OrgAddr1>
1
Report errors to Steven
1.00
1.00
37 82Tuesday, May 21, 2019
37 82Tuesday, May 21, 2019
37 82Tuesday, May 21, 2019
1.00
Page 38
5
4
3
2
1
Trusted Platform Module
D D
C C
B B
TBL3801
SPI_CLK[21]
PLT_RST_BUF#[22,33,34,44]
R3809 0TBL3801
R3802 15
DNP
C3804
22p
0201S_P33
25V
GND
TPM_SPI_CLK
Z_PP_NUVO_NCTPM_PP
R3804
0
TBL3801
R3806
0
TBL3801
+1P8V_TPM
R3808
0
TBL3801
R3807
0
TBL3801
TBL3801
C3807
0.1u
10V
0201S_P33-W39
GND
U3801
19
SCLK
17
RESET
2
NC1
3
NC2
5
NC3
7
NC4
9
NC5
10
NC6
11
NC7
12
NC8
14
NC9
15
NC10
25
NC11
26
NC12
27
NC13
28
NC14
31
NC15
32
NC16
NPCT750SABYX
M1041056-002
TBL3801
VSB
VHIO_8
VHIO_22
SDA/GIO0
SCL/GIO1
SPI_IRQ/GPIO2
GPIO3
GPIO4/SINT
SCS/GPIO5
PP/GPIO6
MOSI/GPIO7
MISO
GND1
GND2
MPAD
+1P8V_TPM
1
8
22
29
30
18
6
13
20
4
21
24
16
23
33
GND
TP3803
TP3804
TP3801
TP3802
NUVO_PP_Z_NC
TPM_SPI_MOSI
TPM_SPI_MISO
ALL
C3801
0.1u
10V
0201S_P33-W39
GND
ALL
C3806
0.1u
0201S_P33-W39
GND
SP_TP_SMDP58
SP_TP_SMDP58
SP_TP_SMDP58
SP_TP_SMDP58
R3805 0TBL3801
R3803 15
R3801 15
10V
GND
PCH_SERIRQ [10]
SPI_TPM_CS# [21]
Neet INT Conn, May need add'l cfg for NatZ
DNP
C3805
0.1u
10V
0201S_P33-W39
SPI_MOSI [21]
SPI_MISO [21]
+1P8VSB +1P8V_TPM
DBG_S
R3817 0.1
0603S_P65-W95
PMTP3801
SP-TP-C0P381
+1P8V_TPM
ALL
R3813
4.99K
0201S_P28-W35
TPM_PP
DNP
R3814
4.99K
0201S_P28-W35
GND
SP-TP-C0P381
PMTP3802
GND GND
A A
5
GND
TPM
TPM
Title:
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
4
3
2
W x H 357 x 231 mm
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
TPM
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
1
1.00
1.00
1.00
38 82Tuesday, May 21, 2019
38 82Tuesday, May 21, 2019
38 82Tuesday, May 21, 2019
Page 39
5
4
3
2
1
+5V_FAN
Imax=0.7A
Trace Width>30mil
+5V_FAN
J3901
7
MTG1
1
1
2
2
D D
C3903
22u 6.3V
0603
THERMAL_MODULE_DET[34]
MTP3904
C C
+1P8VAS
+1P8VSB
Fan Supplier Detect
RB520CS3002L
C3907
0.1u
GND
R3906
499K
D3903
3
3
4
4
5
5
6
6
CFAN_PWM_R_1
AK
8
MTG2
FAN_TACH1 [34]
R3902 4.99K
0201
250uA for 32conv/sec
SAM_SEN_SCL[33,35]
SAM_SEN_SDA[33,35]
C3904
0.1u
Skin4
FAN Connector
+5V_FAN
MTP3902
+3P3V
1
6
4
A K
U3903
SCL
SDA
ADD0
SN1608035
D3901
1N4148WS-R2
75V
C3906
0.1u
DNP
V+
ALERT
GND
R3903 100
5
3
2
7-bit I2C Address = 0x4A
GND
B B
+1P8VAS
VDD_U3904
C3905
0.1u
250uA for 32conv/sec
SAM_SEN_SCL
SAM_SEN_SDA
Skin3
1
6
4
U3904
SCL
SDA
ADD0
SN1608035
ALERT
GND
5
V+
3
R3917
2
THERMAL_MODULE_DET
LOW: AAC
HIGH: DELTA
0603
close to J39001
R3918
DNP
GND
0201S_P28-W35
DNP
GND
0201S_P28-W35
+5V_FAN
0
TEM_DEVICE_RST#
0
TEM_DEVICE_RST#
MTP3901
MTP3903
FAN1_PWM [37]
+1P8VAS
C3901
0.1u
GND
250uA for 32conv/sec
SAM_SEN_SCL
SAM_SEN_SDA
7-bit I2C Address = 0x48
+1P8VAS
C3902
0.1u
GND
+1P8VAS
R3916
100K
U3901
1
6
4
SCL
SDA
ADD0
SN1608035
ALERT
GND
5
V+
3
R3904
0201S_P28-W35
2
TEM_DEVICE_RST#
0
SOTFL-3_1P3XP9XP55_P4
Skin1
GND
250uA for 32conv/sec
SAM_SEN_SCL
SAM_SEN_SDA
1
6
4
U3902
SCL
SDA
ADD0
SN1608035
ALERT
GND
Skin2
7-bit I2C Address = 0x49
+1P8VAS
V+
+3P3VAS_SIL
R3905
100K
Q3901
S
5
3
2
D
G
TEM_DEVICE_RST#
0201S_P28-W35
DNP
0
R3919
GND
DEVICE_RST# [58]
7-bit I2C Address = 0x 4B
GND
temp sensor for the right location testing
A A
20170908sjs1321
title is: Temp Sensor/ System Fan
Temp Sensor/System Fan
Temp Sensor/System Fan
Title:
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
Engineer:
Engineer:
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Temp Sensor/System Fan
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
39 82Tuesday, May 21, 2019
39 82Tuesday, May 21, 2019
39 82Tuesday, May 21, 2019
1
1.00
1.00
1.00
Page 40
E
D
C
B
A
+1P8V_AUDIO_DVDD
4 4
U4009
C8
PCBEEP
MHDA_SDOUT[ 20]
MHDA_SYNC[20]
R4006200K
C4026
ALL
0.1u
R4003 22
AGND
AGND
C4006
22p
DNP
GND
C4009 2.2u
CODEC_AMP_OUTL[42]
CODEC_AMP_OUTR[42]
HPOUT_JD_R
DMIC_CLK_CODEC[54,76]
DMIC_DATA1_CODEC[54,76]
CODEC_CBN1_R
CODEC_CBP1_R
HP_MIC_L[41]
HP_MIC_R[41]
MHDA_BCLK[20]
+1P8V_AUDIO
R4019100K
HPOUT_JD[41,76]
COMBO_JACK[41]
3 3
JP4001
1 2
0201 SHUNT
JP4002
1 2
0201 SHUNT
JP4003
1 2
0201 SHUNT
GND
E4
SDATA_OUT
D5
SYNC
E6
BCLK
D7
JD1
F11
JD2
G10
GPIO1/DMIC_CLK
F9
GPIO0/DMIC_DATA12
E12
LINE2_L
E10
LINE2_R
B9
MIC2_L/RING2
A10
MIC2_R/SLEEVE
H9
GPIO2/I2S_EN/SPDIF_OUT/DMIC_DATA34
G6
I2S_BCLK
D9
I2S_IN
F5
I2S_LRCK
H7
I2C_CLK
H5
I2C_DATA
C10
MIC2_CAP
B1
CBP
A2
CBN
E8
RESETB
ALC3300-GRT
C4017
10u
AGND
MIC2_VREFO_L
MIC2_VREFO_R
I2S_MCLK/I2S_OUT2
DVDD
DVDD_IO
AVDD1
AVDD2
LDO1_CAP
LDO2_CAP
LDO3_CAP
VREF
5VSTB
CPVEE
HPVDD
HPOUT_L
HPOUT_R
SDATA_IN
EAPD
TEST
SCAN
I2S_OUT1
AVSS1
AVSS2
CPGND
DGND_1
DGND_2
H11
F1
C12
D3
A12
D1
E2
D11
A8
B5
B3
A6
A4
SDATA_IN_R
G2
C6
B7
F3
G12
R4002 10K
G4
G8
F7
B11
C2
C4
H3
H1
GND
CODEC_LDO1
CODEC_LDO2
CODEC_LDO3
CPVEE
HPOUT_L [41]
HPOUT_R [41]
HP_MIC_VREFO_L [41]
+1P8V_AUDIO_DVDD
+1P8V_AUDIO
C4002
C4016
0.1u
10u
AGND AGND AGND
R4004 22
GND
AGND
C4029
C4015
0.1u
10u
GND GND GND GND
R4018
C4033
100K
0.1u
C4030
2.2u
C4020
0.1u
C4025
10u
C4023
AGND
AGND AGND AGND
ALC3260_VD5STB
AGND
C4013
10u
C4022
10u
MHDA_SDIN [20]
DNP
0.1u
+1P8V_AUDIO
R40140
C4008
+5VSB +5V_AUDIO
R4036
10K
DNP
AUDIO_VREF
C4001
0.1u
AGND AG ND
10u
GND GND
C4019
2.2u
C4021
0.1u
R4035
10K
+1P8V_AUDIO_DVDD
R4001
10K
+5V_AUIDO_AVDD
C4003
0.1u
C4010
10V
0402
10u
AGNDAGND
CODEC_PD_N [42]
R40340
+5V_AUDIO
2 2
1 1
REALTEK ALC3269C_81BGA
REALTEK ALC3269C_81BGA
REALTEK ALC3269C_81BGA
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A2
A2
A2
W x H 427 x 276 mm
Date: Sheet of
Date: Sheet of
E
D
C
B
Date: Sheet of
Title:
Engineer:
Engineer:
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
A
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
1.0.0.1
1.0.0.1
40 82Tuesday, May 21, 2019
40 82Tuesday, May 21, 2019
40 82Tuesday, May 21, 2019
1.0.0.1
Page 41
E
D
C
B
A
HP/MIC1 Combo Jack
HP_MIC_VREFO_L[40]
R4104
2.2K
4 4
3 3
HP_MIC_R[40]
HP_MIC_L[40]
COMBO_JACK[40]
C4104 4.7u
C4105 4.7u
AGND
C4106
10u
AGND
R4101 1K
C4107
4700p
R4106 22K
HPOUT_L[40]
HPOUT_R[40]
MIC1_CR_FMIC1_CR
R4105
22K
AGND AGND
L4101 place close to CON4101
L4101 GBK160808T-121Y
120 OHM,100MHZ
C4103
100p
R4102 10
R4110
10K
AGND AGND
R4111
10K
HPOUT_JD[40,76]
HPOUT_L_F
HPOUT_R_F
L4102 GBK160808T-121Y
L4103
120 OHM,100MHZ
GBK160808T-121YR4103 10
120 OHM,100MHZ
C4101
100p
AGND AGND
R4107 0
C4102
100p
AGNDGND
D4104
V5.5MLA0402NR
CDS2C05GTA CDS2C05GTA CDS2C05GTA
A1 A2
D4102
V5.5MLA0402NR
A1 A2
GNDGND GND
V5.5MLA0402NR
HP_MIC_LR_CON[76]
HPOUT_R_CON[76]
HPOUT_L_CON[76]
D4103
C4108
A1 A2
100p
GND
This is the
Lynx combo
jack.
Schematic
symbol is only
used for the
footprint
(Screw on
connector).
Therefore, it
is DNP.
AGND
1
3
4
5
2
DNP
J4103
MIC
RIGHT
DET
LEFT
GND
D4101
CDS2C05GTA
V5.5MLA0402NR
A1 A2
GND
SPK_L+_CON[76]
2 2
1 1
SPK_L+[42]
SPK_L-[42]
SPK_R+[42]
SPK_R-[42]
R4114 0
R4115 0
R4116 0
R4117 0
C4121
1000p
C4122
1000p
C4123
1000p
C4124
1000p
GND
GND
D4105
A1A2
V18MLA0402NR
GND
D4108
A1A2
V18MLA0402NR
A1A2
GND
D4106
SPK_L+_CON
SPK_L-_CON
V18MLA0402NR
SPK_L-_CON[76]
SPK_R+_CON[76]
SPK_R+_CON
SPK_R-_CON
D4107
A1A2
V18MLA0402NR
SPK_R-_CON[76]
LYNX Speaker Connector
J4101
1
1
2
2
X872411-001
3
MTG1
4
MTG2
GND
LYNX Speaker Connector
J4102
1
1
2
2
3
MTG1
4
MTG2
GND
CONN_B2B_2-X872411-001
CONN_B2B_2-X872411-001
X872411-001
Universal Jack / Speaker HDR /DMIC HDR
Universal Jack / Speaker HDR /DMIC HDR
Universal Jack / Speaker HDR /DMIC HDR
Title:
Title:
GND GND
E
D
C
B
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Title:
Engineer:
Engineer:
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
A
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
41 82Tuesday, May 21, 2019
41 82Tuesday, May 21, 2019
41 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 42
5
+VSYS
Inductor may be changed based on placement constraints
L4201
R4215 0.02
DNP
D D
PTP4201
25V
DBG_D
CODEC_PD_N
PTP4202
C4221
22u
1.5uH
DBG_D
R4223 0DNP
R4219 150K
DBG_D
C4223
DBG_D
DBG_D
0.1u
VBOOST_BOOT
0201
VBOOST_FSW VBOOST_COMP
VBOOST_EN
R4225
100K
VBOOST_VCC
C4227
Peak current at 3A
2.2u
Switching frequency set to roughly 1 MHz
DBG_D
boost output voltage = 9.375V
4
PTP4203
U4202
11
SW
10
BOOT
1
FSW
9
VIN
7
EN
2
VCC
TPS61089RN
DBG_D
E1 E2
I1 I2
6
VOUT
3
FB
4
COMP
VBOOST_ILIM
8
ILIM
5
GND
R4224
SENS
LOAD
0.01
DBG_S
VBOOST_FB
DBG_D
R4220
127K
OUTNR
DNP
3
PTP4204
R4221 681KDNP
R4222
100K
R4218
4.99K
C4220
10p
DBG_D
C4224
DBG_D
0.01u
Need to confirm with TI for compensation
DBG_D
SPK_R+ [41]
SPK_R- [41]
25V
DBG_D
OUTNL
C4225
22u
DBG_D
C4226
22u
25V
+V_AUDIOBOOST
C4222
22u
25V
DBG_D
OUTPLOUTPR
SPK_L- [41]
SPK_L+ [41]
2
1
R4212R4210
15dB
R4211
10
0201
C C
+V_AUDIOBOOST AMP_VCC
+1P8V_AUDIO
B B
CODEC_PD_N[40]
S
CODEC_AMP_OUTR[40]
G
Q4201
AMP_VCC
C4217
10u
0603
16V
R4201
10K
0201
D
Close IC
+5V_AUDIO
C4207
0.1u
0201
16V
R4205 100K
0201
C4213
1000p
0201
25V
Close IC
AMP_VCC AMP_VCC
Shut-down Control
Hi : Normal
Low: shut-down
AMP_PD_N
C4219
C4216
0.1u
0201
16V
C4212
330p
0201
25V
AGND
0.33u
0201
25V
0201
16V
C4209
0.1u
25
26
27
28
29
30
31
32
33
AGND
C4201
330p
0201
25V
24
GND
OUTPR
BSPR
PVCC
PVCC
SDZ
FAULTZ
INPR
INNR
EPAD
Plimit
1
R4216 10K
R4206
0
0201
DNP
R4202
10
0.33u
0201
25V
23
OUTNR
0201
Close IC
AGND
0201
Close IC
C4210
22
BSNR
GVDD
2
GVDD
C4215
1u
0201
10V
R4203
10
Close IC
20
21
GND
GND
U4201
ALC1304
Gain/SLV3GND4INNL5INPL6MUTE7PBTL/BTL
C4203
0.1u
0201
16V
0201
19
BSNL
AGND
C4211
0.1u
0201
16V
C4218
330p
0201
25V
C4206
0.33u
0201
25V
18
OUTNL
8
17
GND
OUTPL
BSPL
PVCC
PVCC
AVCC
Sync
AM0
AM1
16
15
14
13
12
11
10
9
C4214
330p
0201
25V
C4208
0.33u
0201
25V
GAIN / SLV
CODEC_AMP_OUTL [40]
R4204
10
0201
Close IC
Close IC
GVDD
BTL/PBTL Setting
Gain/SLV Setting
R4210
54.9K
0201
R4212
34.8K
0201
C4204
1000p
0201
25V
R4217
10K
0201
DNP
R4207
10K
0201
C4205
0.1u
0201
16V
15dB
C4202
10u
0603
16V
AM Avoidance Setting
R4214
10K
0201
DNP
R4208
10K
0201
R4213
10K
0201
DNP
R4209
10K
0201
A A
AGND
5
4
3
AGND
ALC1304 AMP
ALC1304 AMP
Title:
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
ALC1304 AMP
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
42 82Tuesday, May 21, 2019
42 82Tuesday, May 21, 2019
1
42 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 43
5
D D
4
3
2
1
C C
B B
A A
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
W x H 737 x 477 mm
Title:
Engineer:
Engineer:
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
1
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
43 82Tuesday, May 21, 2019
43 82Tuesday, May 21, 2019
43 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 44
5
4
3
2
1
1
C4413
47u
RN4405 0DNP
RN4403 0DNP
RN4402 0DNP
C4407
0.1u
GNDGND
2
3
L4402
2 3
1 4
2
3
L4403
2 3
1 4
2
3
2 3
1 4
GND
DLP11TB800UL2L
4
1
4
1
4
L4404
C4416
100p
D4421
PESD5V0H1BSF
K1 K2
GND
DLP11TB800UL2L
DLP11TB800UL2L
GND
M2_PCIECLK_N[20]
M2_PCIECLK_P[20]
D D
+3P3VSB
C4411
0.1u
PCIE_SSD_TN1_C
PCIE_SSD_TP1_C
PCIE_SSD_TN0_C
PCIE_SSD_TP0_C
C4402
0.1u
GND
+3P3V_SSD_CON
R4407
100K
DNP
GND
C4401
100p
GNDGND
+3P3V_SSD_CON
M2_PCIECLK_REQ#[20]
C4412
10p
GND
R4416 10K
R4412
100K
DNP
1
R4406 0DNP
C4414 0.22u
C4404 0.22u
C4406 0.22u
C4408 0.22u
U4401
VCC
A
B2O
GND
SN74LV1T08DCKR
ALL
+3P3V_SSD_CON
C4403
47u
GND
5
4
3
GND
PCIE_SSD_TX1_DN[24]
PCIE_SSD_TX1_DP[24]
PCIE_SSD_TX0_DN[24]
PCIE_SSD_TX0_DP[24]
C C
PLT_RST_BUF#[22,33,34,38]
PCIE_SSD_PERST#[10]
B B
PCIECLK_SSD_N_F
PCIECLK_SSD_P_F
PCIE_SSD_TN1_F
PCIE_SSD_TP1_F
PCIE_SSD_TN0_F
PCIE_SSD_TP0_F
CON4401
74
3.3V_1
72
3.3V_2
70
3.3V_3
68
D4401
SUSCLK(32KHZ)
58
NC1
56
NC2
54
PEWAKE#/NC3
52
CLKREQ#/NC4
50
PERST#/NC5
48
NC6
46
NC7
44
NC8
42
NC9
40
NC10
38
DEVSLP
36
NC11
34
NC12
32
NC13
30
NC14
28
NC15
26
NC16
24
NC17
22
NC18
20
NC19
18
3.3V_4
16
3.3V_5
14
3.3V_6
12
3.3V_7
10
DAS/DSS#/LED1#
8
NC20
6
NC21
4
3.3V_8
2
3.3V_9
76
MTG1
78
MTG3
80
MTG5
82
MTG7
84
MTG9
86
MTG11
88
MTG13
90
MTG15
92
MTG17
M1108459-002
C4417
10p
A K
GND
PESD3V3U1UL315
SSD_RESET_N PCIE_SSD_TP0_F
D4422
PESD5V0H1BSF
K1 K2
GND
PEDET(NC-PCIE/GND-SATA)
Connector Key
NO PINS
PETP0/SATA-A+
PERP0/SATA-B-
PERN0/SATA-B+
PETN0/SATA-A-
GND1
GND2
GND3
NC22
GND4
REFCLKP
REFCLKN
GND5
GND6
GND7
PETP1
PETN1
GND8
PERP1
PERN1
GND9
PETP2
PETN2
GND10
PERP2
PERN2
GND11
PETP3
PETN3
GND12
PERP3
PERN3
GND13
GND14
MTG2
MTG4
MTG6
MTG8
MTG10
MTG12
MTG14
MTG16
75
73
71
69
67
57
55
53
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
77
79
81
83
85
87
89
91
PCIE_SSD_TX2_DN[24]
PCIE_SSD_TX2_DP[24]
PCIE_SSD_TX3_DN[24]
PCIE_SSD_TX3_DP[24]
R4417 0
PCIECLK_SSD_P_C
PCIECLK_SSD_N_C
PCIE_SSD_RP0_C
PCIE_SSD_RN0_C
PCIE_SSD_RP2_C
PCIE_SSD_RN2_C
PCIE_SSD_RP3_C
PCIE_SSD_RN3_C
D4402
D4420
PESD5V0H1BSF
PESD5V0H1BSF
K1 K 2
K1 K 2
+3P3VAS_SIL
PCIE_SSD_RP1_C
PCIE_SSD_RN1_C
D4403
PESD5V0H1BSF
K1 K 2
C4410 0.22u
C4415 0.22u
C4405 0.22u
C4409 0.22u
R4419
1M
0201
1%
DET_A# [58]
D4404
PESD5V0H1BSF
PESD5V0H1BSF
K1 K 2
K1 K 2
D4405
PESD5V0H1BSF
K1 K 2
D4406
PESD5V0H1BSF
K1 K 2
D4407
D4408
PESD5V0H1BSF
PESD5V0H1BSF
K1 K 2
K1 K 2
PCIE_SSD_TN2_C
PCIE_SSD_TP2_C
PCIE_SSD_TN3_C
PCIE_SSD_TP3_C
D4410
D4409
PESD5V0H1BSF
K1 K 2
D4411
PESD5V0H1BSF
PESD5V0H1BSF
K1 K 2
K1 K 2
D4412
PESD5V0H1BSF
K1 K 2
D4413
PESD5V0H1BSF
K1 K 2
D4414
PESD5V0H1BSF
K1 K 2
D4415
PESD5V0H1BSF
K1 K 2
RN4404 0DNP
RN4401 0DNP
D4416
PESD5V0H1BSF
K1 K 2
2
3
L4401
2 3
1 4
2
3
2 3
1 4
D4417
PESD5V0H1BSF
K1 K 2
L4405
D4418
1
DLP11TB800UL2L
4
1
DLP11TB800UL2L
4
R4408 0
R4415 0
R4402 0
R4409 0
R4403 0
R4401 0
R4410 0
R4411 0
R4404 0
R4405 0
D4419
PESD5V0H1BSF
K1 K 2
R4418 0
D4423
PESD5V0H1BSF
K1 K 2
PCIE_SSD_TN2_F
PCIE_SSD_TP2_F
PCIE_SSD_TN3_F
PCIE_SSD_TP3_F
PCIECLK_SSD_P_F
PCIECLK_SSD_N_F
PCIE_SSD_TN0_F
PCIE_SSD_TP1_F
PCIE_SSD_TN1_F
PCIE_SSD_TP2_F
PCIE_SSD_TN2_F
PCIE_SSD_TP3_F
PCIE_SSD_TN3_F
PCIE_SSD_RX0_DP [24]
PCIE_SSD_RX0_DN [24]
PCIE_SSD_RX1_DP [24]
PCIE_SSD_RX1_DN [24]
PCIE_SSD_RX2_DP [24]
PCIE_SSD_RX2_DN [24]
PCIE_SSD_RX3_DP [24]
PCIE_SSD_RX3_DN [24]
+3P3VAS_SIL
R4420
1M
0201
1%
DET_B# [58]
GND
GND
A A
M.2 SSD CONNECTOR
M.2 SSD CONNECTOR
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Title:
Engineer:
Engineer:
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
1
M.2 SSD CONNECTOR
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
44 82Tuesday, May 21, 2019
44 82Tuesday, May 21, 2019
44 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 45
5
E E
USB3_USBA_TX_DN[24]
USB3_USBA_TX_DP[24]
USB3_USBA_RX_DN[24]
D D
USB3_USBA_RX_DP[24]
USB2_USBA_DN[24]
USB2_USBA_DP[24]
4
10V
C4504 0.1u
C4526 0.1u
10V
90 Ohm, Differential Pair
+3P3VSB
R4510
10K
U4503
USBA_OVCUR#[24]
USBA_EN[10]
USB3_USBA_TX_DN_C USB3_USBA_TX_DN_CONN
USB3_USBA_TX_DP_C
R4501
499K
ALL
GND
GND
R = 11.5 K
I(Max) = 2.05 A
I(Typ) = 1.78 A
I(Min) = 1.5 A
U4503 Min VIH = 1.2V
0nH
142
FLAG#3IN
4
EN
5
OUT
GND1
7
ILIM
GND2
NCP380HMUAJAATBG
3
L4506
R4520
11.5K
0201
1%
6
1
2
B1
C4514
10u
10V
GND
C4505
0.1u
10V
GND
USB2_USBA_DN_CONN[76]
USB2_USBA_DP_CONN[76]
D4503
DP_OA1
DM_O
USB3_USBA_TX_DP_CONN
+5VSB
C4507
0.1u
10V
GND
GND
GND
DP_I A2
DM_I B2
ID
GND
90 Ohm, Differential Pair
CON2_VBUS
+
C4517
150u
A K
GND
C2
90 Ohm, Differential Pair
C1
3
R4536
E1 E2
D4504
GND
PMTP4504
SENS
I1 I2
LOAD
DBG_S
GND
GND
PMTP4503
0.01
J4501
1
VBUS
2
Dm
3
Dp
4
GND
5
StdA_SSRXm
6
StdA_SSRXp
7
GND_DRAIN
8
StdA_SSTXm
9
StdA_SSTXp
M1015489-005
MTG12
MTG11
MTG10
MTG9
MTG8
MTG7
MTG6
MTG5
MTG4
MTG3
MTG2
MTG1
21
20
19
18
17
16
15
14
13
12
11
10
GND
2
1
C C
B B
D4509
PESD5V0H1BSF
K1K 2
K1K 2
D4510
PESD5V0H1BSF
GND
K1K 2
D4511
PESD5V0H1BSF
K1K 2
D4512
PESD5V0H1BSF
A A
USB3.0 Port
USB3.0 Port
USB3.0 Port
Title:
Title:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
1
Title:
Engineer:
Engineer:
Engineer:
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
1.00
1.00
1.00
45 82Tuesday, May 21, 2019
45 82Tuesday, May 21, 2019
45 82Tuesday, May 21, 2019
<OrgName>
<OrgName>
<OrgName>
Size Project Name Re v
Size Project Name Re v
Size Project Name Re v
A1
A1
A1
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Page 46
5
D D
4
3
2
1
DNP
+3P3V
R4602
100K
0201S_P28-W35
0.1u
GND
SL_AUX_DP [71]
SL_AUX_DN [71]
R4605
100K
0201S_P28-W35
+3P3V +3P3V
R4606
2.2K
0201S_P3
C C
B B
SLDP_CTRL_CLK[10]
SLDP_CTRL_DATA[10]
TS3USB30E
EN
L AUX for DP [D1 to D]
L
H
S
L
H
X
Connection
DDC for HDMI [D2 to D]
HI-Z
R4607
2.2K
0201S_P3
SL1_CONFIG1[71]
U4601
TS3USB30E
0201S_P33-W39
SLDP_AUX_DP[10]
SLDP_AUX_DN[10]
C4605
0.1uF
25V
GND
0201S_P35-W35
C4603 0.1u
0201S_P33-W39
C4602 0.1u
+3P3VSB
R4601 10K
0201S_P28-W35
10V
10V
DNP
SL1_DP_EN
R4616
0
0201S_P28-W35
GND
qfn10_1p8x1p4xp55_p4mm
D1+
D2+
D1D2-
S
OE
VCC
GND
1
2
7
6
10
8
D+
D-
9
3
5
4
GND
+3P3VSB
C4608
0.1u
0201S_P33-W39
GND
10V C4601
C4604
0.1u
DNP
GND GND
A A
DP Dongle Control
DP Dongle Control
Title:
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A4
A4
A4
W x H 337 x 218 mm
Date: Sheet of
Date: Sheet of
5
4
3
Date: Sheet of
2
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
DP Dongle Control
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
46 82Tuesday, May 21, 2019
46 82Tuesday, May 21, 2019
46 82Tuesday, May 21, 2019
1
1.00
1.00
1.00
Page 47
5
D D
4
3
2
1
C C
B B
A A
mDP
mDP
Title:
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
W x H 392 x 254 mm
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
mDP
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
47 82Tuesday, May 21, 2019
47 82Tuesday, May 21, 2019
1
47 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 48
5
E E
D D
4
3
2
1
C C
B B
A A
<Core Design>
<Core Design>
<Core Design>
uSD
uSD
uSD
This drawing contains information which is proprietary of Microsoft C orporation. T his drawing is rec eived
This drawing contains information which is proprietary of Microsoft C orporation. T his drawing is rec eived
This drawing contains information which is proprietary of Microsoft C orporation. T his drawing is rec eived
in confidenc e and its conte nts may not be d isclosed without the prior written c onsent of Mic rosoft Co rp.
in confidenc e and its conte nts may not be d isclosed without the prior written c onsent of Mic rosoft Co rp.
in confidenc e and its conte nts may not be d isclosed without the prior written c onsent of Mic rosoft Co rp.
Date:
Tuesday, May 21, 2019 <OrgName>
Date:
Tuesday, May 21, 2019 <OrgName>
Date:
5
4
3
2
Tuesday, May 21, 2019 <OrgName>
1
Engineer:
Engineer:
Engineer:
Sheet of
48 82
Sheet of
48 82
Sheet of
48 82
Rev
Rev
Rev
Page 49
5
D D
4
3
2
1
C C
B B
A A
Title:
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
W x H 402 x 260 mm
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
Camera IR
Camera IR
Camera IR
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
1
2.89.6
2.89.6
2.89.6
49 82Tuesday, May 21, 2019
49 82Tuesday, May 21, 2019
49 82Tuesday, May 21, 2019
Page 50
5
LAYOUT NOTE:
WIFI*D50 and WIFI*S50 routed with impedance control
Non-50-Ohm Sy stem -> Follo w Intel Layo ut
BT ON CHA LB
U5001C
A17
D D
B15
B16
C16
E16
F15
G14
D15
HrP_MS_WIFI_CHA
VSS_WIFI_TX_PA_CHA_1
VSS_WIFI_TX_PA_CHA_2
VSS_WIFI_TX_PA_CHA_3
VSS_WIFI_TX_MX_CHA
VSS_WIFI_RX_CHA_1
VSS_WIFI_RX_CHA_2
VSS_WIFI_RX_CHA_3
VSS_WIFI_ADC_CHA
AX-WCS22560 B3
M1072227-003
WIFI_HB_RF_CHA_P
WIFI_HB_RF_CHA_N
WIFI_LB_BT_CHA_P
WIFI_LB_BT_CHA_N
VDD1V8_WIFI_TX_MX_CHA
VDD1V8_WIFI_TX_PA_CHA
VDD1V8_WIFI_RX_CHA
VDD1V8_WIFI_ADC_CHA
3 OF 8
WIFI_HB_CHA_P_D50 WIFI_HB_CHA_S50
A15
WIFI_HB_CHA_N_D50
A16
WIFI_LB_CHA_P_D50
C17
WIFI_LB_CHA_N_D50
D17
B14
B17
F17
E12
+1P8V_RADIO +1P8V_RADIO
C5001
2.2u
20%
X892237-001
C5002
2.2u
4V
C5045
100p
2
3
LDM155G4205FC009
2
3
LDM152G4505FC011
L5001
B2
GND
B3
M1045933-001
L5002
B2
GND
B3
M1045932-001
UB1
UB1
4
1
4
WIFI_LB_CHA_S50
1
4
WiFi Harrison Peak
U5003
1
H-BAND
5
CMN-PORT
3
L-BAND
2
GND2
4
GND4
6
C5047
0.2pDNP
GND6
LFD212G45DS8D893
M1064609-001
3
2
Filters and switches need to be reviewed by RF team and ME
J5003
C5003
0.2pDNP
R5006 0
0201
C5048
0.2pDNP
D5005
A1A2
GND
DIO_0402_P33MM-AA
X935756-001
LXES15AAA1-153
CONN_COAX_4_2P1X2X1P0MM
WIFI_DIPLEX_CHA_D_S50 W IFI_CHA_ANT1_S50
1
PROBE
GND44GND3
X867338-001
OUT2IN
3
CR5002
SIG
GND 2,3,4
Right antenna connector
U5001B
AX-WCS22560 B3
M1072227-003
TP5013
0402 Single Pad
HrP_MS_BT
VDD1V8_BT_OTA_BIAS
VDD1V8_BT_RF
VSS_BT_PA
VSS_BT_1
VSS_BT_2
2 OF 8
CONN_COAX_4_2P1X2X1P0MM
BOT_COAX_NET
1
J5001 added for bottom side study
GND44GND3
X867338-001
DNP
1
+1V8_HRP_PMU_GPIO_LDO_OUT
C5019
10%
C5021
22u
6.3V20%
0603
X869827-001
0.1u
L5007
1800Ohm@100MHz
0402
M1045895-001
+1P8V_RADIO
J16
+1P8V_WIFI_FLTR
H17
G16
H15
K15
J5001
PROBE
OUT2IN
3
C5020
0.1u
10%
6.3V
X811795-001
U5001D
A1
A4
B2
B3
C2
E2
F3
C C
D3
HrP_MS_WIFI_CHB
VSS_WIFI_TX_PA_CHB_1
VSS_WIFI_TX_PA_CHB_2
VSS_WIFI_TX_PA_CHB_3
VSS_WIFI_TX_PA_CHB_4
VSS_WIFI_TX_MX_CHB
VSS_WIFI_RX_CHB_1
VSS_WIFI_RX_CHB_2
VSS_WIFI_ADC_CHB
AX-WCS22560 B3
M1072227-003
WIFI_HB_RF_CHB_P
WIFI_HB_RF_CHB_N
VDD1V8_WIFI_TX_MX_CHB
VDD1V8_WIFI_TX_PA_CHB
VDD1V8_WIFI_RX_CHB
VDD1V8_WIFI_ADC_CHB
4 OF 8
WIFI_LB_CHB_P
WIFI_LB_CHB_N
Confirm CNV strapping for ICL-HrP only
B B
BT_DISABLE#[24 ,33]
WLAN_DISABLE#[24,33]
A A
+3P3V_WW AN_RADIO +3P3V_W WAN_RADIO
R5001
130K
DNP
R5005
130K
DNP
R5004 0
BT_KILL_R WIFI_DIG_I2C_SDA
R5003 0
REFCLK not used by ICL-HrP
TP5004
Non-50-Ohm Sy stem -> Follo w Intel Layo ut
LDM155G4205FC009
LDM152G4505FC011
+1P8V_RADIO
C5042
100p
DIG_RF_RESET_B
DIG_I2C_ALERT_B
DPHY_WGR_CLK_P
DPHY_WGR_CLK_N
DPHY_WGR_D0_P
DPHY_WGR_D0_N
DPHY_WGR_D1_P
DPHY_WGR_D1_N
DPHY_WT_CLK_P
DPHY_WT_CLK_N
DPHY_WT_D0_P
DPHY_WT_D0_N
DPHY_WT_D1_P
DPHY_WT_D1_N
L5003
2
B2
3
B3
M1045933-001
L5004
2
B2
3
B3
M1045932-001
DIG_BRI_DT
DIG_BRI_RSP
DIG_RGI_DT
DIG_RGI_RSP
DIG_CLKREQ0
DIG_CLKREQ1
DIG_I2C_SCL
DIG_I2C_SDA
WIFI_HB_CHB_P_D50 WIFI_HB_CHB_S50
A3
WIFI_HB_CHB_N_D50
A2
WIFI_LB_CHB_P_D50
C1
WIFI_LB_CHB_N_D50
D1
B4
B1
F1
E6
+1P8V_RADIO
20%4V
U5001H
P3
POWER_GOOD
DIG_VPP_OTP
L2
DIG_SPI_DI
DIG_SPI_CLK
H3
DIG_SPI_DO
T6
DIG_SPI_CS_B
K3
DIG_GPIO0
VDD1V8_PLL_REFCLK
BT_RFKILLN
J9
WIFI_RFKILLN
DIG_BT_LED
WIFI_LED
DIG_REFCLK0
DIG_REFCLK1
P4
VDD1V0_DIG_1
P8
VDD1V0_DIG_2
U9
VSS_DPHY
J6
VSS_DIG_1
VSS_DIG_2
VSS_DIG_3
VSS_DIG_4
VSS_DIG_5
U3
VSS_DIG_6
U5
VSS_DIG_7
V2
VSS_DIG_8
VSS_DIG_9
U7
VSS_DIG_10
AX-WCS22560 B3
M1072227-003
C5010
C5011
2.2u
2.2u
HrP_MS_JFP DIGITAL
8 OF 8
+1P8V_RADIO
TP5007
WLAN_KILL_R
WIFI_DIG_REFCLK0
+1P1V_RADIO
C5038
100p
25V
5%
X813058-001
C5009
2.2u
X892237-001
M15
M3
M9
K17
L16
J12
M17
N16
P15
U11
U13
U15
Y15
1
UB1
4
GND
WIFI_LB_CHB_S50
1
UB1
4
GND
U5001A
HrP_MS_GNSS
VDD1V6_LNA_GNSS_LDO_VOUT
1 OF 8
AX-WCS22560 B3
M1072227-003
T9
CNV_BRI_RSP_HRP
P10
N2
CNV_RGI_RSP_HRP
P1
M12
K14
K10
WIFI_DIG_I2C_ALERT_B
M6
WIFI_DIG_I2C_SCL
K4
K8
Y9
V10
Y11
V12
Y13
V14
Y3
V4
Y5
V6
Y7
V8
U5004
3
HB
5
COMM
1
LB
2
GND_2
4
GND_4
6
GND_6
LFD212G45DS9D894
C5051
M1064610-001
0.2pDNP
+1P8V_RADIO
K1
GNSS_RF_IN
H1
VDD1V8_GNSS
CNV_RF_RESET_R#
TP5001
TP5002
TP5003
LNA_EN
TP5016
R5007
0
CNV_BRI_DT [23 ]
CNV_BRI_RSP [23]
CNV_RGI_DT [ 23]
CNV_RGI_RSP [23]
TP5005
TP5006
CNV_WT_CLK_DP_D100 [23]
CNV_WT_CLK_DN_D100 [23]
CNV_WT_D0_DP_D100 [23]
CNV_WT_D0_DN_D100 [23]
CNV_WT_D1_DP_D100 [23]
CNV_WT_D1_DN_D100 [23]
LAYOUT NOTE:
CNV*D100 nets routed as 85 -Ohm differe ntial pairs
R5002
75K
MODEM_CLKREQ [20,33]
M1
J2
VSS_GNSS_RF
G2
VSS_GNSS_MS
R5010 22
R5011 22
CNV_WR_CLK_DP_D100 [23]
CNV_WR_CLK_DN_D100 [23]
CNV_WR_D0_DP_D100 [23]
CNV_WR_D0_DN_D100 [23]
CNV_WR_D1_DP_D100 [23]
CNV_WR_D1_DN_D100 [23]
LAYOUT NOTE:
PLACE CNV_WT* TPS NEAR U50 01;
Stubbs should be minimized and limited to just a VI A for access
Consider remo ving CNV_WT* TPs in later builds
C5013
0.2pDNP
U5001F
AX-WCS22560 B3
M1072227-003
CLKREQ used for init
CNV_RF_RESET# [20,33]
C50445.6p
C5004
0.2pDNP
DIO_0402_P33MM-AA
X935756-001
LXES15AAA1-153
HrP_MS_WIFI_TMUX
WIFI_LB_EPA_DET_CHA_TM1_P
WIFI_HB_EPA_DET_CHA_TM1_N
WIFI_LB_EPA_DET_CHB_TM2_P
WIFI_HB_EPA_DET_CHB_TM2_N
WIFI_ADC_ANATST_CLK
VDD1V8_WIFI_OTA
6 OF 8
+3P3V_WW AN +3P3V_WW AN_RADIO
WIFI_PROBE_CHB_S50
GND
L5012
30 OHM
0402
2.2A
CONN_COAX_4_2P1X2X1P0MM
D5006
A1A2
B10
A9
A14
B12
G10
E9
C5018
10u
25V
0805
GND GND
10%
1
PROBE
GND44GND3
X867338-001
0201
J5004
OUT2IN
3
+1V8_HRP_PMU_GPIO_LDO_OUT
C5035
0.01u 10%
25V
WIFI_CHB_ANT1_S50
WIFI_ CHB_ANT2 W IFI_CHB _ANT4
R5017 0
0402
R5016 0
L5011
0.5p
0402
DNP
GND GND
WIFI_ CHB_ANT3
L5010
0.6pF
0402
DNP
R5015 0
0402
MP5004
1
M1075199-001
FCAOS14B02G1PC
MP5005
1
M1075199-001
FCAOS14B02G1PC
GND
MP5006
1
M1075199-001
FCAOS14B02G1PC
GND
Left antenna spring clip
R5014 200
U5001E
HrP_MS_XTL/SYNT/BG/NTC
C9
VSS_XTL
D10
VSS_WIFI_SYNT_DPLL_VCO
D8
VSS_WIFI_SYNT_DPLL_RING
C8
VSS_WIFI_SYNT_DPLL_TDC
G8
VSS_WIFI_BG
AX-WCS22560 B3
M1072227-003
U5001G
T17
VSS_PMU_SD1V8
T15
VSS_PMU_SD1V8_ISO
T1
VSS_SD1V1
T3
VSS_SD1V1_ISO
AX-WCS22560 B3
M1072227-003
+3P3V_WWAN
3.3V +/- 0.165V
200 mVPP, 10-500kHz
300 mVpp -- allowed power rail noise
TRISE (0-3.3V) < 10mSec
RISING EDGE SHALL BE WITHOUT GLITCHES OR STEPS
RIPPLE SHALL NOT DIP MORE THAN 0.3V; OTHERWISE MAY BE INTERPRETED AS POR
VDD1V8_WIFI_SYNT_DPLL_CORE
5 OF 8
HrP_MS_PMU
VDD1V8_PMU_GPIO_LDO_OUT
7 OF 8
XTL_X1
XTL_X2
XO_SENS
VDD1V8_XTL_LDO
VDD1V8_WIFI_BG
VDD_VBAT_1V8_PMU
VDD_VBAT_PMU_SD1V8
PMU_SD1V8_LX1_1
PMU_SD1V8_LX1_2
PMU_SD1V8_FB
VDD_VBAT_SD1V1
SD1V1_LX1_1
SD1V1_LX1_2
SD1V1_FB
PMU_CLK_32K_IO
VDD3V2_PMU_FEM_CLDO
WIFI_XTAL_X1 WIFI_XTAL_X1_R
A7
WIFI_XTAL_X2
B8
B6
C10
G4
A11
+3P3V_WW AN_RADIO
P17
U16
V17
Y17
R16
U2
+1P1V_RADIO_LX
V1
Y1
R2
V16
T12
P14
C5022
2.2u
20%4V
X892237-001
C5024
10u
20%6.3V
0603
X859524-001
+1V8V_RADIO_LX
L5009
1uH
M1008872-001TP5008
2 4
TP5011
Y5001
31
GND
M1073240-001
60MHz
3225
+1P8V_RADIO
C5023
4.7u
LAYOUT NOTE:
10%6.3V
0603
X809153-001
20.57mOhm
2.7A
L5008
C5040
100p
1uH
M1008872-001
2016
+1V8_HRP_PMU_GPIO_LDO_OUT
C5026
1u
0402
X868173-001
10%10V
TP5010
+1P8V_RADIO
C5041
100p
25V
5%
X813058-001
J5007
FCAOS08A07G1PC
1
TP5012
J5005
FCAOS08A07G1PC
1
GND GND GND
PLACE C5022 at A11
PLACE 4.7UF C5023 as close as possible to A11
+1P8V_RADIO_CAP
C5028
4.3u 0402
2.5V20%
M1064905-001
2
1 3
+1P1V_RADIO
C5030
22u
0603
X869827-001
R5013
150K
DNP
1 3
TP5009
20%6.3V
SUSCLK [20]
J5006
FCAOS08A07G1PC
1
C5025
4.7u 0402
20%6.3V
X855058-001
C5029
4.3u
2
+3P3V_WW AN_RADIO
C5027
10u
X859524-001
Wi-Fi_BT Coex
Wi-Fi_BT Coex
Wi-Fi_BT Coex
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Re v
Size Project Name Re v
Size Project Name Re v
A1
A1
A1
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
Title:
Engineer:
Engineer:
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
1.00
1.00
1.00
50 82Tuesday, May 21, 2019
50 82Tuesday, May 21, 2019
50 82Tuesday, May 21, 2019
Page 51
5
D D
4
3
2
1
C C
B B
A A
Empty
Empty
Title:
Title:
Title:
Engineer:
Engineer:
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
W x H 377 x 244 mm
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Empty
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
1
1.00
1.00
1.00
51 82Tuesday, May 21, 2019
51 82Tuesday, May 21, 2019
51 82Tuesday, May 21, 2019
Page 52
5
D D
4
3
2
1
C C
B B
A A
Camera power
Camera power
Title:
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
W x H 387 x 250 mm
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
Camera power
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
52 82Tuesday, May 21, 2019
52 82Tuesday, May 21, 2019
1
52 82Tuesday, May 21, 2019
2.89.6
2.89.6
2.89.6
Page 53
5
D D
4
3
2
1
C C
B B
Place close to pin 23,25
A A
Blank
Blank
Title:
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
W x H 437 x 328 mm
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
Blank
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
1
2.89.6
2.89.6
2.89.6
53 82Tuesday, May 21, 2019
53 82Tuesday, May 21, 2019
53 82Tuesday, May 21, 2019
Page 54
5
4
3
2
1
Sensor Connector to IR and RGB Cameras, Left and Right Microphones, and ALS Sensor
+1P8VSB
+VSYS
ALL
C5407
0.1u 6.3V
0201
U5404
74AUP1G08GX
VCC
2
A
1
B
GND
0
R5409
DNP
C5413
10u 6.3V
0402
IRLED_A_P[54,76]
Place
C54003 near
connector
+1P8VSB
CAM_IR_STB[5 4,76]
R5406
137K
DNP
D D
R5407
165K
DNP
GND
+3P3VSB
RTD3_CAM_PW REN[25,76]
C5404
1u
GND
C C
CAM_USB_DP_SOC[24]
CAM_USB_DM_SOC[24]
R5404 0
U5402
A2
B2
NX3P1108UK
2
3
VIN
EN
L5402
VOUT
GND
23
14
RN54010 DNP
1
0nH 2.5GHZ
4
GND
+3P3V_CAM_OUT
C5406
0.1u
GND
K1K2
D5401
PESD5V0H1BSF
GND
K1K2
D5404
PESD5V0H1BSF
+5VSB
Q5401A
CAM_USB_DP
CAM_USB_DM
R5418
10K
0201
2
120 Ohm 100MHz
+1P8VA
C5401
0.1u
Q5401B
5
6
L5404
CAM_IR_STB[54,76]
34
R5417 3.48K
Place close to pin 23
1.3A
0402
PCH_SENSOR_I2C_SDA[25,76]
PCH_SENSOR_I2C_SCL[25,76]
CHIMERA_DET_B#[58]
0402
PCH_SENSOR_I2C_SDA
PCH_SENSOR_I2C_SCL
A1
B1
RGB_LED_EN[54]
C5411
0.1u
10V
5
4
Y
3
CAM_IR_STB_1.8V
6.3V
C5405 1u
R5414 10K
0201S_P35-W35
GND GND
Layout Note: J54001 Pin 1 and Odd Pins along North Edge
IRLED_A_P
C5403
0.1u 6.3V
0201
R5402 0
R5403 0 R5430 1K
SEN_HALL_INT#_N[34,76] RGB_LED_EN [54]
RGB_LED_A_P [76]
R5428
100K
1%
0201
DNP
CHIMERA_DET_CON_B #
GND
R5429
100K
Pullups for I 2C are on th e Camera Fle x.
1%
0201
DNP
L5407 220 OHM
0805S_1P1
AK
D5402
RB520CS3002L
DNP
0201S_P28-W35
CAM_IR_STB_ERR_INM
R5421 220K
R5426 4.99K
0201S_P28-W35
CAM_IR_STB_ERR_INP
DNP
0201S_P28-W35
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
2A
0201S_P26
R5425 150K
CAM_IR_STB_ERR_REF
J5401
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
DF40C-30DS-0.4V
R5410 2.05K
U5401
TLV3011
SC70-6_2X1P25X1P1_P65MM-2
4
IN-
5
REF
IN+3V-
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
CHIMERA_23
23
23
CHIMERA_25
25
25
27
27
29
29
GND
CAM_IR_LED_IN
C5416
C5409
10u 16V
0.1u 16V
0603S_1-W 100
0201S_P33
GND GND
CAM_IR_STB_R
CAM_IR_STB_R [76]
+3P3V
6
V+
CAM_IR_STB_ERR
1
OUT
2
GND
3P3_CAM [76]
IRLED_C_N
CHIMERA_DET_CON_A #
R5431 0R5412 0
R5432 0ALL
C5402
0.1u
10V
0201S_P33-W39
GND
R5416 0
1
GND
ALS 7-bit I2C Address = 0x44
C5410 0.01u
25V
0201S_P33
U5403
IR_BST
6
BST
2
IN
3
EN
MP2370DG-Z
R5413 49.9K
0201S_P28-W35
GND
R5415
0
0201S_P28-W 35
SEN_HALL_INT#_S [34,76]
IRLED_C_N [54,76]
CHIMERA_DET_A# [58]
DMIC_DATA1_CODEC [40,76]
DMIC_CLK_CODEC [40,76]
ISP_FW_LOC K# [20 ]
ACS_INT# [ 25]
TDM_DET [35]
+1P8VSB
R5434
100K
ACS_INT#
1
SW
4
FB
5
GND
7
EPAD
GND
+3P3VSB
R5405
100K
DNP
ISP_FW_LOC K#
R5411
100K
L5401 4.7uH100KHz
IR_SW IR_OUT
IR_FB
IND_2P5X2X1_1P9MM
D5403
1000mA
NSR10F30NXT5G
30V
A K
GND
DIO_DSN2_1P45XP65XP31
R5420 100K
0201S_P28-W 35
IR_FB_R
DNP
0201S_P33
GND GND
1.5A
C5414
0.01u
0201S_P33
10V
GND GND GND
R5423
C5418
7.5K
220p
0201S_P3-W 35
25V
0402S_P7-W70
R5419 1K
0201S_P28-W 35
C5408
4.7uF
10V
DNP
C5419
0201S_P33
IRLED_A_P [54,76]
10p
50V
1/20W
R5401 1K
0201S_P28-W35
GND
R5408
0.25
1206S_P7
0.5W
GND
IRLED_C_N [54,76]
B B
Check with Camera/RF/Power team for regulation, filtering, and component info
Power regulation, Privacy LED and sensors moved locally on
sensor board. IRLED Buck regulation local to mb
Odd side of the J54001 connector faces the North edge of the PCB
A A
Camera Front
Camera Front
Camera Front
Title:
Title:
Title:
<OrgAddr1>
<OrgAddr1>
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A2
A2
A2
EDAN_A_EV1
EDAN_A_EV1
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
W x H 392 x 254 mm
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
1
<OrgAddr1>
2.89.6
2.89.6
54 82Tuesday, May 21, 2019
54 82Tuesday, May 21, 2019
54 82Tuesday, May 21, 2019
2.89.6
Page 55
+VSYS
5
4
3
2
1
+V_ALWAYS_ON
Iin=0.28A
Trace Width>30mil
+V_ALWAYS_ON
D5502
A K
D D
40V
RB520CS3002L
DBG_S
R5521 0.02
0603S_P6-W100
+V_ALWAYS_ON
C5506
0.1uF 25V
0201S_P35-W35
GND
Effective Capacitance
2.2uF_0.55mm => @15V=0.255uF
2.2uF_0.55mm => @20V=0.194uF
22 uF_1.45mm => @20V =2.566uF
100K
PWR_SL1_F
D5507
40V
A K
RB520CS3002L
0201S_P28-W35
C C
SL1_PWR_GOOD[70]
+VBUS_P0_CONN
D5504
40V
A K
RB520CS3002L
B B
A A
PWR_SL1_F_S
R5517
100K
5
GND
R5518
249K
DNP
C5510
0.01u 25V
0201S_P33
GND
TRA-P CNL,SM,DFN1010D-3,120 mOHM,30 V,2.
Q5507A
DNP
C5509
0.1u
10V
0201S_P33-W39
Q5505
S
S
PWR_SL1_F_S_DRI
2
61
GND
D
G
G
R5516
200K
0201S_P3
D2
D1
34
5
Q5507B
GND
BAT_LDO[70]
4
R5501
MODE
FLOAT PFM/PWM
PU PWM
D5501
A K
RB520CS3002L
200mA
+3P3VAS
D5503
A K
RB520CS3002L
VCCRTC_RST[35]
R5503 499
10V
20%
3P3VA_GND 3P3VA_GND 3P3VA_GND 3P3VA_GND3P3VA_GND
R5502 1.5K
C5507
10u
25V
0805S_1P2
GND
INT_LDO_5VCC
C5520
1u
+3P3VAS_BATLDO
VCCRTC_RST_R
GND GND
DNP
R5532
1K
C5511
0.1u
10V
DNP
0201S_P33-W39
GND
R5504
100K
0201S_P28-W35
2
1
4
6
7
11
5
12
8
3
GND
R5508
0
D
G
Q5501
S
SOTFL-3_1P3XP9XP55_P4
U5501
VIN1
MODE
EN
PG
BIAS
VCC
NC
AGND
PGND-8
PGND-3
MP2269GD-Z
3
SW
BST
FB
FRQ
SS
+VCC_RTC
R5522
200K
0201S_P3
DNP
GND
+3P3VAS_SW
9
+3P3VAS_BST
10
+3P3VAS_FB
14
15
13
+3P3VAS_FREQ
+3P3VAS_SS
+VCC_RTC
Imax=0.0002A
25V
3P3VA_EN[58]
IND,PMC,6.8uH,330mOhm,1.2A,SM,3.2X2.5X1.
L5501 6.8uH
C5512
1u
12n
GND
C5503
1u
C5513
5.6p
R5515
165KC5521
+3P3VAS
+3P3VAS
R5514
1M
R5510
324K
R5529
100K
0201S_P28-W35
DNP
3P3VA_EN
R5530
100K
0201S_P28-W35
C5505
22u 10V
0603S_1-W100
GND GND
C5508
22u 10V
0603S_1-W100
fs = 86500/(R+6.5)
500KHz
+3P3VAS
R5506 0
+3P3VAS
2
3P3VA_GND GND
C5501
0.1u 10V
0201S_P33-W39
C5523
0.1u 10V
0201S_P33-W39
R5507
0201 SHUNT
GNDGND
GNDGND
DBG_S
R5512 0.1
0603S_P65-W95
12
C5502
1u 6.3V
GND
0201S_P35-W35
U5506
A2
VIN
B2
EN
NX3P1108UK
C5522
1u 6.3V
GND
0201S_P35-W35
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
W x H 447 x 289 mm
Date: Sheet of
Date: Sheet of
Date: Sheet of
PMTP5503
SP-TP-C0P381
U5505
4
VOUT
VIN
3
EN
2
GND
EPAD
NCP170AMX180TCG
A1
VOUT
B1
GND
U5502
4
VOUT
VIN
3
EN
2
GND
EPAD
NCP170AMX180TCG
Custom
Custom
Custom
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
1
5
GND
+3P3VA_REG
GND
1
5
GND
PMTP5504
SP-TP-C0P381
1P8VA_REG
GND
1P8VAS_REG
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
+3P3VAS
Imax<=0.175A
TP5501
C5518
10u 10V
0603S_1-W100
GND
C5504
0.1u
C5524
10u 10V
0603S_1-W100
GND
VA AND VCCRTC
VA AND VCCRTC
VA AND VCCRTC
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
1
DBG_S
R5520 0.1
0603S_P65-W95
+1P8VA
Imax=0.08A
R5505 0.1
DBG_S
PTP5502
+3P3VA
Imax=0.01A
DBG_S
R5533 0.1
0603S_P65-W95
+1P8VAS
Imax=???A
55 82Tuesday, May 21, 2019
55 82Tuesday, May 21, 2019
55 82Tuesday, May 21, 2019
+3P3VA+3P3VAS
+3P3VAS
+1P8VA
PTP5501
+1P8VAS
1.00
1.00
1.00
Page 56
5
4
+5VSB
3
+VCC1.05_OUT_FET
DNP
R5606 0
2
1
+VCCSTG
D D
R5604
100K
0201S_P28-W35
DBG_D
XDP_PRESENT#[18,34]
C C
R5607 0
DBG_D
U5602
1
NC
2
A
3 4
GND
74LVC1G06GM
GND
DBG_D
VCC
NC
Y
+3P3VSB
6
5
C5605
0.1u 10V
0201S_P33-W39
DBG_D
GND
CPU_C10_GATE#[22,33,60,62]
0201S_P3
DBG_D
R5609
499K
XDP_PRESENT
R5602 0
DBG_D
+VCC1.05_OUT_FET
C5612
1u 6.3V
0201S_P35-W35
GND
C5602
0.1u 10V
0201S_P33-W39
GND GND
R5621 0.01
C5604
1u 6.3V
0201S_P35-W35
1
2
GND
R5603 0 DBG_NR5605 0
0603S_P6-W100
DBG_S
PMTP5621
SP-TP-C0P381
+VCCST_CPU
+3P3VSB
U5603
A
B
GND3Y
DBG_D
SN74AUP1G32DRYR
SON6_1P5X1P05XP6_P5-2
+VCCST_CPU
VCC
NC
6
5
4
PMTP5620
SP-TP-C0P381
C5606
0.1u 10V
0201S_P33-W39
DBG_D
GND
U5601
1
VDD
2
D1
3-4
D2
9
ON
SLG5NT1477VTR
ON IS 1.8V LOGIC
S1
S2
GND
5-6
7
8
GND
+VCCSTG_REG
C5603
1u 6.3V
0201S_P35-W35
GND
R5601 0.02
0603S_P6-W100
DBG_S
PMTP5601
SP-TP-C0P381
+VCCSTG
Imax=0.3A
PMTP5602
SP-TP-C0P381
Imax=1.2A
B B
A A
+VCCSTG
+VCCSTG
Title:
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
W x H 377 x 244 mm
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
+VCCSTG
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
1
1.00
1.00
1.00
56 82Tuesday, May 21, 2019
56 82Tuesday, May 21, 2019
56 82Tuesday, May 21, 2019
Page 57
5
4
3
2
1
EDP_I2C_SDA
EDP_I2C_SCL
EDP_FPC_DET_B#[58]
+VCC_EDP_BKLT_OUT
10V
DNP
DNP
C5725 0.1u
0201S_P33-W39
GND GND
10V
C5724 0.1u
0201S_P33-W39
+3P3V_PANEL +3P3V_PANEL
TP5704
EDP_I2C_SDA[76]
EDP_FPC_CONN_DET_B#
R57040
BKLT_FB8[72,76] BKLT_FB7 [72,76]
BKLT_FB6[72,76] BKLT_FB5 [72,76]
BKLT_FB4[72,76] BKLT_FB3 [72,76]
BKLT_FB2[72,76] BKLT_FB1 [72,76]
C5708
0.1u
10V
GND GND
MFG_SDA MFG_SCL
EDP_TXN3_R DEPROM_I2C_SCL
EDP_TXP3_R
EDP_TXN2_R
EDP_TXP2_R PANEL_BIST
EDP_TXN1_R
EDP_TXP1_R PANEL_VSYNCH
EDP_TXN0_R
EDP_TXP0_R
J5701
2
112
4
334
6
556
8
778
9
61
63
GND GND
9
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
313132
333334
353536
373738
393940
414142
434344
454546
474748
494950
515152
535354
555556
575758
595960
MT1
MT3
MT2
MT4
10
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
EDP_I2C_SCL [76]
DEPROM_RESET_N
DEPROM_TWP
DEPROM_I2C_SDA
EDP_HPD [10]
EDP_AUXP_R
EDP_AUXN_R
EDP_FPC_CONN_DET_A#
PTP5701
PTP5702
PTP5703
PTP5704
TP5705
TP5712
C5709
0.1u
10V
PANEL_LOGO [35]
R5703 0
TP5701
EDP_I2C_INT [10,76]
TCON_VENDOR_ID [24,76]
EDP_SPI_CS# [30]
EDP_SPI_INT# [30]
EDP_FPC_DET_A# [58]
RN5705A 0
RN5705B 0
L5701
3
2
0uH
ALL
1 4
2 3
ALL
4
1
DNP
TP5713
PANEL_VSYNCH [30]
+VCC_EDP_BKLT_OUT
0201S_P33-W39
0201S_P33-W39
M57C10.1u10V
M57C20.1u10V
EDP_AUX_DP [10]
EDP_AUX_DN [10]
14
23
14
23
M57L4
ALL
RN5702A0
RN5702B0
RN5703A0
RN5703B0
14
23
M57L5
R5709 0
R5710 0
RN5704A0ALL
RN5704B0
0201S_P28-W35
0201S_P28-W35
PANEL_I2C_SDA[25,33,57]
PANEL_I2C_SCL[25,33,57]
+3P3V_PANEL
U5705
B2
VIN
A2
GND
PANEL_I2C_SCL[25,33,57]
C5707
0.1u 35V
0201S_P33
EN
LD39115J18R_1p8V
X867741-001
C5712
0.1u 10V
0201S_P33-W39
D D
C C
C5728
0.1u
6.3V
C5729
1u
6.3V
GND GND
+VCC_EDP_BKLT_OUT
C5705
0.47u 50V
0805S_1P45
GND
GND GND GND
GND
+3P3V_PANEL+3P3V_PANEL +3P3V_PANEL
C5704
0.47u 6.3V
0201S_P33
C5711
0.1u 35V
0201S_P33
C5702
1u 6.3V
0201S_P35-W35
VOUT
C5706
GND
0805S_1P45
B1
A1
50V
2.2u
GND
C5727
1u
6.3V
GND GND
50V
C5719
0805S_1P45
2.2u
GNDGND
R5729
10K
DNP
+1P8V_PANEL
EDP_TX0_DN[10]
EDP_TX0_DP[10]
EDP_SPI_MISO[30]
EDP_SPI_CLK[30]
ALL
ALL
M57L3
0201S_P33-W39
EDP_TX3_DN[10]
EDP_TX3_DP[10]
EDP_TX2_DN[10]
EDP_TX2_DP[10]
EDP_TX1_DN[10]
EDP_TX1_DP[10]
M57C3 0.1u 10V
M57C4 0.1u 10V
0201S_P33-W39
0201S_P33-W39
M57C7 0.1u 10V
M57C8 0.1u 10V
0201S_P33-W39
0201S_P33-W39
M57C9 0.1u 10V
M57C10 0.1u 10V
0201S_P33-W39
M57C6 0.1u 10V
M57C5 0.1u 10V
EDP_TX3_DN_C
EDP_TX3_DP_C
EDP_TX2_DN_C
EDP_TX2_DP_C
EDP_TX1_DN_C
EDP_TX1_DP_C
EDP_TX0_DN_C
EDP_TX0_DP_C
2 3
1 4
DNP
ALL
ALL
2 3
DNP
1 4
ALL
14
RN5701A0
23
RN5701B0
ALL
M57L2
2 3
1 4
DNP
2 3
1 4
DNP
PANEL_BIST
R5716
100K
U5701
3
SCL1
4
GND
SDA1
2
VREF1
1
GND
PCA9306DQER
X867878-001
U5701_EN_1.8
1.8V logic
+1P8V_PANEL
C5701
0.1u
B B
PANEL_I2C_SDA[25,33,57]
DEPROM_PROG[21]
3.3V logic
The SCL switc h conducts i f EN is = 1 V higher than SCL1
The SDA switc h conducts i f EN is = 1 V higher than SDA1
A A
VIO(Max) = 5V
200K PU not n eeded when V REF1 = VREF2
If EN > Vref1 +0.7V => dev ice will NOT properly iso late the two sides when both sides a re high
6.3V
GND
GND
R5706
137K
R5701
165K
SCL2
SDA2
VREF2
6
5
7
8
EN
C5703
0.1u
6.3V
GND
DEPROM_I2C_SCL
DEPROM_I2C_SDA
D
G
S
GND
G
DEPROM_RESET_N_R
Q5702
DEPROM_TWP
D
Q5701
S
GND
GND
R5702 0DNP
DEPROM_RESET_N
REMOVE 0ohm to avoid resetting tcon durign programming
eDP connector
eDP connector
eDP connector
Title:
Title:
Title:
<OrgAddr1>
<OrgAddr1>
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
W x H 602 x 390 mm
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
1
<OrgAddr1>
1.00
1.00
57 76Tuesday, May 21, 2019
57 76Tuesday, May 21, 2019
57 76Tuesday, May 21, 2019
1.00
Page 58
5
+1P8VAS +1P8VAS
4
3
2
1
5
VCC
4
Y
3
GND
5
VCC
4
Y
3
GND
5
VCC
4
Y
3
GND
R5801
1K
0201S_P28-W35
DNP
+1P8VAS
+1P8VAS
+1P8VAS
+3P3VSB
C5806
0.1u
10V
ALL
C5809
0.1u
10V
ALL
C5811
0.1u
10V
ALL
1K
0201S_P28-W35
ALL
U5807
VCC
2
A
1
B
GND
74LVC1G32GX
ALL
H_THERMTRIP#_BUFF
SP_TP_SMDP58
R5819
100
0201
ALL
C5808
0.1u 10V
0201
Y
TP5805
5
4
3
C5810
0.1u
0201
10V
+1P8VAS
C5807
0.1u
10V
ALL
+1P8VAS
U5805
2
1
74LVC1G32GX
ALL
In RAFLA this Signal will be pulled "LOW" via 1K resistor
DDR_PGD_SIL[58,76]
VCCIN_AUX_PG[34,69]
+0P6V_DDR_PG[60]
PLTRST#[22]
SLG_PWRBTN#
DET_A#[44]
DET_B#[44]
SLG_PWRBTN# [76]
5
VCC
4
Y
A
B
3
GND
R5809 00201
ALL
TP5811 SP_TP_SMDP58
TP5810 SP_TP_SMDP58
TP5808 SP_TP_SMDP58
TP5803 SP_TP_SMDP58
VRM_PWRGD[34,66]
SLP_S3#[22,33,34]
R5812 00201
R5821 00201R5814
R5805 00201
R5806 00201
R5803 00201
R5844 00201
R5845 00201
R5811 00201
C5805
0.1u
10V
ALL
R5841
100K
0201
DNP
R5842
100K
0201
DNP
DEVICE_RST#[39]
+1P8VAS
R5828
100K
DNP
2
1
R5834
0402
0
H_THERMTRIP#_SIL
+1P8VAS
+1P8VAS
R5832
100K
U5810
74AUP1G08GX
2
1
U5811
A
B
74AUP1G86GX
VCC
GND
C5813
0.1u
10V
GND
5
4
Y
3
ALL
R5829 150K
GND
C5814
2.2u
3P3VA_EN_SILEGO
PIN17=PIN2*PIN12*PIN3*PIN6
SIL_SLP_S3_DRV#
SUS_PGD_SIL
VRM_PGD_SIL
DDR_PGD_SIL
SLP_3#_SIL
PLT_RST#_SIL
DET_A#_SIL
DET_B#_SIL
DEVICE_RST#_SIL
R5837
0
0201
ALL
Silego Controller
+3P3VAS_SIL
TP5807
SP_TP_SMDP58
U5801
12
SPL_3_DRV
2
SUS_PGD
10
VRM_PGD
3
DDR_PGD
6
SLP_3
20
THERMTRIP
19
PLT_RST
14
START
5
DET_A
8
DET_B
7
RST
SLG4U42544
VCORE_EN
BAT_SHUTDOWN
FORCE_OFF
START_ONESHOT
MCU_PWR_CTRL
S_DBG-MCU_DBG
SSD_LS_EN
I2C control from SAM
C5802
0.1u 10V
0201
VDD
GND
+3P3VAS
1
17
4
16
18
13
15
9
11
+3P3VAS_BATLDO
R5810
0
DNP
0201
SYS_PWGD_SIL
SSD_BATSHUTDN#_SIL
SAM_RST#_SIL
SAM_DBG_MODE_R
SSD_LS_EN_SIL
GND
R5804 00201
Both of these BOM install options
keep SSD ON during modern stdby
SLP_S4_DRV#[35,60,62]
SLP_S3_DRV#[35,58,65]
VCC
A
B
GND
R5813
0
0201
ALL
R5824 00201
R5823 0
R5820 0
+1P8VAS
C5812
0.1u
5
4
Y
3
SP_TP_SMDP58
SP_TP_SMDP58
SP_TP_SMDP58
SP_TP_SMDP58
SP_TP_SMDP58
3P3VA_EN_SILEGO
DNP
R5849 0
DNP
R5852 0
ALL
U5803 is BYPASS IN CASE WE WANT OD
10V
R5818 IS BYPASS for 3P3VA_EN_SILEGO
R5830
100K
0201
DNP
U5803
VCC
I2O
1
NC1
GND
74AUP1G07GX
DNP
R5833 0ALL
R5818 00201
DNP
ALL_SYS_PWRGD [66]
U5804
VCC
I2O
1
NC1
GND
74AUP1G07GX
TP5816
TP5812
TP5813
TP5814
TP5815
IO_PGD @ pin 4 for Skyway 3
R5816
0
0201
DNP
R5843
100K
0201
DNP
R5808 10K0201
+3P3VSB
5
4
3
5
4
3
GND
R5840
100K
0201
DNP
C5803
0.1u
0201S_P33-W39
GND
R5807
100K
0201
DNP
+1P8VAS
C5804
0.1u 10V
DNP
3P3VA_EN [55]
+VCCST_CPU+3P3VSB
10V
R5802
1K
0201S_P28-W35
DDR_PGD_SIL [58,76]
Optional BAT_SHUTDOWN# PU on pg70.
BAT_SHUTDOWN# [33,70,76]
SAM_RESET# [29,33,34,76]
BATEN_PULSE [34,70]
SAM_DBG_MODE [29]
SIL_SSD_VR_EN [65]
VCCST_PWRGD [22]
R5815
R5825
1M
1M
0201
0201
1%
CHIMERA_DET_A#[54]
CHIMERA_DET_B#[54]
D D
KIP_FPC_DET_A#[74]
KIP_FPC_DET_B#[74]
EDP_FPC_DET_A#[57]
EDP_FPC_DET_B#[57] FPC_DET_LOGIC_OVERRIDE#[33,76]
C C
1%
+1P8VAS +1P8VAS
R5817
1M
0201
1%
+1P8VAS +1P8VAS
R5826
1M
0201
1%
SP_TP_SMDP58
SLP_S3_DRV#[35,58,65]
R5822
1M
0201
1%
R5827
1M
0201
1%
TP5806
R5831
100K
U5806
2
A
1
B
74LVC1G32GX
ALL
U5808
2
A
1
B
74LVC1G32GX
ALL
U5809
2
A
1
B
74LVC1G32GX
ALL
R5831 need change back to 100K after SAM PU disable
+3P3V+VCCST_CPU
C5801
0.1u
10V
U5802
B B
H_THERMTRIP#[10]
1
74AUP1G07GX
DNP
VCC
I2O
NC1
GND
5
4
3
GND
0201S_P33-W39
DNP
GND
PWRBTN#_3V3[31,74]
A A
20160727sjs0530
title is: Silego Controller
Silego Controller
Silego Controller
Silego Controller
Title:
Title:
Title:
<OrgAddr1>
<OrgAddr1>
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
W x H 542 x 351mm
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
1
<OrgAddr1>
1.00
1.00
58 82Tuesday, May 21, 2019
58 82Tuesday, May 21, 2019
58 82Tuesday, May 21, 2019
1.00
Page 59
5
PM_5VSB_IN+ [28]
C595110u
DBG_T
R5947
47
DBG_T
+VSYS
D D
PMTP5913
PMTP5914
R5948
DBG_T
DBG_TS
R59100.0 05
0
PM_5VSB_IN- [28]
4
+5VSB_VIN
C5930
10u 16V
C5922
10u 16V
C5921
0.1u 16V
3
2
1
+5VSB
Imax=7.5A
10
9
13
12
3
2
4
5
6
7
7
R5916
6
2
3
4
GND
R5909
2.2
+5VSB_SW
+5VSB_FB
GND
2.2
+3P3VSB_PHASE1_S
R5938
422K
DNP
C5935 0.22u
R5937
499
C5920
0.22u
R5929
R5902 0ALL
C5931
1u
10V
GND GND
IND,PMC,2.2uH,3 5mOhm,7A,SM,6.6X7X1.8
2.2uH
C5947 220p
IND,PMC,1.5uH,2 0mOhm,8A TYP,SM,7.1X6.6X2
L5904
7.1X6.6X2.4
1.5uH
274K
DNP
C5901
1u
10V
L5902
R5940
200K
C5946 220p
R5928
499
+1P8VA
R5904
499K
R5957 0
DNP
R5912
18.7K
R5913
10.2K
GND
SUS_PWRGD_5VS B [34]
SUS_PWRGD_3V3
C5937
10p 50V
GND GND GND GND GND
C5936
0.1u 10V
C5926
10p
50V
GND GND GND GND GND GND
+3P3VSB
R5954
1M
DNP
R5905
100K
C5909
47u 6.3V
1
C5927
0.1u
10V
U5905
VCC
I2O
NC1
GND
74AUP1G07GX
DNP
R5956 0
0201
C5910
47u 6.3V
C5923
47u
6.3V
5
4
3
+3P3VA
C5924
47u
6.3V
C5948
0.1u 10V
C5911
47u 6.3V
+1P8VA
C5925
47u
6.3V
DNP
R5953
10K
SUS_PWRGD [34]
GND
C5904
47u
DNP
C5950
47u
6.3V
DNP
+3P3VSB
Imax=5.25A
+3P3VSB
GND
+5VSB
R5903
100K
DNP
5.1V
R5911
100K
DNP
GND
R5932
0
+5VSB_EN[35]
VSUS_ON[35,62, 69]
C C
PMTP5904
B B
R5908 0
R5949
47
DBG_T
+VSYS
SB_PWR_ON SUS_PW RGD_3V3_5VSB
R5906
10K
DNP
GND GND
DBG_T
DBG_TS
PMTP5903
R5901 0ALL
R5907 0
DNP
C5919
0.1u
10V
PM_3P3VSB_IN+ [28]
+3P3VSB_VIN
PM_3P3VSB_IN- [28]
C5933
10u 16V
GND GND
C595210u
0
R5950
DBG_T
R59170.01
+5VSB_EN_R
C5934
10u 16V
C5902
1u
10V
DNP
For NB502
R5933
0
R5931
232K
DNP
GND GND GND
C5932
0.1u 16V
GND
C5903
1u
10V
0201
For NB502
SB_PWR_ON
GND GND
U5904
1
VIN
16
MODE2
14
MODE1
15
EN
11
CLM
8
R5927
NC
0
NB502
CLM MODE1 MODE1
0 7 A 700 kHz < 3 V
90k 10 A 1 MHz < 3 V
150K 13 A 1 MHz >= 3 V
230k or floating 16.5 A 700 kHz >= 3 V
U5902
8
VCC
1
VIN
11
EN
PGND_1
PGND_2
PGND_3
PGND_4
PGND_5
BST
PGND_1
PGND_2
PGND_3
BST
SW
FB
PG
3V3
SW
SUS_PWRGD_3V3
A A
GND
5
4
5
PG
9
AGND
NB691GG-Z
GND
10
FB
R5939
43.2K
GND
+5VSB & +3P3VSB
+5VSB & +3P3VSB
+5VSB & +3P3VSB
Title:
Title:
Title:
<OrgAddr1>
<OrgAddr1>
<OrgName>
<OrgName>
<OrgName>
Size Proj ect Name Rev
Size Proj ect Name Rev
Size Proj ect Name Rev
Custom
Custom
Custom
W x H 577 x 373 mm
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
1
<OrgAddr1>
1.00
1.00
59 82Tuesday, May 21, 2 019
59 82Tuesday, May 21, 2 019
59 82Tuesday, May 21, 2 019
1.00
Page 60
5
D D
DFN5_P85XP85XP4_P48
U6004
74AUP1G08GX
SLP_S4#[22,33,34]
SLP_S4_DRV#[35,58,62]
C C
2
1
R6010 0
GND
5
VCC
4
Y
A
B
3
GND
DNP
C6038 0.01u 10V
+1P8VSB
C6007
0.1u
0201S_P33-W 39
4
10V
SLP_S4_AND#
3
PM_1P1V_DDR_VDD2_IN- [ 28]
PM_1P1V_DDR_VDD2_IN+ [2 8]
C6001 10u
DBG_T
+VSYS
+1P1V_DDR_VDD2_VIN
TP6007
SP_TP_SMDP58
R6019
0
0201
R6009
0
1P1V_DDR_VDD2_EN
R6020
0
DNP
0201
GND GND GND GND GND GND GND GND
CLM MODE1 MODE1
0 7 A 700 kHz < 3 V
90k 10 A 1 MHz < 3 V
150K 13 A 1 MHz >= 3 V
230k or floating 16.5 A 700 kHz >= 3 V
C6020
10u 16V
0603S_1-W 100
GND GND GND GND
1
16
14
15
R6011
150K
11
8
R6018
0
Iin=2.25 A
Trace Width>150mil
C6021
10u 16V
0603S_1-W 100
U6001
VIN
MODE2
MODE1
EN
PGND_1
CLM
PGND_2
PGND_3
PGND_4
PGND_5
NC
NB502
C6010
10u 16V
0603S_1-W 100
10
BST
+1P1V_DDR_VDD2_SW
9
SW
+1P1_DDR_FB
13
FB
12
PG
3
3V3
2
4
5
6
7
C6014
10u 16V
0603S_1-W 100
R6013 2.2
GND
C6013
0.1u 16V
0201S_P33
GND
0.22u
R6023
0201
C6002
1u
10V
0201
GND GND GN D
0
R6007
DBG_T
PMTP6010
SP-TP-C0P381
C6012
25V
0402S_P55
1%
DNP
C6009 220p
274K
R6017 5.1
0402
C6011
1u
10V
0201
R6016
SENSE
LOAD
0.02
5.4X5.2X1.5
L6001
0.68uH
R6012
499
0201
1%
+3P3VSB
E1E2
DBG_TS
I1I2
0402S_P55
R6022
R6021
R6021
10K
0201
11.8K
DBG_T
R6006
47
PMTP6009
SP-TP-C0P381
+VSYS
C6019
10p
50V
+3P3VSB
C6018
C6015
0.1u
47u
6.3V
10V
0805S_1P45
R6002 100K
C6016
47u
6.3V
0805S_1P45
C6017
47u
6.3V
0805S_1P45
2
+1P1V_DDR_VDD2
Iin=10.8 A
+1P1V_DDR_VDD2
+1P1V_DDR_PG [76]
Trace Width>150mil
R6014
100K
0201S_P28-W 35
DNP
GND
1
+VCCPLL_OC
+5VSB +1P1V_DDR_VDD2
B B
A A
C6034
0.1u
0201S_P33-W 39
GND
10V
CPU_C10_GATE#[22,33,56,62]
C6037
1u
0201S_P35-W 35
GND
6.3V
U6005
SLG5NT1533V
DFN8_1P65X1P05XP6_P4
1
VDD
2
ON
3-4
D1-D2
S1-S2
CAP
GND
5-6
7
8
GND
Iin=0.170 A
Trace Width>20mil
+VCCPLL_OC_REG
C6035
1u
C6008
0201S_P35-W 35
100p
GND
GND
+0P6V_DDR_PG[58]
6.3V
R6005 0.05
C6036
10u
0603S_1-W 100
GND
+3P3VSB
+VCCPLL_OC
DBG_S
0603S_P6-W 105
PMTP6006
SP-TP-C0P381
10V
+1P1V_DDR_PG 0P6V_DD R_VDDQ_RI_EN
R6024
100K
0201S_P28-W 35
PMTP6005
SP-TP-C0P381
R6037 0
0201S_P28-W 35
R6038 0
0201S_P28-W 35
GND
5
6
3
2
9
VOS
PGOOD
AGND
PGND1
PGND2
U6006
RT5715GQW
8
VIN
1
EN
7
LX
4
FB
L6003 0.47uH
+3P3VSB
PMTP6015
SP-TP-C0P381
R6036
0.1
DBG_S
0603S_P65-W 95
PMTP6016
SP-TP-C0P381
C6031
10u
20%
6.3V
0402
R6034
13K
R6035
38.3K
GND
C6039
0.1u
C6040
10p 50V
0201S_P33
C6041
22u 10V
0603S_1-W 100
0P6V_DDR_VDDQ_RI_EN
+0P6V_DDR_VDDQ
Iin= 0.43 A
C6042
22u 10V
0603S_1-W 100
DNP
+3P3VSB
R6001
100K
G
D
Q6002
S
+0P6V_DDR_VDDQ
+0P6V_DDR_VDDQ
R6003
31.6
D
Q6001
G
S
+1P2V_DUAL&+VTT
+1P2V_DUAL&+VTT
+1P2V_DUAL&+VTT
Title:
Title:
Title:
<OrgAddr1>
<OrgAddr1>
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A2
A2
A2
EDAN_A_EV1
EDAN_A_EV1
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
1
<OrgAddr1>
1.00
1.00
60 82Tuesday, May 21, 2019
60 82Tuesday, May 21, 2019
60 82Tuesday, May 21, 2019
1.00
Page 61
5
D D
4
3
2
1
C C
B B
A A
VNN BYPASS Rails
VNN BYPASS Rails
Title:
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
W x H 402 x 260 mm
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
VNN BYPASS Rails
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
61 82Tuesday, May 21, 2019
61 82Tuesday, May 21, 2019
1
61 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 62
5
4
3
2
1
PM_1P8VSB_IN+ [28]
C6203 10u
DBG_T
R6220
47
+VSYS
D D
C C
B B
DBG_T
R6203 0.02DBG_TS
PMTP6201
SP-TP-C0P381
VSUS_ON[35,59,69]
SLP_SUS#[22,34]
+3P3VSB
RTD3_AUD_PWR_1P8[25]
R6230
150K
DNP
R6231
51.1K
DNP
PM_1P8VSB_IN- [28]
0
R6221
DBG_T
PMTP6202
SP-TP-C0P381
DFN5_P85XP85XP4_P48
U6201
74AUP1G08GX
2
A
1
B
R6202 0
DNP
R6232 0
DNP
C6207
10u 16V
0603S_1-W100
VCC
Y
GND
R6207 0
0201S_P28-W35
+1P8VSB_VIN
+1P8VA
C6202
0.1u
0201S_P33-W39
5
4
3
1P8VSB_PG[69]
C6212
1u 6.3V
0201S_P35-W35
C6208
10u 16V
0603S_1-W100
GND GNDGND
10V
+1P8VSB
+1P8V_AUD_REG _EN
C6219
10u 16V
0603S_1-W100
GND
+1P8VSB
A2
B2
C6205
0.1u 16V
0201S_P33
R6201
100K
0201S_P28-W35
U6202
VOUT
VIN
GND
EN
NX3P1108UK
+1P8VSB_EN
GND
+1P8V_AUD_REG
A1
B1
GND
U6204
8
VCC
1
VIN
11
EN
5
PG
9
AGND
NB691GG-Z
C6206
0.1u 10V
0201S_P33-W39
GND
BST
SW
PGND_1
PGND_2
PGND_3
FB
DBG_S
R6206 0.05
0603S_P6-W105
PMTP6204
SP-TP-C0P381
R6218
7
6
2
3
4
GND
10
C6254 0.22u
2.2
0402S_P4
+1P8VSB_SW
+1P8VSB_FB
+1P8V_AUDIO
+1P8V_AUDIO
Imax=0.3A
0201S_P33
PMTP6203
SP-TP-C0P381
need to update R6216=887K
IND_4P2X4P2X2-3
L6201
Idc=5.8A/Isat=8.7A
1uH
R6216
887K
C6253 220p
R6217
499
0402S_P4
CPU_C10_GATE#[22,33,56,60]
0201S_P35-W35
+VSYS
Iin=2 A
Trace Width>100mil
0201S_P33
R6212 0
0201S_P28-W35
+1P8VSB
C6215
1u 6.3V
GND
R6219
43.2K
1%
0201
R6215
20.5K
0201
1%
C6211
10p 50V
0201S_P33
+5VSB
VCC1P8A_REG_E N
C6255
47u
6.3V
C6201
0.1u 10V
0201S_P33-W39
GND
1
2
3-4
C6204
47u
6.3V
U6206
VDD
ON
D1-D2
SLG5NT1533V
S1-S2
CAP
GND
C6218
0.1u 10V
0201S_P33-W39
GND
5-6
7
8
GND
VCC1P8A_REG
C6251
100p
GND
R6213 0.005
0603S_P75-W100
PMTP6207
SP-TP-C0P381
C6214
0.1u 10V
0201S_P33-W39
GND
DBG_S
R6211 0.02
DBG_S
0603S_P6-W100
PMTP6211
SP-TP-C0P381
+1P8VSB
Imax=4A
+1P8VSB
PMTP6208
SP-TP-C0P381
+VCC1P8A
PMTP6212
SP-TP-C0P381
+VCC1P8A
Imax=0.3A
+1P8VSB
C6209
1u 6.3V
+1P8VSB
C6213
1u 6.3V
0201S_P35-W35
SLP_S4_DRV#[35,58,60]
A A
R6210 0
0201S_P28-W35
5
+1P8V_DUAL_REG _EN
U6203
A2
VIN
B2
EN
NX3P1108UK
VOUT
GND
A1
B1
+1P8V_DUAL_REG
GND
4
C6250
0.1u 10V
0201S_P33-W39
GND
DBG_S
R6209 0.01
0603S_P6-W100
PMTP6206
SP-TP-C0P381
+1P8V_DDR_VDD1
Imax=1A
+1P8V_DDR_VDD1
PMTP6205
SP-TP-C0P381
RTD3_TPANEL_PWR[25,64]
3
0201S_P35-W35
R6204 0
0201S_P28-W35
GND
+1P8V_TS_REG _EN
U6205
NX3P1108UK
BGA4_2X2_P98XP98XP59_P5
A2
VIN
B2
EN
2
VOUT
GND
A1
B1
+1P8V_TS_REG
C6210
0.1u 10V
GND
0201S_P33-W39
GND
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
W x H 422 x 273 mm
Date: Sheet of
Date: Sheet of
Date: Sheet of
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
DBG_TS
0603S_P6-W105
R62050.05
PMTP6210
SP-TP-C0P381
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
+1.8VSB & Load SW
+1.8VSB & Load SW
+1.8VSB & Load SW
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
1
+1P8V_TS
PMTP6209
SP-TP-C0P381
+1P8V_TS
Imax=0.455A
62 82Tuesday, May 21, 2019
62 82Tuesday, May 21, 2019
62 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 63
5
+3P3VAS
4
PWR_SL1_ F
3
2
1
EXT_DC_IN
C6343
B2
10u
C2
D2
E1
E2
A2
R6315
1M
0201
1%
D1
1
2
9
5
D2S1
6
7
Place L6302 close to L6301 as place holder for larger inductor.
4
10
S2
GND
GND
CHG_BTST1 CHG_BTST2
CHG_SW 1
CHG_LODRV1
CHG_HIDRV1
CHG_VBUS
CHG_ACN
CHG_ACP
CHG_VCCA
CHG_ILIM_HIZ
U6302
30
32
29
31
1
2
3
7
6
16
CHG_PROCHOT#
11
13
12
4
5
15
14
BQ25713RSNR
GND
C6330
330p
DNP
R6317
56
DNP
BTST1
SW1
LODRV1
HIDRV1
VBUS
ACN
ACP
VDDA
ILIM_HIZ
COMP1
PROCHOT
SCL
SDA
CHRG_OK
OTG/VAP
CMPOUT
CMPIN
L6301
2.2uH
CELL_BATPRESZ
SL1_EN_N [76]
C6345
10u
SL1_EN_N
U6301_OVLO
R6335
71.5K
1%
0201
D D
R6313 0
D
D
Q6301
SAM_SL1_PW R_EN[35,79]
R6334 0
SAM_SL1_PW R_EN_R
R6328
100K
G
NX3008NBKMB
G
S
S
R6314
100K
1%
0201
R6328 need ch ange back to 100K after SAM PU disab le
EXT_DC_IN
C C
C6324
C6333
22u
25V
20%
CHARGER_SDA[35]
C6315
+
GND
CHARGER_SCL[35]
CHRG_OK[34]
22u
25V
20%
C6332
22u
25V
25V
GND
GND GND GND GND
+1P8VA
R6331
200K
+
GND
B B
0.022u
+1P8VA
GND
25V
DNP
R6333
10K
R6341
10K
C6323
0.022u
R6338
2K
GND
C6321
22u
25V
+1P8VA
GND
GND GND
R6316
2K
R6303 0.01
1508
C6322
R6308
22u
25V
10
0201
C6341
C6305 0.1u
0.01u
25V
CHG_REGN_D
DNP
R6305
499K
R6301
120K
GND GND
R6306
10
0201
C6342
0.01u
25V
R630710
C6326
1u
GND
GND
C6301
C6304
1000p
0.01u
25V
25V
GND
GND
C6303 1800p
H_PROCHOT#[ 10,26,66,76]
C6320
0.022u
25V
GND
CHG_COMP1_R CHG_COMP1
25V
25V
C6344
1u
U6301
A1
VINT1
B1
C1
D1
B3
C3
D3
E3
C6311
0.022u
VBUS1
VINT2
VBUS2
VINT3
VBUS3
VBUS4
VINT4
VBUS5
OVLO
EN_NA3ACK
GND1
GND2
GND3
NX20P5090
OVLO: 17.44V to 19.29V
Q6302
Q1
G1
8
Q2
G2
3
AONP36376
C6335
100p
GND GND
0.047u
C6302
R6320 40.2K
C630633p
R6329 100
CHG_OTG_EN
R6327 0
C6310
330p
DNP
R6325
DNP
BTST2
SW2
LODRV2
HIDRV2
VSYS
BATDRV
SRP
SRN
REGN
COMP2
IADPT
IBAT
PSYS
PGND
MPAD
+1P8VSB
R6319
TP6301
100K
1%
0201
SL1_ACK#
Q6304
D1
1
2
Q1
9
G1
5
D2S1
6
7
4
10
GND
56
GND
25
CHG_SW 2
23
CHG_LODRV2
26
CHG_HIDRV2
24
CHG_VSYS
22
21
CHG_SRP_A_R
20
CHG_SRN_A_R
19
CHG_REGN_D
28
CHG_COMP2 CH G_COMP2_R
17
CHG_CELL_BATPRES
18
CHG_IADPT
8
CHG_IBAT
9
Q2
S2
AONP36376
C6331 0.047u
CHG_BATDRV_A
R6302 10K
C6308 15p
G2
C6336
180p
10
27
33
GND
C6327
100p
GND
C6319
100p
PM_VSYS+ [28]
C631810u
R6312
47
DBG_T
PTP6301
C6340
0.01u
8
GND GND G ND
GND
C6316
22u
C6337
22u
C6338
22u
C6329
+
47u
GND GND
C6334
+
47u
+VSYS: 6V(TBD) to 8.75V
DBG_T
PTP6302
R6330
E1 E2
I1 I2
0.005
DBG_TS
R6311
DBG_T
0
PM_VSYS- [28]
+VSYS
3
PWR_SL1_F MAX Voltage: 17.2V
PSU_VOLT MAX Voltage: 0.697V
PWR_SL1_ F
61
Q6308B
AK
D6301
RB520CS3002L
R6321
130K
R6322
5.49K
34
5
GND
R6337
137K
C6307
PMON_R
C6328
GND
680p
R6336 0
100p
Q6303
3
2
1
S
G
4
R6332 10
R6318 10
GND
DNP
C6314
10u
+VDD_BATA_PACK
C6339
10u
PSU_VOLT[35]
GND
EXT_VOLT_ADC_EN[35]
+1P8VA
GND
Q6308A
2
R6323
100K
5,6,7,8
5
D
C6313
1u
GND
CHG_SRP_A
CHG_SRN_A
C6312
2.2u
GND
R6340
18.7K
DNP
GND
R6304 0.01
1508
PJP6303
0201 SHUNT
1 2
C6309 0.1u
PMON [66]
PJP6304
0201 SHUNT
1 2
CHG_VCCA
C6317
10u
DNP
GND GND
R6310
348K
R6309
249K
GND
ILIM_HIZ current limit equation - (VILIM_HIZ – 1 V ) / 40 = ACP - ACN
7-bit I2C Address = 0x6B
A A
CHARGER
CHARGER
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Title:
Engineer:
Engineer:
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
1
CHARGER
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
63 82Tuesday, May 21, 2019
63 82Tuesday, May 21, 2019
63 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 64
5
D D
+5VSB
U6407
A2
C6415
0201S_P35-W35
RTD3_TPANEL_PWR[25,62]
1u6.3V
GND
R6425 0
+5V_TS_EN
C6413
0.1u 10V
0201S_P33-W39
B2
C2
OUT_A1
IN_A2
OUT_B1
IN_B2
EN
NCP451AFCT2G
A1
B1
C1
GND
GND GND
+5V_TS_REG
4
R6417 0.1
C6414
0402S_P7-W70
0603S_P65-W95
10u6.3V
+5V_TS
DBG_TS
PMTP6413
SP-TP-C0P381
PMTP6414
SP-TP-C0P381
+5V_TS
Iin=0.25A
Trace Width>20mil
3
2
1
GND
C C
0201S_P35-W35
SAM_KBTP_PWR_EN[35]
+5VSB
C6408
1u 6.3V
0201S_P35-W35
B B
RTD3_AUD_PWR_5P0[25]
R6423 0
0201S_P28-W35
ON_+5V_AUDIO_REG
U6404
A2
IN_A2
B2
IN_B2
C2
EN
NCP451AFCT2G
+5VSB
C6412
1u6.3V
GND
R6415 1K
GND
A1
B1
C1
OUT_A1
OUT_B1
KIP_EN
C6411
0.1u 10V
0201S_P33-W39
GND
+5V_AUDIO_REG
GND
U6403
A2
IN_A2
B2
IN_B2
C2
EN
NCP451AFCT2G
KIP_EN [76]
DBG_S
R6413 0.05
0603S_P6-W105
PMTP6410
SP-TP-C0P381
C6420
10u 6.3V
0402S_P7-W70
TMAX=0.65mm
GND
OUT_A1
OUT_B1
GND
+5V_KIP_REG
A1
B1
C1
GND GND
+5V_AUDIO
C6417
0402S_P7-W70
PMTP6411
SP-TP-C0P381
0603S_P6-W105
10u6.3V
+5V_Audio
Iin=0.66A
Trace Width>20mil
DBG_TS
R64120.05
PMTP6401
SP-TP-C0P381
+5V_KIP
Iin=???A
Trace Width>20mil
+5V_KIP
PMTP6402
SP-TP-C0P381
+5VSB
+5V_FAN
C6416
1u 6.3V
0201S_P35-W35
A A
+5V_FAN_EN[35]
5
R6408 1K
0201S_P28-W35
ON_+5V_FAN_REG
MTP6402
U6408
A2
IN_A2
B2
IN_B2
C2
EN
NCP451AFCT2G
4
OUT_A1
OUT_B1
GND
A1
B1
C1
+5V_FAN_REG
GND
R6420 0.02
C6418
10u 6.3V
0402S_P7-W70
TMAX=0.65mm
GND
0603S_P6-W100
DBG_S
PMTP6408
SP-TP-C0P381
PMTP6409
SP-TP-C0P381
+5V_Fan
Iin=0.5A
Trace Width>20mil
3
+5V Load SW
+5V Load SW
Title:
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
+5V Load SW
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
64 82Tuesday, May 21, 2019
64 82Tuesday, May 21, 2019
64 82Tuesday, May 21, 2019
1
1.00
1.00
1.00
Page 65
5
D D
+1P8VSB
C6501
0.1u
U6503
R6529
47K
2
A
1
B
74AUP1G32GX
PCH_VDD_PANEL_EN[10,30]
SAM_VDD_PANEL_EN[35]
R6501
100K
GND
C C
GND
VCC
GND
5
4
Y
3
+3P3V_PANEL_EN_R
GND
GND
R6519 1K
+3P3V_PANEL_EN_R [10]
R6510 0.01
+3P3VSB
DBG_S
PTP6506
4
C6503
1u
GND
+3P3V_PANEL_EN
+3P3V_PANEL
Imax=0.433A
Trace Width> mil
U6504
A2
IN_A2
B2
IN_B2
C2
EN
NCP451AFCT2G
+3P3V_PANEL_EN [76]
+3P3V
PTP6505
OUT_A1
OUT_B1
GND
+3P3V_PANEL_REG
A1
B1
C1
GND
+3P3VSB
R6548
499K
+3P3V_PANEL_DISC_CTRL
34
5
Q6501B
3
PM_3P3V_PANEL_IN+ [28]
C6521 10u
DBG_T
R6557
47
DBG_T
DBG_TS
R6508 0.02
C6502
1u
GND
0
R6558
DBG_T
+3P3V_PANEL
PTP6502PTP6501
DSG_+3P3V_PANEL
61
2
GND
PM_3P3V_PANEL_IN- [28]
R6544
47
Q6501A
2
1
+3P3V
Imax=0.02A
+3P3VSB
SLP_S3_DRV#[35,58]
C6514
1u
GND
+3P3VSB
B B
SIL_SSD_VR_EN[58]
C6511
1u
GND
R6564 0
Trace Width> mil
U6511
A2
VIN
B2
EN
NX3P1108UK
U6502
A2
B2
C2
OUT_A1
IN_A2
OUT_B1
IN_B2
EN
NCP451AFCT2G
GND
VOUT
GND
A1
B1
C1
GND
PM_3P3V_SSD+ [28]
A1
B1
GND
C6513
0.1u
GND
+3P3V_REG
C6512
1u
GND
C6517 10u
DBG_T
R6516
47
DBG_T
R6511 0.02
DBG_TS
PTP6504
+3P3VSB
Q6505B
5
G
R6554
200K
3P3V_SSD_DCH
3
D
S
4
PM_3P3V_SSD- [28]
0
R6515
DBG_T
+3P3V_SSD_CON
PTP6503
Q6505A
2
G
GND
+3P3V_SSD_CON
Imax=2.25A
Trace Width>100mil
6
1
R6555
140
0402
1/16W
D
S
R6556
140
0402
1/16W
+3P3VSB
C6522 10u
DBG_T
R6553
47
DBG_T
R6514 0.02
PM_3P3V_WWAN+ [28]
PM_3P3V_WWAN- [28]
0
R6552
DBG_T
DBG_TS
+3P3V_WWAN
PTP6509PTP6510
+3P3V_WWAN
GND
+3P3VSB
A A
BB0_PD_LS_EN_R
GND
BB0_PD_LS_EN[79]
1u
R6559 0
5
U6509
A2
VIN
B2
EN
NX3P1108UK
VOUT
GND
A1
B1
GND
C6525
0.1uC6524
+3P3V_BB0
Imax=0.22A
R6560 0.02
DBG_TS
Trace Width> mil
GND
4
+3P3V_BB0+3P3V_TBT_BB0_REG
PTP6514PTP6513
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
C6508
1u
GND
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Imax=2A
Trace Width>60mil
+3P3V Load SW
+3P3V Load SW
+3P3V Load SW
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
65 82Tuesday, May 21, 2019
65 82Tuesday, May 21, 2019
1
65 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 66
+3P3VSB
1
R6604
0402
4.7
R6634
TEMP_VCCIN[67]
A A
0
R6635
49.9K
GND GND
R6608 0
GND
6.3V
C6612 1u
PMON[63]
CSSUM_VCC IN
DNP
C66060.1u
+VCCIN
DNP R6638 100
C6603
4.7uF
10V
GND
Scale to 0.80V for Psys Max.
C6601
4700p
GNDGND
VFB_VCCIN
R6609 100
VCCIN_VIN_SEN SE[13]
VCCIN_VSS_SEN SE[13]
R6613 100
GND
VDD33_VCCIN
R6601
8.06K
ALL
R6626 1.5K
R6627 1.5K
+VSYS
CS_VCCIN2[67]
CS_VCCIN1[67]
R6610 0
R6611 0
R6636
2M
GND
R6607 806
VOSEN_VCCIN
VORTN_VCCIN
R6603
133K
VCCIN_SEN
GND
1
2
3
4
5
6
7
C6602
0.01u
CS3
CS2
CS1
VDIFF
VFB
VOSEN
VORTN
28
29
MPAD
24
25
26
27
PSYS
TEMP
VDD33
VIN_SEN
CSSUM8IMON9IREF10VDD1811SCLK/VID012SDIO/VID113ALT#
U6601
PWM322PWM223PWM1
EN
PE
STB
SCL_P
SDA_P
VRHOT#
VRRDY
MP2940AGRT-002A-Z
14
C6613 DNP
21
20
19
IMVP_SCL_VCCIN
18
IMVP_SDA_VCC IN
17
16
15
+3P3VSB
GND
VR_HOT#_VCCIN
VR_READY_VCCIN
+VCCST_CPU
R6602 499K
ALL
ALL_SYS_PWRG D [58]
SYNC_VCCIN [67]
R6605100
R660645.3
PE_VCCIN
R6637 0
DNP
PWM_VC CIN1 [67]
PWM_VC CIN2 [67]
+3P3VSB+3P3VSB
R66232K
R662410K
R66222K
R6612 0
R6615 0
R66390
IMVP_PROGRAM _ENABLE [35]
IMVP_SCL_P [33,35]
IMVP_SDA_P [33,35]
H_PROCHOT# [10,26,63,76]
VRM_PW RGD [34,58]
C6608
220p
CSSUM_VCC IN
IMONA_CORE
IREF_VCCIN
GND
R6621
61.9K
R6631
53.6K
1%
70A
GNDGND
C6604
1u
VDD1V8_CORE
GND
1
SVID_ALERT#_R
VIDSOUT_R
VIDSCLK_R
R66160
R66170
R66140
SVID_ALERT# [13]
VIDSOUT [13]
VIDSCLK [13]
CONTROLLER: CORE, SA
CONTROLLER: CORE, SA
CONTROLLER: CORE, SA
Title:
Title:
Title:
<OrgAddr1>
<OrgAddr1>
<OrgName>
<OrgName>
<OrgName>
Size Project N ame Rev
Size Project N ame Rev
Size Project N ame Rev
Custom
Custom
Custom
W x H517 x 335 mm
Date: Sheet of
Date: Sheet of
Date: Sheet of
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
<OrgAddr1>
66 82Tuesday, May 21, 2019
66 82Tuesday, May 21, 2019
66 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 67
1
<RevCode>
<RevCode>
<RevCode>
Need to find 1.5W Sense resistor
PM_VCCIN_IN+[28]
+VCCIN_IN
PM_VCCIN_IN-[28]
PMTP6702
C6702
6.3V
1u
+3P3VSB
GND
Place at DrMOS
U6701
PWM_VCCIN1[66]
SYNC_VCCIN[66]
TEMP_VCCIN[66]
15 21
PWM
16
SYNC
17
VTEMPFLT
20
VCC
18
CS
DRIVE CONTROL
GND
19
AGND
MP86902B
CS_VCCIN1[66]
BST
VIN1
VIN14
HSFET
SW2
SW3
SW4
LSFET
PGND13
PGND12
PGND511
1
14
2
3
4
13
12
5-11
C6701
1u
0201
GND
VCCIN1_SW
C6721
470p
DNP
R6721
0
DNP
GND
C6714
1u
0402
25V
GND
L6704
0.15uH
30A
IND_6P8X6P8X2P4-3
GND
C6730
10u
16V
0603
GND
C6731
10u
16V
0603
C6704
+
47u
C6705
+
47u
Place at DrMOS
U6702
PWM_VCCIN2[66]
SYNC_VCCIN
TEMP_VCCIN
A A
+3P3VSB
C6711
6.3V
1u
GND
15 21
PWM
16
SYNC
17
VTEMPFLT
20
VCC
18
CS
DRIVE CONTROL
CS_VCCIN2[66]
19
AGND
BST
VIN1
VIN14
HSFET
SW2
SW3
SW4
LSFET
PGND13
PGND12
PGND511
1
14
2
3
4
13
12
5-11
C6707
1u
10V
0201S_P4-W40
VCCIN2_SW
0402S_P55
470p
R6723
C6723
50V
0
0603S_P6-W95
DNP
DNP
L6703
0.15uH
30A
C6713
1u
25V
0402
C6732
10u
16V
0603
C6733
10u
16V
0603
C6743
+
47u
C6744
+
47u
C6709
+
47u
DNP
C6706
+
47u
DNP
C6703 10u
DBG_T
0
R6702
DBG_T
E1 E2
I1 I2
DBG_TS
1K
R6724
0201S_P28-W35
DNP
GND
R6701
0.005
R6703
47
DBG_T
PMTP6704
TP6702
TP6701
+VSYS
ICCMAX: 70A
ITDC: 39A
+VCCIN
GND
+
C6712
180uF
MP86902B
<Core Design>
<Core Design>
<Core Design>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
W x H 357 x 241 mm
Custom
Custom
Custom
IA and SA
IA and SA
IA and SA
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
67 82Tuesday, May 21, 2019
67 82Tuesday, May 21, 2019
67 82Tuesday, May 21, 2019
Page 68
1
<RevCode>
<RevCode>
<RevCode>
A A
<Core Desig n>
<Core Desig n>
<Core Desig n>
Title
Title
Title
<Title>
<Title>
<Title>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
EDAN_A_EV1
Custom
EDAN_A_EV1
Custom
EDAN_A_EV1
Custom
Date: Sheet of
Date: Sheet of
1
Date: Sheet of
68 82Tuesday, May 21, 2019
68 82Tuesday, May 21, 2019
68 82Tuesday, May 21, 2019
Page 69
PM_VCCIN_AUX_IN+ [28]
1
C690710u
DBG_T
R6903
47
DBG_T
+VSYS +VCCIN_AUX_IN
CORE_VID1[26]
CORE_VID0[26]
A A
VCCIN_AUX_PG[34,58]
PMTP6902
0
0
R6915
R6919
R6910
DNP
R6912
+3P3VSB +1P8VSB
R6909
100K
0
R6907
R6901
E1 E2
SENSE
I1 I2
LOAD
0.02
DBG_TS
+3P3VSB +1P8VSB
R6921 100K
R6905 100K
10K
DNP
GND GND GND
100K
DNP
0
R6902
DBG_T U6902
C6903
+
47u
DNP
R6918 100K
R6922 10K
PM_VCCIN_AUX_IN- [28]
PMTP6901
C6909
10u
16V
0603
DNP
R6913 100K
CORE_VID1_R
CORE_VID0_R
C6908
GND GND
10u
16V
0603
+3P3VSB
C6902
1u
0201S_P35-W35
6.3V
C6910
1u
25V
0603S_P94-W95
0603
GND
18
19
2
5
6
9
1
3
4
VIN
VID1
VID0
PG
3V3
PGND1
PGND2
PGND3
PGND4
+1P8VSB
C6904
0.1u
10V
0201S_P33-W39
VCCIN_AUX_EN
R6920
100K
0201S_P28-W35
R6924 0
8
FS
7
13
U6901
EN
BST1
VOUT
RGND
MODE
15
14
SW1
SW2
BST2
CLM
MP2941GL
12
11
10
VOSEN_VCCIN_AUX
16
VORTN_VCCIN_AUX
17
C6901
0.22u
VCCIN_AUX1_SW
C6905
0.22u
74AUP1G08GX
5
VCC
4
Y
3
GND
R6906
0
R6904
0
A
B
DNP
GND
R69110
2
1
R6923
100
R6908
100
VSUS_ON [35,59,62]
1P8VSB_PG [62]
Idc 30A/Isat 40A
L6905
0.15uH
31A
VCCIN_AUX_VIN_SENSE [26]
VCCIN_AUX_VSS_SENSE [26]
IND_6P8X6P8X2
+
GND
ICCMAX: 26A
+VCCIN_AUX
C6906
220u
ITDC: 10A
GND
R6914
150K
1
R6917
0
GND GND
R6916
150K
DNP
GT Controller
GT Controller
Title:
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
W x H 357 x 241 mm
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
GT Controller
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
69 82Tuesday, May 21, 2019
69 82Tuesday, May 21, 2019
69 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 70
5
4
PWR_S L1_F+V SYS
3
2
1
+3P3VAS
K
D7011
+3P3VA
R7021
SL1_20v0
R7024
10K
SL1_5v5
R7027
R7046
1.5K
DNP
A1
499K
0201S_P3
12.1K
SL1_PWR_GOOD#
+VSYS
BAT54CW
SL1_HPD1A_O
6
D
Q7005A
S
1
6
D
S
1
D D
U7000
SAM_SL1_TX[ 37]
SAM_SL1_RX[37]
SL1_RX_S EL#[3 5]
R7007
R7006
499K
TP7009
SL1_ADC[35 ]
ADC_RD_EN[34,35]
C C
SL1_PSU_ DET[34,76]
SL1_PW R_GOOD[55]
B B
R7035 0
R7026 330
R7018
Present State
SL1_UART_TX
SL1_UART_RX
1W/2W
Detect
Low
Low
High
High
High
A A
Low
High
Low
High
High
Detach
1W
1W
2W
2W
5
200K
R7011
100K
100
Trigger
Initial
A/D read
n/a
n/a
n/a
Valid
Invalid
R7005
200K
1
Dp
8
Sp
2
Dm
10
Sm
R7008
4.32K
R7010
5.49K
SL1_ADC_RD_EN_R
D
G
Q7000
SOTFL-3_1P3XP9XP55_P4
S
SL1_UART_TX_SEL_N
DG2723DN-T1 -E4
Low
High
Low
Low Low
High
HSD1p
HSD2p
HSD1m
HSD2m
QFN10_1P85X1P45XP6_P4
+1P8VA
R7022
150K
SL1_PSU_DETr
VDD
GND
+3P3VA
SL1_UART_RX_SEL_N
+3P3VA
9
7
5
6
4
3
D7004
A K
RB520CS30 02L
C7015
A K
R7001
249K
GND
Output
Low
Low
High
High
SL1_HPD1B_U
SL1_HPD1A_U
C7003
0.1u
10V
0.1uF
25V
R7023
499K
D7006
RB520CS30 02L
4
A2
R7002
R7004
140
140
PSU Voltage Comparator
PWR_SL1_F_COMP_VDD
SL1_PWR_GOODg
SL Polarity
Straight up
Straight up
(9.4V-17.2V)
2
6
1
5
INA+
INB+
R7099
8.66K
G
Detach
Reversed
Reversed
U7004
VDD
OUTA
INA+
OUTB
INB-
GND
TPS3700DS ER
SON6_1P55X1P55XP8_P5
<400mV
OUTA=Low
>400mV
OUTB=Low
D
D
G
S
S
4
3
Q7001
NX3008NBK MB
A1
SL1_HPD1B_O
R7042
100K
2
G
PWR_S L1_F
D7005
AK
RB520CS30 02L
C7016
0.022u
25V
0201S_P 33
R7030
33K
1
R7033
51K
DNP
R7045
1.5K
Q7003A
2
G
R7043
249K
A2
D7010
BAT54CW
K
1
S
Q7006A
3
D
G
Q7006B
S
4
PWR_SL1_F
C7009
0.1uF
25V
0201S_P 35-W3 5
R7031
1K
0603S_P6-W95
SL1_DISCHARGER
SL1 port discharger
G
2
5
C7006
100p
0201S_P33
25V
limits PSU anti-arc pulse voltage
32
Q7002
SC70-3_2P2X1P35X1_P65
+3P3VAS_ SIL
R7044
1M
Q7003B
3
4
D
S
5
G
3
BAT_SHUTDOW N#
D
R7014
8.06
PWR_SL1_F_C
C7013
25V
0603S_P94-W95
BATEN_PUL SE[34,58]
+3P3V_HP D
R7000
R7040
R7039
Q7005B
G
5
BAT_DET#[3 4]
D
R7017
8.06
3
L7000
L7001
12
POS
SHUNT-NO-MSPN-002 70
NEG
R7015
8.06
POWE R_SMB_SDA[33 ,35]
POWE R_SMB_SCL[33,35]
4
C7022
S
0.1uF
R7016
8.06
BAT_SHUTDOW N#[3 3,58,76]
25V
6
1u
100
100
100
C7001
100p
25V
X865917-001
70 OHM
3A
0805S_1P1
X865917-001
70 OHM
3A
0805S_1P1
X865917-001
70 OHM
L7007
0805S_1P1
DNP
TP7007
NO-MSPN-00270
SL1_HPD2 [71 ,76]
SL1_HPD1A [7 1,76]
SL1_HPD1B [7 1,76]
C7000
100p
25V
C7002
100p
DNP
DNP
25V
PESD24VS1UL
PESD24VS1UL
PESD24VS1UL
DIO-ESD,SM,PESD24VS1UL,24 V,50 pF,1X.6X.
DIO-ESD,SM,PESD24VS1UL,24 V,50 pF,1X.6X.
DIO-ESD,SM,PESD24VS1UL,24 V,50 pF,1X.6X.
A K
A K
A K
D7000
D7001
D7008
PWR_S L1
C7010
25V
C7018
100p
25V
0.1uF
C7012
25V
0.1uF
1K
R7003
C7017
100p
DNP
25V
DNP
1K
R7037
BAT_LDO[55] BAT_LDO_PACK [76]
C7007
3A
100p
C7005
100p
25V
R7034
C7020
100p
+1P8VA
150K
25V
C7008
25V
25V
BATEN_PULSE_R BATEN_PULSE_CONN
C7004
100p
25V
@100MHz
120 OHM
0402S_P55
L7003
BAT_SMDATA[76]
BAT_SMCLK[76]
@100MHz
120 OHM
0402S_P55
L7004
BATA_DET# _CON[76]
BATA_DET#rr
C7021
100p
25V
100p
120 OHM
0402S_P55
L7006
1.2A
1.2A
120 OHM
C7011
100p
25V
0402S_P55
L7005
@100MHz
R7019
499K
1.2A
1.2A
120 OHM
L7002
0402S_P55
A K
R7029
200K
DNP
BAT_SMDATA
D7003 PESD24VS1UL
DIO-ESD,SM,PESD24VS1UL,24 V,50 pF,1X.6X.
BAT_SMCLK
1.2A
BATEN_PUL SE_CONN [76]
M1106392-0 01
8
BATA_DET#_CON
7
6
5
N3
N2
N1
+VDD_BATA_ PACK
R7050
499K
0201S_P3
AK
D7013
Red
RED
+VDD_BATA_ PACK
4
4
8
7
6
5
N3
N2
N1
P3
P2
P1
J7001
3
3
2
2
1
1
P3
P2
P1
C7019
0.1uF
20160823sjs0632 : SL1 Power, Battery Connector Report errors to Steven
Title:
Title:
Title:
SL1 Power, Battery Conn
SL1 Power, Battery Conn
SL1 Power, Battery Conn
<OrgName>
<OrgName>
<OrgName>
Size Pro ject Name Rev
Size Pro ject Name Rev
Size Pro ject Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
WxH 502 x 325 mm
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
1
1.00
1.00
70 82Tuesday, May 21, 2019
70 82Tuesday, May 21, 2019
70 82Tuesday, May 21, 2019
1.00
Page 71
5
4
3
SL1_LANE1N_R
SL1_LANE0P_R
SL1_LANE0N_R
SL1_LANE1P_R
K1K2
D7103
PESD5V0H1BSF
K1K2
D7108
PESD5V0H1BSF
K1K2
D7113
PESD5V0H1BSF
K1K2
D7116
PESD5V0H1BSF
2
SL1_LANE3P_R
SL1_LANE3N_R
K1K2
D7107
PESD5V0H1BSF
K1K2
D7118
PESD5V0H1BSF
SL1_LANE2P_R
SL1_LANE2N_R
1
K1K2
D7112
PESD5V0H1BSF
K1K2
D7105
PESD5V0H1BSF
GND GND
D D
C C
4
SL_DATA0_DP[10]
SL_DATA0_DN[ 10]
SL_DATA1_DP[10]
SL_DATA1_DN[ 10]
3
2
L7101
3
2
L7102
0nH
1
4
0nH
1
SL1_LANE0P_R
SL1_LANE0N_R
SL1_LANE1P_R
SL1_LANE1N_R
GND GND
SL1_HPD1A[70, 76]
SL1_HPD2[70,71,76]
SL1_HPD2[70,71,76]
SL1_HPD1B[70, 76]
PWR_SL1
USB3_SL1_RXP4_R
USB3_SL1_RXN4_R
USB3_SL1_TXP4_R
USB3_SL1_TXN4_R
SL1_LANE3P_R
SL1_LANE3N_R
SAM_DBG2_SL1_DP_HP D_CON
SAM_DEBUG_UART _RX_CON
USB2_SL1_D+_R
USB2_SL1_D-_R
SL1_LANE4N_R
SL1_LANE4P_R
SAM_DEBUG_UART _TX_CON
SAM_DBG4_SL1_CONF IG1_CON
SL1_LANE2N_R
SL1_LANE2P_R
SL1_LANE1N_R
SL1_LANE1P_R
SL1_LANE0N_R
SL1_LANE0P_R
GND GND
Same IPEX connector as LANCELOT
J7101
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
19
MTG22
20
MTG21
21
MTG20
22
MTG19
23
MTG18
24
MTG17
25
MTG16
26
MTG15
27
MTG14
28
MTG13
29
MTG12
30
MTG11
31
MTG10
32
MTG9
33
MTG8
34
MTG7
35
MTG6
36
MTG5
37
MTG4
38
MTG3
39
MTG2
4040MTG1
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
4
SL_DATA2_DP[10]
SL_DATA2_DN[ 10]
SL_DATA3_DN[ 10]
SL_DATA3_DP[10]
B B
U7104
SL_AUX_DN[46]
SL_AUX_DP[46]
4
USB3_SL1_RXN4[24]
USB3_SL1_RXP4[24]
USB3_SL1_TXN4[ 24]
USB3_SL1_TXP4[24]
A A
USB2_SL1_DN[24]
USB2_SL1_DP[24]
C7101 0.1u
C7102 0.1u
USB3_SL1_TXN4_C
USB3_SL1_TXP4_C
5
3
1
2
L7105
L7107
1
2
3
23
14
RN71070 DNP
0nH 2.5GHZ
4
DP_OA1
B1
DM_O
Note: IP3319CX6 D+ and D- is interchageable
0nH
4
3
1
2
L7106
K1K2
USB3_SL1_RXN4_R
USB3_SL1_RXP4_R
0nH
K1K2
D7119
D7106
PESD5V0H1BSF
PESD5V0H1BSF
DP_I A 2
DM_I B2
ID
GND
C2
C1
GND
USB2_SL1_D-_R
USB2_SL1_D+_R
SL1_LANE4N_R
SL1_LANE4P_R
USB3_SL1_TXN4_R
USB3_SL1_TXP4_R
4
USB3_SL1_RXP4_R
USB3_SL1_TXN4_R
USB3_SL1_TXP4_R
USB3_SL1_RXN4_R
K1K2
GND GNDGND
K1K2
D7102
D7117
PESD5V0H1BSF
PESD5V0H1BSF
K1K2
D7104
PESD5V0H1BSF
K1K2
D7109
PESD5V0H1BSF
3
3
2
L7103
3
2
L7104
0nH
1
4
0nH
1
SL1_LANE2P_R
SL1_LANE2N_R
SL1_LANE3N_R
SL1_LANE3P_R
TP7101
SL1_DP_HPD[10]
+5VSB
R7102
10K
SL1_HPD_DP_G
G
S
Q7102
2
SAM_DBG_RX[29,33,34,76]
SAM_DBG_TX[29,33,34,76]
D
GND
R7125
100K
R7101 0
R7103 0
SL1_CONFIG1[46]
SAM_DBG_RX_FILT
SAM_DBG_TX_FILT
SL1_DP_HPD_BUF
R7113
1M
GND
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
Date: Sheet of
U7109
1
I1
I
2
3
4
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
O
I2
I3
I4
GND PAD
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
1
GND
12p
SAM_DEBUG_UART _RX_CON
8
O1
SAM_DEBUG_UART _TX_CON
7
O2
SAM_DBG2_SL1_DP_HP D_CON
6
O3
SAM_DBG4_SL1_CONF IG1_CON
5
O4
9
GND
SL1 SINGNALS
SL1 SINGNALS
SL1 SINGNALS
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
71 82Tuesday, May 21, 2019
71 82Tuesday, May 21, 2019
71 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 72
5
+3P3VA
R7202 0.01
PTP7201
D D
SL1_HPD2_EN#[35,76]
GND
PTP7202
C7201
1u
R7206
499K
G
+3P3VA
R7201
499K
D
Q7201
S
+3P3V_HPD_VIN
+3P3V_HDP_EN
+3P3V_HPD_ILIMIT
R7204
20K
GND
U7201
A1
B1
C3
C2
FPF2495UCX
VIN_A1
VIN_B1
ON
ISET
VOUT_A3
VOUT_B3
OCFLAGB
GND_A2
GND_B2
A3
B3
C1
A2
B2
GND
4
+3P3V_HPD_OCFLAG
C7202
1u
GND
+3P3V_HPD
Imax=165uA
07132016
+3P3V_HPD
R7239
499K
GND
TP7204
3
2
1
GND
C C
B B
GND
+VCC_EDP_BKLT_IN
R7209 1K
R7208 1K
GND GND
+VCC_EDP_BKLT_IN
U7202
1
VCC
VIN
5
PWM
2
EN
6
A0
7
A1
4
SCL
3
SDA
FT
AGND_EP
MP3376AGR-0300
C7213
10u
OUT
LED8
LED7
LED6
LED5
LED4
LED3
LED2
LED1
NC22
NC19
NC17
PGND
BST
C7205
10u
18
20
SW
21
8
9
10
11
12
13
14
15
22
19
17
16
+VCC_BKLT
C7204
1u
GND
R7224
0
DNP
C7203
2.2u
DNP
10V
C7210
10u
GND GND GND
24
BKLT_PWM _R
BKLT_ENBKLT_EN_R
23
25
GND
7-bit I2C Address = 0x28
BKLT_BST
BKLT_FB8_R
BKLT_FB7_R
BKLT_FB6_R
BKLT_FB5_R
BKLT_FB4_R
BKLT_FB3_R
BKLT_FB2_R
BKLT_FB1_R
GND
L7201
10uH
R7231 0
R7230 0
R7223 0
R7222 0
R7221 0
R7220 0
R7219 0
R7218 0
BKLT_SW
BKLT_BST_SW
C7209
0.22u
R7229
47
BKLT_FB8 [57,76]
BKLT_FB7 [57,76]
BKLT_FB6 [57,76]
BKLT_FB5 [57,76]
BKLT_FB4 [57,76]
BKLT_FB3 [57,76]
BKLT_FB2 [57,76]
BKLT_FB1 [57,76]
C7206
2.2u
50V
GND GND GND
5
G
R7233
10K
S
6
R7227 0 0603
1/10W
DNP
R7228 0 0603
1/10W
2
G
Q7204A
D
4
R7207 10
C7218
1u
GND
1
S
R7203 0
R7210 0
BKLT_SCL
BKLT_SDA
R7226 0D NP
L_BKLT_CTRL_R
R7225
0
ALL
BKLT_PWM _R[76]
BKLT_EN[76]
+5VSB
SAM_PANEL_SCL[35]
SAM_PANEL_SDA[35]
Q7204B
3
D
+VCC_EDP_BKLT_OUT
Imax=0.16A
07132016
F7201 0.75A
C7208
C7207
2.2u
2.2u
50V
50V
+VCC_EDP_BKLT_OUT
PM_BKLT_IN+ [28]
0
R7241
DBG_T
R7216
5.1K
+VCC_EDP_BKLT_IN_DISC
3
D
G
S
4
GND
4
PM_BKLT_IN- [28]
+VCC_EDP_BKLT_IN
R7215
5.1K
+3P3VSB
+1P8VSB
R7238
R7242
0
R7256 0ALL
0
L_BKLT_CTRL_R
DNP
U7205
74AUP1G08GX
R7254
100K
2
1
PCH_LCD_BKLT_EN[10,34, 72]
PCH_BKLT_CTRL_PW M[10,72]
R7255
100K
ALL
GND GND
5
VCC
4
Y
A
B
3
GND
3
C7211
0.1u
10V
C7221 10u
DBG_T
R7240
C7216
0.1uF
47
DBG_T
R7217 0.02
DBG_TS
PTP7204
Q7202B
5
+VSYS
R7213
200K
GND
R7211 22KDNP
R7212
100K
DNP
SAM_LCD_BKLT_EN
A A
+3P3V_PANEL
C7215
1000p
+VCC_EDP_BKLT_IN_DRI
+VCC_EDP_BKLT_IN_R
5
R7235
GND
Q7203
2
S
1
0
ALL
C7214
0.1u
DNP
3
D
G
Q7202A
2
G
+VCC_EDP_BKLT_IN_REG
R7214
100K
6
D
S
1
GND
PTP7203
DNP
GND
+VCC_EDP_BKLT_IN_DRI_R
DG2723 AND MP3376 ARE 1.8V LOGIC ON EN, PWM AND I2C
+3P3VSB
C7220
0.1u
DNP
SAM_LCD_BKLT_EN[35]
PCH_LCD_BKLT_EN[10,34, 72]
SAM_BKLT_CTRL_PW M[3 5]
PCH_BKLT_CTRL_PW M[10,72]
GND
R7205
100K
GND
2
R7232
100K
DNP
GND
9
7
5
6
4
3
GND
ALL
VDD
HSD1p
HSD2p
HSD1m
HSD2m
GND
DG2723DN-T1-E4
DNP
R72340
U7204
Dp
Sp
Dm
Sm
BKLT_EN_MUX
1
8
L_BKLT_CTRL_MUX
2
10
R7236
47K
DNP
GND
BKLT_EN_R
R72500 DNP
R72510DNP
R7237 0DNP
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Proj ect Name Rev
Size Proj ect Name Rev
Size Proj ect Name Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
Date: Sheet of
Title:
Engineer:
Engineer:
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
L_BKLT_CTRL_R
PCH_SAM_INST_ON [23,34]
+3P3V_HPD/LCD backlight
+3P3V_HPD/LCD backlight
+3P3V_HPD/LCD backlight
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
72 82Tuesday, May 21, 2019
72 82Tuesday, May 21, 2019
72 82Tuesday, May 21, 2019
1
1.00
1.00
1.00
Page 73
5
D D
4
3
2
1
C C
B B
A A
PCIe GPU
PCIe GPU
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Proj ect Name Rev
Size Proj ect Name Rev
Size Proj ect Name Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
Title:
Engineer:
Engineer:
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
1
PCIe GPU
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
73 82Tuesday, May 21, 2019
73 82Tuesday, May 21, 2019
73 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 74
5
4
3
2
1
KBTP CONNECTOR
Pin1 Top Left
D D
KIP_SWD_C LK[29,76]
C C
BLADE_UART_DBG_EN[34]
KIP_FPC_DET_B#[58]
KIP_TRACE_SW O[29]
SAM_KIP_UART_TX[34,74,76]
PWRBTN #_3V3[31,58] SAM_KIP_UART_RX [34,74]
R7402
100K
DBG_D
R7427 100
+1P8VSB
C7405
1000p
D7413
A K
DNP
R74030
C7435
0.1u
6.3V
DBG_D
SAM_KIP_UART_RX[34,74]
SAM_KIP_UART_TX[34,74,76]
KIP_FPC_CONN_DET_B#
KIP_PWR_S W_N
D7405
D7409
A K
A K
DNP
DNP
+1P8VSB
GND
J7401
PINS REVERSED
2
2
4
4
6
6
8
8
10
10
12
12
14
MTG2
16
MTG4
DF40B-12DS-0.4V( 51)
U7410
8
VCC
7
1A
6
1B
3
2A
2
2B
SN74AUP2G08RSER
1
3
5
7
9
11
MTG1
MTG3
X912843-001
DBG_D
1
3
5
7
KIP_FPC_CONN_DET_A#
9
11
13
15
1Y
2Y
GND
D7408PESD3V3U1UL315
D7407PESD3V3 U1UL315
A K
A K
DNP
DNP
1
SAM_KIP_UART_RX_DBG [29,33]
5
SAM_KIP_UART_TX_DBG [29,33]
4
GND
R7401 0
R7421
499K
ALL
KIP_SWD_D IO [ 29]
SAM_KIP_RST# [29,35]
KIP_FPC_DET_A# [58]
D7414
PESD5V0F1USF315
DNP
+5V_KIP
A K
1P8V_KIP[76]
1P8V_KIP
C7403
0.1u10V
R7417 0
DNP
GND
R7418 0ALL
BGA4_2X2_P98XP98XP59_P5
VOUTA1VIN
GNDB1EN
DBG_D
GND
U7402
NX3P1108UK
KIP_LS_EN_R[76]
A2
B2
+1P8VA +1P8VSB
C7404
GND
R7414
R7415
0
0
ALL
DNP
1u6.3V
R74161K
KIP_LS_EN [35]
KIP UART Debug gated Sniffer (Dual AND gate, )
Place U7410 close to J7401 UART lines to minimize stubs
B B
A A
Blade Interface
Blade Interface
Blade Interface
Title:
Title:
Title:
<OrgAddr1>
<OrgAddr1>
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A2
A2
A2
EDAN_A_EV1
EDAN_A_EV1
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
1
<OrgAddr1>
1.00
1.00
74 82Tuesday, May 21, 2019
74 82Tuesday, May 21, 2019
74 82Tuesday, May 21, 2019
1.00
Page 75
5
D D
4
3
2
1
C C
B B
A A
Power Protect
Power Protect
Title:
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
W x H 357 x 231 mm
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
Power Protect
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
75 82Tuesday, May 21, 2019
75 82Tuesday, May 21, 2019
75 82Tuesday, May 21, 2019
1
1.00
1.00
1.00
Page 76
5
MTP7674
MTP7631
MTP7669
MTP7607
MTP7655
MTP7619
MTP7656
MTP7657
MTP7639
MTP7613
D D
MTP7671 MTP76113
MTP7690
MTP7659
MTP7684
MTP7667
MTP7638
MTP7687
MTP7651
MTP7612
MTP7675
MTP7629
MTP7682
C C
MTP7654
MTP7647
MTP7658
MTP7608
MTP7694
MTP7695
MTP7696
MTP7923
MTP7649
MTP7699
MTP7670
MTP7927
XDP_TCK [10,18]
XDP_TDI [10,18]
XDP_TDO [10,18]
XDP_TMS [10,18]
XDP_TRST# [10,18]
SPI_CLK_R1 [21]
SPI_MOSI_R1 [21]
SPI_MISO_R1 [21]
SPI_WP_IO2_R1 [21]
SPI_HOLD#_IO3_R1 [21]
SPI_CS#0_R [21]
EDP_I2C_INT [10,57]
KIP_SWD_CLK [29,74]
1P8V_KIP [74]
SAM_KIP_UART_TX [34,74]
PCH_TRST# [10,18]
PCH_JTAG_TCK [10,18]
PCH_JTAG_TDI [10,18]
PCH_JTAG_TDO [10,18]
PCH_JTAG_TMS [10,18]
PCH_JTAGX [10,18]
SAM_UEFIROM_EN [21,35]
PMI_I2C_SDA [25,28,33]
PMI_I2C_SCL [25,28,33]
BKLT_PWM_R [72]
BKLT_EN [72]
BKLT_FB8 [57,72]
BKLT_FB7 [57,72]
BKLT_FB6 [57,72]
BKLT_FB5 [57,72]
BKLT_FB4 [57,72]
BKLT_FB3 [57,72]
BKLT_FB2 [57,72]
BKLT_FB1 [57,72]
MTP7635
MTP7626
+1P1V_DDR_VDD2
MTP7604
MTP7679
MTP7625
MTP7681
MTP7648
MTP7627
MTP7636
MTP7652
MTP7693
MTP7634
4
+5V_KIP
PWR_SL1_F
+0P6V_DDR_VDDQ
+VCCPLL_OC
+3P3VSB
+5VSB
+VCCSTG
+VCC_RTC
+1P8VSB
+VCC1P8A
+1P8V_DDR_VDD1
MTP7606
MTP7691
MTP7614
MTP7644
MTP7672
MTP7661
MTP7664
MTP7645
MTP7620
MTP7677
MTP7628
MTP76100
MTP76101
MTP76110
MTP7642
MTP7663
MTP7617
MTP7697
MTP76104
MTP76173
MTP76174
RGB_LED_A_P [54]
RTD3_CAM_PWREN [25,54]
IRLED_C_N [54]
IRLED_A_P [54]
3P3_CAM [54]
CAM_IR_STB [54]
CAM_IR_STB_R [54]
SL1_EN_N [63]
SEN_HALL_INT#_S [34,54]
SEN_HALL_INT#_N [34,54]
PWRBTN#_1V8_FILT [31]
VOL_UP#_FILT [31]
VOL_DOWN#_FILT [31]
SAM_SWD_SWO [29,33,34]
SAM_SWD_CLK [29,33,34]
SAM_SWD_DIO [29,33,34]
SL1_HPD2_EN#_MTP
3
SL1_HPD2 [70,71]
SL1_HPD1A [70,71]
SL1_HPD1B [70,71]
BAT_LDO_PACK [70]
R7601 1K
SL1_HPD2_EN# [35,72]
+VDD_BATA_PACK
MTP7633
MTP7650
MTP7688
MTP7643
MTP7668
MTP76111
MTP7618
MTP7640
Place close to J7702
MTP7616
MTP7685
MTP76131
MTP76132
MTP76133
MTP76134
MTP76136
MTP76137
MTP76138
MTP76139
MTP76140
MTP76170
MTP76171
MTP76172
2
MTP7959
MTP7610
MTP7660
MTP7680
MTP76112
MTP7605
MTP7622
GND MTP Close to J5401
GND MTP Close to J5401
GND MTP close to U5505
GND MTP close to J5701
GND MTP close to J5701
GND MTP close to J5401
GND MTP close to J7701
GND MTP close to J7701
GND MTP close to J7701
GND MTP close to J7701
GND MTP close to J7701
GND MTP close to J7701
PWR_SL1
MTP76154
MTP76155
MTP76156
MTP76157
MTP76158
MTP76159
MTP76160
MTP76161
Place close to J7101
MTP76190
MTP76197MTP76135
1
MTP76162
MTP76163
MTP76164
MTP76165
MTP76166
MTP76167
MTP76168
MTP76169
Place Close(Under) to JP4001
H_PROCHOT# [10,26,63,66]
AGND
MTP7653
MTP7676
B B
MTP7609
MTP7602
MTP7666
MTP7673
MTP7630
MTP7683
MTP76122
MTP76123
MTP76124
MTP76125
MTP76129
MTP76130
A A
MTP76142
MTP76143
MTP76144
MTP76145
PMI1_I2C_SCL_R [28]
PMI1_I2C_SDA_R [28]
+3P3V_PANEL_EN [65]
PIO5_20 [33,35]
PIO5_21 [33,35]
SLG_PWRBTN# [58]
PCH_SENSOR_I2C_SDA [25,54]
PCH_SENSOR_I2C_SCL [25,54]
HP_MIC_LR_CON [41]
HPOUT_R_CON [41]
HPOUT_L_CON [41]
HPOUT_JD [40,41]
DMIC_DATA1_CODEC [40,54]
DMIC_CLK_CODEC [40,54]
SPK_R+_CON [41]
SPK_R-_CON [41]
SPK_L+_CON [41]
SPK_L-_CON [41]
5
MTP76114
MTP76115
MTP76116
MTP76117
MTP76118
MTP76119
MTP76120
MTP7621
MTP7637
MTP7665
MTP7603
MTP7632
MTP7692
MTP7624
+VBUS_P0_CONN
+VCC_EDP_BKLT_OUT
+1P8V_AUDIO
+VCCST_CPU
+VCCIN
4
MTP76176
MTP76182
MTP76183
MTP76184
MTP76185
MTP76186
MTP76187
+VCCIN_AUX
+5V_KIP
+1P8VA
+5V_AUDIO
MTP76141
MTP76146
MTP76147
MTP76148
MTP76149
MTP76150
MTP76151
MTP76152
MTP76153
+3P3V_PANEL
+VSYS
MTP76126
MTP76127
MTP76128
EXT_DC_IN
CON2_VBUS
+3P3VA
+3P3V
+3P3V_SSD_CON
SAM_RESET# [29,33,34,58]
USB2_USBA_DN_CONN [45]
USB2_USBA_DP_CONN [45]
TCP0_CONN_CC1 [77]
USB2_TCP0_CONN_A_DP [77]
USB2_TCP0_CONN_A_DN [77]
TCP0_CONN_SBU1 [77]
TCP0_CONN_SBU2 [77]
USB2_TCP0_CONN_B_DN [77]
USB2_TCP0_CONN_B_DP [77]
TCP0_CONN_CC2 [77]
3
+3P3V_BB0
MTP76191
MTP76192
MTP76193
MTP76194
MTP76196
In RAFLA this Signal will be pulled "LOW" via 1K resistor
MTP7646
MTP7698
MTP76102
MTP7662
MTP76103
MTP76105
MTP76106
MTP76107
MTP7615
MTP76108
MTP7689MTP76121
MTP76109
MTP76175
MTP76177
MTP76178
MTP76179
MTP76180
MTP76181
MTP76188
MTP76189
DDR_PGD_SIL [58]
+1P1V_DDR_PG [60]
EDP_I2C_SCL [57]
EDP_I2C_SDA [57]
SAM_PIO0_3 [34]
SAM_PIO0_4_ISP0 [34]
SAM_PIO0_5_ISP1 [34]
SAM_PIO0_6_ISP2 [34]
SAMRTS_PCHCTS [25,29,33,34]
TCON_VENDOR_ID [24,57]
PCHRTS_SAMCTS [25,29,33,34]
TP_CATERR#_R [10]
SL1_PSU_DET [34,70]
BATEN_PULSE_CONN [70]
BAT_SMCLK [70]
BAT_SMDATA [70]
BATA_DET#_CON [70]
BAT_SHUTDOWN# [33,58,70]
KIP_LS_EN_R [74]
KIP_EN [64]
PCH_DBG_TX [25,29,33]
PCH_DBG_RX [25,29,33]
SAM_DBG_TX [29,33,34,71]
SAM_DBG_RX [29,33,34,71]
FPC_DET_LOGIC_OVERRIDE# [33,58]
2
GND
Frames, Holes, & Mechanical
Frames, Holes, & Mechanical
Title:
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
W x H 427 x 276 mm
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
Frames, Holes, & Mechanical
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
76 82Tuesday, May 21, 2019
76 82Tuesday, May 21, 2019
1
76 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 77
5
TCP0_EE_DI
TCP0_EE_DO
TCP0_EE_CS#
TCP0_EE_CLK
+VCC3P3_LC_TCP0
R7727
10K
R7747
10K
R7744
D D
10K
10K
R7766
R7734
100 1%
0201S_P28-W35
+3P3VSB
TP7702
TP7707
TCP0_TDI
TCP0_TMS
TCP0_TCK
TCP0_TDO
TP7701
TP7708
TP7706
BB0_TEST_PWR_GOOD
TP7703 SP_TP_SMDP58
TP7705
SP_TP_SMDP58
D7701
A K
RB520CS3002L
U7700A
C6
EE_DI
B4
EE_DO
B6
EE_CS
C7
EE_CLK
A3
TDI
C3
TMS
B5
TCK
C5
TDO
M11
THERMDA
M12
TEST_EDM
B2
FUSE_VQPS_64
A11
MONDC
L12
MONDC_SVR
B3
TEST_PWR_GOOD
B11
TEST_EN
A1
ATEST_P
A2
ATEST_N
QUTZ 9999HF
M1111477-001
FLASH_BUSY
POC_GPIO_10
POC_GPIO_11
POC_GPIO_12
XTAL_25_OUT
3P3V_RT_FLASH
C7709
2.2u
I2C_SCL
I2C_SDA
I2C_INT
FORCE_PWR
POC_GPIO_5
POC_GPIO_6
PERST
SMBUS_SCL
SMBUS_SDA
RESET
XTAL_25_IN
RSENSE
RBIAS
C7747
0.22u
10V
GND
TCP0_EE_CS#
TCP0_EE_DO
C C
R7725
R7726
TP7711 SP_TP_SMDP58
TP7713
SP_TP_SMDP58
0201S_P28-W35
0
0201S_P28-W35
R7721 2.2K
0
R7722 3.32K
R7713 2.2K
1
2
3
4
9
U7702
CS#
SO/SIO1
WP#
GND
EPAD
VCC
HOLD#
SCLK
SI/SIO0
8
7
6
5
MX25L8006EZUI-12G
+3P3V
BB0_POC_GPIO_6
R7714
10K
+3P3V_BB0
BB_FORCE_PWR
BB0_FLASH_SHARE_EN
R7739 10K
TCP0_I2C_SCL_R
C9
E7
A10
B10
A9
B9
A8
A4
A5
A6
B8
A7
B7
L11
L9
M9
L5
L4
BB0_RESET#
TCP0_I2C_SDA_R
TCP0_I2C_INT#_R
BB0_FORCE_PWR_R
BB0_POC_GPIO_5
BB0_POC_GPIO_6
BB0_FLASH_SHARE_EN
BB0_FLASH_MASTER
BB0_POC_GPIO_12
BB0_PERST#_R
DNP
R7704 0
R7705 0
R7706 0
R7757 0
R7761 0
1M
R7701
0201S_P28-W35
R7765
TCP0_XTAL_25_OUT
TCP0_XTAL_25_IN
C7707
PD_SML0_SCL [25]
PD_SML0_SDA [25]
18p
ALL
0201S_P33
R7712 4.75K
TP7712
SP_TP_SMDP58
TP7710
SP_TP_SMDP58
R7720 3.32K
R7723
0201S_P28-W35
R7724
0201S_P28-W35
TBT_LSX0_TXD[10]
TBT_LSX0_RXD[10]
R7743
DNP
R7703
DNP
1M
1M
0
0
0201S_P28-W35
0201S_P28-W35
TCP0_EE_CLK
TCP0_EE_DI
TCP0_TX_P0[10]
TCP0_TX_N0[10]
TCP0_TXRX_P0[10]
TCP0_TXRX_N0[10]
TCP0_TX_P1[10]
TCP0_TX_N1[10]
TCP0_TXRX_P1[10]
TCP0_TXRX_N1[10]
TCP0_AUX_DP[10]
TCP0_AUX_DN[10]
R7738 10K ALL
BB0_FLASH_MASTER
R7719 10K DNP
B B
BB0_POC_GPIO_12
BB0_POC_GPIO_5
R7737
10K
DNP
R7767 10K DNP
R7752 10K
BB0_POC_GPIO_12: Has internal PU
BB_FORCE_PWR:
'0' - By default
'1' - For debug only/FW update
BB0_FLASH_SHARE_EN (internal-PU)
'0' - Flash isn't shared, 1 flash per re-timer
'1' - Flash is shared between 2 re-timers
BB0_FLASH_MASTER (internal-PU)
'0' - Set re-timer to be slave on shared flash SPI I/F
'1' - Set re-timer to be master on shared flash SI I/F
0201S_P28-W35
0
0201S_P28-W35
Y7701
2 4
GND
ALL
25MHz
4
TP7714
TP7715
TP7716
PD_I2C2_SCL [21,79]
PD_I2C2_SDA [21,79]
PD_BB_I2C2_INT# [22,79]
BB_FORCE_PWR [10,79]
BB_PERST# [22]
BB0_PD_RESET# [79]
31
R7755 100
C7734
0.22u
C7730
0.22u
C7736
C7733
C7722
C7732
C7729
C7726
R7748 0
R7707 0
TCP0_TXRX_C_P0
0.22u
TCP0_TXRX_C_N0
0.22u
0.22u
0.22u
TCP0_TXRX_C_P1
0.22u
TCP0_TXRX_C_N1
0.22u
TCP0_AUX_DP_R
TCP0_AUX_DN_R
+3P3VSB
10K
R7710
18p
ALL
0201S_P33
TCP0_TX_C_P0
TCP0_TX_C_N0
TCP0_TX_C_P1
TCP0_TX_C_N1
10u
0402S_P7-W70
C7713
J1
J2
G1
G2
C1
C2
E1
E2
M7
L7
L8
M8
C7712
6.3V
U7700D
ASSRXP1
ASSRXN1
ASSTXP1
ASSTXN1
ASSRXP2
ASSRXN2
ASSTXP2
ASSTXN2
PA_LSTX_SBU1
PA_LSRX_SBU2
PA_AUX_P
PA_AUX_N
QUTZ 9999HF
M1111477-001
TCP0_DBG0_A_DP[29]
TCP0_DBG1_A_DN[29]
BSSRXP1
BSSRXN1
BSSTXP1
BSSTXN1
BSSRXP2
BSSRXN2
BSSTXP2
BSSTXN2
BSBU1
BSBU2
3
+3P3V_BB0
R7717 0
VCCP3P3_SVR_TCP0
A12
B12
D11
D12
J5
J6
L3
B1
D1
D2
F1
F2
F7
F9
F11
U7700C
NC1
NC2
NC3
NC4
VSS_ANA_1
VSS_ANA_2
VSS_ANA_3
VSS_ANA_4
VSS_ANA_5
VSS_ANA_6
VSS_ANA_7
VSS_ANA_8
VSS_ANA_9
VSS_ANA_10
VSS_ANA_11
QUTZ 9999HF
M1111477-001
Use 25V cap on the connector side to protect pin short to VBUS
J12
J11
G12
G11
C12
C11
E12
E11
M10
L10
TCP0_TXRX_RT_P0
TCP0_TXRX_RT_N0
TCP0_TX_RT_P0
TCP0_TX_RT_N0
TCP0_TXRX_RT_P1
TCP0_TXRX_RT_N1
TCP0_TX_RT_P1
TCP0_TX_RT_N1
TCP0_BB_SBU1 [29]
TCP0_BB_SBU2 [29]
R7749 0
R7750 0
R7768 2.2
R7769 2.2
R7770 2.2
R7771 2.2
R7772 2.2
R7773 2.2
R7774 2.2
R7775 2.2
TCP0_DBG0_A_DP_R
TCP0_DBG1_A_DN_R
TCP0_TXRX_RT_P0_RC
TCP0_TXRX_RT_N0_RC
TCP0_TX_RT_P0_RC
TCP0_TX_RT_N0_RC
TCP0_TXRX_RT_P1_RC
TCP0_TXRX_RT_N1_RC
TCP0_TX_RT_P1_RC
TCP0_TX_RT_N1_RC
D7703
D7710
D7707
A1 A2
A1 A2
A1 A2
ESDL2011PFCT5G
ESDL2011PFCT5G
VSS_ANA_12
VSS_ANA_13
VSS_ANA_14
VSS_ANA_15
VSS_ANA_16
VSS_ANA_17
VSS_ANA_18
VSS_ANA_19
VSS_ANA_20
VSS_ANA_21
VSS_ANA_22
D7716
D7711
A1 A2
A1 A2
ESDL2011PFCT5G
ESDL2011PFCT5G
4
L7708
1
ALL
2 3
1 4
RN7704 0 DNP
VSS_1
VSS_2
VSS_3
A1 A2
ESDL2011PFCT5G
3
2
TCP0_CONN_SBU2[76]
USB2_TCP0_CONN_B_DN[76]
USB2_TCP0_CONN_B_DP[76]
TCP0_CONN_CC2[76]
D7718
ESDL2011PFCT5G
DLP11TB800UL2L
F3
F5
G5
F12
G7
H1
H11
H12
H2
J9
K1
K11
K12
K2
C7719 0.33u 25V 0201
C7721 0.33u 25V 0201
C7720 0.22u 25V 0201
C7718 0.22u 25V 0201
C7738 0.33u 020125V
C7745 0.33u 020125V
C7737 0.22u 020125V
C7743 0.22u 020125V
D7712
D7714
A1 A2
A1 A2
ESDL2011PFCT5G
ESDL2011PFCT5G
TCP0_CC1[79]
TCP0_CC2[79]
TCP0_SBU1[29]
TCP0_SBU2[29]
USB2_TCP0_CONN_A_DP
USB2_TCP0_CONN_A_DN
D7721 PESD5V0H1BSF
K1K2
D7720 PESD5V0H1BSF
K1K2
2
+3P3V_PD_OUT
C7708
6.3V
1u
0201S_P35-W35
0201S_P28-W35
R7709 100K
TCP0_SBUEN TCP0_FLG
U7703
A3
VSYS
A2
CC1
B2
CC2
C2
SBU1
D2
SBU2
D3
SBUEN
B3
GND
NX20P0407UK
CON_CC1
CON_CC2
CON_SBU1
CON_SBU2
FLAG
GND
TCP0_TX_CONN_P0
TCP0_TX_CONN_N0
TCP0_CONN_CC1[76]
USB2_TCP0_CONN_A_DP[76]
USB2_TCP0_CONN_A_DN[76]
TCP0_CONN_SBU1[76]
TCP0_TXRX_CONN_N1
TCP0_TXRX_CONN_P1
TCP0_TXRX_CONN_P0
TCP0_TXRX_CONN_N0
TCP0_TX_CONN_N1
TCP0_TX_CONN_P1
TCP0_CONN_CC1
USB2_TCP0_CONN_A_DP
USB2_TCP0_CONN_A_DN
TCP0_CONN_SBU1
R7777 220K
R7779 220K
R7776 220K
R7780 220K
R7778 220K
R7781 220K
DNP
DNP
DNP
R7784 220K
DNP
A1
B1
C1
D1
C3
ALL
R7783 220K
R7711 100K
K1K2
K1K2
PESD24VF1BL
D7702
PESD24VF1BL
D7708
ALL
0201S_P28-W35
+VBUS_P0_CONN
TCP0_CONN_SBU2
USB2_TCP0_CONN_B_DN
USB2_TCP0_CONN_B_DP
TCP0_CONN_CC2
DNP
DNP
100p
C7725
10%
100p
C7724
10%
K1K2
ALL
D7709
PESD24VF1BL
TCP0_CONN_CC1
TCP0_CONN_CC2
TCP0_CONN_SBU1
TCP0_CONN_SBU2
R7708 1M
0201S_P28-W35
K1K2
ALL
D7715
PESD24VF1BL
R7702 1M
0201S_P28-W35
J7701
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
M1084960-001
D7717
A K
GND_A1
TX1p
TX1m
VBUS_A4
CC1
Dp_A
Dm_A
SBU_A
VBUS_A9
RX2m
RX2p
GND_12
GND_B12
RX1p
RX1m
VBUS_B9
SBU_B
Dm_B
Dp_B
CC2
VBUS_B4
TX2m
TX2p
GND_B1
R7756
39.2K
0201 1%
PTVS24VS1UR
1
1
MTG1
2
MTG2
3
MTG3
4
MTG4
5
MTG5
6
MTG6
7
MTG7
8
MTG8
9
MTG9
10
MTG10
11
MTG11
35V
C77060.1u
0.1u
C7717
35V
C7711
0.1u
0.1u
35V
C7710
35V
C7748
0.22u
10V
+VCC3V3A_TCP0
C7759
47u
0805S_1P45
6.3V
+VCC3V3_TCP0
C7735
2.2u
0201S_P39-W39
0201S_P39-W39
R7782 00603
4
2.2u
C7714
2.2u
0201S_P39-W39
+3P3V_DEBUG
U7704
D1+
D2+
D1D2-
S
OE
VCC
GND
USB2_TCP0_CONN_B_DP
USB2_TCP0_CONN_B_DN
D7719 PESD5V0H1BSF
K1K2
D7722 PESD5V0H1BSF
K1K2
C7750
0.1u
9
10V
3
D+
5
D-
4
USB2_TCP0_DP [24]
USB2_TCP0_DN [24]
20160609sjs1551
title is: Blank_602x390
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
WxH 602 x 390mm
Title:
Engineer:
Engineer:
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
1
Report errors to Steven
Report errors to Steven
Blank_602x390
Blank_602x390
Blank_602x390
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
77 94Tuesday, May 21, 2019
77 94Tuesday, May 21, 2019
77 94Tuesday, May 21, 2019
1.00
1.00
1.00
TCP0_DBG2_B_DP[29]
TCP0_DBG3_B_DN[29]
R7753 0
R7754 0
TCP0_DBG2_B_DP_R
TCP0_DBG3_B_DN_R
4
L7707
1
ALL
2 3
1 4
3
2
DLP11TB800UL2L
RN7703 0 DNP
C7704
L7706
0.68uH
+VCC3V3A_TCP0
+VCC0V9_SVR_TCP0
C7758
47u
0603
C7727
18p
C7740
C7739
2.2u
C7741
2.2u
2.2u
C7744
C7742
2.2u
C7746
2.2u
2.2u
+3P3V_DEBUG
R7758
100K
1%
0201
PD_USB2_MUX_FLIP[ 79]
USB2_TCP_MUX_EN#
1
2
7
6
10
8
TS3USB30E
U7704 Layout Short during PV/DV
D
R7759
100K
1%
0201
G
Q7701
S
3
C7752
MUX0_EN#[29]
10u
C7703
2.2u
6.3V
C7702
0402S_P7-W70
DNP
18p
20%
+3P3V_BB0
+VCC3V3_TCP0
R7732 00603
6.3V
+VCC0V9_SVR_TCP0
U7700B
L2
VCC3P3_ANA
E5
VCC3P3_LC
E3
VCC0P9_SVR_1
G3
VCC0P9_SVR_2
E9
VCC0P9_SVR_PB_ANA_1
G9
VCC0P9_SVR_PB_ANA_2
F6
VCC0P9_SVR_ANA_1
G6
VCC0P9_SVR_ANA_2
J3
VCC0P9_LC
L6
VCC0P9_LVR
M6
VCC0P9_LVR_SENSE
QUTZ 9999HF
M1111477-001
5
VCC3P3_SX
VCC3P3_SVR_1
VCC3P3_SVR_2
VCC3P3A
SVR_IND_1
SVR_IND_2
SVR_VSS_1
SVR_VSS_2
E6
M4
M5
J7
L1
M1
M2
M3
C7731
2.2u
GND
+VCC0P9_SVR_TCP0_PHASE
+VCC3P3_LC_TCP0
+VCC3P3_ANA_TCP0
C7705
2.2u
A A
C7715
2.2u
+VCC0P9_LC_TCP0
+VCC0P9_LVR_TCP0
C7723
2.2u
C7701
2.2u
C7749
10u
0402S_P7-W70
Page 78
5
D D
4
3
2
1
C C
B B
A A
Blank
Blank
Blank
Title:
Title:
Title:
<OrgAddr1>
<OrgAddr1>
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
WxH 602 x 390mm
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
1
<OrgAddr1>
1.00
1.00
78 94Tuesday, May 21, 2019
78 94Tuesday, May 21, 2019
78 94Tuesday, May 21, 2019
1.00
Page 79
5
4
3
2
1
+5VSB
+3P3VSB
D D
DBG_N
R7985 0
U7908
VCC
SAM_3P3V_PD_EN[35]
PD_SAM_DBG_ACC_MODE[29,37,79]
R7983
100K
1%
0201
DBG_D
C C
2
A
1
B
74LVC1G32GX
M1004687-001
DBG_D
R7982
100K
1%
0201
DBG_D
GND
PD_SAM_INT#[34]
+3P3VA
PLACE
ONE CAP
R7973 0
R7974 0
DNP
+1P8VA
C7921
C7945
0.1u
5
4
Y
3
10V
DBG_D
3P3V_PD_EN
+1P8VA +3P3V_PD_OUT
1u
0201
20%
TP7909 R7931 0DNP
R7977 1K
R7970
100K
1%
0201
R7981
R7925
10K
ALL
G
D
Q7901
SOTFL-3_1P3XP9XP55_P4
10K
S
R7975 0
DNP
U7907
A2
VIN
B2
EN
NX3P1108UK
SAM_PD_SDA[18,29,33,35]
SAM_PD_SCL[18,29,33,35]
R7980
100K
1%
0201
A1
VOUT
B1
GND
0201S_P28-W35
R7904
10K
R7960 0.1DBG_TS
0603
+1P8V_PD_OUT
R7905
10K
0201S_P28-W35
TP7904
TP7908
TP7906
PER PIN
C7908
10u
6.3V
0402S_P7-W70
SAM_SL1_PWR_EN[35,63]
BB0_PD_LS_EN[65]
DBG_TS 0603S_P6-W100
R7957 0.01
+
C7943
150u
+5VSB
4.7u
10V
20%
C7911
3P3V_PD_VIN_R
SAM_PD_HRESET[35]
BB0_PD_RESET#[77]
PD_SAM_DBG_ACC_MODE[29,37,79]
PD_SPI_MISO
PD_SPI_MOSI P0_SPI_MOSI_R
PD_SPI_CLK
PD_SPI_SS# P0_SPI_SS#_R
PD_USB2_MUX_FLIP[ 77]
TP7902
TP7901
TP7912
PD_I2C2_SDA[21,77]
PD_I2C2_SCL[21,77]
PD_BB_I2C2_INT#[22,77]
R7913 0
0201S_P28-W35
R7908 0
R7909 0
R7907 0
R7956 0
TCP0_OC#[24]
TP7910
TP7911
R7918 0TP7907
USB_PD_GPIO16
USB_PD_GPIO17
BC_PROCHOT#[26]
BB_FORCE_PWR[10,77]
EXT_DC_IN
C7909
4.7u
20%
10V
PD_ADCIN1
PD_ADCIN2
SAM_SL1_PWR_EN_PD
P0_SPI_MISO_R
P0_SPI_CLK_R
PD_PROCHOT#
C7919
+
DNP
11-12
1-2
C7944
22u
10u
25V
35V
Place C7919 close to U7902
U7902
PP_HV1
PP_HV2
25
PP_CABLE
5
VIN_3V3
44
HRESET
6
ADCIN1
10
ADCIN2
16
GPIO0
17
GPIO1
18
GPIO2
30
HPD/GPIO3
31
GPIO4
21
I2C3_SCL/GPIO5
22
I2C3_SDA/GPIO6
23
I2C3_IRQ*/GPIO7
28
I2C1_SDA
27
I2C1_SCL
33
I2C2_SDA
32
I2C2_SCL
29
I2C1_IRQ*
34
I2C2_IRQ*
36
SPI_MISO/GPIO8
37
SPI_MOSI/GPIO9
38
SPI_CLK/GPIO10
39
SPI_SS*/GPIO11
40
GPIO12
41
GPIO13
42
GPIO14/PWM
43
GPIO15/PWM
48
GPIO16/PEXT1
49
GPIO17/PEXT2
PTPS65987DDJRSHR
C7906
VBUS1
VBUS2
LDO_1V8
LDO_3V3
C_CC1
C_CC2
C_USB_P/GPIO18
C_USB_N/GPIO19
GPIO20
GPIO21
DRAIN2_1
DRAIN2_2
DRAIN2_3
DRAIN2_4
DRAIN1_1
DRAIN1_2
DRAIN1_3
DRAIN1_4
GND1
GND2
GND3
GND4
GND5
MPAD_GND
1u
25V
C7913
1u
25V
13-14
3-4
35
9
24
26
50
53
54
55
7
52
56
57
8
15
19
58
20
45
46
47
51
59
D7905
RB520CS3002L
A K
+VBUS_P0_CONN
C7910
10u
0402S_P7-W70
ALL
R7962 0.01
0402S_P5-W65
6.3V
+3P3V_PD_OUT +1P8V_PD_OUT
C7901
4.7u
0402S_P65-W65
20% 10V
ALL
TCP0_CC1 [ 77]
TCP0_CC2 [ 77]
R7930 to guarantee MISO is
high for PD controller to
detect SPI flash
C7903220p
C7912220p
ALL
PD_SPI_SS#
PD_SPI_MISO
10K
R7930
DNP
10K
10K
R7910
R7906
10K
R7902
U7901
1
CS#
2
SO/SIO1
3
WP#
4
GND
9
EPAD
W25X05CLUXIGTR
VCC
HOLD#
SCLK
SI/SIO0
+3P3V_PD_OUT
8
7
PD_SPI_CLK
6
PD_SPI_MOSI
5
C7920
0.1u
10V
10K
R7903
+3P3V_PD_OUT
R7901
need double check ADCIN1 setting
B B
BB0_PD_RESET#
+3P3V_BB0
R7919
10K
+3P3VSB
ALL
R7921
49.9K
ADCIN1: EXTERNAL BUS POWER
DNP
ADCIN2: I2C SETTINGS
2K
R7912
12.1K
R7945
100K
DNP
PD_ADCIN1
PD_ADCIN2
R7911
0
7-BIT I2C ADDRESS
I2C1 - 0X20
10K
10K
10K
ALL
ALL
ALL
R7953 10K ALL
49.9K
49.9K
DNP
DNP
R7952
R7924
PD_BB_I2C2_INT#
SAM_PD_HRESET
TCP0_OC#
BB0_PD_LS_EN
A A
R7933
R7920
R7934
I2C2- 0X38
PD_USB2_MUX_FLIP
5
R7968
49.9K
ALL
Type C Power
Type C Power
Type C Power
Title:
Title:
Title:
<OrgAddr1>
<OrgAddr1>
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
4
3
2
WxH 602 x 390mm
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
1
<OrgAddr1>
1.00
1.00
79 82Tuesday, May 21, 2019
79 82Tuesday, May 21, 2019
79 82Tuesday, May 21, 2019
1.00
Page 80
5
4
3
2
1
D D
MP8005
M1100762-001
H8001
1
MH3.8x2.5d
H8003
1
1
MTG_HOLE_4.3padx3drill
H8002
1
1
MTG_HOLE_4.3padx3drill
H8004
1
C C
1
MTG_HOLE_4.3padx3drill
H8005
1
1
MTG_HOLE_4.3padx3drill
H8007
1
1
MTG_HOLE_4.3padx3drill
H8008
1
1
MTG_HOLE_4.3padx3drill
X8001
SHIELD
1
2
3
4
M1110426-001
ZID = 000
ZOD = 000
SHIELD,FENCE,SM,T1
X8004
SHIELD
1
M1110432-001
ZID = 00
ZOD = 00
SHIELD,FENCE,SM,T4
MP8003
1
1
M1110434-001
MP8001
1
1
M1110434-001
X8002
SHIELD
1
2
3
4
5
M1110427-001
ZID = 000
ZOD = 000
SHIELD,FENCE,SM,T2
X8005
SHIELD
1
M1110815-001
ZID = 00
ZOD = 00
SHIELD,FENCE,T5,SM
MP8004
1
M1110435-001
MP8002
1
M1110435-001
X8006
SHIELD
1
M1110816-001
ZID = 00
ZOD = 00
SHIELD,FENCE,T6,SM
1
1
X8003
SHIELD
1
2
3
4
5
6
7
8
9
10
M1110429-001
ZID = 000
ZOD = 000
SHIELD,FENCE,SM,T3
H8009
1
1
3.00X6.00 MM SLOT
H8010
1
1
3.00X5.00 MM SLOT
H8011
1
1
3.00X4.90 MM SLOT
H8012
NP
NO-MSPN-00324
1
X8007
SHIELD
1
2
3
M1110431-001
ZID = 000
ZOD = 000
SHIELD,FENCE,SM,T7
B B
A A
X8008
SHIELD
1
M1110425-001
ZID = 00
ZOD = 00
SHIELD,FENCE,SM,B1
Mechanical
Mechanical
Mechanical
Title:
Title:
Title:
<OrgAddr1>
<OrgAddr1>
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
WxH 602 x 390mm
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
1
<OrgAddr1>
1.00
1.00
80 82Tuesday, May 21, 2019
80 82Tuesday, May 21, 2019
80 82Tuesday, May 21, 2019
1.00
Page 81
5
D D
4
3
2
1
C C
B B
A A
ACC Radio
ACC Radio
Title:
Title:
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Title:
Engineer:
Engineer:
Engineer:
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
1
ACC Radio
<OrgAddr1>
<OrgAddr1>
<OrgAddr1>
81 82Tuesday, May 21, 2019
81 82Tuesday, May 21, 2019
81 82Tuesday, May 21, 2019
1.00
1.00
1.00
Page 82
5
D D
4
3
2
1
C C
B B
A A
Holes, Shields & Fences
Holes, Shields & Fences
Holes, Shields & Fences
Title:
Title:
Title:
<OrgAddr1>
<OrgAddr1>
<OrgName>
<OrgName>
<OrgName>
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
WxH 602 x 390mm
EDAN_A_EV1
EDAN_A_EV1
EDAN_A_EV1
Engineer:
Engineer:
Engineer:
1
<OrgAddr1>
1.00
1.00
82 82Tuesday, May 21, 2019
82 82Tuesday, May 21, 2019
82 82Tuesday, May 21, 2019
1.00
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