Microsemi Corporation LX1668CPW, LX1668CDW Datasheet

LIN DOC #:
1668
LX1668
PROGRAMMABLE MULTIPLE OUTPUT DC:DC CONTROLLER
T HE I NFINITE P OWER OF I NNOVATION
DESCRIPTION KEY FEATURES
The LX1668 is a Monolithic Switching Regulator Controller IC designed to pro-
vide a low cost, high performance adjustable power supply for advanced microprocessors and other applications requiring a very fast transient response and a high degree of accuracy. It provides a programmable switching regulator output, together with one internal linear low dropout regulator and one adjustable linear regulator driver. The LX1668 offers a triple-output single-chip power sup­ply for Pentium
®
II and other processors.
Programmable Synchronous Rectifier
Driver for CPU Core. The main output is
adjustable from 1.3 to 3.5V using a TTL­compatible 5-bit digital code to meet Intel specifications. The IC can read the signal from a DIP-switch, hardwired to Pentium II processor’s pins or from software. The 5-bit code adjusts the output voltage between 1.30 and 2.05V in 50mV increments, and between
2.0 and 3.5V in 100mV increments. The device can drive dual MOSFET’s resulting in typical efficiencies of 85 – 90%, even with loads in excess of 10A.
NOTE: For current data & package dimensions, visit our web site: http://www.linfinity.com.
Internal Low Dropout [LDO] Regulator
provides a fixed 2.5V output for powering the clock circuit at up to 250mA.
External Linear Regulator Driver out­put can be connected to a MOSFET to provide a high-current adjustable LDO function suit­able for supplying the GTL+ bus circuitry on a Pentium II processor motherboard at 1.5V.
Short-circuit Current Limiting without Expensive Current Sense Resistors. The
current sensing mechanism can use a PCB trace resistance or the parasitic resistance of the main inductor. For applications requiring a high degree of accuracy, a conventional sense resistor can be used.
Ultra-Fast Transient Response Re­duces System Cost. The fixed frequency
modulated off-time architecture results in the fastest transient response for a given inductor. Small Package Size. The LX1668 is available in an economical 20-pin wide body SOIC or a space-saving 20-pin TSSOP package.
P RODUCTION DAT A SHEET
5-Bit Programmable Output For CPU Core
Supply
Internal Fixed 2.5V Low Dropout Regulator
Adjustable Linear Regulator Driver
Complete Single-Chip Power Solution For
No Sense Resistor Required For Short-Circuit
Current Limiting
Soft-Start And Hiccup-Mode Current Limiting
Functions
Modulated Constant Off-Time Control
Mechanism For Fast Transient Response And Simple System Design
Power Good Flag
Over-Voltage Pin & SCR
Digital-Compatible Inputs (Including VID Pins)
Output Disable Function Shuts Off PWM While
Keeping 2.5V LDO Active - Compatible With "Green PC" And "Instant On" Requirements
Compatible to VRM8.2 - 8.4 Specifications
APPLICATIONS
Pentium II & Pentium III Processor Supplies
Voltage Regulator Modules
General Purpose And Microprocessor DC:DC
Supplies
PRODUCT HIGHLIGHT
5V
L2
1µH
PGND
BDRV AGND SS/EN
V
V
CORE
PWRGD
OVP VID4 VID3
C2
L1
2.5µH
Q2
IRL3303
1500µFx3
2.5m
R
SENSE
Q1
IRL3102
20
19
18
17
C
0.1µF
SS
16
FB
15
14
13
12
11
PWRGD
VID4 VID3 VID2 VID1
V
OUT2
2.5V
3.3V
V
OUT3
1.5V
C5
22µF
330µF
C8
1µF
C4
C6
330µF
C3
1µF
C9
1µF
R1, 0
R2, 50k
Q3
IRLZ44
12V
C7
1µF
1
TDRV
2
V
CC12
3
V
CC5
4
V
OUT2
5
V
CC3
L
DRV
L
FB
VID0 VID1 VID2
LX1668
6
7
8
9
10
VID0
PACKAGE ORDER INFORMATION
T
(°C)
A
Plastic SOWB
DW
20-pin
Plastic TSSOP
PW
20-pin
0 to 70 LX1668CDW LX1668CPW
Note: All surface-mount packages are available in Tape & Reel, append the letter "T" to part number. (i.e. LX1668CPWT)
2N6504
R3 10k
3.3V / 5V
Q4*
SCR
CPU Core
V
CORE
C1
1500µF x 6
*
Q4 optional
OVP crowbar
Copyright © 1999 Rev. 1.0 4/99
L INF INITY MICROELECTRONICS INC.
11861 WESTERN AVENUE, GARDEN GROVE, CA. 92841, 714-898-8121, FAX: 714-893-2570
1
LX1668
PRODUCT DATABOOK 1996/1997
PROGRAMMABLE MULTIPLE OUTPUT DC:DC CONTROLLER
RODUCTION DATA SHEET
P
ABSOLUTE MAXIMUM RATINGS (Note 1 & 2)
12V Supply Voltage (V 5V Supply Voltage (V Supply Voltage (Internal LDO)/(V
Output Drive Peak Current Source (500ns)....................................................... 1.0A
) .................................................................................. 18V
CC12
) ....................................................................................... 7V
CC5
) ................................................................... 7V
CC3
Output Drive Peak Current Sink (500ns) ........................................................... 1.0A
Input Voltage (SS, VID[0:4]) ................................................................... -0.3V to 6V
Operating Junction Temperature .................................................................... 150°C
Storage Temperature Range ........................................................... -65°C to +150°C
Lead Temperature (Soldering, 10 Seconds) .................................................... 300°C
Note 1. Exceeding these ratings could cause damage to the device. All voltages are with
Note 2. V
respect to Ground. Currents are positive into, negative out of the specified terminal.
supply is used as input to internal low dropout regulator. Voltages above
CC3
3.3V will cause increased thermal dissipation in the package. Power dissipation should be limited to keep junction temperature below maximum rating.
THERMAL DATA
DW PACKAGE:
D
x θ
θθ
θ
θθ
JA
θθ
θ
θθ
JA
).
JA
85°C/W
110°C/W
THERMAL RESISTANCE-JUNCTION TO AMBIENT,
PW PACKAGE:
THERMAL RESISTANCE-JUNCTION TO AMBIENT,
Junction Temperature Calculation: TJ = TA + (P The θ
numbers are guidelines for the thermal performance of the device/pc-board
JA
system. All of the above assume no ambient airflow.
PACKAGE PIN OUTS
TDRV
V
V
VID0 VID1 VID2
DW PACKAGE — 20-Pin
TDRV
V
CC12
V
CC5
V
OUT2
V
CC3
L
DRV
L
FB
VID0 VID1 VID2
PW PACKAGE — 20-Pin
1 20 219
CC12
V
318
CC5
417
OUT2
V
516
CC3
L
615
DRV
L
714
FB
813 912 10 11
(Top View)
1 20 219 318 417 516 615 714 813 912 10 11
(Top View)
PGND BDRV AGND SS/ENABLE V
FB
V
CORE
PWRGD OVP VID4 VID3
PGND BDRV AGND SS/ENABLE V
FB
V
CORE
PWRGD OVP VID4 VID3
2
Copyright © 1999
Rev. 1.0 4/99
PRODUCT DATABOOK 1996/1997
PROGRAMMABLE MULTIPLE OUTPUT DC:DC CONTROLLER
P RODUCTION DAT A SHEET
ELECTRICAL CHARACTERISTICS
(
Unless otherwise specified, 4.75V < V
T = 25°C.
)
Parameter
Reference & DAC
Initial Accuracy V
Cumulative Regulation Accuracy 1.3V ≤ V
Timing
Off Time OT V Swicthing Frequency Freq V
Error Comparator / CS-
Input Bias Current I
E
Delay to Output Overdrive 5mV
C
Current Sense +
Input Resistance R Pulse By Pulse Current Limit V
Current Sense Delay To Output Overdrive 5mV
Output Drivers
Drive Rise Time, Fall Time T Drive High V
Drive Low V
UVLO and Soft-Start (SS)
V
Start-Up Threshold V
CC5
Hysteresis
SS Resistor R
SS Output Enable V Hiccup Duty Cycle DC
Supply Current
V
Dynamic Supply Current I
CC12
Static Supply Current 12V I
5V I
3.3V I
Power Good / Over-Voltage Protection (OVP)
Threshold (V
Hysteresis Power Good Voltage Low I
Over-Voltage Threshold (V OVP Sourcing Current V
Fixed Linear Regulator (V
OUT2
Voltage Reference Tolerance V
Regulation -10mA ≤ I
Current Limit V
Linear Regulator Controller
Voltage Reference Tolerance V Source Current I
Sink Current I
VID Pins
Low Input VILInternally pulled up to V
High Input V
< 5.25V and 10.8V < V
CC5
Symbol
CORE
FB
CORE
CLP
RF
DHISOURCE
DLISINK
ST
SS
EN
HICCSS
CD
VCC12VSS
VCC5VSS
VCC3VSS
)
LDRVILDRV
LDRV
IH
< 13.2V, 0°C ≤ TA 70°C. Test conditions: V
CC12
Test Conditions
(Less 40mV output adaptive positioning)
3.5V
CORE
= 2.0V
CORE
= 1.3V to 3.5V
CORE
1.0V < VSS = VFB < 3.5V
0V < VFB = V
CL = 3000pF
= 20mA
= 20mA
V
> 3.9V
CC12
= 0.1µF, V
Out Freq = 200kHz, CL = 3000pF, Synch., VSS > 0.5V
< 0.5V
< 0.5V
< 0.5V
/ V
CORE
(V
/ V
CORE
= 4mA
PWRGD
/ V
CORE
= 2.0V
OVP
= 2.5V, C
OUT2
2V
OUT2
= 1.5V, C
LFB
flows from V
) V
SET
) V
SET
), V
SET
OUT2
< 3.5V
CORE
= 2.00V, F
DAC
rising, V
CORE
falling, V
CORE
rising
CORE
= 220µF
OUT
-150mA
= 330µF
OUT
CC12
= 100Hz
REQ
OUT2
OUT2
thru 30k
CC5
2.0V
2.0V
,
1.3V ≤ V
35V, T = 25°C
CORE
LX1668
= V
, V
CC3
Min. Typ. Max.
-1 +1 %
-1.5 1.5 %
45 60 mV
10 11 V
3.9 4.2 4.6 V
0.4 0.5 V
108 110 111 %
90 91 92 %
110 117 125 %
35 60 mA
-2.3 +2.0 %
-1 +1 %
250 mA
-2.3 +1.5 % 30 mA
2.0 V
= 5V, V
CC5
CC5
CC12
LX1668
2.4 µs
250 kHz
-0.3 -1 µ A
100 ns
12 k
100 ns
100 ns
0.1 V
0.10 V
18 k
10 %
24 mA
69mA
13 18 mA
0.4 2 mA
2%
0.5 0.7 V
0.2 mA
0.8 V
= 12V,
Units
Copyright © 1999 Rev. 1.0 4/99
3
LX1668
PRODUCT DATABOOK 1996/1997
PROGRAMMABLE MULTIPLE OUTPUT DC:DC CONTROLLER
RODUCTION DATA SHEET
P
ELECTRICAL CHARACTERISTICS
Table 1 - Adaptive Transient Voltage Output (Output Voltage Setpoint — Typical)
Processor Pins
0 = Low, 1 = High
VID4 VID3 VID2 VID1 VID0
011111.34V 1.30V
011101.39V 1.35V
011011.44V 1.40V
011001.49V 1.45V
010111.54V 1.50V
010101.59V 1.55V
010011.64V 1.60V
010001.69V 1.65V
001111.74V 1.70V
001101.79V 1.75V
001011.84V 1.80V
001001.89V 1.85V
000111.94V 1.90V
000101.99V 1.95V
000012.04V 2.00V
000002.09V 2.05V
111112.04V 2.00V
111102.14V 2.10V
111012.24V 2.20V
111002.34V 2.30V
110112.44V 2.40V
110102.54V 2.50V
110012.64V 2.60V
110002.74V 2.70V
101112.84V 2.80V
101102.94V 2.90V
101013.04V 3.00V
101003.14V 3.10V
100113.24V 3.20V
100103.34V 3.30V
100013.44V 3.40V
100003.54V 3.50V
* Nominal = DAC setpoint voltage with no adaptive output voltage positioning.
Output Voltage (V
0.0A
Nominal Output* (V
SET
)
)
SET
Note:
Adaptive Transient Voltage Output
In order to improve transient response a 40mV offset is built into the voltage comparator. At high currents, the peak output voltage will be lower than the nominal set point , as shown in Figure 4. The actual output voltage will be a function of the sense resistor, output current and output ripple.
4
Copyright © 1999
Rev. 1.0 4/99
PRODUCT DATABOOK 1996/1997
PROGRAMMABLE MULTIPLE OUTPUT DC:DC CONTROLLER
P RODUCTION DAT A SHEET
CHARACTERISTICS CURVES
LX1668
100
95
90
85
EFFICIENCY (%)__
80
EFFICIENCY A T 3. 1V EFFICIENCY A T 2. 8V
75
70
123456 7891011121314
EFFICIENCY A T 1. 8V
I
OUT
(A)
FIGURE 1 — Efficiency Test Results:
V
CORE
60mV
40mV
= 5V
IN
V
FB
16
CS Comp
Error Comp
Hiccup
2.5V
V
Non-Synchronous Operation, V
15
+5V
5
V
CC3
4
V
OUT2
6
L
DRV
PWRGD
OVP
VID[0:4]
7
L
FB
14
Power Good
& OVP
13
V
REF
8
9 10 11 12
OUT3
DAC
2.5V
1.5V
R
SS
20k
V
SET
100
95
90
85
EFFICIENCY (%)__
80
75
70
1234567891011121314
BLOCK DIAGRAM
R
SQ
Set
PWM
Q
Off-Time
Control
I
RESET
V
RESET
Hiccup
EFFICIENCY AT 3.1V EFFICIENCY A T 2.8V EFFICIENCY A T 1.8V
I
(A)
OUT
FIGURE 2 — Efficiency Test Results:
Synchronous Operation, VIN = 5V
+12V
VIN (5V)
2
V
CC12
1
TDRV
19
BDRV
20
PGND
18
AGND
+5V
UVLO
UVLO
3
V
CC5
C
IN
R
SENSE
L
V
CORE
ESR
C
OUT
Copyright © 1999 Rev. 1.0 4/99
SS/ENABLE
17
C
SS
FIGURE 3 — Block Diagram
5
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