The LX1562 is a second-generation
family of power factor correction
controllers using a discontinuous mode
of operation. They are optimized for
electronic ballast applications. Many
improvements have been made over
the original SG3561A controller
introduced by Silicon General Semiconductor in 1992.
New features include the addition of
an internal start-up circuit eliminating
bulky external components while
allowing independent boost converter
operation. Addition of internal current
sense blanking eliminating the need for
an external R/C filter network. Internal
clamping of the error amplifier and
multiplier outputs improves turn on
overshoot characteristics and current
limiting. Special circuitry has also been
added to prevent no load runaway
conditions. And finally, output drive
clamps limiting power MOSFET gate
drive independent of supply voltage
greatly enhance the products practical
application.
Although the IC design has been
optimized for electronic ballast applications, it can also be used for power
factor correction in lower power (typ <
300W) AC-DC converters. One unique
feature of the device is encompassed
by the addition of internal logic
circuitry to detect zero crossing of the
inductor current thus maintaining the
discontinuous current mode of operation. This feature prevents large
current gaps from appearing thereby
minimizing distortion and enhancing
power factor correction.
PRODUCT HIGHLIGHT
TYPICAL APPLICATIONOFTHE LX1562 INAN 80W
F
LUORESCENT LAMP BALLASTWITH ACTIVE POWER FACTOR CONTROL
450µH
61T #22AWG
L1
AC-
C+
120V
AC
D1D3
EMI FILTER
D2
1N4004
1N4004
1N4004
1N4004
100k
½W
R3
2.2M
R1
1%
1µF
C1
250V
D4
29k
R2
1%
C4
.01µF
7T
D5
22µF
R10
4.7M
1N4935
C2
C3
R4
22k
0.1µF
3
VINI
MULT
IN
8
DET
COMP
LX1562
GND
6
5
OUT
INV
C.S.
1N4148
7
2
1
4
D6
47
Ω
R5
R9 620k
C5
0.1µF
1/4W
P RODUCTION DATA SHEET
■■
■ INTERNAL START-UP CIRCUIT
■■
■■
■ INTERNAL CURRENT SENSE BLANKING
■■
■■
■ IMPROVED MICROPOWER START-UP
■■
CURRENT (300µA max.)
■■
■ CLAMPED E.A. OUTPUT FOR LOWER
■■
TURN-ON OVERSHOOT
■■
■ MULTIPLIER CLAMP LIMITS MAXIMUM
■■
INPUT CURRENT
■■
■ INTERNAL OVERVOLTAGE PROTECTION
■■
REPLACES BUILT-IN C.S. OFFSET
■■
■ PWM OUTPUT CLAMP LIMITS MOSFET
■■
GATE DRIVE VOLTAGE
■■
■ INCREASED UVLO HYSTERESIS REDUCES
■■
START-UP TIMING (LX1562 only)
■ LOW OPERATING CURRENT CONSUMPTION
■ INTERNAL 1.5% REFERENCE
■ TOTEM POLE OUTPUT STAGE
■ AUTOMATIC CURRENT LIMITING OF BOOST
STAGE
■ DISCONTINUOUS MODE OF OPERATION
WITH NO CURRENT GAPS
■ NO SLOPE COMPENSATION REQUIRED
APPLICATIONS
V
BOOST
MR854
230V
D7
1M
Ω
R7
1%
Q1
1RF730
11k
1%
3x
R6
1.3
Ω
C6
100µF
400V
R8
FLOURESCENT LAMP BALLAST
■■
■ ELECTRONIC BALLAST
■■
■ SWITCHING POWER SUPPLIES
A VAILABLE OPTIONSPER PART #
Part #Start-UpHysteresis
LX156213.1V5.2V
LX15639.8V2.1V
VoltageVoltage
Note: Thick trace on schematic shows high-frequency, high-current path in circuit.
Lead lengths must be minimized to avoid high-frequency noise problems.
PACKAGE ORDER INFORMATION
T
(°C)
A
0 to 100LX1562IMLX1562IDM
Plastic DIP
M
8-pin
Plastic SOIC
DM
8-pin
0 to 100LX1563IMLX1563IDM
Note: All surface-mount packages are available in Tape & Reel.
Append the letter "T" to part number. (i.e. LX1562IDMT)
Note 4. Range over which the device is functional.
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for the LX1562/1563 with 0°C ≤ TA ≤ 100°C; V
testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
Input Bias CurrentI
Current Sense Delay to Outputt
C.S. Blanking Timet
C.S. Input Offset VoltageV
0V ≤ VCS ≤ 1.7V
CSB
E.A.
d
BLK
OFFVEA0
= 3.7V, VCS = 0 to 1.2V, VM1 = 1V
OUT
= 2.2V, VM1 = 0V, I
DETC
= 0V
Detect Section
Input Voltage Threshold - HighV
HysteresisH
Input LO Clamp VoltageV
Input HI Clamp VoltageV
Input CurrentI
Input HI/LO Clamp Diode CurrentI
HI
D
DLIDET
DZIDET
1V ≤ V
DB
DMXVDET
= 100µA
= 3mA
≤ 6V
DET
< 0.9V, V
DET
> 6V
Restart Timer Section
Restart Timet
RST
Output Driver Section
Output High VoltageV
Output Low VoltageV
Output Rise Timet
Output Fall TimetfCL = 1000pF
Maximum Output VoltageV
Notes: 5. Because the reference is not brought out externally, these specifications are tested at probe only, and cannot be tested on the packaged part.
They are guaranteed by design, and shown for illustrative purposes only.
∆V
6. K =≈
(∆V
) x (V
M1
C.S.
- V
)
EA0
REF
(V
M1
7. This parameter, although guaranteed, is not tested in production.
8. Initial accuracy includes input offset voltage of error amplifier.
Input supply voltage return. Must always be the lowest potential of all the pins.
Inverting input of the Error Amplifier. The output of the Boost converter should be resistively divided to 2.5V and
connected to this pin.
The output of the Error Amplifier. A feedback compensation network is placed between this pin and the INV pin.
Input to the multiplier stage. The full-wave rectified AC is divided to less than 2V and is connected to this pin.
Input to the PWM comparator. Current is sensed in the Boost stage MOSFET by a resistor in the source lead, and is
fed to this pin. An internal blanking circuit eliminates the RC low pass filter that otherwise is required to eliminate leading
edge spike.
5
A current driven logic input with internal clamp.
A second winding on the Boost inductor senses the flyback voltage associated with the zero crossing of the inductor
current and feeds it to the I
PWM output pin. A totem-pole output stage specially designed for direct driving the MOSFET.
pin through a limiting resistor. Low on this pin causes VO (pin 7) to go high.
The operation of the IC is best described by referring to the
block-diagram. The output of the multiplier stage generates a
voltage proportional to the product of the rectified AC line and
the output of the error amplifier. This voltage serves as the
reference for the inductor peak current that is sensed by the
resistor in series with the external power MOSFET. When the
sense voltage exceeds this threshold, C.S. comparator trips and
resets the latch as well as turning the power MOSFET off.
The energy stored during switch on-time is now transferred
and stored in the output capacitor, causing the inductor current
Inductor Peak
Current Envelope
Average
AC Input Current
FIGURE 23 — INDUCTOR CURRENT
TONT
UNDERVOLTAGE LOCK OUT
The LX1562/63 undervoltage lock-out is designed to maintain
an ultra low quiescent current of less than 300µA, while guaranteeing the IC is fully functional before the output stage is
activated. Comparing this to the SG3561A device, a 40% reduction in start-up current is achieved, resulting in 40% less power
dissipation in the start-up resistor. This is especially important
in electronic ballast applications that are designed to operate in
harsh environments, with convection cooling as the only means
of heat dissipation.
Figure 24 shows an efficient supply voltage using the ultra
low start-up current of the LX1562 in conjunction with a bootstrap winding off of the power transformer. Circuit operation
is as follows:
The start-up capacitor (C1) is charged by current through
resistor (R1) minus the start-up current drawn by the IC. This
resistor is typically chosen to provide 2X the maximum start-up
current at low line to guarantee start-up under the worst case
condition. Once the capacitor voltage reaches the start-up
threshold, the IC turns on, starting the switching cycle. The
operation of the IC demands an increase in operating current
which results in discharging the capacitor. During the discharge
cycle, the flyback voltage of the auxiliary winding is rectified
and filtered via rectifier (D1) and charges the capacitor above
the minimum operating voltage of the device and takes over as
the supply voltage. The start-up capacitor and auxiliary winding must be selected such that it satisfies worst case IC conditions. Figure 25 shows start-up time and voltage of capacitor C1.
to ramp down. When current reaches zero level (inductor runs
out of energy) , boost diode (D1) stops conducting and the
residual inductor energy and the drain to source capacitance of
the power MOSFET create an LC tank circuit which causes drain
voltage to resonate at this frequency. The resonating voltage is
detected by the secondary winding (Idet winding) of the inductor. When this voltage swings negative “I detect” pin senses
it and activates the blanking circuit , sets the latch, and turns
power MOSFET on, repeating the cycle. This operation continues for the entire cycle of the AC rectified input resulting in an
inductor current as shown in Figure 23. The high frequency
I
L
content of this current is then filtered by the input capacitor
(C1) resulting in a sine wave input current in phase with the
AC line voltage.
Output voltage regulation is accomplished when the error
amplifier compares this voltage to an internal 2.5V reference
and generates an error voltage. This voltage then controls the
amplitude of the multiplier output adjusting the peak inductor
current proportional to the load and line variations, maintain-
OFF
ing a well regulated voltage.
IC DESCRIPTION
Table 1 shows the start-up voltage and hysteresis for LX1562
and LX1563. The LX1562 is used for stand alone pre-regulator
applications while LX1563 is ideal for applications where supply voltage is derived elsewhere and requires less than 14V
start-up.
FIGURE 24 — TYPICAL APPLICATION OF START-UP CIRCUITRY
The voltage reference is a low drift bandgap design which provides a stable +2.5V output with maximum of ±1.5% initial accuracy. This voltage is internally tied to the non-inverting input of the amplifier and is not available for external connection. The initial accuracy of the reference includes error amplifier input offset voltage. Figure 26 shows typical variation of
the reference voltage vs. temperature.
2.52
2.51
2.50
VCC = 12V
= 1nF
C
L
ERROR AMPLIFIER
The error amplifier is an internally compensated op-amp with
access to the inverting input and the output pin. The noninverting input is internally connected to the voltage reference
and is not available for external connection. The amplifier is
designed for an open loop gain of 80dB, along with a typical
bandwidth of 1.7MHz and 49 degrees of phase margin. The
boost output voltage of the power factor pre-regulator is divided down and monitored by the inverting input. Input bias
current (0.5µA max) can cause an output voltage error that is
equal to the product of the input bias current and the value of
the upper divider resistor. The amplifier's output is available
for external loop compensation. Typically, the loop bandwidth
is set below 10Hz in order to reject the low frequency ripple
associated with 2X the line frequency. For example, if the
t
error amplifier is configured as an integrator with 1.2Hz bandwidth, it will have 40dB ripple rejection at 120Hz frequency.
This means that if the output of the error amp is allowed to
have 100mV of ripple, the boost converter must be limited to
less than 10V of ripple on its output.
To prevent boost output run away condition that may occur
during removal of the output load, a separate comparator monitors the E.A. output voltage and compares it to an internal 1.8V
reference. When load is removed, E.A. output swings lower
than 1.8V, trips the comparator and turns output driver off till
the inverting input voltage drops below 2.5V. At this point, the
E.A. output swings positive, turns the output driver back on
and repeats the cycle until the load is returned to normal condition.
To reduce output overshoot during line and load transients,
the E.A. output is clamped to two diode drops above the reference voltage. This prohibits the amplifier from being saturated, allowing it to recover faster thus minimizing the boost
voltage overshoot.
2.49
2.48
2.47
) Reference Voltage - (V)
R
(V
2.46
2.45
-50
-250
25
5075100125
(TA) Ambient Temperature - (°C)
FIGURE 26 — REFERENCE VOLTAGE (Including Offset) vs. TEMPERATURE
14
V
R10
O
R9
I
9
1
Bias
V
C4
REF
1.8V
From I
BW =
I9 >> I
2
Logic
DET
1
π
R9 C4
2
BIAS
2f
f = Line Freq.
FIGURE 27 — THE AMPLIFIER CONFIGURED AS AN INTEGRATOR
The LX1562/63 features a one quadrant multiplier stage having
two inputs. One (VM2) is internally driven by a DC voltage
which is the difference of E.A. output and V
is connected to an external resistor divider monitoring the rectified AC line. The output of the multiplier which is a function
of both inputs, controls inductor peak current during each cycle
of operation. This allows the inductor peak current to follow
the AC line thus forcing the average input current to be sinusoidal.
The multiplier is in the linear region if the V
to less than 2V and the E.A. output is kept below 3.5V under all
line and load conditions. The output is internally clamped to
1.24V typically to limit the MOSFET peak current during turn on
or under excessive load conditions. The equation below describes the relationship between multiplier output voltage and
the its inputs.
V
= K * V
M0
M1
*
(V
EA0
- V
REF
)
where: K = Multiplier gain (typ. 0.65)
V
= Voltage at pin3 (0 to 2V)
M1
V
= Error amp output voltage (2.5 to 3.5V)
EA0
= Multiplier output voltage
V
M0
E.A.
OUTPUT
2
V
EA
Σ
V
INV.
INPUT
AC
R1
R2
1
V
REF
2.5V
V
3
M1
FIGURE 28 — MULTIPLIER SECTION
CURRENT SENSE COMPARATOR
Current sense comparator is configured as a PNP input differential stage with one input internally tied to the multiplier output and the other available for current sensing. Current is converted to voltage using an external sense resistor in series with
the external power MOSFET. When sense voltage exceeds the
threshold set by the multiplier output, the current sense comparator terminates the gate drive to the MOSFET and resets the
PWM latch. The latch insures that the output remains in a low
state after the switch current falls back to zero. The LX1562/63
features a leading edge blanking circuit that eliminates the need
. The other (VM1),
REF
input is limited
M1
MULT.
OUTPUT
V
V
M2
M0
C.S.
INPUT
4
LX1562/1563
for an external RC filter otherwise required for proper operation of the circuit. This function is described in detail under
“current detect logic” section.
The current sense comparator voltage is limited by an internal 1.24V (typ.) voltage clamp of the multiplier output. Therefore maximum switch current is typically given by:
I
= 1.24V / R
PK (MAX)
Maximum switch peak current happens at full load and minimum line conditions.
TO
PIN 7
3
R
S
V
M0
5
FIGURE 29 — CURRENT SENSE SECTION
CURRENT DETECT LOGIC
The function of “current detect logic” is to sense the operating
state of the boost inductor and to enable the output driver
accordingly. To achieve this, the downward slope of the inductor current is indirectly detected by monitoring the voltage
across a separate winding and connecting it to the detector
input “I
level, the voltage across the winding reverses polarity and
changes the “I
state (See Figure 30). When comparator changes state, it sets
” pin. Once the inductor current reaches ground
DET
” input and the comparator output to the low
DET
the latch and turns on the output driver for a period of 1µs
(typ.) regardless of any changes in the latch output (Q) within
this period. This ensures that if the C.S. comparator changes
state due to any turn-on spike, the driver output remains on
and does not turn off prematurely.
However if the spike lasts longer than 1µs, the output driver
turns off and the MOSFET stops conducting. This type of digital current sense blanking which is not amplitude dependent
has higher noise immunity than the commonly used external
RC filtering, allowing for more flexibility in board layout.
Since inductor voltage swings both positive and negative,
internal voltage clamping is provided to protect the IC. The
switch off time, while during the on time the lower 0.7V
ing
clamp prevents substrate injection. An internal current limit
resistor protects the lower clamp transistor in case the “I
is accidently shorted to ground.
DET
” pin
START-UP TIMER
A start-up timer circuit eliminates the need for an external oscillator when used in stand alone applications. The timer, as
shown in Figure 30, provides a means to automatically start the
pre converter if the latch output Q comes up in a wrong (HI)
state. The timer capacitor ramps up and resets the latch to a
low state, turning the output driver on.
V
REF
I
DEF
300
Ω
5
L1
V
1.72V
TIMER
C.S.
C.S. Latch
OUTPUT DRIVER STAGE
The LX1562/63 output driver is designed for direct driving of
an external power MOSFET. It is a totem pole stage with
±500mA peak current capability. This typically results in a
130ns rise and fall times into a 1000pF capacitive load. Additionally the output is held low during the undervoltage condition to ensure that the MOSFET remains in the off state until
supply voltage reaches the start-up threshold.
Internal voltage clamping ensures that output driver is always lower than 13.8V (typ.) when supply voltage variation
exceeds more than rated V
nal MOSFET. This eliminates an external zener diode and extra
threshold (typ 20V) of the exter-
GS
power dissipation associated with it that otherwise is required
for reliable circuit operation.
HI
C.S.
V
M0
S
1µs
Delay
R
Q
Q
L1
OUT
7
C.S.
4
16
FIGURE 30 — START-UP TIMER & CURRENT DETECT LOGIC CIRCUITRY
The application circuit shown in Figure 31 uses the LX1562 as the
controller to implement a boost type power factor regulator. The
I.C. controls the regulator, such that the inductor current is always
operating in a discontinuous conduction mode with no current
gaps. This mode of operation has several advantages over the
fixed frequency discontinuous conduction mode: 1) The switching frequency adjusts itself to the AC line envelope, causing a
sinusoidal current draw, 2) Since there is no current gap between
the switching cycles, the inductor voltage does not oscillate,
causing less radiated noise, 3) The lower peak inductor current
causes less power dissipation in the power MOSFET.
LX1562/1563
A set of formulas have been derived specifically for this mode,
and are used throughout the design procedure. An example with
the following specifications for the boost converter is given as:
Input Voltage Range- 100 to 130V RMS
Output Power- 80W
Efficiency-95% at full load
Power Factor-> 0.99 at full load
Total Harmonic Distortion-< 10% at full load
followed by a step by step design procedure which walks through
component selection.
AC-
C+
120V
AC
450µH
61T #22AWG
L1
100k
D1D3
1N4004
1N4004
EMI FILTER
D2
C1
D4
1N4004
1N4004
Note: Thick trace on schematic shows high-frequency, high-current path in circuit.
FIGURE 31 — TYPICAL APPLICATION OF THE LX1562 IN AN 80W FLUORESCENT LAMP
½W
2.2M
R1
1%
1µF
250V
29k
R2
1%
Lead lengths must be minimized to avoid high-frequency noise problems.
7T
R3
D5
R10
4.7M
C4
.01µF
BALLAST WITH ACTIVE POWER FACTOR CONTROL
C2
22µF
R4
22k
1N4935
C3
0.1µF
8
V
IN
MULT
IN
3
LX1562
GND
6
I
DET
OUT
COMP
INV
C.S.
1N4148
47
7
R5
R9 620k
2
1
4
D6
5
Ω
C5
0.1µF
1/4W
3x
MR854
1M
Q1
1RF730
R6
1.3
Ω
D7
1%
11k
1%
V
BOOST
230V
Ω
R7
C6
100µF
400V
R8
FLOURESCENT LAMP BALLAST
OUTPUT VOLTAGE REQUIREMENT
Since the converter is a boost type topology, it requires the output
voltage to always be higher than the input voltage. It is
recommended to select this voltage at least 15% higher than the
maximum input voltage in order to: A) Avoid the inductor
saturation during line transience, and B) To keep the operating
frequency above the audible range at high line.
Figure 32 (next page) shows that when boost voltage is
selected near the maximum AC line, the increase in off-time could
reduce the operating frequency below the audible frequency and
cause inductor humming. In fact, Figure 32 (next page) shows
that for ±13% (100V to 130V) change in the line voltage the
optimum range of the operating frequency is when off-time duty
cycle (D') is between 0.57 and 0.75. This means that the boost
voltage needs to be 245V when selecting D' = 0.75 at maximum
AC line.
In this example, D' is chosen to be 0.8, to slightly reduce the
voltage rating of the back end DC to AC fluorescent lamp inverter.
This sets the boost voltage at:
130
√2
== 230V
V
O
*
0.8
17
Page 18
LX1562/1563
PRODUCT DATABOOK 1996/1997
S ECOND-GENERATION POWER FACTOR CONTROLLER
RODUCTION DATA SHEET
P
APPLICATION INFORMATION
OUTPUT VOLTAGE REQUIREMENT (continued)
0.2
fn = (1 - D') D'²
0.15
0.1
2 V
D' =
0.05
f =f
) Normalized Operating Frequency
n
(f
0.3
0.40.5
AC
V
O
η
VO²
n
4 LP
O
0.6
0.70.80.91.0
(D') Off Time Duty Cycle
FIGURE 32 — NORMALIZED OPERATING FREQUENCY vs.
OFF-TIME DUTY CYCLE
INDUCTOR PEAK CURRENT
It can be shown by referring to Figure 33 that the inductor peak
current is always twice the average input current.
Inductor Peak
Current Envelope
Average
AC Input Current
FIGURE 33 — INDUCTOR CURRENT
I
=AVE [ IL (t) ]
IN(t)
Σ
(IL) (T)
1
I
IN
I
INpeak
I
LP
==
T
= IP =
2
I
LP
2
= Inductor peak current at peak input voltage.
I
L
2
I
L
TONT
OFF
Maximum peak input current can be calculated using:
2P
O
=
I
P
ηV
P
where: η≡Converter efficiency
V
≡ Peak AC input voltage
P
assuming: η = 95%, P
2 x 80
== 1.2A
I
P
(.95)(141)
I
= 2 * 1.2 = 2.4A
LP/min AC
= 80W, V
O
= 100√2 = 141
Pmin
INDUCTOR DESIGN
The inductor value is calculated assuming a 50KHz operating
frequency at the nominal AC voltage using the following equation:
VO - V
P
O
O
230 - 120√2
230
2
P
4 * 80
V
≡ Output DC voltage
O
≡ Peak AC input voltage
V
P
T ≡ Switching period
≡ Output Power
P
O
(120√2)
*
2
ηT V
=where: η≡Efficiency
L
1
L1 == 448µH
V
4 P
.95 () 20 * 10-6
choose T = 20µsec (50kHz)
Figure 32 shows that at nominal AC line (D' = 0.74) the normalized
frequency is 0.142 and dropping to 0.13 at maximum line
condition. This translates to a 10% drop in operating frequency
which is still well above the audible range.
Once the inductance is known, we can either use the area
product method (AP) or the K
for selecting proper core size. In this example, we apply the K
Step 2: Choose a core with higher Kg than the one calculated in
Step 1.
Kg/core = k
AW A
l
2
E
W
where: k≡ Winding coefficient (typ. k=0.4)
A
≡ Bobbin window area
W
≡ Effective core area
A
E
l
≡ Mean length per turn
W
K
factor for TDK PQ2625:
g
= 47.7mm
A
W
AE= 118mm
2
2
lW= 56.2mm
56.2
2
-12 m5
(47.7) (118)
= 0.4(mm)5 = 4.7 * 10
K
g
Step 3: Determine number of turns.
L I
N =
N == 61 turns
A
LP
B A
E
450 * 10-6 * 2.4
0.15 * 118 * 10
A
W
= k= 0.4= 0.31mm
WIRE
N
-6
47.7
61
= 480mil
2
2
choose #22 AWG with r = 0.0165Ω/feet resistance.
R
= N * lw * r
W
R
= 0.185Ω
W
Step 4: Calculate air gap.
µO N2 A
4π
*
L
10
E
-7
(61)
*
450 * 10
2
118*10
*
-6
-6
=
l
g
l
== 0.122cm = 48 mil
q
CURRENT SENSE RESISTOR
Current sense resistor, R6 is selected using the minimum multiplier output clamp voltage and the maximum inductor peak
current such that:
V
CLAMP(MIN)
R6 === 0.45Ω
I
L (MAX)
1.1
2.4
Power dissipation is approximated by:
1
≈I
P
R
6
1
P
≈(2.4)
R
6
2
(1 - D'
2 (MAX)
2
(1 - 0.61) = 0.374
),where D'
MIN
MIN
= 1 -
√2 V
V
AC(MIN)
BOOST
Select THREE 1.3Ω , ¼W carbon comp resistors in parallel.
MULTIPLIER COMPONENT SELECTION
Calculate R1 & R2 resistor values such that under low line AC input
the multiplier output is lower than the minimum clamp voltage.
R2
R1 + R2
√2 V
*
AC (MIN)
* K * (V
EA0 (MAX)
- V
REF
) < V
CLAMP (MIN)
where: K≡ Mult. Gain
V
≡ Maximum error amp output where
EA)(MAX)
multiplier is still in linear range.
This voltage is ≈ 3.5V.
For K = 0.65 & V
R1
> 83
R2
CLAMP (MIN)
= 1.1V, the ratio of R1/R2 is:
Assuming R1 is selected to be:
* R1 = 2.2M (1%)
2.2M
R2 == 26.4k (1%)select R
83
= 26.7k (1%)
2
* For high input applications such as 277V, R1 must be divided
into two resistors in series to meet the maximum rated voltage of
the resistors.
To improve THD further (typ. 2-3%), a high value resistor can
be connected from the supply voltage to this pin to allow an
increase in the switch on-time at the zero crossing by adding an
effective offset at the multiplier output.
ERROR AMPLIFIER COMPONENT SELECTION
Boost voltage is programmed with R7 & R8 resistor dividers using
the following equation:
R7
R8
V
BOOST
=-1,
V
REF
assuming that the product of R7 and the E.A. input bias current
does not cause significant error in the output voltage setting.
ΩΩ
Assuming R7 = 1M
two resistors may be added in series to meet the voltage
requirement of the resistor.)
∆V
(106) (0.5 * 10-6) = 0.5V,which is < 0.25% of the
ERROR
(for output voltage of higher than 250V,
Ω
ΩΩ
output voltage.
Calculating R8:
V
BOOST
V
REF
R7
- 1
R8 == 11k (1%)
Worst case output tolerance is the total of ±3.75% which is the sum
of ±1.5% (Ref), ±2% (resistor dividers), and ±0.25% (E.A. input
bias current).
Capacitor C5 is primarily selected to reject the output ripple
associated with twice the line frequency. For a 40dB ripple
rejection:
C5 ≥where f
C5 ≥= 0.062µF, Select C5 = 0.1µF
100
2π f
R7
l
2π
120*2.2*10
*
100
= 2x line frequency
l
6
Resistor R9 can be used to improve load transient response at the
cost of loosing 1 or 2% of load regulation. The value of this resistor
should be much greater than R8:
R9 = 620k
One way of achieving desired load transient response without
resorting to a complex mathematical model of the converter, is to
dynamically switch the output load and empirically find the
compensation network. The value of resistor R9 is selected using
the method shown in Figure 34.
V
BOOST
Min.
R
L
10Hz
50% D.C.
FIGURE 34 — LOAD TRANSIENT RESPONSE CIRCUIT
I
COMPONENT SELECTION
DETECT
Load
Figure 35 shows voltage envelope generated by flyback voltage
across I
Select turns ratio n such that,
n =
n == 0.11
I
selected to be 7T.
winding:
DET
5V
- √2 V
V
BOOST
5V
230 - √2
winding turns are
DET
*
130
AC (MAX)
(V
- VAC)
n
BOOST
V
n
AC
FIGURE 35 — FLYBACK VOLTAGE
ACROSS I
WINDING
DET
and R4 resistor:
n* V
BOOST
< R4 < 500k
-3
3 * 10
0.11 * 230
3 * 10
< R4 < 500k, or8.4k < R4 < 500k
-3
Select R4 = 22k
SUPPLY VOLTAGE
Resistor R3 must be selected such that it ensures converter startup at low line and is rated for high line power dissipation.
√2 V
R3 <where: I
R3 <= 466kΩ
R3 > 4 V
AC (MIN)
I
ST (MAX)
√2
100
*
0.3 * 10
-3
(to keep power dissipation below 0.5W)
AC (MAX)
≡ Maximum start-up
ST
V
ST
T
ST(MAX)
current
≡ Start-up voltage
≡ Maximum start-up
time at AC power-on
R3 > 68k , select R3 = 120k.
Start-up time of converter is given by:
V
T
ST (MAX)
≈ C2
√2 V
AC (MIN)
R3
ST
- I
ST
for our application this will be 25ms/µF.
The start-up capacitor is selected such that capacitor discharge
time is always longer than the time it takes for the bootstrap
voltage to reach above the minimum start-up threshold of the IC.
I
* ∆t
C3 <where: I
OP
∆V
MIN
≡ Maximum dynamic
OP
supply current of the IC
∆t≡ Rise time of the
bootstrap voltage
≡ Minimum hysteresis
∆V
MIN
10 * 10-3 * 10 * 10
C3 <= 29µF
4
-3
(4V for 1562,
voltage
1.7V for 1563)
Select C3 = 33µF.
Start-up time is approximately 0.8 seconds.
The auxiliary winding turns are selected such that it provides 15V
of operating voltage.
V
N
≈ N
S
S
*= 61 *= 4T
P
V
O
However, in this example I
which eliminates the need for a third winding. This is possible
V
S
V
O
winding is used to power the IC
DETECT
since the internal clamping of the output drive limits the gate
drive voltage to 14V (typ.) if the supply voltage exceeds this limit.
The voltage rating of MOSFET and rectifier must be higher than
the maximum value of the output voltage.
≥ 1.2 V
V
DS
O MAX
The RMS current can be approximated by multiplying the RMS
current at the peak of the line by 0.7.
I
= 0.7 I
RMS
D = 0.39 at V
I
= (0.7)(2.4)(√.39/3) = 0.61A
I
RMS
R
P
√D/3D ≡ On-time duty cycle
LP
= 2.4A
LP
≤
DS
≡ allowable powerI
DC
AC
P
DC
2
I
RMS
dissipation.
1
≤= 1.6Ω
R
DS
0.61
IRF730 with R
requirements.
DS
= 1
INPUT RECTIFIER AND CAPACITOR SELECTION
The current through each diode is a half-wave rectified sine wave.
The maximum current happens at minimum line with a peak
value of 1.2A.
I
I
PEAK
=== 0.38A
AVE
π
choose 1N4004 with 1A rating.
= (I
P
DISS
= TA + P
T
J
T
= 80 + (.344)(65) = 102°C
J
) (VF) = 0.38 x 0.9 = 0.344W
AVE
x θ
D
JA
= 100V
ΩΩ
Ω and V
ΩΩ
1.2
π
V
≥ 282V
DS
RMS
= 400V meets the above
DS
assuming θ
lead length.
= 65°C/W for 1/8"
JA
I
LP
D
/triangle = I
√D/3
LP
LX1562/1563
Assuming ϕ is the percentage of allowable input current ripple,
C1 can be calculated using the following equations:
2 P
R
EFF
C1 ≥f
if ϕ = 3%
R
EFF
C1 ≥= 0.9µF
choose 1µF, 250V capacitor.
OUTPUT CAPACITOR SELECTION
There are mainly two criteria for selecting the output capacitor:
A large enough capacitance to maintain a low ripple voltage, and
a low ESR value in order to prevent high power dissipation due
to RMS currents.
The output capacitance can be approximated from the following
equation: