Micron Technology EDW4032BABG Datasheet

4Gb: x16, x32 GDDR5 SGRAM

Features

GDDR5 SGRAM

EDW4032BABG – 8 Meg x 32 I/O x 16 banks, 16 Meg x 16 I/O x 16 banks

Features

• VDD = V

• Data rate: 6.0 Gb/s, 7.0 Gb/s, 8.0 Gb/s

• 16 internal banks

• Four bank groups for tCCDL = 3 tCK

• 8n-bit prefetch architecture: 256-bit per array read
or write access for x32; 128-bit for x16

• Burst length (BL): 8 only

• Programmable CAS latency: 7–25

• Programmable WRITE latency: 4–7

• Programmable CRC READ latency: 2–3

• Programmable CRC WRITE latency: 8–14

• Programmable EDC hold pattern for CDR

• Precharge: Auto option for each burst access

• Auto refresh and self refresh modes

• Refresh cycles: 16,384 cycles/32ms

• Interface: Pseudo open drain (POD-15) compatible
outputs: 40Ω pull-down, 60Ω pull-up

• On-die termination (ODT): 60Ω or 120Ω (NOM)

• ODT and output driver strength auto calibration
with external resistor ZQ pin: 120Ω

• Programmable termination and driver strength off­sets

• Selectable external or internal V
programmable offsets for internal V

• Separate external V
inputs

• TC = 0°C to +95°C

• x32/x16 mode configuration set at power-up with
EDC pin

• Single-ended interface for data, address, and
command

• Quarter data rate differential clock inputs CK_t,
CK_c for address and commands

• Two half data rate differential clock inputs, WCK_t
and WCK_c, each associated with two data bytes
(DQ, DBI_n, EDC)

• DDR data (WCK) and addressing (CK)

• SDR command (CK)

• Write data mask function via address bus (single/
double byte mask)

• Data bus inversion (DBI) and address bus inversion
(ABI)

• Input/output PLL on/off mode

• Duty cycle corrector (DCC) for data clock (WCK)

• Digital RAS lockout

= 1.6V/1.55V/1.5V ±3% and 1.35V ±3%

DDQ

for data inputs;

REF

REF

for address/command

REF

• Address training: Address input monitoring via DQ
pins

• WCK2CK clock training: Phase information via EDC
pins

• Data read and write training via read FIFO (FIFO
depth = 6)

• Read FIFO pattern preloaded by LDFF command

• Direct write data load to read FIFO by WRTR com­mand

• Consecutive read of read FIFO by RDTR command

• Read/write data transmission integrity secured by
cyclic redundancy check (CRC-8)

• Read/write EDC on/off mode

• Low power modes

• RDQS mode on EDC pin

• On-die temperature sensor with readout

• Automatic temperature sensor controlled self
refresh rate

• Vendor ID, FIFO depth and density info fields for
identification

• Mirror function with MF pin

• Boundary scan function with SEN pin

Options

1

Marking

• Organization
– Density 40
– 128 Meg x 32 (words x bits) 32

• FBGA package
– 170-ball (12mm x 14mm) BG

• Package environment code
– Lead- and halogen-free

-F

(RoHS-compliant)

• Package media
– Dry pack (tray) -D
– Reel -R

• Timing – maximum data rate
– 6.0 Gb/s, 5.0 Gb/s -60
– 7.0 Gb/s, 6.0 Gb/s -70
– 8.0 Gb/s, 6.0 Gb/s -80

• Operating temperature
– Commercial (0°C ≤ TC ≤ +95°C) None

• Revision A

Note:

1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on http://www.micron.com
for available offerings.

09005aef858b7e92
4gb_gddr5_sgram_brief.pdf - Rev. E 6/17 EN

Products and specifications discussed herein are subject to change by Micron without notice.

1

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2014 Micron Technology, Inc. All rights reserved.

Figure 1: Part Numbering

Micron Memory

Type
D = Packaged device

Product Family
W = GDDR5 SGRAM

Density/Bank
40 = 4Gb/16-bank

Organization
32 = x32

Power Supply, Interface
B = VDD = 1.6V/1.55V/1.5V

E D W 40 32 B A BG - 70 - -F D

Packing Media
D = Dry pack (tray)
R = Reel

Environment Code
F = Lead-free (RoHS-compliant)
and halogen-free

Speed

-60 = 6.0 Gb/s

-70 = 7.0 Gb/s

-80 = 8.0 Gb/s

Package
BG = 170-ball FBGA, 12mm x 14mm

Revision

4Gb: x16, x32 GDDR5 SGRAM

Features

Note:

1. This Micron GDDR5 SGRAM is available in different speed bins. The operating range and AC timings of a
faster speed bin are a superset of all slower speed bins. Therefore it is safe to use a faster bin device as a
drop-in replacement of a slower bin device when operated within the supply voltage and frequency range
of the slower bin device.

FBGA Part Marking Decoder

Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s web site:
http://www.micron.com.

09005aef858b7e92
4gb_gddr5_sgram_brief.pdf - Rev. E 6/17 EN

2

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2014 Micron Technology, Inc. All rights reserved.

Ball Assignments and Descriptions

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

(Top view)

GroundSupplyGDDR5AddressesData

1

V

SSQ

V

DDQ

V

SSQ

V

DDQ

V

SSQ

V

DDQ

V

DD

V

SS

MF

V

SS

V

DD

V

DDQ

V

SSQ

V

DDQ

V

SSQ

V

DDQ

V

SSQ

2

DQ1

DQ3

EDC0

DBI0_n

DQ5

DQ7

V

DDQ

V

SSQ

RESET_n

V

SSQ

V

DDQ

DQ31

DQ29

DBI3_n

EDC3

DQ27

DQ25

3

V

SSQ

V

DDQ

V

SSQ

V

DDQ

V

SSQ

V

DDQ

RAS_n

V

DDQ

CKE_n

V

DDQ

CAS_n

V

DDQ

V

SSQ

V

DDQ

V

SSQ

V

DDQ

V

SSQ

4

DQ0

DQ2

V

SSQ

WCK01_t

DQ4

DQ6

V

DD

A10, A0

ABI_n

A8, A7

V

DD

DQ30

DQ28

WCK23_t

V

SSQ

DQ26

DQ24

6 7 8 9 10

V

REFD

V

SS

V

DD

V

SS

V

DDQ

V

SSQ

V

SS

BA3, A3

SEN

BA1, A5

V

SS

V

SSQ

V

DDQ

V

SS

V

DD

V

SS

V

REFD

11

DQ8

DQ10

V

SSQ

V

DD

DQ12

DQ14

V

DD

BA0, A2

CK_c

BA2, A4

V

DD

DQ22

DQ20

V

DD

V

SSQ

DQ18

DQ16

12

V

SSQ

V

DDQ

V

SSQ

V

DDQ

V

SSQ

V

DDQ

CS_n

V

DDQ

CK_t

V

DDQ

WE_n

V

DDQ

V

SSQ

V

DDQ

V

SSQ

V

DDQ

V

SSQ

13

DQ9

DQ11

EDC1

DBI1_n

DQ13

DQ15

V

DDQ

V

SSQ

ZQ

V

SSQ

V

DDQ

DQ23

DQ21

DBI2_n

EDC2

DQ19

DQ17

14

V

SSQ

V

DDQ

V

SSQ

V

DDQ

V

SSQ

V

DDQ

V

DD

V

SS

V

REFC

V

SS

V

DD

V

DDQ

V

SSQ

V

DDQ

V

SSQ

V

DDQ

V

SSQ

5

NC

V

SS

V

DD

WCK01_c

V

DDQ

V

SSQ

V

SS

A9, A1

A12, A13

A11, A6

V

SS

V

SSQ

V

DDQ

WCK23_c

V

DD

V

SS

NC

Figure 2: 170-Ball FBGA – MF = 0 (Top View)

4Gb: x16, x32 GDDR5 SGRAM

Ball Assignments and Descriptions

09005aef858b7e92
4gb_gddr5_sgram_brief.pdf - Rev. E 6/17 EN

Note:

1. Balls shown with a heavy, solid outline are off in x16 mode.

3

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2014 Micron Technology, Inc. All rights reserved.