Microchip Technology Inc PIC16F871-I-P, PIC16F870-I-SO, PIC16F870-I-SS, PIC16F871-I-L Datasheet



1999 Microchip Technology Inc.

Preliminary DS30569A-page 1

Devices Included in this Data Sheet:

Microcontroller Core Features:

•High-performance RISC CPU

•Only 35 single word instructions to learn

•All single cycle instructions except for program
branches which are two cycle

•Operating speed:DC - 20 MHz clock input

DC - 200 ns instruction cycle

•2K x 14 words of FLASH Program Memory
128 x 8 bytes of Data Memory (RAM)
64 x 8 bytes of EEPROM Data Memory

•Pinout compatible to the PIC16CXXX 28 and 40­pin devices

•Interrupt capability (up to 11 sources)

•Eight level deep hardware stack

•Direct, indirect and relative addressing modes

•Power-on Reset (POR)

•Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)

•Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation

•Programmable code-protection

•Power saving SLEEP mode

•Selectable oscillator options

•Low-power, high-speed CMOS FLASH/EEPROM
technology

•Fully static design

•In-Circuit Serial Programming (ICSP) via two
pins

•Single 5V In-Circuit Serial Programming capability

•In-Circuit Debugging via two pins

•Processor read/write access to program memory

•Wide operating voltage range: 2.0V to 5.5V

•High Sink/Source Current: 25 mA

•Commercial and Industrial temperature ranges

•Low-power consumption:

-< 1.6 mA typical @ 5V, 4 MHz

-20 µA typical @ 3V, 32 kHz

-< 1 µA typical standby current

Pin Diagram

Peripheral Features:

•Timer0: 8-bit timer/counter with 8-bit prescaler

•Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via external
crystal/clock

•Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler

•One Capture, Compare, PWM module

-Capture is 16-bit, max. resolution is 12.5 ns

-Compare is 16-bit, max. resolution is 200 ns

-PWM max. resolution is 10-bit

•10-bit multi-channel Analog-to-Digital converter

•Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI) with 9-bit address
detection

•Parallel Slave Port (PSP) 8-bits wide, with
external RD

, WR and CS controls (40/44-pin only)

•Brown-out detection circuitry for
Brown-out Reset (BOR)

•PIC16F870 •PIC16F871

RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2

RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5
RC4
RD3/PSP3
RD2/PSP2

MCLR/VPP/THV

RA0/AN0
RA1/AN1

RA2/AN2/VREF-

RA3/AN3/VREF+

RA4/T0CKI

RA5/AN4

RE0/RD/AN5

RE1/WR/AN6

RE2/CS/AN7

VDD
VSS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI

RC2/CCP1

RC3

RD0/PSP0
RD1/PSP1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

PIC16F871

PDIP

PIC16F870/871

28/40-Pin 8-Bit CMOS FLASH Microcontrollers

PIC16F870/871

DS30569A-page 2 Preliminary 

1999 Microchip Technology Inc.

Pin Diagrams

PIC16F870

10
11

2
3
4
5
6

1

8

7

9

12
13
14

15

16

17

18

19

20

23

24

25

26

27

28

22
21

MCLR/VPP/THV

RA0/AN0
RA1/AN1

RA2/AN2/V

REF-

RA3/AN3/V

REF+

RA4/T0CKI

RA5/AN4

V

SS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI

RC2/CCP1

RC3

RB7/PGD
RB6/PGC
RB5
RB4
RB3/PGM
RB2
RB1
RB0/INT
V

DD

VSS
RC7/RX/DT
RC6/TX/CK
RC5
RC4

10
11
12
13
14
15
16
17

181920212223242526

44

8

7

65432

1

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

9

PIC16F871

RA4/T0CKI

RA5/AN4

RE0/RD

/AN5

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CK1

NC

RE1/WR

/AN6

RE2/CS

/AN7

V

DD

VSS

RB3/PGM
RB2
RB1
RB0/INT
V

DD

VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT

RA3/AN3/VREF+

RA2/AN2/V

REF-

RA1/AN1

RA0/AN0

MCLR

/VPP/THV

NC

RB7/PGD

RB6/PGC

RB5

RB4

NC

NC

RC6/TX/CK

RC5

RC4

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3

RC2/CCP1

RC1/T1OSI

10
11

2
3
4
5
6

1

1819202122

121314

15

38

8

7

4443424140

39

16

17

29

30

31

32

33

23

24

25

26

27

28

363435

9

PIC16F871

37

RA3/AN3/VREF+

RA2/AN2/V

REF-

RA1/AN1

RA0/AN0

MCLR

/VPP/THV

NC

RB7/PGD

RB6/PGC

RB5

RB4

NC

RC6/TX/CK

RC5

RC4

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3

RC2/CCP1

RC1/T1OSI

NC

NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
V

SS

VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4
RA4/T0CKI

RC7/RX/DT

RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7

V

SS

VDD

RB0/INT

RB1
RB2

RB3/PGM

PLCC

TQFP

DIP, SOIC, SSOP



1999 Microchip Technology Inc.

Preliminary DS30569A-page 3

PIC16F870/871

Key Features

PICmicro™ Mid-Range Reference Manual (DS33023)

PIC16F870 PIC16F871

Operating Frequency DC - 20 MHz DC - 20 MHz
Resets (and Delays) POR, BOR

(PWRT, OST)

POR, BOR

(PWRT, OST)

FLASH Program Memory
(14-bit words)

2K 2K

Data Memory (bytes) 128 128
EEPROM Data Memory 64 64
Interrupts 10 11
I/O Ports Ports A,B,C Ports A,B,C,D,E
Timers 3 3
Capture/Compare/PWM modules 1 1
Serial Communications USART USART
Parallel Communications — PSP

10-bit Analog-to-Digital Module 5 input channels 8 input channels
Instruction Set 35 Instructions 35 Instructions

PIC16F870/871

DS30569A-page 4 Preliminary 

1999 Microchip Technology Inc.

Table of Contents

1.0 Device Overview............................. ..... ...... ..... ................................................... ...... ..... .. .... ..... ...... ...... .................5

2.0 Memory Organization..........................................................................................................................................11

3.0 I/O Ports..............................................................................................................................................................27

4.0 Data EEPROM and FLASH Program Memory.................................................................................................... 39

5.0 Timer0 Module....................................................................................................................................................47

6.0 Timer1 Module....................................................................................................................................................51

7.0 Timer2 Module....................................................................................................................................................55

8.0 Capture/Compare/PWM Module.........................................................................................................................57

9.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) ........................................63

10.0 Analog-to-Digital Converter (A/D) Module...........................................................................................................79

11.0 Special Features of the CPU...............................................................................................................................89

12.0 Instruction Set Summary...................................................................................................................................105

13.0 Development Support.......................................................................................................................................113

14.0 Electrical Characteristics.................................................. ................................................... ..... .........................119

15.0 DC and AC Characteristics Graphs and Tables................................................................................................135

16.0 Packaging Information ...................................................................................................................................... 137

Index .......................................................................................................................................................................... 145

On-Line Support..........................................................................................................................................................151

Reader Response.......................................................................................................................................................152

Product Identification System......................................................................................................................................153

To Our Valued Customers

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When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter-

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Corrections to this Data Sheet

We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure
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We appreciate your assistance in making this a better document.



1999 Microchip Technology Inc.

Preliminary DS30569A-page 5

PIC16F870/871

1.0 DEVICE OVERVIEW

This document contains device-specific information.

Additional information may be found in the PICmicro™
Mid-Range Reference Manual, (DS33023), which may
be obtained from your local Microchip Sales Represen­tative or downloaded from the Microchip website. The
Reference Manual should be considered a comple­mentary document to this data she et, and is high ly rec­ommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.

There are two devices (PIC16F870 and PIC16F871 )
covered by this data sheet. The PIC16F870 device
comes in a 28-pin package and the PIC16F871 device
comes in a 40-pin package. The 28-pin device does not
have a Parallel Slave Port implemented.

The following two figures are device block diagrams
sorted by pin number; 28-pin for Figure 1-1 and 40-pin
for Figure 1-2. The 28-pin and 40-pin pinouts are listed
in Table 1-1 and Table 1-2, respectively.

FIGURE 1-1: PIC16F870 BLOCK DIAGRAM

FLASH
Program
Memory

13

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

Direct Addr

7

RAM Addr (1)

9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN
OSC2/CLKOUT

MCLR

VDD, VSS

PORTA

PORTB

PORTC

RA4/T0CKI
RA5/AN4

RB0/INT

RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1

RC3
RC4
RC5
RC6/TX/CK
RC7/RX/DT

8

8

Brown-out

Reset

Note 1: Higher order bits are from the STATUS register.

USART

CCP1

10-bit A/DTimer0 Timer1 Timer2

RA3/AN3/VREF+

RA2/AN2/VREF-

RA1/AN1

RA0/AN0

8

3

Data EEPROM

RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD

Device Program

FLASH

Data Memory Data

EEPROM

PIC16F870 2K 128 Bytes 64 Bytes

In-Circuit

Debugger

Low-Voltage

Programming

PIC16F870/871

DS30569A-page 6 Preliminary 

1999 Microchip Technology Inc.

FIGURE 1-2: PIC16F871 BLOCK DIAGRAM

FLASH
Program

Memory

13

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

Direct Addr

7

RAM Addr (1)

9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Tim er

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN
OSC2/CLKOUT

MCLR

VDD, VSS

PORTA

PORTB

PORTC

PORTD

PORTE

RA4/T0CKI
RA5/AN4

RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3
RC4
RC5
RC6/TX/CK
RC7/RX/DT

RD7/PSP7:RD0/PSP0

RE0/AN5/RD
RE1/AN6/WR

RE2/AN7/CS

8

8

Brown-out

Reset

Note 1: Higher order bits are from the STATUS register.

USART

CCP1

10-bit A/DTimer0 Timer1 Timer2

RA3/AN3/VREF+

RA2/AN2/VREF-

RA1/AN1

RA0/AN0

8

3

Data EEPROM

RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD

Device Program

FLASH

Data Memory Data

EEPROM

PIC16F871 2K 128 Bytes 64 Bytes

In-Circuit

Debugger

Low-Voltage

Programming

Parallel Slave Port



1999 Microchip Technology Inc.

Preliminary DS30569A-page 7

PIC16F870/871

TABLE 1-1: PIC16F870 PINOUT DESCRIPTION

Pin Name

DIP

Pin#

SOIC

Pin#

I/O/P
Type

Buffer

Type

Description

OSC1/CLKIN 9 9 I

ST/CMOS

(3)

Oscillator crystal input/external clock source input.

OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal

oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT
which has 1/4 the frequency of OSC1 , and denot es th e instruc tion
cycle rate.

MCLR

/VPP/THV 1 1 I/P ST Master clear (reset) input or programming voltage input or high

voltage test mode control. This pin is an active low reset to the
device.

PORTA is a bi-directional I/O port.
RA0/AN0 2 2 I/O TTL RA0 can also be analog input0
RA1/AN1 3 3 I/O TTL RA1 can also be analog input1
RA2/AN2/V

REF- 4 4 I/O TTL RA2 can also be analog input2 or negative analog reference

voltage

RA3/AN3/V

REF+ 5 5 I/O TTL RA3 can also be analog input3 or positive analog reference

voltage

RA4/T0CKI 6 6 I/O ST RA4 can also be the clock input to the Timer0 module. Output

is open drain type.

RA5/AN4 7 7 I/O TTL RA5 can also be analog input4

PORTB is a bi-directi onal I/O port. PORTB can be software

programmed for internal weak pull-up on all inputs.
RB0/INT 21 21 I/O

TTL/ST

(1)

RB0 can also be the exte rnal interrupt pin.

RB1 22 22 I/O TTL
RB2 23 23 I/O TTL
RB3/PGM 24 24 I/O

TTL/ST

(1)

RB3 can als o be the low voltage pro gramming inp u t

RB4 25 25 I/O TTL Interrupt on cha n g e pi n .
RB5 26 26 I/O TTL Interrupt on cha n g e pi n .
RB6/PGC 27 27 I/O

TTL/ST

(2)

Interrupt on change pin or In-Circuit Debugger pin. Serial
programming clock.

RB7/PGD 28 28 I/O

TTL/ST

(2)

Interrupt on change pin or In-Circuit Debugger pin. Serial
programming data.

PORTC is a bi-directional I/O port.
RC0/T1OSO /T 1 C K I 11 11 I/O ST RC0 can al so be the Timer1 os ci l lat o r ou tp ut or Timer1 cl ock

input.
RC1/T1OSI 12 12 I/O ST RC1 can also be the Timer1 oscillator input
RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Compar e1 output/PWM1

output.
RC3 14 14 I/O ST
RC4 15 15 I/O ST
RC5 16 16 I/O ST
RC6/TX/CK 17 17 I/O ST RC6 can also be the USART Asynchronous Transmit or

Synchron ou s C l ock.
RC7/RX/DT 18 18 I/O ST RC7 can also be the USART Asynchronou s Receive or

Synchron ou s D at a.
V

SS 8, 19 8, 19 P — Ground reference f or logic and I/O pins.

V

DD 20 20 P — Positive suppl y for logic and I/O pins.

Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as t he external interrupt or LVP mode.

2: This buffer is a Schmitt Trigger input when use d i n serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

PIC16F870/871

DS30569A-page 8 Preliminary 

1999 Microchip Technology Inc.

TABLE 1-2: PIC16F871 PINOUT DESCRIPTION

Pin Name

DIP

Pin#

PLCC

Pin#

QFP
Pin#

I/O/P
Type

Buffer

Type

Description

OSC1/CLKIN 13 14 30 I

ST/CMOS

(4)

Oscillator crystal input/external clock source input.

OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in

crystal oscillator mode. In RC mode, OSC2 pin outputs CLK­OUT which has 1/4 the frequency of OSC1, and denotes the
instruction cycle rate.

MCLR

/VPP/THV 1 2 18 I/P ST Master clear (reset) input or prog r amming v oltag e inpu t o r high

voltage test mode control. This pin is an active low reset to the
device.

PORTA is a bi-direction al I/O port.
RA0/AN0 2 3 19 I/O TTL RA0 can also be analog input0
RA1/AN1 3 4 20 I/O TTL RA1 can also be analog input1
RA2/AN2/V

REF- 4 5 21 I/O TTL RA2 can also be analog input2 or negative analog

reference voltage

RA3/AN3/V

REF+ 5 6 22 I/O TTL RA3 can also be analog input3 or positive analog

reference voltage

RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0 timer/

counter. Output is open drain type.

RA5/AN4 7 8 24 I/O TTL RA5 can also be analog input4

PORTB is a bi-directional I/O port. PORTB can be software

programmed for internal weak pull-up on all inputs.
RB0/INT 33 36 8 I/O

TTL/ST

(1)

RB0 can also be the exte rnal interrupt pin.

RB1 34 37 9 I/O TTL
RB2 35 38 10 I/O TTL
RB3/PGM 36 39 11 I/O

TTL/ST

(1)

RB3 can also be the low voltage programming input

RB4 37 41 14 I/O TTL Interrupt on change pin.
RB5 38 42 15 I/O TTL Interrupt on change pin.
RB6/PGC 39 43 16 I/O

TTL/ST

(2)

Interrupt on change pin or In-Circuit Debugger pin. Serial
programming clock.

RB7/PGD 40 44 17 I/O

TTL/ST

(2)

Interrupt on change pin or In-Circuit Debugger pin. Serial
programming data.

PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a Timer1

clock input.
RC1/T1OSI 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input
RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/

PWM1 output.
RC3 18 20 37 I/O ST
RC4 23 25 42 I/O ST
RC5 24 26 43 I/O ST
RC6/TX/CK 25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit or

Synchronous Clock.
RC7/RX/DT 26 29 1 I/O S T RC7 can also be the USART Asynchronous Receive or

Synchronous Data.
Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt or LVP mode.

2: This buffer is a Schmitt Trigger input when use d i n serial programming mode.
3: This buffer is a Schmitt Trigger input when con figured as general purpose I/O and a TTL input when used in the Parallel Slave

Port mode (for int erfacing to a mic r op r ocessor bus).

4: This buffer is a Schmitt Trigger input when configured in RC oscillat or mode and a CMOS input otherwise.



1999 Microchip Technology Inc.

Preliminary DS30569A-page 9

PIC16F870/871

PORTD is a bi-directional I/O port or parallel slave port when

interfacing to a mi croprocessor bus.

RD0/PSP0 19 21 38 I/O

ST/TTL

(3)

RD1/PSP1 20 22 39 I/O

ST/TTL

(3)

RD2/PSP2 21 23 40 I/O

ST/TTL

(3)

RD3/PSP3 22 24 41 I/O

ST/TTL

(3)

RD4/PSP4 27 30 2 I/O

ST/TTL

(3)

RD5/PSP5 28 31 3 I/O

ST/TTL

(3)

RD6/PSP6 29 32 4 I/O

ST/TTL

(3)

RD7/PSP7 30 33 5 I/O

ST/TTL

(3)

PORTE is a bi-directional I/O port.

RE0/RD

/AN5 8 9 25 I/O

ST/TTL

(3)

RE0 can also be read control fo r the par alle l sla v e port, or
analog input5.

RE1/WR

/AN6 9 10 26 I/O

ST/TTL

(3)

RE1 can also be write control for the parallel slave port, or
analog input6.

RE2/CS

/AN7 10 11 27 I/O

ST/TTL

(3)

RE2 can also be select control for the parallel slave port,
or analog input7.

V

SS 12,31 13,34 6,29 P — Ground reference for logic and I /O pins.

V

DD 11,32 12,35 7,28 P — Positive supply for logic and I/O pins.

NC — 1,17,28,4012,13,

33,34

— These pins are not internally con nected. These pins should be

left unconnected.

TABLE 1-2: PIC16F871 PINOUT DESCRIPTION (CONTINUED)

Pin Name

DIP

Pin#

PLCC

Pin#

QFP

Pin#

I/O/P
Type

Buffer

Type

Description

Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt or LVP mode.

2: This buffer is a Schmitt Trigger input when use d i n serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave

Port mode (for int erfacing to a mic r op r ocessor bus).

4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

PIC16F870/871

DS30569A-page 10 Preliminary 

1999 Microchip Technology Inc.

NOTES:



1999 Microchip Technology Inc.

Preliminary DS30569A-page 11

PIC16F870/871

2.0 MEMORY ORGANIZATION

There are three memory blocks in each of these
PICmicro

®

MCUs. The Program Memory and Data
Memory have separate buses, so that concurrent
access can occur, and is detailed in this section. The
EEPROM data memory block is detailed in
Section 4.0.

Additional inf ormation on de vice m emory may be f ound
in the PICmicro Mid-Range Reference Manual,
(DS33023).

2.1 Program Memory Organization

The PIC16F870/871 devices have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. The PIC16F870/871 devices have 2K
x 14 words of FLASH program memor y. Accessing a
location above the physically implemented address will
cause a wraparound.

The reset vector is at 0000h and the interrupt vector is
at 0004h.

FIGURE 2-1: PIC16F870/871 PROGRAM

MEMORY MAP AND STACK

2.2 Data Memory Organization

The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Regi sters. Bits RP1(STA TUS<6 >) and
RP0 (STATUS<5>) are the bank select bits.

Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers . Abo v e the Spec ial Fun ction Re gis­ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special

Function Registers. Some “high use” Special Function
Registers from one bank may be mirrored in another
bank for code reduction and quicker access.

2.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be a ccessed ei ther direc tly, or indi-

rectly through the File Select Register FSR.

PC<12:0>

13

0000h

0004h
0005h

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-Chip

CALL, RETURN
RETFIE, RETLW

1FFFh

Stack Level 2

Program
Memory

Page 0

07FFh
0800h

RP<1:0> Bank

00 0
01 1
10 2
11 3

Note: EEPROM Data Memory description can be

found in Section 4.0 of this Data Sheet

PIC16F870/871

DS30569A-page 12 Preliminary 

1999 Microchip Technology Inc.

FIGURE 2-2: PIC16F870/871 REGISTER FILE MAP

Indirect addr.

(*)

TMR0

PCL

STATUS

FSR
PORTA
PORTB
PORTC

PCLATH
INTCON

PIR1

TMR1L
TMR1H
T1CON

TMR2

T2CON

CCPR1L
CCPR1H

RCSTA

OPTION_REG

PCL

STATUS

FSR
TRISA
TRISB
TRISC

PCLATH
INTCON

PIE1

PCON

PR2

00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh

80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh

20h

A0h

7Fh

FFh

Bank 0

Bank 1

File

Address

Indirect addr .

(*)

Indirect addr.

(*)

PCL

STATUS

FSR

PCLATH
INTCON

PCL

STATUS

FSR

PCLATH
INTCON

100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh

180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh

17Fh

1FFh

Bank 2

Bank 3

Indirect addr.

(*)

ADRESL

TMR0

OPTION_REG

PIR2

PIE2

ADRESH
ADCON0 ADCON1

General
Purpose
Register

General
Purpose
Register

1EFh
1F0h

accesses

A0h - BFh

16Fh
170h

accesses

70h-7Fh

TRISB

PORTB

96 Bytes

32 Bytes

10Ch
10Dh
10Eh
10Fh
110h

18Ch
18Dh
18Eh
18Fh
190h

EEDATA

EEADR

EECON1
EECON2

EEDATH

EEADRH

Reserved

(1)

Reserved

(1)

Unimplemented data memory locations, read as ’0’.

* Not a physical register.

Note 1: These registers are reserved; maintain these registers clear.

2: These registers are not implemented on the PIC16F870.

120h

1A0h

accesses

70h-7Fh

accesses

70h-7Fh

accesses

20h-7Fh

C0h
EFh

F0h

1C0h

1BFh

BFh

TXREG

RCREG

CCP1CON

TXSTA

SPBRG

PORTD

(2)

PORTE

(2)

TRISD

(2)

TRISE

(2)

File

Address

File

Address

File

Address



1999 Microchip Technology Inc.

Preliminary DS30569A-page 13

PIC16F870/871

2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by

the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.

The Special Function Registers can be classified into
two sets; core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 B it 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on

all other

resets

(2)

Bank 0

00h

(4)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

02h

(4)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

03h

(4)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu

04h

(4)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

05h PORTA

— — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu

08h

(5)

PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu

09h

(5)

PORTE — — — — —RE2RE1RE0---- -xxx ---- -uuu

0Ah

(1,4)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

0Bh

(4)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1

PSPIF

(3)

ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

0Dh PIR2

— — — EEIF — — — — ---0 ---- ---0 ----
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON

— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h
14h
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON

— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG USART Transmit Data Register 0000 0000 0000 0000
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
1Bh
1Ch
1Dh
1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu

1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0

GO/

DONE

—ADON0000 00-0 0000 00-0

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter.

2: Other (non power-up) resets include external reset through MCLR

and Watchdog Timer Reset.

3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.

PIC16F870/871

DS30569A-page 14 Preliminary 

1999 Microchip Technology Inc.

Bank 1
80h

(4)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

81h OPTION_REG RBPU

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

82h

(4)

PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000

83h

(4)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu

84h

(4)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

85h TRISA

— — PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111

88h

(5)

TRISD PORTD Data Direction Register 1111 1111 1111 1111

89h

(5)

TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111

8Ah

(1,4)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

8Bh

(4)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

8Ch PIE1

PSPIE

(3)

ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

8Dh PIE2

— — — EEIE — — — — ---0 ---- ---0 ----
8Eh PCON

— — — — — —PORBOR ---- --qq ---- --uu
8Fh — Unimplemented — —
90h — Unimplemented — —
91h
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h
94h
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC

— BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
9Fh ADCON1 ADFM

— — — PCFG3 PCFG2 PCFG1 PCFG0 0--- 0000 0--- 0000

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 B it 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on

all other

resets

(2)

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter.

2: Other (non power-up) resets include external reset through MCLR

and Watchdog Timer Reset.

3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.



1999 Microchip Technology Inc.

Preliminary DS30569A-page 15

PIC16F870/871

Bank 2

100h

(4)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

102h

(4)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

103h

(4)

STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu

104h

(4)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
105h — Unimplemented — —
106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
107h — Unimplemented — —
108h — Unimplemented — —
109h — Unimplemented — —
10Ah

(1,4)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
10Bh

(4)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Ch EEDATA EEPROM data register xxxx xxxx uuuu uuuu
10Dh EEADR EEPROM address register xxxx xxxx uuuu uuuu

10Eh EEDATH

— — EEPROM data register high byte xxxx xxxx uuuu uuuu

10Fh EEADRH

— — — EEPROM address register high byte xxxx xxxx uuuu uuuu

Bank 3

180h

(4)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
181h OPTION_REG RBPU

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

182h

(4)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
183h

(4)

STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
184h

(4)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
185h — Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
187h — Unimplemented — —
188h — Unimplemented — —
189h — Unimplemented — —
18Ah

(1,4)

PCLATH — — —

Write Buffer for the upper 5 bits of the Program Counter

---0 0000 ---0 0000

18Bh

(4)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
18Ch EECON1 EEPGD

— — — WRERR WREN WR RD x--- x000 x--- u000
18Dh EECON2 EEPROM control register2 (not a physical register) ---- ---- ---- ---­18Eh — Reserved maintain clear 0000 0000 0000 0000
18Fh — Reserved maintain clear 0000 0000 0000 0000

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 B it 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on

all other

resets

(2)

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’, r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter.

2: Other (non power-up) resets include external reset through MCLR

and Watchdog Timer Reset.

3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.

PIC16F870/871

DS30569A-page 16 Preliminary 

1999 Microchip Technology Inc.

2.2.2.1 STATUS REGISTER
The STATUS Registe r con tain s the arithmet ic s tatus of

the ALU, the R ESET st atus an d the ba nk sel ect bi ts f or
data memory.

The STATUS Register can be the destination for any
instruction, as with any other register. If the STATUS
Register is the destina tion f or an ins truction tha t aff ects
the Z, DC or C bits, then the write to these three bits is
disabled. The se bi ts ar e set or c leared a ccordi ng to the
device logic. Fur th erm ore, the TO

and PD bits are not
writable, therefore, the result of an instruction with the
STATUS Register as destination may be different than
intended.

For example, CLRF STATUS will clea r t h e up per -t h r ee
bits and set the Z bi t. T his l ea v es the STATUS register
as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C or DC bi ts from the STATUS Regi ster.
For other instructions not affecting any status bits, see
the "Instruction Set Summary."

REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)

Note 1: The C and DC bits operate as a borrow

and digit borrow bit, respectively, in sub­traction. See the SUBLW and SUBWF
instructions for examples.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C R = Readable bit

W = Writable bit
U = Unimplemented bit,

read as ‘0’

- n= Value at POR reset

bit7 bit0

bit 7: IRP: Register Bank Select bit (used for indirec t addressing)

1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (0 0h - FFh)

bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes

bit 4: TO

: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred

bit 3: PD

: Power-down bit

1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP in struction

bit 2: Z: Zero bit

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

bit 1: DC: Digit carry/borrow

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

(for borrow

the polarity is reversed)

1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result

bit 0: C: Carry/borrow

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred

Note: For borrow

the polarity is reversed. A subtraction is executed by adding the two’s complement of
the second operand . For rotate (RRF, RLF) instructions, this bit is loade d w it h ei the r the hig h or l o w o rder
bit of the source register.



1999 Microchip Technology Inc.

Preliminary DS30569A-page 17

PIC16F870/871

2.2.2.2 OPTION_REG REGISTER
The OPTION_REG Register i s a read ab le and writab le

register , which contai ns various c ontrol bits to c onfigure
the TMR0 prescaler/WDT postscaler (single assign­able regist er kno wn also as the prescale r), the Ext ernal
INT Interrupt, TMR0 and the w eak pul l-ups on PO R TB .

REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h, 181h)

Note: To achieve a 1:1 pres caler assi gnment for

the TMR0 register, assign the prescaler to
the Watchdog Timer.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit

W = Writable bit
U = Unimplemented bit,

read as ‘0’

- n= Value at POR reset

bit7 bit0

bit 7: RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values

bit 6: INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin

bit 5: T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)

bit 4: T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3: PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module

bit 2-0: PS2:PS0: Prescaler Rate Select bits

000
001
010
011
100
101
110
111

1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256

1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128

Bit Value TMR0 Rate WDT Rate

PIC16F870/871

DS30569A-page 18 Preliminary 

1999 Microchip Technology Inc.

2.2.2.3 INTCON REGISTER
The INTCON Regi ster i s a rea dab le a nd w ritabl e regi s-

ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.

REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)

Note: Interrupt flag bits get set when an interrupt

condition occurs , regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft­ware should ensure the appropriate inter­rupt flag bits are clear prior to enabling an
interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE R BIE T0IF INTF RBIF R = Readable bit

W = Writable bit
U = Unimplement ed bit,

read as ‘0’

- n= Value at POR reset

bit7 bit0

bit 7: GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts
0 = Disables all interrupts

bit 6: PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts

bit 5: T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt

bit 4: INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt

bit 3: RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt

bit 2: T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow

bit 1: INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur

bit 0: RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state



1999 Microchip Technology Inc.

Preliminary DS30569A-page 19

PIC16F870/871

2.2.2.4 PIE1 REGISTER
The PIE1 Register contains the individual enable bits

for the peripheral interrupts.

REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

PSPIE

(1)

ADIE RCIE TXIE  CCP1IE TMR2IE TMR1IE R = Readable bit

W = Writable bit
U = Unimplemented bit,

read as ‘0’

- n= Value at POR reset

bit7 bit0

bit 7: PSPIE

(1)

: Parallel Slave Port Read/Write Interrupt Enable bit

1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt

bit 6: ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt

bit 5: RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt

bit 4: TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt

bit 3: Unimplemented: Read as ‘0’
bit 2: CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt

bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt

bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt

Note 1: PSPIE is reserved on the PIC16F870; always maintain this bit clear.

PIC16F870/871

DS30569A-page 20 Preliminary 

1999 Microchip Technology Inc.

2.2.2.5 PIR1 REGISTER
The PIR1 Register contains the individual flag bits for

the peripheral interrupts.

REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch)

Note: Interrupt flag bits get set when an interrupt

condition occurs , regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft­ware should ensure the appropriate inter­rupt bits are clear prior to enabling an
interrupt.

R/W-0 R/W-0 R-0 R-0 U-0 R/W-0 R/W-0 R/W-0

PSPIF

(1)

ADIF RCIF TXIF  CCP1IF TMR2IF TMR1IF R = Readable bit

W = Writable bit

- n= Value at POR reset

bit7 bit0

bit 7: PSPIF

(1)

: Parallel Slave Port Read/Write Interrupt Flag bit

1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred

bit 6: ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed
0 = The A/D conversion is not complete

bit 5: RCIF: USART Receive Interrupt Flag bit

1 = The USART receive buffer is full
0 = The USART receive buffer is empty

bit 4: TXIF: USART Transmit Interrupt Flag bit

1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full

bit 7: Unimplemented: Read as ‘0’
bit 2: CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred

PWM Mode
Unused in this mode

bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred

bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow

Note 1: PSPIF is reserved on the PIC16F870; always maintain this bit clear.



1999 Microchip Technology Inc.

Preliminary DS30569A-page 21

PIC16F870/871

2.2.2.6 PIE2 REGISTER
The PIE2 Register contains the individual enab le bit for

the EEPROM write operation interrupt.

REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh)

U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0

——— EEIE — — — — R = Readable bit

W = Writable bit
U = Unimplemented bit,

read as ‘0’

- n= Value at POR reset

bit7 bit0

bit 7-5: Unimplemented: Read as '0'
bit 4: EEIE: EEPROM Write Operation Interrupt Enable

1 = Enable EE Write Interrupt
0 = Disable EE Write Interrupt

bit 3-0: Unimplemented: Read as '0'

PIC16F870/871

DS30569A-page 22 Preliminary 

1999 Microchip Technology Inc.

2.2.2.7 PIR2 REGISTER
The PIR2 Register contains the flag bit for the

EEPROM write operation interrupt.

.

REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh)

Note: Interrupt flag bits get set when an interrupt

condition occurs , regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft­ware should ensure the appropriate inter­rupt flag bits are clear prior to enabling an
interrupt.

U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0

— — — EEIF — — — — R = Readable bit

W = Writable bit
U = Unimplemented bit,

read as ‘0’

- n= Value at POR reset

bit7 bit0

bit 7-5: Unimplemented: Read as '0'
bit 4: EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started

bit 3-0: Unimplemented: Read as '0'

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1999 Microchip Technology Inc.

Preliminary DS30569A-page 23

PIC16F870/871

2.2.2.8 PCON REGISTER
The Power Control (PCON) Register contains flag bits

to allow differentiation between a Power-on Reset
(POR), a Brown-o ut Re set ( BOR) , a Watch-d og Re set
(WDT) and an external MCLR

Reset.

REGISTER 2-8: PCON REGISTER (ADDRESS 8Eh)

Note: BOR is unknown on POR. It must be set by

the user and c hecked on subsequent rests
to see if BOR is clear, indicating a brown­out has occurred. The BOR status bit is a

don’t care and is not predictable if the
brown-out circuit is disabled (by clearing
the BODEN bit in the configuration word).

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-1

— — — — — —PORBOR R = Readable bit

W = Writable bit
U = Unimplemented bit,

read as ‘0’

- n= Value at POR reset

bit7 bit0

bit 7-2: Unimplemented: Read as '0'
bit 1: POR

: Power-on Reset Status bit

1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0: BOR

: Brown-out Reset Status bit

1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

PIC16F870/871

DS30569A-page 24 Preliminary 

1999 Microchip Technology Inc.

2.3 PCL and PCLATH

The Program Counter (PC) is 13-bits wide. The low
byte comes from the PC L Register , w hich is a readab le
and writable register. The upper bits (PC<12:8>) are
not readable, but are indirectly writable through the
PCLA TH register . On an y reset, the upp er bits of the PC
will be cleared. Figure2-3 shows the two situations for
the loading of the PC. The upper example in the figure
shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the fig-
ure shows ho w the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3> → PCH).

FIGURE 2-3: LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.1 COMPUTED GOTO
A computed GOTO is accompli shed by adding an offset

to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if t he table location crosse s a PCL
memory boundary (each 256 byte block). Refer to the
application note,

“Implementing a Table Read"

(AN556).

2.3.2 STACK
The PIC16FXXX family has an 8-level deep x 13-bit

wide hardware stack. The stack space is not part of
either program or data space and the stack pointer is
not readable or writable. The PC is PUSHed onto the
stack when a CALL instru ctio n is executed or an inte r­rupt causes a branch. The stack is POPed in the event
of a RETURN,RETLW or a RETFIE instruction execu­tion. PCLATH is not affected by a PUSH or POP opera­tion.

The stack oper ates as a circular b uffer . This means that
after the stack has been PUSHed e ight ti mes , th e nin th
push overw rites th e value that was stored fro m the firs t
push. The tenth push overwrites the second push (an d
so on).

2.4 Program Memory Paging

The PIC16FXXX architecture is capable of addressing
a continuous 8K word block of program memory. The
CALL and GOTO instructions provide 11 bits of the
address, which al lows br anche s within an y 2K prog ram
memory page. Therefore, the 8K words of program
memory are broken into four pages. Since the
PIC16F872 has only 2K words of program memory or
one page, ad ditional code is not requ ired to e nsure th at
the correct page is selected before a CALL or GOTO
instruction is executed. The PCLATH<4:3> bits should
always be maintai ned as z ero s. If a return from a CALL
instruction (or interrupt) is executed, the entire 13-bit
PC is popped off the stack. Manipulation of the
PCLATH is not required for the return instructions.

2.5 Indirect Addressing, INDF and FSR
Registers

The INDF Register is not a physical register. Address­ing the INDF Register will cause indirect addressing.

Indirect addressing is possible by using the INDF Reg­ister. Any instruction using the INDF Register actually
accesses the register po inted to b y the File Sele ct Reg­ister, FSR. Reading the INDF Register itself indirectly
(FSR = ’0’) will read 00h. Writing to the INDF Register
indirectly results i n a no-operation (alth ou gh st atus bits
may be affected). An eff ectiv e 9-bit addres s is obta ined
by concatenatin g the 8-bit FSR Register a nd the IRP bit
(STATUS<7>), as shown in Figure 2-4.

A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example2-1.

EXAMPLE 2-1: INDIRECT ADDRESSING

movlw 0x20 ;initialize pointer
movwf FSR ;to RAM

NEXT clrf INDF ;clear INDF register

incf FSR,F ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;no clear next

CONTINUE

: ;yes continue

PC

12 8 7 0

5

PCLATH<4:0>

PCLATH

Instruction with

ALU

GOTO,CALL

Opcode <10:0>

8

PC

12 11 10 0

11

PCLATH<4:3>

PCH PCL

87

2

PCLATH

PCH PCL

PCL as
Destination

Note 1: There are no status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions that
occur from the execution of the CALL,
RETURN, RETLW and RETFIE instruc­tions or the vectoring to an interrupt
address.



1999 Microchip Technology Inc.

Preliminary DS30569A-page 25

PIC16F870/871

FIGURE 2-4: DIRECT/INDIRECT ADDRESSING

Note 1: For register file map detail see Figure 2-2.

Data
Memory

(1)

Indirect AddressingDirect Addressing

bank select location select

RP1:RP0 6

0

from opcode

IRP FSR register

7

0

bank select

location select

00 01 10 11

Bank 0 Bank 1 Bank 2 Bank 3

FFh

80h

7Fh

00h

17Fh

100h

1FFh

180h

PIC16F870/871

DS30569A-page 26 Preliminary 

1999 Microchip Technology Inc.

NOTES:



1999 Microchip Technology Inc.

Preliminary DS30569A-page 27

PIC16F870/871

3.0 I/O PORTS

Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.

Additional information on I/O ports may be found in the

PICmicro™ Mid-Range Reference Manual,
(DS33023).

3.1 PORTA and the TRISA Register

PORTA is a 6-bit wide bi-directional port. The corre­sponding data direction register is TRISA. Setting a
TRISA bit (=1) will m ak e the corresponding POR TA pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISA bit (=0) will
make the corresp onding POR TA pin an output (i.e., put
the contents of the output latch on the selected pin).

Reading the PORTA Register reads the status of the
pins, whereas writin g to it w i ll write t o th e p ort latch. All
write operations are read-modify-write operations.
Therefore , a write to a port implies that the port pins are
read, the value is modified and then written to the port
data latch.

Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other PORTA pins have TTL input levels and full
CMOS output drivers.

Other PORTA pins are multiplexed with analog inputs
and analog V

REF input. The operation of each pin is

selected by clearing/setting the control bits in the
ADCON1 Register (A/D Control Register1).

The TRISA R egister controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA Register
are maintained set wh en us ing th em as an alo g i np uts.

EXAMPLE 3-1: INITIALIZING PORTA

BCF STATUS, RP0 ;
BCF STATUS, RP1 ; Bank0
CLRF PORTA ; Initialize PORTA by

; clearing output

; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0x06 ; Configure all pins
MOVWF ADCON1 ; as digital inputs
MOVLW 0xCF ; Value used to

; initialize data

; direction
MOVWF TRISA ; Set RA<3:0> as inputs

; RA<5:4> as outputs

; TRISA<7:6> are always

; read as ’0’.

FIGURE 3-1: BLOCK DIAGRAM OF

RA3:RA0 AND RA5 PINS

FIGURE 3-2: BLOCK DIAGRAM OF RA4/

T0CKI PIN

Note: On a Power-on Reset, these pins are con-

figured as analog inputs and read as '0'.

Data
Bus

QD

Q

CK

QD

Q

CK

QD

EN

P

N

WR
Port

WR
TRIS

Data Latch

TRIS Latch

RD TRIS

RD PORT

V

SS

VDD

I/O pin

(1)

Note 1: I/O pins have protection diodes to VDD and VSS.

Analog
Input
Mode

TTL
Input
Buffer

To A/D Converter

Data
Bus

WR
PORT

WR
TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Schmitt
Trigger
Input
Buffer

N

V

SS

I/O pin

(1)

TMR0 clock input

QD

Q

CK

QD

Q

CK

EN

QD

EN

Note 1: I/O pin has protection diodes to VSS only.

PIC16F870/871

DS30569A-page 28 Preliminary 

1999 Microchip Technology Inc.

TABLE 3-1: PORTA FUNCTIONS

TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit# Buffer Function

RA0/AN0 bit0 TTL Input/output or analog input
RA1/AN1 bit1 TTL Input/output or analog input
RA2/AN2 bit2 TTL Input/output or analog input
RA3/AN3/VREF bit3 TTL Input/output or analog input or VREF
RA4/T0CKI bit4 ST Input/output or external clock input for Timer0

Output is open drain type
RA5/AN4 bit5 TTL Input/output or analog input
Legend: TTL = TTL input, ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on

all

other

resets

05h P ORTA — — RA5 RA4 RA3 RA2 RA1 RA0

--0x 0000 --0u 0000

85h TRISA — — PORTA Data Direction Register

--11 1111 --11 1111

9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0

--0- 0000 --0- 0000

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by

PORTA.



1999 Microchip Technology Inc.

Preliminary DS30569A-page 29

PIC16F870/871

3.2 PORTB and the TRISB Register

PORTB is an 8-bit wide, bi-directional port. The corre­sponding data direction register is TRISB. Setting a
TRISB bit (=1) will make the correspon ding POR TB pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).

Three pins of PORTB a re multiple xed wit h the Low V olt­age Programming function; RB3/PGM, RB6/PGC and
RB7/PGD. The alternate functions of these pins are
described in the Special F eat ures Secti on.

Each of the PORTB pins has a w ea k in ternal p ull -up. A
single control bit ca n turn on all the pull-ups . This is per­formed by clea ring bit R BPU

(OPTION_REG<7>). The
weak pull-up i s automa tically tur ned off wh en the po rt
pin is configured as an output. The pull-ups are dis­abled on a Power-on Reset.

FIGURE 3-3: BLOCK DIAGRAM OF

RB3:RB0 PINS

Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to oc cur (i.e . any RB7:RB4 pin con­figured as an output is excluded from the interrupt on
change comparison). The input pins (of RB7:RB4) are
compared with th e o ld value latched on the la st rea d of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Inter­rupt with flag bit RBIF (INTCON<0>).

This interrupt can wake the device from SLEEP. The
user, i n the interrupt service routine , can clea r the inter­rupt in the following manner:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.

Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.

The interrupt on change feature is recommended for
wake-up on key depression operation and opera tions
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.

This interrupt on mismatch feature, together with soft­ware configurable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key-depression. Refer to the Embedded
Control Handbook,

“Implementing Wake-Up on Key

Stroke”

(AN552).

RB0/INT is an external interrupt inp ut pin and is confi g­ured using the INTEDG bit (OPTION_REG<6>).

RB0/INT is discussed in detail in Section 11.10.1.

FIGURE 3-4: BLOCK DIAGRAM OF

RB7:RB4 PINS

Data Latch

RBPU

(2)

P

V

DD

QD

CK

QD

CK

QD

EN

Data Bus

WR Port

WR TRIS

RD TRIS

RD Port

weak
pull-up

RD Port

RB0/INT

I/O
pin

(1)

TTL
Input
Buffer

Schmitt Trigger
Buffer

TRIS Latch

Note 1: I/O pins have diode protection to V

DD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RBPU

bit (OPTION_REG<7>).

RB3/PGM

Data Latch

From other

RBPU

(2)

P

V

DD

I/O

QD

CK

QD

CK

QD

EN

QD

EN

Data Bus

WR Port

WR TRIS

Set RBIF

TRIS Latch

RD TRIS

RD Port

RB7:RB4 pins

weak
pull-up

RD Port

Latch

TTL
Input
Buffer

pin

(1)

ST

Buffer

RB7:RB6 in serial programming mode

Q3

Q1

Note 1: I/O pins have diode protection to V

DD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RBPU

bit (OPTION_REG<7>).

PIC16F870/871

DS30569A-page 30 Preliminary 

1999 Microchip Technology Inc.

TABLE 3-3: PORTB FUNCTIONS

TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name Bit# Buffer Function

RB0/INT bit0 TTL/ST

(1)

Input/output pin or external interrupt input. Internal software

programmable weak pull-up.
RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.
RB3/PGM bit3 TTL/ST

(1)

Input/output pin or programming pin in LVP mode. Internal software

programmable weak pull-up.
RB4 bit4 TTL Input/output pin (with interrupt on change). In ternal softw are prog ra mmab l e

weak pull-up .
RB5 bit5 TTL Input/output pin (with interrupt on change). In ternal softw are prog ra mmab l e

weak pull-up .
RB6/PGC bit6 TTL/ST

(2)

Input/output pin (with interrupt on change) or In-Circuit Debugger pin.

Internal software programmable weak pull-up. Serial programming clock.
RB7/PGD bit7 TTL/ST

(2)

Input/output pin (with interrupt on change) or In-Circuit Debugger pin.

Internal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt or LVP mode.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,
BOR

Value on all

other

resets

06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h, 186h T RISB PORTB Data Direction Register 1111 1111 1111 1111
81h, 181h O P TION_REG RBPU

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.