Microchip Technology Inc PIC16F628-20I-SO, PIC16F627-04-P, PIC16F627-04I-SO, PIC16F627-04I-SS, PIC16F627-20I-P Datasheet

PIC16F62X

FLASH-Based 8-Bit CMOS Microcontrollers

Devices included in this data sheet:

• PIC16F627 • PIC16F628
Referred to collectively as PIC16F62X .

High Performance RISC CPU:

• Only 35 instructions to learn

• All single-cycle instructions (200 ns), except for
program branches which are t wo- cy c le

• Operating speed:

- DC - 20 MHz clock input

- DC - 200 ns instruct ion cycle

Memory

Device

PIC16F627 1024 x 14 224 x 8 128 x 8
PIC16F628 2048 x 14 224 x 8 128 x 8

• Interrupt capability

• 16 special function hardware registers

• 8-level deep hardware stack

• Direct, Indirect and Relative ad dressing modes

FLASH

Program

RAM
Data

EEPROM

Data

Peripheral Features:

• 15 I/O pins with individual direction control

• High current sink/source for direct LED drive

• Analog comparator module with:

- Two analog comparators

- Programmable on-chip voltage reference

REF) module

(V

- Programmable input multi plexing fr om device

inputs and internal voltage reference

- Comparator outputs are ext erna lly ac ce ss ibl e

• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler

• Timer1: 16-bit timer/counter with external crystal/
clock capability

• Timer2: 8-bit timer/counter with 8-bit period regis­ter, prescaler and postscaler

• Capture, Compare, PWM (CCP) module

- Capture is 16-bit, max. resolution is 12.5 ns

- Compare is 16-bit, max. resolution is 200 ns

- PWM max. resolution is 10-bit

• Universal Synchronous/Asynchronous Receiver/
Transmitter USART/SCI

• 16 Bytes of common RAM

Special Microcontroller Features:

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)

• Brown-out Detect (BOD)

• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation

• Multiplexed MCLR

• Programmable weak pull-ups on PORTB

• Programmable code protection

• Low voltage programming

• Power saving SLEEP mode

• Selectab le oscillat or options

- FLASH configuration bits for oscillator options

- ER (External Resistor) oscillator

- Reduced part count

- Dual speed INTRC

- Lower current consumption

- EC External Clock input

- XT oscillator mode

- HS oscillator mode

- LP oscillator mode

• Serial in-circuit programming (via two pins)

• Four user programmable ID locations

-pin

CMOS Technology:

• Low-power, high-speed CMOS FLASH technology

• Fully stat ic design

• Wide operating voltage range

- PIC16F627 - 3.0V to 5.5V

- PIC16F628 - 3.0V to 5.5V

- PIC16LF627 - 2.0V to 5.5V

- PIC16LF628 - 2.0V to 5.5V

• Commercial, industrial and extended temperature
range

• Low power consumption

- < 2.0 mA @ 5.0V, 4.0 MHz

-15 µA typical @ 3.0V, 32 kHz

-< 1.0 µA typical standby current @ 3.0V

 1999 Microchip Technology Inc. Preliminary DS40300B-page 1

PIC16F62X

Pin Diagrams

PDIP, SOIC

RA2/AN2/V

RA3/AN3/CMP1

RA4/TOCKI/CMP2

RA5/MCLR

REF

/THV

VSS

RB0/INT
RB1/RX/DT
RB2/TX/CK

RB3/CCP1

•1
2

3
4
5
6
7
8
9

18

PIC16F62X

17
16

15
14
13
12
11
10

RA1/AN1
RA0/AN0

RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT

DD

V
RB7/T1OSI
RB6/T1OSO/T1CKI
RB5
RB4/PGM

SSOP

RA2/AN2/V

RA3/AN3/CMP1

RA4/TOCKI/CMP2

RA5/MCLR

REF

/THV

SS

V
VSS

RB0/INT
RB1/RX/DT
RB2/TX/CK

RB3/CCP1 RB4/PGM

•1

2
3
4
5
6

7
8

9
10

20
19

PIC16F62X

18
17
16
15
14
13
12
11

RA1/AN1
RA0/AN0
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT

VDD
VDD
RB7/T1OSI
RB6/T1OSO/T1CKI

RB5

Device Differences

Device

Voltage

Range

Oscillator

PIC16F627 3.0 - 5.5 See Note 1 0.7

Process

Technology

(Microns)

PIC16F628 3.0 - 5.5 See Note 1 0.7
PIC16LF627 2.0 - 5.5 See Note 1 0.7
PIC16LF628 2.0 - 5.5 See Note 1 0.7

Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.

DS40300B-page 2 Preliminary  1999 Microchip Technology Inc.

PIC16F62X

Table of Contents

1.0 General Description.......................................... ........................................ ................................. ............. ......................... ............5

2.0 PIC16F62X Device Varieties......................... ........................... ........................................ ...... ............. ............ .......................... .7

3.0 Architectural Overview................................................................................................................................................................9

4.0 Memory Organization................................................................................................................................................................ 13

5.0 I/O Ports............................... .......................... ......................... ......................... .................................. ......................... ..............27

6.0 Timer0 Module .......................................................................................................................................................................... 45

7.0 Timer1 Module .......................................................................................................................................................................... 50

8.0 Timer2 Module .......................................................................................................................................................................... 54

9.0 Comparator Module.......................................... ........................... ............................................................. ......................... ........ 57

10.0 Capture/Compare/PWM (CCP) Module ................................................. ............................. ...................................................... 63

11.0 Voltage Reference Module.................................................. ........................... ............................................ ......................... ...... 69

12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART).............................. ...................................................... 71

13.0 Data EEPROM Memory.................... ............. ......................... ......................... ................................ ......................... ................ 91

14.0 Special Features of the CPU..................................................................................................................................................... 95

15.0 Instruction Set Summary......................................................................................................................................................... 113

16.0 Development Support.............................................................................................................................................................. 125

17.0 Electrical Specifications...........................................................................................................................................................131

18.0 Device Characterization Information....................................................................................................................................... 145

19.0 Packaging Information........................... ........................................ ........................... ................... .......................... .................. 147

Index............................................................ ............. ......................... ............ ......................................................... ......................... ..151

On-Line Support.................... ........................................ ........................... ............................................................. ............. ................ 155

Reader Response..............................................................................................................................................................................156

PIC16F62X Product Identification System............. ........................... ........................... ............................................................... ...... 157

To Our Valued Customers

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An errata sheet may exist for current devices, des cribing minor operational differences (from the data sheet) a nd recommended
workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revi­sion of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

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When contacting a sales office or the literature center , please speci fy which device, revision of silicon and data sheet (include liter-

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Corrections to this Data Sheet

We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure
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We appreciate your assistance in making this a better document.

 1999 Microchip Technology Inc. Preliminary DS40300B-page 3

PIC16F62X

NOTES:

DS40300B-page 4 Preliminary  1999 Microchip Technology Inc.

PIC16F62X

1.0 GENERAL DESCRIPTION

The PIC16F62X are 18-Pin FLASH-based mem bers of
the versatile PIC16CXX family of low-cost,
high-performance, CMOS, fully-static, 8-bit
microcontrollers.

®

All PICmicro
RISC architecture. The PIC16F62X have enhanced
core features, eight- level deep stack, and multi ple inter­nal and external interrupt sources. The separate
instruction and data buses of the Harvard architec ture
allow a 14-bit wide instruction word with the separate
8-bit wide data. The two-stage instruction pipeline
allows all instructions to execute in a single-cycle,
except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction
set) are available . Additionally , a large register set gives
some of the architectural in novation s used to achieve a
very high performance.

PIC16F62X microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.

PIC16F62X de vices have spec ial features to r educe
external components, thus reducing system cost,
enhancing system reliability and reducing power con­sumption. There are eight oscillator configurations, of
which the single pin ER oscillator provides a low-cost
solution. The LP os ci ll ator minimizes power consump­tion, XT is a standard crystal, INTRC is a self-contained
internal oscillator and the HS is for High Speed crys­tals. The SLEEP (power-down) mode offers power sav­ings. The user can wake up the chip from SLEEP
through several external and internal interrupts and
reset.

A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software
lock- up.

Table 1-1 shows the features of the PIC16F62X
mid-range mic r o c on t r o l l e r fa m ilies.

A simplified block d iagram of the PIC16F62 X is shown
in Figure 3-1.

The PIC16F62X series fits in applica tions ranging fro m
battery chargers to low-power remote sensors. The
FLASH technology makes customization of applicatio n
programs (detection levels, pulse generation, timers,
etc.) extremely fas t and conv enient. The small foo tprint
packages make this microcontroller series ideal for all
applications with space limitations. Low-cost,
low-power , high-p erformance, eas e of use and I/O flex­ibility make the PIC16F62X ve ry versatile.

microcontrollers employ an advanced

1.1 Development Support

The PIC16F62X family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a low-cost development programmer and a
full-featured programmer. A Third Party “C” compiler

support tool is also available.

 1999 Microchip Technology Inc. Preliminary DS40300B-page 5

PIC16F62X

TABLE 1-1: PIC16F62X FAMILY OF DEVICES

PIC16F627 PIC16F628 PIC16LF627 PIC16LF628

Clock

Memory

Peripherals

Features

Maximum Frequency
of Operation (MHz)

FLASH Program Memory (words) 1024 2048 1024 2048
RAM Data Memory (bytes) 224 224 224 224
EEPROM Data Memory (bytes) 128 128 128 128
Timer Module(s) TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2
Comparators(s) 2 2 2 2
Capture/Compare/PWM modules 1 1 1 1
Serial Communications USART USART USART USART
Internal Voltage Reference Yes Yes Yes Yes
Interrupt Sources 10 10 10 10
I/O Pins 16 16 16 16
Voltage Range (Volts) 3.0-5.5 3.0-5.5 2.0-5.5 2.0-5.5
Brown-out Detect Yes Yes Yes Yes
Packages 18-pin DIP ,

All PICmicro® Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current
capability. All P IC 16F62X Family devices use serial programming with clock pin RB6 and data pin RB7.

20 20 20 20

SOIC;
20-pin SSOP

18-pin DIP,
SOIC;
20-pin SSOP

18-pin DIP,
SOIC;
20-pin SSOP

18-pin DIP,
SOIC;
20-pin SSOP

DS40300B-page 6 Preliminary  1999 Microchip Technology Inc.

2.0 PIC16F62X DEVICE VARIETIES

A variety of frequency ranges and packaging options are
available. Depending on application and production
requirements the proper device option can be selected
using the information in the PIC16F62X Product
Identification System section at the end of this data
sheet. When placing orders, please use this page of the
data sheet to specify the correct part number.

2.1 Flash Devices

These devices are offered in the lower cost plastic
package, even though the device can be erased and
reprogrammed. This al lows the same device to be used
for prototype development and pilot programs as well
as production.

A further advantage of the electrically-erasable Flash
version is that it can be erased and reprogrammed
in-circuit, or by device programmers, such as
Microchip’s PICSTART
programmers.

®

Plus or PRO MATE® II

PIC16F62X

2.2 Quick-Turnaround-Production (QTP) Devices

Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who chose not to program a medium
to high quantity of un its a nd whose code patterns have
stabilized. The devices are standard FLASH devices
but with all progr am locations and configu ration option s
already pro gramme d by th e fact ory. Certain code and
prototype verification procedures apply before
production shipments are available. Please contact
your Microchip T ec hnology sal es office for more deta ils.

2.3 Serialized Quick-T urnar ound-Production (SQTPSM) Devices

Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.

Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.

 1999 Microchip Technology Inc. Preliminary DS40300B-page 7

PIC16F62X

NOTES:

DS40300B-page 8 Preliminary  1999 Microchip Technology Inc.

PIC16F62X

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC1 6F62X family can be
attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16F62X uses a Harvard architecture, in
which, program and data are accessed from separate
memories using separate busses. This improves
bandwidth over traditional von Neumann architecture
where program and data are fetched from the same
memory . Separa ting prog ram and data memory furth er
allows instructi ons to be si zed differe ntly than 8-bit wide
data word. Instruction op codes are 14-bits w ide making
it possible to have all single word instructions. A 14-bit
wide program memory access bus fetches a 14-bit
instruction in a single cycle. A two-stage pipeline over­laps fetch and exec ution of instructions. Consequently,
all instructions (3 5) execute in a sing le-cycle (200 ns @
20 MHz) except for program branches.

The Table below lists program memory (Flash, Data
and EEPROM).

Memory

Device

PIC16F627 1024 x 14 224 x 8 128 x 8
PIC16F628 2048 x 14 224 x 8 128 x 8
PIC16LF627 1024 x 14 224 x 8 128 x 8
PIC16LF628 2048 x 14 224 x 8 128 x 8

The PIC16F62X can directly or indirectly address its
register files or data memory. All special function
registers including the program counter are mapped in
the data memory. The PIC16F62X have an orthog onal
(symmetrica l) instruct ion set that m akes it possib le to
carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of

‘special optimal situations’ make programming with the
PIC16F62X simple yet efficient. In addition, the
learning curve is reduced significantly.

FLASH

Program

RAM
Data

EEPROM

Data

The PIC16F62X devices contain an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between d ata i n t he w ork ing re gi ste r a nd any
register file.

The ALU is 8-bit wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register). The other operand is a file register or an
immediate constant . In sin gle ope rand in structi ons, th e
operand is either the W register or a file register.

The W register is an 8-bit working regi ster used for ALU
operations. It is not an addressable register.

Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS regi ster . The C and D C bits
operate as a Bo
respectively, bit in subtraction. See the SUBLW and
SUBWF instructions for examples.

A simplified block diagram is shown in Figure 3-1, with
a description of the device pins in Table 3-1.

Two types of data memory are provided on the
PIC16F62X devices. Non-volatile EEPROM data
memory is provided for long term storage of data such
as calibration value s, look up table da ta, and any oth er
data which may require periodic updating in the field.
This data is not lost when po wer is removed. Th e other
data memory provided is regular RAM data memory.
Regular RAM data memory is provide d for tempo rary
storage of data during norm al operati on. It is lost when
power is removed.

rrow and Digit Borrow out bit,

 1999 Microchip Technology Inc. Preliminary DS40300B-page 9

PIC16F62X

FIGURE 3-1: BLOCK DIAGRAM

Program

Bus

OSC1/CLKIN
OSC2/CLKOUT

FLASH

Program
Memory

14

Instruction reg

Instruction

Decode &

Control

Timing

Generation

13

Program Counter

8 Level Stack

Direct Addr

8

Power-up

Oscillator

Start-up Timer

Power-on

Watchdog
Brown-out

Low-Voltage

Programming

(13-bit)

Timer

Reset

Timer

Detect

RAM Addr (1)

7

8

Data Bus

Addr MUX

3

RAM

File

Registers

FSR reg

STATUS reg

ALU

W reg

9

8

MUX

8

Indirect

Addr

Data EEPROM

PORTA

PORTB

RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3/CMP1

RA4/T0CK1/CMP2
RA5/MCLR
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN

RB0/INT
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
RB4/PGM
RB5
RB6/T1OSO/T1CKI
RB7/T1OSI

/THV

VDD, VSS

MCLR

Comparator

VREF

Timer0 Timer1 Timer2

CCP1

USART

Memory

Device

FLASH

Program

RAM
Data

EEPROM

Data

PIC16F627 1024 x 14 224 x 8 128 x 8
PIC16F628 2048 x 14 224 x 8 128 x 8
PIC16LF627 1024 x 14 224 x 8 128 x 8
PIC16LF628 2048 x 14 224 x 8 128 x 8

Note 1: Higher order bits are from the STATUS register.

DS40300B-page 10 Preliminary  1999 Microchip Technology Inc.

PIC16F62X

TABLE 3-1: PIC16F62X PINOUT DESCRIPTION

DIP/

Name

RA0/AN0 17 19 I/O ST Bi-directional I/O port/Analog comparator input
RA1/AN1 18 20 I/O ST Bi-directional I/O port/Analog comparator input
RA2/AN2/V

RA3/AN3/CMP1 2 2 I/O ST Bi-directional I/O port/Analog comparator input/compara-

RA4/T0CKI/CMP2 3 3 I/O ST Bi-directional I/O port/Can be configured as T0CKI/com-

RA5/MCLR

RA6/OSC2/CLKOUT 15 17 I/O ST Bi-directional I/O port/Oscillator crystal output. Connects

RA7/OSC1/CLKIN 16 18 I/O ST Bi-directional I/O port/Oscillator crystal input/external

RB0/INT 6 7 I/O

RB1/RX/DT 7 8 I/O TTL/ST

RB2/TX/CK 8 9 I/O TTL/ST

RB3/CCP1 9 10 I/O TTL/ST

RB4/PGM 10 11 I/O TTL/ST

RB5 11 12 I/O TTL Bi-directional I/O port/Wake-up from SLEEP on pin

RB6/T1OSO/T1CKI 12 13 I/O TTL/ST

RB7/T1OSI 13 14 I/O TTL/ST

SS 55,6 P — Ground reference for logic and I/O pins.

V

DD 14 15,16 P — Pos itive supply for logic and I/O pins.

V

REF 1 1 I/O ST Bi-directional I/O port/Analog comparator input/VREF out-

/THV 4 4 I ST In put port/master clear (reset input/programming voltage

SOIC
Pin #

SSOP

Pin #

Legend: O = output I/O = input/output P = power

— = Not used I = Input ST = Schmitt Trigger input
TTL = TTL input I/OD =input/open drain output

Note 1: This buffer is a Schmitt Trigger input when config ured as the external interrupt.
Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
Note 3: This buffer is a Schmitt Trigger I/O when used in USART/Synchronous mode.
Note 4: This buffer is a Schmitt Trigger I/O when used in CCP mode.
Note 5: This buffer is a Schmitt Trigger input when used in low voltage program mode.

I/O/P
Type

Buffer

Type

TTL/ST

(3)

(3)

(4)

(5)

(2)

(2)

Description

put

tor output

parator output

input. When configured as MCLR
reset to the device. Voltage on MCLR
exceed V

to crystal or resonator in crystal oscillator mode. In ER
mode, OSC2 pin outputs CLKOUT which has 1/4 the fre­quency of OSC1, and denotes the instruction cycle rate.

clock source input. ER biasing pin.

(1)

Bi-directional I/O port/external interrupt. Can be software
programmed for internal weak pull-up.

Bi-directional I/O port/ USART receive pin/synchronous
data I/O. Can be software programmed for internal weak
pull-up.

Bi-directional I/O port/ USART transmit pin/synchronous
clock I/O. Can be software programmed for internal weak
pull-up.

Bi-directional I/O port/Capture/Compare/PWM I/O. Can
be software programmed for internal weak pull-up.

Bi-directional I/O port/Low voltage programming input pin.
Wake-up from SLEEP on pin change. Can be software
programmed for internal weak pull-up. When low voltage
programming is enabled, the interrupt on pin change and
weak pull-up resistor are disabled.

change. Can be software programmed for internal weak
pull-up.

Bi-directional I/O port/Timer1 oscillator output/Timer1
clock input. Wake up from SLEEP on pin change. Can be
software programmed for internal weak pull-up.

Bi-directional I/O port/Timer1 oscillator input. Wake up
from SLEEP on pin change. Can be software programmed
for internal weak pull-up.

DD during normal device operation.

, this pin is an active low

/THV must not

 1999 Microchip Technology Inc. Preliminary DS40300B-page 11

PIC16F62X

3.1 Clocking Scheme/Instruction Cycle

The clock input (OSC1/CLKIN/RA7 pin) is internally
divided by four to generate four non-overlapping
quadrature clocks namely Q 1, Q2, Q3 and Q4. Inter­nally, the program coun ter (PC) is inc remented ever y
Q1, the instruction is fetched from the program memo ry
and latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-2.

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

Q2 Q3 Q4

OSC1

Q1
Q2
Q3

Q4
PC

OSC2/CLKOUT

(ER mode)

Q1

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

Q1

3.2 Instruction Flow/Pipelining

An “Instructi on Cycle” consists of four Q cy cles (Q1,
Q2, Q3 and Q4). The instruc tio n fe tch and ex ecu te a r e
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles a re required to c omplete the i nstruction
(Example 3-1).

A fetch cycle begins with the program counter (PC)
incrementing in Q1.

In the execution cy cle, the fetched instruction i s latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read duri ng Q2
(operand read) and written during Q4 (destination
write).

Q2 Q3 Q4

Execute INST (PC) Fetch INST (PC+2)

Q2 Q3 Q4

Q1

Execute INST (PC+1)

Internal
phase
clock

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

1. MOVLW 55h

2. MOVWF PORTB

3. CALL SUB_1

4. BSF PORTA, BIT3

All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

DS40300B-page 12 Preliminary  1999 Microchip Technology Inc.

Fetch 1 Execute 1

Fetch 2 Execute 2

Fetch 3 Execute 3

Fetch 4 Flush

Fetch SUB_1 Execute SUB_1

PIC16F62X

4.0 MEMORY ORGANIZATION

4.1 Program Memory Organization

The PIC16F62X has a 13-bi t program c ounter capabl e
of addressing an 8K x 14 program memory space . Only
the first 1K x 14 (0000h - 03FFh) for the PIC16F627
and 2K x 14 (0000h - 07FFh) for the PIC16F628 are
physically implemented. Accessing a location above
these boundaries will cause a wrap-around within the
first 1K x 14 space (PIC16F627) or 2K x 14 space
(PIC16F628). The reset vector is at 0000h and the
interrupt vector is at 0004h (Figu re 4-1 and Figure 4-2).

FIGURE 4-1: PROGRAM MEMORY MAP

AND STACK FOR THE
PIC16F627

PC<12:0>

CALL, RETURN
RETFIE, RETLW

Stack Level 1

Stack Level 2

Stack Level 8

Reset Vector

13

000h

FIGURE 4-2: PROGRAM MEMORY MAP AND

STACK FOR THE PIC16F628

PC<12:0>

CALL, RETURN
RETFIE, RETLW

Stack Level 1

Stack Level 2

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

13

000h

0004
0005

07FFh
0800h

1FFFh

4.2 Data Memory Organization

Interrupt Vector

On-chip Program

Memory

0004
0005

03FFh
0400h

1FFFh

The data memory (Figure4-3) is partitioned into four
Banks which contain the general purpos e registers and
the special function registers. The Special Function
Registers are located in the first 32 locations of ea ch
Bank. Register l ocations 20-7 Fh, A0h-FF h, 120h-14F h,
170h-17Fh and 1F0h-1FFh are general purpose regis­ters implem ented as static RAM.

The Table below lists how to access the four banks of
registers:

RP1 RP0

Bank0 0 0
Bank1 0 1
Bank2 1 0
Bank3 1 1

Addresses F0h-FFh, 170h-17Fh and 1F0h-1FFh are
implemented as common RAM and mapped back to
addresses 70h-7Fh.

4.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized as 224 x 8 in the

PIC16F62X. Each is accessed either directly or indi­rectly through the File Select Register FSR
(Section 4.4).

 1999 Microchip Technology Inc. Preliminary DS40300B-page 13

PIC16F62X

FIGURE 4-3: DATA MEMORY MAP OF THE PIC16F627 AND PIC16F628

File

Address

Indirect addr.(*)

TMR0

PCL

STATUS

FSR
PORTA
PORTB

PCLATH
INTCON

PIR1

TMR1L
TMR1H
T1CON

TMR2

T2CON

CCPR1L

CCPR1H

CCP1CON

RCSTA
TXREG
RCREG

CMCON

General
Purpose
Register

96 Bytes

Bank 0

00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h

7Fh

Indirect addr.(*)

OPTION

PCL

STATUS

FSR
TRISA
TRISB

PCLATH
INTCON

PIE1

PCON

PR2

TXSTA

SPBRG

EEDATA

EEADR

EECON1

EECON2*

VRCON

General
Purpose
Register
80 Bytes

accesses

70h-7Fh

Bank 1

80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh

A0h

EFh
F0h

FFh

Indirect addr.(*)

TMR0

PCL

STATUS

FSR

PORTB

PCLATH
INTCON

General
Purpose
Register
48 Bytes

accesses

70h-7Fh

Bank 2

100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh

11Fh
120h

14Fh
150h

16Fh
170h

17Fh

Indirect addr.(*)

OPTION

PCL

STATUS

FSR

TRISB

PCLATH
INTCON

accesses
70h - 7Fh

Bank 3

180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh

1EFh
1F0h

1FFh

Unimplemented data memory locations, read as ’0’.

* Not a physical register.

DS40300B-page 14 Preliminary  1999 Microchip Technology Inc.

PIC16F62X

4.2.2 SPECIAL FUNCTION REGISTERS The special fu nctio n regi sters are re gisters us ed by the

CPU and Peripheral functions for controlling the
desired operation of the device (Table 4-1). These
registers are static RAM.

The special registers can be classified into two sets
(core and peripheral). The special function registers

associated with the “core” functions are described in
this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.

TABLE 4-1: SPECIAL REGISTERS SUMMARY BANK0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

POR

Reset

Bank 0

Value on

00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
01h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu

02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
03h STATUS

04h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
07h Unimplemented — —
08h Unimplemented — —
09h Unimplemented — —
0Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000
0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1
0Dh Unimplemented — —
0Eh TMR1L Holding register for the least significant byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the most significant byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu
10h T1CON
11h TMR2 TMR2 module’s register 0000 0000 0000 0000
12h T2CON
13h Unimplemented — —
14h Unimplemented — —
15h CCPR1L Capture/Compare/PWM register (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM register (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON
18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit data register 0000 0000 0000 0000
1Ah RCREG USART Receive data register 0000 0000 0000 0000
1Bh Unimplemented — —
1Ch Unimplemented — —
1Dh Unimplemented — —
1Eh Unimplemented — —
1Fh CMCON C2OUT C1OUT

IRP RP1

RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000 xxxx 0000

EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -uuu uuuu

— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

RP0 TO

C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000

PD ZDCC0001 1xxx 000q quuu

Legend: — = Unimplemented locati ons read as ‘0’, u = unchanged, x = un known, q = value depends on c on diti on ,

shaded = unimplemented

Note 1: Other (non power-up) resets include MCLR

Reset, Brown-out Detect and Watchdog Timer Reset during

normal operation.

Value on

all other

Resets

(1)

 1999 Microchip Technology Inc. Preliminary DS40300B-page 15

PIC16F62X

TABLE 4-2: SPECIAL FUNCTION REGISTERS SUMMARY BANK1

Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

POR

Reset

Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical reg-

81h OPTION RBPU
82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
83h STATUS IRP RP1 RP0 TO
84h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA TRISA7 TRISA6

86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
87h Unimplemented — —
88h Unimplemented — —
89h Unimplemented — —
8Ah PCLATH
8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 EEIE CMIE RCIE TXIE
8Dh Unimplemented — —
8Eh PCON
8Fh Unimplemented
90h Unimplemented — —
91h Unimplemented — —
92h PR2 Timer2 Period Register 11111111 11111111
93h Unimplemented — —
94h Unimplemented — —
95h Unimplemented — —
96h Unimplemented — —
97h Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
9Ah EEDATA EEPROM data register xxxx xxxx uuuu uuuu
9Bh EEADR
9Ch EECON1
9Dh EECON2 EEPROM control register 2 (not a physical register) -------- -------­9Eh Unimplemented — —
9Fh VRCON VREN VROE VRR

ister)

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

PD ZDCC0001 1xxx 000q quuu

— TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 11-1 1111 11-1 1111

— — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000

— CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

— — — — OSCF —POR BOD ---- 1-0x ---- 1-uq

— BRGH TRMT TX9D 0000 -010 0000 -010

— EEPROM address register xxxx xxxx uuuu uuuu
— — — — WRERR WREN WR RD ---- x000 ---- q000

— VR3 VR2 VR1 VR0 000- 0000 000- 0000

xxxx xxxx xxxx xxxx

Value on

all other
resets

Legend: : — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

shaded = unimplemented

Note 1: Other (non power-up) resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during

normal operation.

(1)

DS40300B-page 16 Preliminary  1999 Microchip Technology Inc.

TABLE 4-3: SPECIAL FUNCTION REGISTERS SUMMARY BANK2

PIC16F62X

Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

POR

Reset

Bank 1
100h INDF Addressing this location uses contents of FSR to address data memory (not a physical reg-

101h TMR0 RBPU
102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
103h STATUS IRP RP1 RP0 TO
104h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
105h

106h
107h Unimplemented — —
108h Unimplemented — —
109h Unimplemented — —
10Ah PCLATH
10Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Ch — —
10Dh Unimplemented — —
10Eh — —
10Fh Unimplemented
110h Unimplemented — —
111h Unimplemented — —
112h
113h Unimplemented — —
114h Unimplemented — —
115h Unimplemented — —
116h Unimplemented — —
117h Unimplemented — —
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh Unimplemented — —
11Fh

Unimplemented — —
PORTB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111

ister)

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

PD ZDCC0001 1xxx 000q quuu

— — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000

xxxx xxxx xxxx xxxx

— —
— —
— —
— —
— —
— —

— —

Value on

all other
resets

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

shaded = unimplemented

Note 1: Other (non pow e r-up) res ets in cl ude M C LR R eset, Brown-out Detect and Watchdog Timer Reset during

normal operation.

(1)

 1999 Microchip Technology Inc. Preliminary DS40300B-page 17

PIC16F62X

TABLE 4-4: SPECIAL FUNCTION REGISTERS SUMMARY BANK3

Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

POR

Reset

Bank 1
180h INDF Addressing this location uses contents of FSR to address data memory (not a physical reg-

181h OPTION RBPU
182h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
183h STATUS IRP RP1 RP0 TO
184h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
185h Unimplemented — —

186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
187h Unimplemented — —
188h Unimplemented — —
189h Unimplemented — —
18Ah PCLATH
18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh

ister)

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

PD ZDCC0001 1xxx 000q quuu

— — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000

xxxx xxxx xxxx xxxx

Value on
all other

resets

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

shaded = unimplemented

Note 1: Other (non pow e r-up) res ets in cl ude M C LR R eset, Brown-out Detect and Watchdog Timer Reset during

normal operation.

(1)

DS40300B-page 18 Preliminary  1999 Microchip Technology Inc.

PIC16F62X

4.2.2.1 STATUS REGISTER
The STATUS register, shown in Register 4-1, contains

the arithmetic status o f the ALU, the RESET status and
the bank select bits for data memory (SRAM).

The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits ar e set or cl eared acco rding to the
device logic. Furthermore, the TO
writable. Therefore, the result of an instruction with the
STATUS regis ter as destina tion may be differen t than
intended.

For example, CLRF STATUS will clear the upper-three
bits and set the Z bi t. This lea ves the status register as
000uu1uu (where u = unchanged).

and PD bits are not

It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect any stat us bit. For other instructi ons, not affectin g

any status bits, see the “Instruction Set Summary”.

Note 1: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in
subtractio n. See the SUBLW and SUBWF
instructi ons for examples.

REGISTER 4-1: STATUS REGISTER (ADDRESS 03H OR 83H)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C R = Readable bit
bit7 bit0

bit 7: IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)

bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)

bit 4: TO

bit 3: PD

bit 2: Z: Zero bit

bit 1: DC: Digit carry/borrow

bit 0: C: Carry/borrow

: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred

: Power-down bit

1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most si gnificant bit of the result occurred

Note: For borrow
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low or der bit of
the source register.

the polarity is re versed. A subtraction is executed by add in g th e two’s complement of the

W = Writable bit
U = Unimplemented bit,
read as ’0’

-n = Value at POR reset

-x = Unknown at POR reset

 1999 Microchip Technology Inc. Preliminary DS40300B-page 19

PIC16F62X

4.2.2.2 OPTION REGISTER
The OPTION register is a readable and writable

register which conta ins vario us control bits to conf igure
the TMR0/WDT prescaler, the external RB0/INT
interrupt, TMR0, and the weak pull-ups on PORTB.

REGISTER 4-2: OPTION REGISTER (ADDRESS 81H)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit
bit7 bit0

bit 7: RBPU

bit 6: INTEDG: Interrupt Edge Select bit

bit 5: T0CS: TMR0 Clock Source Select bit

bit 4: T0SE: TMR0 Source Edge Select bit

bit 3: PSA: Prescaler Assignment bit

bit 2-0: PS2:PS0: Prescaler Rate Select bits

: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values

1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin

1 = Transition on RA4/T0CKI pin
0 = Internal in struction cycle clock (CLKOUT)

1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin

1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module

Bit Value TMR0 Rate WDT Rate

000
001
010
011
100
101
110
111

1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256

1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128

Note: To achieve a 1:1 prescaler assignment for

TMR0, assign the prescaler to the WDT
(PSA = 1). See Section 6.3.1

W = Writable bit

-n = Value at POR reset

DS40300B-page 20 Preliminary  1999 Microchip Technology Inc.

PIC16F62X

4.2.2.3 INTCON REGISTER
The INTCON register is a readable and writable

register which cont ains the v arious enable and flag bits
for all interrupt sourc es e xcept the com parator modul e.
See Section 4.2.2.4 and Section 4.2.2.5 for a
description of the co mparator enable and flag bits.

Note: Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).

REGISTER 4-3: INTCON REGISTER (ADDRESS 0BH OR 8BH)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit

bit7 bit0

bit 7: GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts
0 = Disables all interrupts

bit 6: PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts

bit 5: T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt

bit 4: INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt

bit 3: RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt
0 = Disables the RB port change inter rupt

bit 2: T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has over flowed (must be cleared in software)
0 = TMR0 register did not overflow

bit 1: INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur

bit 0: RBIF: RB Port Change Interrupt Flag bit

1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state

W = Writable bit
U = Unimplemented bit, read

as ’0’

-n = Value at POR reset

-x = Unknown at POR reset

 1999 Microchip Technology Inc. Preliminary DS40300B-page 21

PIC16F62X

4.2.2.4 PIE1 REGISTER
This register contains interrupt enable bits.

REGISTER 4-4: PIE1 REGISTER (ADDRESS 8CH)

R/W-0 R/W-0 R/W-0 R/W-0 U R/W-0 R/W-0 R/W-0
EEIE CMIE RCIE TXIE - CCP1IE TMR2IE TMR1IE R = Readable bit

bit7 bit0

bit 7: EEIE: EE Write Complete Interrupt Enable Bit

1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt

bit 6: CMIE: Comparator Interrupt Enable bit

1 = Enables the comparator interrupt
0 = Disables the comparator interrupt

bit 5: RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt

bit 4: TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt

bit 3: Unimplemented: Read as ‘0’
bit 2: CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt

bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt

bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overfl ow interrupt
0 = Disables the TMR1 overflow interrupt

W = Writable bit
U = Unimplemented bit, read

as ’0’

-n = Value at POR reset

DS40300B-page 22 Preliminary  1999 Microchip Technology Inc.

PIC16F62X

4.2.2.5 PIR1 REGISTER
This register contains interrupt flag bits.

Note: Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.

REGISTER 4-5: PIR1 REGISTER (ADDRESS 0CH)

R/W-0 R/W-0 R-0 R-0 U R/W-0 R/W-0 R/W-0
EEIF CMIF RCIF TXIF - CCP1IF TMR2IF TMR1IF R = Readable bit

bit7 bit0

bit 7: EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not been started

bit 6: CMIF: Comparator Interrupt Flag bit

1 = Comparator input has changed
0 = Comparator input has not changed

bit 5: RCIF: USART Receive Interrupt Flag bit

1 = The USART receive buffer is full
0 = The USART receive buffer is empty

bit 4: TXIF: USART Transmit Interrupt Flag bit

1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full

bit 3: Unimplemented: Read as ‘0’
bit 2: CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode

bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in so ftware)
0 = No TMR2 to PR2 match occurred

bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow

W = Writable bit
U = Unimplemented bit, read

as ’0’

-n = Value at POR reset

 1999 Microchip Technology Inc. Preliminary DS40300B-page 23

PIC16F62X

4.2.2.6 PCON REGISTER
The PCON register contains flag bits to differentiate

between a Power-on Reset, an external MCLR
WDT reset or a Brown-out Detec t.

Note: BOD is unknown on Power-on Reset. It

must then be set by the user and checked
on subsequent resets to see if BOD
cleared, indicating a brown-out has
occurred. The BOD status bit is a "don’t
care" and is not necessarily predictable if
the brown-out circuit is disabled (by
programming BOREN bit in the
Configuration word).

REGISTER 4-6: PCON REGISTER (ADDRESS 8Eh)

U-0 U-0 U-0 U-0 R/W-1 U-0 R/W-q R/W-q

— — — — OSCF —PORBOD R = Readable bit
bit7 bit0

bit 7-4,2:Unimplemented: Read as '0'
bit 3: OSCF: INTRC/ER oscillator speed

1 = 4 MHz typical
0 = 37 KHz typical

bit 1: POR

bit 0: BOD

: Power-on Reset Status bit

1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Detect Status bit

1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

(1)

reset,

is

W = Writable bit
U = Unimplemented bit, read
as ’0’

-n = Value at POR reset

Note 1: When in ER o scillator mode, setting OSCF = 1 w ill cause the osc illator speed to c hange to the spee d

specified by the external resistor.

DS40300B-page 24 Preliminary  1999 Microchip Technology Inc.

PIC16F62X

4.3 PCL and PCLATH

The program counter (PC) is 13-bits wide. Th e low byte
comes from the PCL register, which is a readable a nd
writable register. The high byte (PC<12:8>) is not directly
readable or writable and co mes from PCLATH. On any
reset, the PC is cleared. Figure 4-7 shows the two
situations for the loading of the PC. The upper example in
the figure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the figure
shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3> → PCH).

FIGURE 4-7: LOADING OF PC IN

DIFFERENT SITUATIONS

PCH PCL

12 8 7 0

PC

PCLATH<4:0>

5

PCLATH

PCH PCL

12 11 10 0

PC

2

87

PCLATH<4:3>

11

8

Instruction with
PCL as
Destination

ALU result

GOTO, CALL

Opcode <10:0>

4.3.2 STACK The PIC16F62X family has an 8 level deep x 13-bit

wide hardware stack (Figure 4-1 and Figure 4-2). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stac k when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLW or a RET-
FIE instruction execution. PCLATH is not affected by a
PUSH or POP operation.

The stack operates as a circular buf fer . This means th at
after the stack has been PUSH ed eight times , the ninth
push overwrites th e valu e that was s tored fro m the firs t
push. The tenth pus h ov erwr i tes the se cond push (and
so on).

Note 1: There are no STATUS bits to

indicate stack overflow or stack
underflow conditions.

Note 2: There are no instructions/mnemonics

called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
interrupt address.

PCLATH

4.3.1 COMPUTED GOTO A computed GOTO is accomplished by adding an offset

to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the tab le locati on cro sses a PCL
memory boundary (each 256 byte block). Refer to the
application note

“Implementing a T able Read"

(AN556).

 1999 Microchip Technology Inc. Preliminary DS40300B-page 25

PIC16F62X

4.4 Indirect Addressing, INDF and FSR

EXAMPLE 4-1: INDIRECT ADDRESSING

Registers

The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.

Indirect address ing is possible by using the INDF register .
Any instruction u sing the I NDF regis ter actuall y accesse s
data pointed to by the file select register (FSR). Reading
INDF itself indire ctly will pro duce 00h. W riting t o the INDF
register indirectly results in a no-operation (although sta­tus bits may be affected). An effective 9-bit address is
obtained by concatenating the 8-bit FSR register and the
IRP bit (STATUS<7>), as shown in Figure 4-8.

A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 4-1.

NEXT clrf INDF ;clear INDF register

CONTINUE:

FIGURE 4-8: DIRECT/INDIRECT ADDRESSING PIC16F62X

RP1 RP0 6

from opcode

0

movlw 0x20 ;initialize pointer
movwf FSR ;to RAM

incf FSR ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;no clear next

;yes continue

Indirect AddressingDirect Addressing

IRP FSR register

7

0

bank select location select

00h

Data
Memory

7Fh

Bank 0 Bank 1 Bank 2 Bank 3

For memory map detail see Figure 4-3.

00 01 10 11

bank select

180h

1FFh

location select

DS40300B-page 26 Preliminary  1999 Microchip Technology Inc.

PIC16F62X

5.0 I/O PORTS

The PIC1 6F6 2X have two ports, PORTA and PORTB.
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.

5.1 PORTA and TR ISA Registers

PORTA is an 8-bit wide latch. RA4 i s a Schmitt Trigger
input and an open drain o utput. Port RA4 is multiplexed
with the T0CKI clock input. RA5 is a Schmitt Trigger input
only and has no output drivers. All other RA port pins have
Schmitt Trigger input levels and full CMOS output drivers.
All pins have data direction bits (TRIS registers) which can
configure these pins as input or output.

A ’1’ in the TRISA register p uts the cor responding o utput
driver in a hi- impedance mode. A ’0’ in the TRISA register
puts the contents of the output latch on the selected pin(s).

Reading the PORT A register reads the status of the pins
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then this
value is modified and written to the port data latch.

The PORTA pins are multiplexed with comparator and
voltage reference functions. The operation of these
pins are selected by control bits in the CMCON
(comparator control register) register and the VRCON
(voltage reference control register) register. When
selected as a comparator input, these pins will read
as ’0 ’s.

Note 1: On reset, the TRISA register is set to all

inputs. The digi tal in puts are disabled and
the comparator inputs are forced to
ground to reduce excess current con­sumption.

Note 2: When RA6/OSC2/CLKOUT is configured

as CLKOUT , the corresponding TRI S bit is
overridden and the p in is conf igured as a n
output. The PORTA data bit reads 0, and
the PORTA TRIS bit reads 0.

TRISA controls the di rection of the RA pins , even whe n
they are being used as comparator inputs. The user
must make sure to keep the pins configured as inputs
when using them as comparator inputs.

The RA2 pin will also function as the output for the
voltage reference. W hen in th is mode, th e V
very high impedance output. The user must configure
TRISA<2> bit as an input and use high impedance
loads.

In one of the comparator modes defined by the
CMCON register, pins RA3 and RA4 become outputs
of the comparators. The TRISA<4:3> bits must be
cleared to enable outputs to use this function.

REF pin is a

EXAMPLE 5-1: INITIALIZING PORTA

CLRF PORTA ;Initialize PORTA by setting

MOVLW 0X07 ;Turn comparators off and
MOVWF CMCON ;enable pins for I/O

BCF STATUS, RP1
BSF STATUS, RP0 ;Select Bank1
MOVLW 0x1F ;Value used to initialize

MOVWF TRISA ;Set RA<4:0> as inputs

;output data latches

;functions

;data direction

;TRISA<7:5> are always
;read as ’0’.

 1999 Microchip Technology Inc. Preliminary DS40300B-page 27

PIC16F62X

FIGURE 5-1: BLOCK DIAGRAM OF

RA0/AN0:RA1/AN1 PINS

Data
Bus

WR
PORTA

Data Latch

WR
TRISA

TRIS Latch

RD PORTA

To Comparator

CK

CK

RD TRISA

QD

VDD

Q

QD

Q

Analog

Input Mode

Schmitt Trigger

P

N

SS

V

Input Buffer

DQ

EN

VDD

VSS

I/O Pin

FIGURE 5-2: BLOCK DIAGRAM OF

REF PIN

RA2/V

Data
Bus

WR
PORTA

Data Latch

WR
TRISA

TRIS Latch

RD PORTA

To Comparator

CK

CK

RD TRISA

VROE

QD

VDD

Q

QD

Q

Analog

Input Mode

Schmitt Trigger

P

N

SS

V

Input Buffer

DQ

EN

VDD

RA2 Pin

VSS

VREF

DS40300B-page 28 Preliminary  1999 Microchip Technology Inc.

FIGURE 5-3: BLOCK DIAGRAM OF THE RA3/AN3 PIN

Data
Bus

WR
PORTA

WR
TRISA

Data Latch

TRIS Latch

RD PORTA

CK

CK

RD TRISA

QD

Comparator Output

Q

QD

Q

Comparator Mode = 110

PIC16F62X

VDD

1

0

Input Mode

DQ

EN

VDD

P

N

SS

V

Analog

Schmitt Trigger

Input Buffer

RA3 Pin

VSS

To Comparator

FIGURE 5-4: BLOCK DIAGRAM OF RA4/T0CKI PIN

Data
Bus

WR
PORTA

WR
TRISA

Data Latch

TRIS Latch

RD PORTA

CK

CK

RD TRISA

QD

Comparator Output

Q

QD

Q

Comparator Mode = 110

1
0

RA4 Pin

VSS

DQ

EN

N

SS

V

Schmitt Trigger

Input Buffer

TMR0 Clock Input

 1999 Microchip Technology Inc. Preliminary DS40300B-page 29

PIC16F62X

FIGURE 5-5: BLOCK DIAGRAM OF THE RA5/MCLR/THV PIN

MCLRE

MCLR circuit

Program mode

Data
Bus

WR
PORT

WR
TRIS

CK
Data Latch
D

CK

TRIS Latch

RD TRIS

MCLR

Filter(1)

HV Detect

QD

Q

Q

Q

DQ

VDD

P

N

V

SS

VDD

RA5/MCLR/THV

VSS

RD Port

EN

DS40300B-page 30 Preliminary  1999 Microchip Technology Inc.