Microchip Technology Inc PIC16CE623-JW, PIC16CE624-JW, PIC16CE625-JW Datasheet

Download



1998 Microchip Technology Inc.

Preliminary

DS40182A-page 1

Devices included in this data sheet:

• PIC16CE623

• PIC16CE624

• PIC16CE625

High Performance RISC CPU:

• Only 35 instructions to learn

• All single-cycle instructions (200 ns), except for program branches which are two-cycle

• Operating speed:

- DC - 20 MHz clock input

- DC - 200 ns instruction cycle

• Interrupt capability

• 16 special function hardware registers

• 8-level deep hardware stack

• Direct, Indirect and Relative addressing modes

Peripheral Features:

• 13 I/O pins with individual direction control

• High current sink/source for direct LED drive

• Analog comparator module with:

- Two analog comparators

- Programmable on-chip voltage reference

REF

) module

- Programmable input multiplexing from de vice

inputs and internal voltage reference

- Comparator outputs can be output signals

• Timer0: 8-bit timer/counter with 8-bit programmable prescaler

Special Microcontroller Features:

• In-Circuit Serial Programming (ICSP™) (via two pins)

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Brown-out Reset

• Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

Device Program

Memory

RAM Data

Memory

EEPROM

Data

Memory

PIC16CE623 512x14 96x8 128x8 PIC16CE624 1Kx14 96x8 128x8 PIC16CE625 2Kx14 128x8 128x8

Pin Diagrams

Special Microcontroller Features (cont’d)

• 1,000,000 erase/write cycle EEPROM data memory

• EEPROM data retention > 40 years

• Programmable code protection

• Power saving SLEEP mode

• Selectable oscillator options

• Four user programmable ID locations

CMOS Tec hnology:

• Low-power, high-speed CMOS EPROM/EEPROM technology

• Fully static design

• Wide operating voltage range

- 3.0V to 5.5V

• Commercial, industrial and extended temperature range

• Low power consumption

- < 2.0 mA @ 5.0V, 4.0 MHz

- 15 µA typical @ 3.0V, 32 kHz

- < 1.0 µA typical standby current @ 3.0V

RA1/AN1 RA0/AN0

OSC2/CLKOUT V

RB7 RB6 RB5 RB4

OSC1/CLKIN

RA2/AN2/V

REF

RA3/AN3

MCLR

VSS

RB0/INT

RB1 RB2 RB3

RA4/T0CKI

PIC16CE62X

RA1/AN1 RA0/AN0

OSC2/CLKOUT V

RB7 RB6 RB5 RB4

OSC1/CLKIN

RA2/AN2/V

REF

RA3/AN3

MCLR

VSS VSS

RB0/INT

RB1 RB2

RA4/T0CKI

PIC16CE62X

RB3RB3

PDIP, SOIC, Windowed CERDIP

SSOP

2 3 4 5 6 7 8 9 10

•1

2 3 4 5 6 7 8 9

•1

19 18

16 15 14 13 12 11

18 17

15 14 13 12 11 10

OTP 8-Bit CMOS MCU with EEPROM Data Memory

PIC16CE62X

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1998 Microchip Technology Inc.

Table of Contents

1.0 General Description..................................................................................................................................................................... 3

2.0 PIC16CE62X Device Varieties.................................................................................................................................................... 5

3.0 Architectural Overview ................................................................................................................................................................ 7

4.0 Memory Organization................................................................................................................................................................ 11

5.0 I/O Ports .................................................................................................................................................................................... 23

6.0 EEPROM Peripheral Operation................................................................................................................................................. 29

7.0 Timer0 Module .......................................................................................................................................................................... 35

8.0 Comparator Module................................................................................................................................................................... 41

9.0 Voltage Reference Module........................................................................................................................................................47

10.0 Special Features of the CPU.....................................................................................................................................................49

11.0 Instruction Set Summary........................................................................................................................................................... 65

12.0 Development Support................................................................................................................................................................ 77

13.0 Electrical Specifications............................................................................................................................................................. 81

14.0 Packaging Information............................................................................................................................................................... 93

Appendix A: Code for Accessing EEPROM Data Memory ............................................................................................................. 99

Index ..................................................................................................................................................................................................101

PIC16CE62X Product Identification System...................................................................................................................................... 105

To Our Valued Customers

We constantly strive to improve the quality of all our products and documentation. To this end, we recently converted to a new publishing software package which we believe will enhance our entire documentation process and product. As in any conversion process, information may have accidently been altered or deleted. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you ﬁnd any information that is missing or appears in error from the previous version of this data sheet (PIC16CE62X Data Sheet, Literature Number DS40182A), please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document.

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1998 Microchip Technology Inc.

Preliminary

DS40182A-page 3

PIC16CE62X

1.0 GENERAL DESCRIPTION

The PIC16CE62X are 18 and 20 Pin EPROM-based members of the versatile PICmicro™ family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers with EEPROM data memory.

All PICmicro™ microcontrollers employ an advanced RISC architecture. The PIC16CE62X have enhanced core features, eight-le vel deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two-stage instruction pipeline allows all instructions to execute in a single-cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available . Additionally , a large register set giv es some of the architectural innovations used to achie ve a very high performance.

PIC16CE62X microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class.

The PIC16CE623 and PIC16CE624 have 96 bytes of RAM. The PIC16CE625 has 128 bytes of RAM. Each microcontroller contains a 128x8 EEPROM memory array for storing non-volatile information such as calibration data or security codes. This memor y has an endurance of 1,000,000 erase/write cycles and a retention of 40 plus years.

Each device has 13 I/O pins and an 8-bit timer/counter with an 8-bit programmable prescaler. In addition, the PIC16CE62X adds two analog comparators with a programmable on-chip voltage reference module. The comparator module is ideally suited for applications requiring a low-cost analog interface (e.g., battery chargers, threshold detectors, white goods controllers, etc).

PIC16CE62X devices have special features to reduce external components, thus reducing system cost, enhancing system reliability and reducing power consumption. There are f our oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) mode offers power savings. The user can wake up the chip from SLEEP through several external and internal interrupts and reset.

A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lock- up.

A UV-erasable CERDIP-packaged version is ideal for code development while the cost-effective One-Time Programmable (OTP) version is suitable for production in any volume.

Table 1-1 shows the features of the PIC16CE62X mid-range microcontroller families.

A simpliﬁed block diagram of the PIC16CE62X is shown in Figure 3-1.

The PIC16CE62X series ﬁt perfectly in applications ranging from multi-pocket battery chargers to low-power remote sensors. The EPROM technology makes customization of application programs (detection levels, pulse generation, timers, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low-cost, low-power, high-performance, ease of use and I/O ﬂexibility make the PIC16CE62X very versatile.

1.1 De

velopment Support

The PIC16CE62X family is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a low-cost development programmer and a full-featured programmer. A “C” compiler and fuzzy logic support tools are also available.

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1998 Microchip Technology Inc.

TABLE 1-1: PIC16CE62X FAMILY OF DEVICES

PIC16CE623 PIC16CE624 PIC16CE625

Clock

Maximum Frequency of Operation (MHz)

20 20 20

Memory

EPROM Program Memory (x14 words)

512 1K 2K

Data Memory (bytes) 96 96 128

Peripherals

EEPROM Data Memory (bytes) 128 128 128 Timer Module(s) TMR0 TMR0 TMR0 Comparators(s) 2 2 2 Internal Reference

Voltage

Yes Yes Yes

Features

Interrupt Sources 4 4 4 I/O Pins 13 13 13 Voltage Range (Volts) 3.0-5.5 3.0-5.5 3.0-5.5 Brown-out Reset Yes Yes Yes Packages 18-pin DIP,

SOIC; 20-pin SSOP

18-pin DIP, SOIC; 20-pin SSOP

All PICmicro™ Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16CE62X Family devices use serial programming with clock pin RB6 and data pin RB7.

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Preliminary

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PIC16CE62X

2.0 PIC16CE62X DEVICE VARIETIES

A variety of frequency ranges and packaging options are available . Depending on application and production requirements the proper device option can be selected using the information in the PIC16CE62X Product Identiﬁcation System section at the end of this data sheet. When placing orders, please use this page of the data sheet to specify the correct part number.

2.1 UV Erasab

le Devices

The UV erasable version, offered in CERDIP package is optimal for prototype development and pilot programs. This version can be erased and reprogrammed to any of the oscillator modes.

Microchip's PICSTART



and PRO MATE



programmers both support programming of the PIC16CE62X.

2.2 One-Time-Pr

ogrammable (OTP)

Devices

The availability of OTP devices is especially useful for customers who need the ﬂexibility for frequent code updates and small volume applications. In addition to the program memory, the conﬁguration bits must also be programmed.

2.3 Quic

k-Turn-Programming (QTP)

Devices

Microchip offers a QTP Programming Service for factory production orders. This service is made available f or users who chose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and conﬁguration options already programmed by the factory. Certain code and prototype veriﬁcation procedures apply before production shipments are available. Please contact your Microchip Technology sales ofﬁce for more details.

2.4 Serializ

ed Quick-Turn-Programming

(SQTP

)

Devices

Microchip offers a unique programming service where a few user-deﬁned locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential.

Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number.

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Preliminary

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1998 Microchip Technology Inc.

NOTES:

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Preliminary

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PIC16CE62X

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC16CE62X family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CE62X uses a Harvard architecture, in which, program and data are accessed from separate memories using separate busses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory. Separating program and data memory further allows instructions to be sized differently than 8-bit wide data word. Instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (35) execute in a single-cycle (200 ns @ 20 MHz) except for program branches.

The PIC16CE623 addresses 512 x 14 on-chip program memory. The PIC16CE624 addresses 1K x 14 program memory. The PIC16CE625 addresses 2K x 14 program memory. All program memory is internal.

The PIC16CE62X can directly or indirectly address its register ﬁles or data memory. All special function registers including the program counter are mapped in the data memory. The PIC16CE62X have an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetr ical nature and lack of ‘special optimal situations’ make programming with the PIC16CE62X simple yet efﬁcient. In addition, the learning curve is reduced signiﬁcantly.

The PIC16CE62X devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register ﬁle.

The ALU is 8-bit wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a ﬁle register or an immediate constant. In single operand instructions, the operand is either the W register or a ﬁle register.

The W register is an 8-bit working register used for ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a Bo

rrow and Digit Borrow out bit,

respectively, bit in subtraction. See the

SUBLW

and

SUBWF

instructions for examples.

A simpliﬁed block diagram is shown in Figure 3-1, with a description of the device pins in Table 3-1.

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1998 Microchip Technology Inc.

FIGURE 3-1: BLOCK DIAGRAM

EPROM

Program

Memory

Data Bus

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

Direct Addr

RAM Addr

(1)

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN OSC2/CLKOUT

MCLR

VDD, VSS

Voltage

Brown-out

Reset

Note 1: Higher order bits are from the STATUS register.

Device Program Memory

Data Memory

(RAM)

EEPROM DATA

MEMORY

PIC16CE623 PIC16CE624 PIC16CE625

512 X 14 1K X14 2K X 14

96 X 8 96 X 8 128 X 8

128 X 8 128 X 8 128 X 8

TMR0

I/O Ports

PORTB

Comparator

RA3/AN3

RA2/AN2/VREF

RA1/AN1

RA0/AN0

Reference

RA4/T0CKI

EEPROM

Data

Memory

128x8

VDD

SDA

EEINTF

SCL

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Preliminary

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PIC16CE62X

TABLE 3-1: PIC16CE62X PINOUT DESCRIPTION

Name

DIP/ SOIC Pin #

SSOP

Pin #

I/O/P Type

Buffer

Type

Description

OSC1/CLKIN 16 18 I ST/CMOS Oscillator crystal input/external clock source input. OSC2/CLKOUT 15 17 O — Oscillator crystal output. Connects to crystal or resonator

in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.

MCLR

4 4 I/P ST Master clear (reset) input/programming voltage input.

This pin is an active low reset to the device.

PORTA is a bi-directional I/O port. RA0/AN0 17 19 I/O ST Analog comparator input RA1/AN1 18 20 I/O ST Analog comparator input RA2/AN2/V

REF

1 1 I/O ST Analog comparator input or V

REF

output RA3/AN3 2 2 I/O ST Analog comparator input /output RA4/T0CKI 3 3 I/O ST Can be selected to be the clock input to the Timer0

timer/counter or a comparator output. Output is open drain type.

PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.

RB0/INT 6 7 I/O

TTL/ST

(1)

RB0/INT can also be selected as an external

interrupt pin. RB1 7 8 I/O TTL RB2 8 9 I/O TTL RB3 9 10 I/O TTL RB4 10 11 I/O TTL Interrupt on change pin. RB5 11 12 I/O TTL Interrupt on change pin. RB6 12 13 I/O TTL/ST

(2)

Interrupt on change pin. Serial programming clock. RB7 13 14 I/O TTL/ST

(2)

Interrupt on change pin. Serial programming data. V

5 5,6 P — Ground reference for logic and I/O pins.

14 15,16 P — Positive supply for logic and I/O pins.

Legend: O = output I/O = input/output P = power

— = Not used I = Input ST = Schmitt Trigger input

TTL = TTL input Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt. Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.

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3.1 Cloc

king Scheme/Instruction Cycle

The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution ﬂow is shown in Figure 3-2.

3.2 Instruction Flo

w/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.,

GOTO

) then two cycles are required to complete the instruction (Example 3-1).

A fetch cycle begins with the program counter (PC) incrementing in Q1.

In the execution cycle , the fetched instruction is latched into the “Instruction Register (IR)” in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Q2 Q3 Q4

OSC1

Q1 Q2 Q3

Q4 PC

OSC2/CLKOUT

(RC mode)

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

Execute INST (PC) Fetch INST (PC+2)

Execute INST (PC+1)

Internal phase clock

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “ﬂushed” from the pipeline while the new instruction is being fetched and then executed.

1. MOVLW 55h

Fetch 1 Execute 1

2. MOVWF PORTB

Fetch 2 Execute 2

3. CALL SUB_1

Fetch 3 Execute 3

4. BSF PORTA, BIT3

Fetch 4 Flush

5. Instruction @ address SUB_1

Fetch SUB_1 Execute SUB_1

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Preliminary

DS40182A-page 11

PIC16CE62X

4.0 MEMORY ORGANIZATION

4.1 Pr

ogram Memory Organization

The PIC16CE62X has a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the ﬁrst 512 x 14 (0000h - 01FFh) for the PIC16CE623, 1K x 14 (0000h - 03FFh) for the PIC16CE624 and 2K x 14 (0000h - 07FFh) for the PIC16CE625 are physically implemented. Accessing a location above these boundaries will cause a wrap-around within the ﬁrst 512 x 14 space (PIC16CE623) or 1K x 14 space (PIC16CE624) or 2K x 14 space (PIC16CE625). The reset v ector is at 0000h and the interrupt vector is at 0004h (Figure 4-1, Figure 4-2, Figure 4-3).

FIGURE 4-1: PROGRAM MEMORY MAP

AND STACK FOR THE PIC16CE623

PC<12:0>

000h

0004 0005

01FFh 0200h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN RETFIE, RETLW

Stack Level 2

FIGURE 4-2: PROGRAM MEMORY MAP

AND STACK FOR THE PIC16CE624

FIGURE 4-3: PROGRAM MEMORY MAP

AND STACK FOR THE PIC16CE625

PC<12:0>

000h

0004 0005

03FFh 0400h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN RETFIE, RETLW

Stack Level 2

PC<12:0>

000h

0004 0005

07FFh 0800h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN RETFIE, RETLW

Stack Level 2

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4.2 Data Memor

y Organization

The data memory (Figure 4-4 and Figure 4-5) is partitioned into two Banks which contain the general purpose registers and the special function registers. Bank 0 is selected when the RP0 bit is cleared. Bank 1 is selected when the RP0 bit (STATUS <5>) is set. The Special Function Registers are located in the ﬁrst 32 locations of each Bank. Register locations 20-7Fh (Bank0) on the PIC16CE623/624 and 20-7Fh (Bank0) and A0-BFh (Bank1) on the PIC16CE625 are general purpose registers implemented as static RAM. Some special purpose registers are mapped in Bank 1. In all three microcontrollers, address space F0h-FFh is mapped to 70-7Fh.

4.2.1 GENERAL PURPOSE REGISTER FILE The register ﬁle is organized as 96 x 8 in the

PIC16CE623/624 and 128 x 8 in the PIC16CE625. Each is accessed either directly or indirectly through the File Select Register FSR (Section 4.4).

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PIC16CE62X

FIGURE 4-4: DATA MEMORY MAP FOR

THE PIC16CE623/624

INDF

(1)

TMR0

PCL

STATUS

FSR PORTA PORTB

PCLATH INTCON

PIR1

CMCON

INDF

(1)

OPTION

PCL

STATUS

FSR TRISA TRISB

PCLATH INTCON

PIE1

PCON

VRCON

00h 01h 02h 03h 04h 05h 06h 07h 08h

09h 0Ah 0Bh 0Ch 0Dh 0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h 1Ah 1Bh 1Ch 1Dh 1Eh

1Fh

80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh

20h

A0h

General Purpose Register

7Fh

FFh

Bank 0 Bank 1

File

Address

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

File

Address

EEINTF

EFh F0h

Accesses

70h-7Fh

FIGURE 4-5: DATA MEMORY MAP FOR

THE PIC16CE625

INDF

(1)

TMR0

PCL

STATUS

FSR PORTA PORTB

PCLATH INTCON

PIR1

CMCON

INDF

(1)

OPTION

PCL

STATUS

FSR TRISA TRISB

PCLATH INTCON

PIE1

PCON

VRCON

00h 01h 02h 03h 04h 05h 06h 07h 08h

09h 0Ah 0Bh 0Ch 0Dh 0Eh

0Fh 10h

11h

12h 13h 14h 15h 16h 17h 18h

19h 1Ah 1Bh 1Ch 1Dh 1Eh

1Fh

80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh

20h

A0h

General Purpose Register

7Fh

FFh

Bank 0 Bank 1

File

Address

BFh C0h

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

File

Address

General Purpose Register

EEINTF

Accesses

70h-7Fh

F0h

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4.2.2 SPECIAL FUNCTION REGISTERS The special function registers are registers used by the

CPU and Peripheral functions for controlling the desired operation of the device (Table 4-1). These registers are static RAM.

The special registers can be classiﬁed into two sets (core and peripheral). The special function registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.

TABLE 4-1: SPECIAL REGISTERS FOR THE PIC16CE62X

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR/BOR

Reset

Value on all

other

resets

(1)

Bank 0

00h INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

xxxx xxxx xxxx xxxx

01h TMR0 Timer0 Module’s Register

xxxx xxxx uuuu uuuu

02h PCL Program Counter's (PC) Least Signiﬁcant Byte

0000 0000 0000 0000

03h STATUS

IRP

(2)

RP1

(2)

RP0 T

O PD Z DC C

0001 1xxx 000q quuu

04h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h PORTA

— — — RA4 RA3 RA2 RA1 RA0 ---x 0000 ---u 0000 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 07h Unimplemented — — 08h Unimplemented — — 09h Unimplemented — — 0Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000 0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 0Ch PIR1

— CMIF — — — — — — -0-- ---- -0-- ---- 0Dh-1Eh Unimplemented — — 1Fh CMCON C2OUT C1OUT

— — CIS CM2 CM1 CM0 00-- 0000 00-- 0000

Bank 1

80h INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

xxxx xxxx xxxx xxxx

81h OPTION RBPU

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000 83h STATUS IRP RP1 RP0 T

O PD Z DC C 0001 1xxx 000q quuu 84h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRISA

— — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111 87h Unimplemented — — 88h Unimplemented — — 89h Unimplemented — — 8Ah PCLATH

— — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000 8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 8Ch PIE1

— CMIE — — — — — — -0-- ---- -0-- ---- 8Dh Unimplemented — — 8Eh PCON

— — — — — — POR BOR ---- --0x ---- --uq 8Fh-9Eh Unimplemented — — 90h EEINTF

— — — — — EESCL EESDA EEVDD uuuu u111 uuuu u111 9Fh VRCON VREN VROE VRR

— VR3 VR2 VR1 VR0 000- 0000 000- 0000

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

shaded = unimplemented

Note 1: Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during

normal operation.

Note 2: IRP & RPI bits are reserved, always maintain these bits clear.

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4.2.2.1 STATUS REGISTER The STATUS register, shown in Figure 4-6, contains

the arithmetic status of the ALU, the RESET status and the bank select bits for data memory.

The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the T

O and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This lea ves the status register as 000uu1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect any status bit. For other instructions, not affecting any status bits, see the “Instruction Set Summary”.

Note 1: The IRP and RP1 bits (STATUS<7:6>)

are not used by the PIC16CE62X and should be programmed as ’0'. Use of these bits as general purpose R/W bits is NOT recommended, since this may affect upward compatibility with future products.

Note 2: The C and DC bits operate as a Borro

w and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

FIGURE 4-6: STATUS REGISTER (ADDRESS 03H OR 83H)

Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1

RP0 TO PD Z DC C R = Readable bit

W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset

-x = Unknown at POR reset

bit7 bit0

bit 7: IRP: The IRP bit is reserved on the PIC16CE62X, always maintain this bit clear. bit 6:5 RP1: RPO: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes. The RP1 bit is reserved, always maintain this bit clear.

bit 4: T

O: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred

bit 3: PD

: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

bit 2: Z: Zero bit

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

bit 1: DC: Digit carry/borro

w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result

bit 0: C: Carry/borro

w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most signiﬁcant bit of the result occurred 0 = No carry-out from the most signiﬁcant bit of the result occurred Note: For borro

w the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.

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4.2.2.2 OPTION REGISTER The OPTION register is a readable and writable

register which contains various control bits to conﬁgure the TMR0/WDT prescaler, the external RB0/INT interrupt, TMR0, and the weak pull-ups on PORTB.

Note: To achieve a 1:1 prescaler assignment for

TMR0, assign the prescaler to the WDT (PSA = 1).

FIGURE 4-7: OPTION REGISTER (ADDRESS 81H)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit

W = Writable bit

- n = Value at POR reset

bit7 bit0

bit 7: RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values

bit 6: INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin

bit 5: T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT)

bit 4: T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3: PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

bit 2-0: PS2:PS0: Prescaler Rate Select bits

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Bit Value TMR0 Rate WDT Rate

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4.2.2.3 INTCON REGISTER The INTCON register is a readable and writable

register which contains the various enable and ﬂag bits for all interrupt sources except the comparator module. See Section 4.2.2.4 and Section 4.2.2.5 for a description of the comparator enable and ﬂag bits.

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).

FIGURE 4-8: INTCON REGISTER (ADDRESS 0BH OR 8BH)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

-x = Unknown at POR reset

bit7 bit0

bit 7: GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts 0 = Disables all interrupts

bit 6: PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts

bit 5: T0IE: TMR0 Overﬂow Interrupt Enable bit

1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt

bit 4: INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt

bit 3: RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt

bit 2: T0IF: TMR0 Overﬂow Interrupt Flag bit

1 = TMR0 register has overﬂowed (must be cleared in software) 0 = TMR0 register did not overﬂow

bit 1: INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur

bit 0: RBIF: RB Port Change Interrupt Flag bit

1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state

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4.2.2.4 PIE1 REGISTER This register contains the individual enable bit for the

comparator interrupt.

FIGURE 4-9: PIE1 REGISTER (ADDRESS 8CH)

U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

— CMIE — — — — — — R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: Unimplemented: Read as '0' bit 6: CMIE: Comparator Interrupt Enable bit

1 = Enables the Comparator interrupt 0 = Disables the Comparator interrupt

bit 5-0: Unimplemented: Read as '0'

4.2.2.5 PIR1 REGISTER This register contains the individual ﬂag bit for the com-

parator interrupt.

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt ﬂag bits are clear prior to enabling an interrupt.

FIGURE 4-10: PIR1 REGISTER (ADDRESS 0CH)

U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

— CMIF — — — — — — R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: Unimplemented: Read as '0' bit 6: CMIF: Comparator Interrupt Flag bit

1 = Comparator input has changed 0 = Comparator input has not changed

bit 5-0: Unimplemented: Read as '0'

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4.2.2.6 PCON REGISTER The PCON register contains ﬂag bits to differentiate

between a Power-on Reset, an external MCLR

reset,

WDT reset or a Brown-out Reset.

Note: BOR is unknown on Power-on Reset. It

must then be set by the user and checked on subsequent resets to see if BOR

is cleared, indicating a brown-out has occurred. The BOR

status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (by programming BODEN bit in the Conﬁguration word).

FIGURE 4-11: PCON REGISTER (ADDRESS 8Eh)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — — POR BOR R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-2: Unimplemented: Read as '0' bit 1: POR

: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0: BOR

: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

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4.3 PCL and PCLATH

The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any reset, the PC is cleared. Figure 4-12 shows the two situations for the loading of the PC. The upper example in the ﬁgure shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH). The lo wer example in the ﬁgure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> → PCH).

FIGURE 4-12: LOADING OF PC IN

DIFFERENT SITUATIONS

4.3.1 COMPUTED GOTO A computed GOTO is accomplished by adding an

offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the tab le location crosses a PCL memory boundary (each 256 byte block). Refer to the application note

“Implementing a Table Read"

(AN556).

12 8 7 0

PCLA TH<4:0>

PCLA TH

Instr

uction with

ALU result

GOTO, CALL

Opcode <10:0>

12 11 10 0

PCLATH<4:3>

PCH PCL

8 7

PCLATH

PCH PCL

PCL as Destination

4.3.2 STACK The PIC16CE62X family has an 8 level deep x 13-bit

wide hardware stack (Figure 4-2 and Figure 4-3). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the e vent of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buff er . This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the ﬁrst push. The tenth push overwrites the second push (and so on).

Note 1: There are no STATUS bits to indicate

stack overﬂow or stack underﬂow conditions.

Note 2: There are no instruction mnemonics

called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions, or the vectoring to an interrupt address.

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4.4 Indirect Addressing, INDF and FSR Registers

The INDF register is not a physical register . Addressing the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the ﬁle select register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-13. However, IRP is not used in the PIC16CE62X.

A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 4-1.

EXAMPLE 4-1: INDIRECT ADDRESSING

movlw 0x20 ;initialize pointer movwf FSR ;to RAM

EXT clrf INDF ;clear INDF register

incf FSR ;inc pointer btfss FSR,4 ;all done? goto NEXT ;no clear next

;yes continue

CONTINUE:

FIGURE 4-13: DIRECT/INDIRECT ADDRESSING PIC16CE62X

For memory map detail see Figure 4-4 and Figure 4-5. Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.

Data Memory

Indirect AddressingDirect Addressing

bank select location select

(1)

RP1 RP0 6

from opcode

IRP

(1)

FSR register

bank select

location select

00 01 10 11

00h

7Fh

00h

7Fh

Bank 0 Bank 1 Bank 2 Bank 3

not used

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NOTES:

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PIC16CE62X

5.0 I/O PORTS

The PIC16CE62X parts have two ports, PORTA and PORTB. Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.

5.1 PORTA and TRISA Registers

PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input and an open drain output. P ort RA4 is multiplexed with the T0CKI clock input. All other RA port pins have Schmitt Trigger input levels and full CMOS output driv ers. All pins have data direction bits (TRIS registers) which can conﬁgure these pins as input or output.

A '1' in the TRISA register puts the corresponding output driver in a hi- impedance mode. A '0' in the TRISA register puts the contents of the output latch on the selected pin(s).

Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are ﬁrst read, then this value is modiﬁed and written to the port data latch.

The PORTA pins are multiplexed with comparator and voltage reference functions. The operation of these pins are selected by control bits in the CMCON (comparator control register) register and the VRCON (voltage reference control register) register. When selected as a comparator input, these pins will read as '0's.

FIGURE 5-1: BLOCK DIAGRAM OF

RA1:RA0 PINS

Note: I/O pins have protection diodes to VDD and VSS.

Data bus

WR PortA

WR TRISA

Data Latch

TRIS Latch

RD TRISA

RD PORTA

Analog

VDD

I/O Pin

Input Mode

To Comparator

Schmitt Trigger

Input Buffer

TRISA controls the direction of the RA pins, even when they are being used as comparator inputs. The user must make sure to keep the pins conﬁgured as inputs when using them as comparator inputs.

The RA2 pin will also function as the output for the voltage reference. When in this mode, the V

REF pin is a

very high impedance output. The user must conﬁgure TRISA<2> bit as an input and use high impedance loads.

In one of the comparator modes deﬁned by the CMCON register, pins RA3 and RA4 become outputs of the comparators. The TRISA<4:3> bits must be cleared to enable outputs to use this function.

EXAMPLE 5-1: INITIALIZING PORTA

FIGURE 5-2: BLOCK DIAGRAM OF RA2 PIN

Note: On reset, the TRISA register is set to all

inputs. The digital inputs are disabled and the comparator inputs are forced to ground to reduce excess current consumption.

CLRF PORTA ;Initialize PORTA by setting

;output data latches MOVLW 0X07 ;Turn comparators off and MOVWF CMCON ;enable pins for I/O

;functions BSF STATUS, RP0 ;Select Bank1 MOVLW 0x1F ;Value used to initialize

;data direction MOVWF TRISA ;Set RA<4:0> as inputs

;TRISA<7:5> are always

;read as '0'.

Note: I/O pins have protection diodes to VDD and VSS.

Data bus

WR PortA

WR TRISA

Data Latch

TRIS Latch

RD TRISA

RD PORTA

Analog

VSS

VDD

RA2 Pin

Input Mode

To Comparator

Schmitt Trigger

Input Buffer

VROE VREF

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FIGURE 5-3: BLOCK DIAGRAM OF RA3 PIN

FIGURE 5-4: BLOCK DIAGRAM OF RA4 PIN

Data bus

WR PortA

WR TRISA

Data Latch

TRIS Latch

RD TRISA

RD PORTA

Analog

VSS

VDD

RA3 Pin

To Comparator

Schmitt Trigger

Input Buffer

Input Mode

Comparator Output

Comparator Mode = 110

Note: I/O pins have protection diodes to VDD and VSS

Data bus

WR PortA

WR TRISA

Data Latch

TRIS Latch

RD TRISA

RD PORTA

VSS

RA4 Pin

TMR0 Clock Input

Schmitt Trigger

Input Buffer

Comparator Output

Comparator Mode = 110

Note: RA4 has protection diodes to VSS only

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TABLE 5-1: PORTA FUNCTIONS

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit #

Buffer

Type

Function

RA0/AN0 bit0 ST Input/output or comparator input RA1/AN1 bit1 ST Input/output or comparator input RA2/AN2/V

REF bit2 ST Input/output or comparator input or VREF output

RA3/AN3 bit3 ST Input/output or comparator input/output RA4/T0CKI bit4 ST Input/output or external clock input for TMR0 or comparator output.

Output is open drain type.

Legend: ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR / BOR

Value on All Other

Resets

05h PORTA — — — RA4 RA3 RA2 RA1 RA0 ---x 0000 ---u 0000 85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111 1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 0000 00-- 0000 9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000

Legend: — = Unimplemented locations, read as ‘0’

Note: Note: Shaded bits are not used by PORTA.

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5.2 PORTB and TRISB Registers

PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. A '1' in the TRISB register puts the corresponding output driver in a high impedance mode. A '0' in the TRISB register puts the contents of the output latch on the selected pin(s).

Reading PORTB register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the por t pins are ﬁrst read, then this value is modiﬁed and written to the port data latch.

Each of the PORTB pins has a weak internal pull-up (≈200 µA typical). A single control bit can turn on all the pull-ups. This is done by clearing the RBPU (OPTION<7>) bit. The weak pull-up is automatically turned off when the port pin is conﬁgured as an output. The pull-ups are disabled on Power-on Reset.

Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins conﬁgured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin conﬁgured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RBIF interrupt (ﬂag latched in INTCON<0>).

FIGURE 5-5: BLOCK DIAGRAM OF

RB7:RB4 PINS

Data Latch

From other

RBPU

(2)

I/O

Q D

Data bus

WR PortB

WR TRISB

Set RBIF

TRIS Latch

RD TRISB

RD PortB

RB7:RB4 pins

weak pull-up

RD Port

Latch

TTL Input Buffer

(1)

Note 1: I/O pins have diode protection to VDD and VSS.

Note 2: TRISB = 1 enables weak pull-up if RBPU

= '0'

(OPTION<7>).

ST Buffer

RB7:RB6 in serial programming mode

This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear ﬂag bit RBIF. A mismatch condition will continue to set ﬂag bit RBIF.

Reading PORTB will end the mismatch condition, and allow ﬂag bit RBIF to be cleared.

This interrupt on mismatch feature, together with software conﬁgurable pull-ups on these four pins allow easy interface to a key pad and make it possible for wake-up on key-depression. (See AN552 in the Microchip

Embedded Control Handbook

The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.

FIGURE 5-6: BLOCK DIAGRAM OF

RB3:RB0 PINS

Note: If a change on the I/O pin should occur

when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt ﬂag may not get set.

Data Latch

RBPU

(2)

Q D

Data bus

WR PortB

WR TRISB

RD TRISB

RD PortB

weak pull-up

RD Port

RB0/INT

I/O pin

(1)

TTL Input Buffer

Note 1: I/O pins have diode protection to V

DD and VSS.

Note 2: TRISB = 1 enables weak pull-up if RBPU

= '0'

(OPTION<7>).

ST Buffer

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TABLE 5-3: PORTB FUNCTIONS

TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name Bit # Buffer Type Function

RB0/INT bit0

TTL/ST

(1)

Input/output or external interrupt input. Internal software programmable

weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software

programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software

programmable weak pull-up. RB6 bit6

TTL/ST

(2)

Input/output pin (with interrupt on change). Internal software

programmable weak pull-up. Serial programming clock pin. RB7 bit7

TTL/ST

(2)

Input/output pin (with interrupt on change). Internal software

programmable weak pull-up. Serial programming data pin.

Legend: ST = Schmitt Trigger, TTL = TTL input Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt. Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR / BOR

Value on All Other

Resets

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Note: Shaded bits are not used by PORTB.

u = unchanged x = unknown

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5.3 I/O Programming Considerations

5.3.1 BI-DIRECTIONAL I/O PORTS Any instruction which writes, operates internally as a

read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, ex ecute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs deﬁned. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used as a bidirectional I/O pin (e.g., bit0) and it is deﬁned as an input at this time, the input signal present on the pin itself would be read into the CPU and re-written to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch may now be unknown.

Reading the port register, reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read modify write instructions (ex. BCF, BSF , etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch.

Example 5-2 shows the effect of two sequential read-modify-write instructions (ex., BCF, BSF, etc.) on an I/O port.

A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin (“wired-or”, “wired-and”). The resulting high output currents may damage the chip.

EXAMPLE 5-2: READ-MODIFY-WRITE

INSTRUCTIONS ON AN I/O PORT

5.3.2 SUCCESSIVE OPERATIONS ON I/O PORTS The actual write to an I/O port happens at the end of an

instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-7). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that ﬁle to be read into the CPU is executed. Otherwise , the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with an NOP or another instruction not accessing this I/O port.

;;Initial PORT settings: PORTB<7:4> Inputs

; PORTB<3:0> Outputs ;;PORTB<7:6> have external pull-up and are not

connected to other circuitry ; ; PORT latch PORT pins ; ---------- ----------

BCF PORTB, 7 ;01pp pppp 11pp pppp BCF PORTB, 6 ;10pp pppp 11pp pppp BSF STATUS,RP0 ; BCF TRISB, 7 ;10pp pppp 11pp pppp

BCF TRISB, 6 ;10pp pppp 10pp pppp ; ; Note that the user may have expected the pin ; values to be 00pp pppp. The 2nd BCF caused ; RB7 to be latched as the pin value (High).

FIGURE 5-7: SUCCESSIVE I/O OPERATION

Note: This example shows write to PORTB

followed by a read from PORTB. Note that:

data setup time = (0.25 T

CY - TPD)

where TCY = instruction cycle and TPD = propagation delay of Q1 cycle to output valid.

Therefore, at higher clock frequencies, a write followed by a read may be problematic.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

RB <7:0>

Port pin sampled here

PC + 1 PC + 2 PC + 3

NOPNOPMOVF PORTB, W

Read PORTB

MOVWF PORTB

Write to PORTB

Instruction

fetched

Execute

MOVWF

PORTB

Execute

MOVF

PORTB, W

Execute

NOP

RB7:RB0

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PIC16CE62X

6.0 EEPROM PERIPHERAL OPERATION

The PIC16CE623/624/625 each have 128 bytes of EEPROM data memory. The EEPROM data memory supports a bi-directional 2-wire bus and data transmission protocol. These two-wires are serial data (SDA) and serial clock (SCL), that are mapped to bit1 and bit2, respectively , of the EEINTF register (SFR 90h). In addition, the power to the EEPROM can be controlled using bit0 (EEV

DD) of the EEINTF register. For most

applications, all that is required is calls to the following functions:

; Byte_Write: Byte write routine ; Inputs: EEPROM Address EEADDR ; EEPROM Data EEDATA ; Outputs: Return 01 in W if OK, else return 00 in W ; ; Read_Current: Read EEPROM at address currently held by EE device. ; Inputs: NONE ; Outputs: EEPROM Data EEDATA ; Return 01 in W if OK, else return 00 in W ; ; Read_Random: Read EEPROM byte at supplied address ; Inputs: EEPROM Address EEADDR ; Outputs: EEPROM Data EEDATA ; Return 01 in W if OK,

else return 00 in W

The code for these functions is not yet determined, but will be available on our web site (www.microchip.com) when it is completed. The code will be accessed by either including the source code FLASH62X.INC or by linking FLASH62X.ASM.

6.0.1 SERIAL DATA SDA is a bi-directional pin used to transfer addresses

and data into and data out of the memory. For normal data transfer SD A is allowed to change only

during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions.

6.0.2 SERIAL CLOCK This SCL input is used to synchronize the data tr ansf er

from and to the memory.

6.0.3 EEINTF REGISTER The EEINTF register (SFR 90h) controls the access to

the EEPROM. Figure 6.1 details the function of each bit. User code must generate the clock and data signals.

FIGURE 6-1: EEINFT REGISTER (ADDRESS 90h)

U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1

- - - - - EESCL EESDA EEVDD R = Readable bit W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-3: Unimplemented: Read as '0' bit 2: EESCL: Clock line to the EEPROM

1 = Clock high 0 = Clock low

bit 1: EESDA: Data line to EEPROM

1 = Data line is high (pin is tri-stated, line is pulled high by a pull-up resistor) 0 = Data line is low

bit 0: EEVDD: V

DD control bit for EEPROM

1 = V

DD is turned on EEPROM

0 = V

DD is turned off EEPROM (all pins are tri-stated and the EEPROM is powered down)

Note: EESDA, EESCL and EEV

DD will read ‘0’ if EEVDD is turned off

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6.1 BUS CHARACTERISTICS

In this section, the term “processor” ref ers to the portion of the PIC16CE62X that interfaces to the EEPROM through software manipulating the EEINTF register. The following bus protocol is to be used with the EEPROM data memory.

• Data transfer may be initiated only when the bus is not busy.

• During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted by the EEPROM as a START or STOP condition.

Accordingly , the following bus conditions have been deﬁned (Figure 6-2).

6.1.1 BUS NOT BUSY (A)

Both data and clock lines remain HIGH.

6.1.2 START DATA TRANSFER (B)

A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition.

6.1.3 STOP DATA TRANSFER (C)

A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.

6.1.4 DATA VALID (D)

The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW period of the clock signal. There is one bit of data per clock pulse.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the processor and is theoretically unlimited, although only the last sixteen will be stored when doing a write operation. When an overwrite does occur, it will replace data in a ﬁrst-in, ﬁrst-out fashion.

6.1.5 ACKNOWLEDGE The EEPROM will generate an acknowledge after the

reception of each byte. The processor must generate an extra clock pulse which is associated with this acknowledge bit.

When the EEPROM acknowledges, it pulls down the SDA line during the acknowledge cloc k pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. The processor must signal an end of data to the EEPROM by not generating an acknowledge bit on the last byte that has been clocked out of the EEPR OM. In this case, the EEPROM must leave the data line HIGH to enable the processor to generate the STOP condition (Figure 6-3).

Note: Acknowledge bits are not generated if an

internal programming cycle is in progress.

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PIC16CE62X

FIGURE 6-2: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 6-3: ACKNOWLEDGE TIMING

(A)

(B)

(C)

(D)

(A)(C)

SCL

SDA

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

SCL

987654321 1 2 3

Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data.

Receiver must release the SDA line at this point so the Transmitter can continue sending data.

Data from transmitter

SDA

Acknowledge

Bit

6.2 Device Addressing

After generating a START condition, the processor transmits a control byte consisting of a EEPROM address and a Read/Wr

ite bit that indicates what type of operation is to be performed. The EEPROM address consists of a 4-bit device code (1010) follo wed by three don't care bits.

The last bit of the control byte determines the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected. (Figure 6-4). The bus is monitored for its corresponding EEPROM address all the time . It generates an acknowledge bit if the EEPROM address was true and it is not in a programming mode.

FIGURE 6-4: CONTROL BYTE FORMAT

1 0 1 0 X X XS ACKR/W

Device Select

Bits

Don’t Care

Bits

EEPROM Address

Acknowledge Bit

Start Bit

Read/Wr

ite Bit

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6.3 WRITE OPERATIONS

6.3.1 BYTE WRITE Following the start signal from the processor, the

device code (4 bits), the don't care bits (3 bits), and the R/W

bit which is a logic low is placed onto the bus by

the processor. This indicates to the EEPROM that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore the next b yte transmitted by the processor is the word address and will be written into the address pointer of the EEPROM. After receiving another acknowledge signal from the EEPROM the processor will transmit the data word to be written into the addressed memory location. The EEPROM acknowledges again and the processor generates a stop condition. This initiates the internal write cycle, and during this time the EEPROM will not generate acknowledge signals (Figure 6-6).

6.3.2 PAGE WRITE The write control byte, word address and the ﬁrst data

byte are transmitted to the EEPROM in the same way as in a byte write. But instead of generating a stop condition the processor transmits up to eight data bytes to the EEPROM which are temporarily stored in the onchip page buffer and will be written into the memory after the processor has transmitted a stop condition. After the receipt of each word, the three lower order address pointer bits are internally incremented by one. The higher order ﬁve bits of the word address remains constant. If the processor should transmit more than eight words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an internal write cycle will begin (Figure 6-7).

6.4 ACKNOWLEDGE POLLING

Since the EEPROM will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the processor, the EEPROM initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the processor sending a start condition followed by the control byte for a write command (R/W

= 0). If the device is still busy with the write cycle, then no A CK will be returned. If no ACK is returned, then the start bit and control byte must be re-sent. If the cycle is complete, then the device will return the ACK and the processor can then proceed with the next read or write command. See Figure 6-5 for ﬂow diagram.

FIGURE 6-5: ACKNOWLEDGE POLLING

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did EEPROM Acknowledge

(ACK = 0)?

Operation

YES

FIGURE 6-6: BYTE WRITE

BUS ACTIVITY PROCESSOR

SDA LINE

BUS ACTIVITY

S T A R T

S T O P

CONTROL

BYTE

WORD

ADDRESS

DATA

A C K

1 0 X1 0 XX X

X = Don’t Care Bit

X X X

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PIC16CE62X

FIGURE 6-7: PAGE WRITE

S P

BUS ACTIVITY PROCESSOR

SDA LINE

BUS ACTIVITY

S T A R T

S T O P

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n DATAn + 7

DATAn + 1

A C K

6.5 READ OPERATION

Read operations are initiated in the same way as write operations with the exception that the R/W

bit of the EEPROM address is set to one. There are three basic types of read operations: current address read, random read, and sequential read.

6.6 Current Address Read

The EEPROM contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the EEPROM address with R/W

bit set to one, the EEPROM issues an acknowledge and transmits the eight bit data word. The processor will not acknowledge the transfer but does generate a stop condition and the EEPROM discontinues transmission (Figure 6-8).

6.7 Random Read

Random read operations allow the processor to access any memory location in a random manner. To perform this type of read operation, ﬁrst the word address must be set. This is done by sending the word address to the EEPROM as part of a write operation. After the word address is sent, the processor generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the processor issues the control byte again but with the R/W

bit set to a one. The EEPROM will then issue an acknowledge and transmits the eight bit data word. The processor will not acknowledge the transfer but does generate a stop condition and the EEPROM discontinues transmission (Figure 6-9).

6.8 Sequential Read

Sequential reads are initiated in the same way as a random read except that after the EEPROM transmits the ﬁrst data byte, the processor issues an acknowledge as opposed to a stop condition in a random read. This directs the EEPROM to transmit the next sequentially addressed 8-bit word (Figure 6-10).

To provide sequential reads the EEPROM contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation.

6.9 Noise Protection

The EEPROM employs a VCC threshold detector circuit which disables the internal erase/write logic if the V

is below 1.5 volts at nominal conditions. The SCL and SDA inputs hav e Schmitt trigger and ﬁlter

circuits which suppress noise spikes to assure proper device operation even on a noisy bus.

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DS40182A-page 34 Preliminary  1998 Microchip Technology Inc.

FIGURE 6-8: CURRENT ADDRESS READ

FIGURE 6-9: RANDOM READ

FIGURE 6-10: SEQUENTIAL READ

S P

BUS ACTIVITY PROCESSOR

SDA LINE

BUS ACTIVITY

S T A R T

CONTROL

BYTE

DATA n

A C K

N O

A C K

S T O P

S P

BUS ACTIVITY PROCESSOR

SDA LINE

BUS ACTIVITY

S T A R T

S T O P

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n

A C K

N O

A C K

CONTROL

BYTE

A C K

S T A R T

SDA LINE

BUS ACTIVITY

S T O P

CONTROL

BYTE

DATA n

A C K

N O

A C K

DATA n + 1 DATA n + 2 DATA n + X

BUS ACTIVITY PROCESSOR

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PIC16CE62X

7.0 TIMER0 MODULE

The Timer0 module timer/counter has the following features:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overﬂow from FFh to 00h

• Edge select for external clock Figure 7-1 is a simpliﬁed block diagram of the Timer0

module. Timer mode is selected by clearing the T0CS bit

(OPTION<5>). In timer mode , the TMR0 will increment every instruction cycle (without prescaler). If Timer0 is written, the increment is inhibited for the following two cycles (Figure 7-2 and Figure 7-3). The user can work around this by writing an adjusted value to TMR0.

Counter mode is selected by setting the T0CS bit. In this mode Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the source edge (T0SE) control

bit (OPTION<4>). Clearing the T0SE bit selects the rising edge. Restrictions on the e xternal clock input are discussed in detail in Section 7.2.

The prescaler is shared between the Timer0 module and the WatchdogTimer. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale value of 1:2, 1:4, ..., 1:256 are selectable. Section 7.3 details the operation of the prescaler.

7.1 TIMER0 Interrupt

Timer0 interrupt is generated when the TMR0 register timer/counter overﬂows from FFh to 00h. This overﬂow sets the T0IF bit. The interrupt can be masked by clearing the T0IE bit (INTCON<5>). The T0IF bit (INTCON<2>) must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The Timer0 interrupt cannot wake the processor from SLEEP since the timer is shut off during SLEEP. See Figure 7-4 for Timer0 interrupt timing.

FIGURE 7-1: TIMER0 BLOCK DIAGRAM

FIGURE 7-2: TIMER0 (TMR0) TIMING: INTERNAL CLOCK/NO PRESCALER

Note 1: Bits T0SE, T0CS, PS2, PS1, PS0 and PSA are located in the OPTION register.

2: The prescaler is shared with Watchdog Timer (Figure 7-6)

RA4/T0CKI

T0SE

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

clocks

TMR0

PSout

(2 cycle delay)

PSout

Data bus

Set Flag bit T0IF

on Overﬂow

PSA

PS2:PS0

PC-1

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC (Program Counter)

Instruction

Fetch

TMR0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2

MOVWF TMR0

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0 executed

Read TMR0 reads NT0

Read TMR0 reads NT0 + 1

Read TMR0 reads NT0 + 2

Instruction Executed

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DS40182A-page 36 Preliminary  1998 Microchip Technology Inc.

FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

FIGURE 7-4: TIMER0 INTERRUPT TIMING

PC-1

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC (Program Counter)

Instruction

Fetch

TMR0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 NT0+1

MOVWF TMR0

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0 executed

Read TMR0 reads NT0

Read TMR0 reads NT0 + 1

T0+1

NT0

Instruction Execute

Q2Q1 Q3 Q4Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT(3)

TMR0 timer

T0IF bit (INTCON<2>)

FEh

GIE bit (INTCON<7>)

INSTR

UCTION FLOW

Instruction fetched

PC +1 PC +1 0004h 0005h

Instruction executed

Inst (PC)

Inst (PC-1)

Inst (PC+1)

Inst (PC)

Inst (0004h) Inst (0005h)

Inst (0004h)Dummy cycle Dummy cycle

FFh 00h 01h 02h

Note 1: T0IF interrupt ﬂag is sampled here (every Q1).

2: Interrupt latency = 4T

CY, where TCY = instruction cycle time.

3: CLKOUT is available only in RC oscillator mode.

Interrupt Latency Time

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PIC16CE62X

7.2 Using Timer0 with External Clock

When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (T

OSC)

synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization.

7.2.1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 7-5). Therefore, it is necessary for T0CKI to be high for at least 2T

OSC (and a small RC delay of 20 ns)

and low for at least 2T

OSC (and a small RC delay of

20 ns). Refer to the electrical speciﬁcation of the desired device.

When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4T

OSC (and a small RC delay of

40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that the y do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical speciﬁcation of the desired device.

7.2.2 TIMER0 INCREMENT DELAY Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the external clock edge occurs to the time the TMR0 is actually incremented. Figure 7-5 shows the delay from the external clock edge to the timer incrementing.

FIGURE 7-5: TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

External Clock Input or Prescaler output

(2)

External Clock/Prescaler Output after sampling

Increment Timer0 (Q4)

Timer0

T0 T0 + 1 T0 + 2

Small pulse misses sampling

Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).

Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs.

(3)

(1)

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7.3 Prescaler

An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 7-6). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that there is only one prescaler available which is mutually exclusive between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa.

The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,

BSF 1,x....etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable.

FIGURE 7-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

T0CKI

T0SE

M U

CLKOUT (=Fosc/4)

SYNC

Cycles

TMR0 reg

8-bit Prescaler

8-to-1MUX

U X

M U X

Watchdog

Timer

PSA

WDT

Time-out

PS0 - PS2

Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.

PSA

WDT Enable bit

M U

Data Bus

Set ﬂag bit T0IF

on Overﬂow

PSA

T0CS

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7.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software

control (i.e., it can be changed “on the ﬂy” during program execution). To avoid an unintended device RESET, the following instruction sequence (Example 7-1) must be executed when changing the prescaler assignment from Timer0 to WDT.

EXAMPLE 7-1: CHANGING PRESCALER

(TIMER0→WDT)

1.BCF STATUS, RP0 ;Skip if already in ; Bank 0

2.CLRWDT ;Clear WDT

3.CLRF TMR0 ;Clear TMR0 & Prescaler

4.BSF STATUS, RP0 ;Bank 1

5.MOVLW '00101111’b; ;These 3 lines (5, 6, 7)

6.MOVWF OPTION ; are required only if

; desired PS<2:0> are

7.CLRWDT ; 000 or 001

8.MOVLW '00101xxx’b ;Set Postscaler to

9.MOVWF OPTION ; desired WDT rate

10.BCF STATUS, RP0 ;Return to Bank 0

To change prescaler from the WDT to the TMR0 module use the sequence shown in Example 7-2. This precaution must be taken even if the WDT is disabled.

EXAMPLE 7-2: CHANGING PRESCALER

(WDT→TIMER0)

CLRWDT ;Clear WDT and

;prescaler BSF STATUS, RP0 MOVLW b'xxxx0xxx' ;Select TMR0, new

;prescale value and

;clock source MOVWF OPTION_REG BCF STATUS, RP0

TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR / BOR

Value on All Other

Resets

01h TMR0 Timer0 module register xxxx xxxx uuuu uuuu 0Bh/8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111

Legend: — = Unimplemented locations, read as ‘0’.

Note: Shaded bits are not used by TMR0 module.

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NOTES:

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PIC16CE62X

8.0 COMPARATOR MODULE

The comparator module contains two analog comparators. The inputs to the comparators are multiplexed with the RA0 through RA3 pins. The on-chip Voltage Reference (Section 9.0) can also be an input to the comparators.

The CMCON register, shown in Figure 8-1, controls the comparator input and output multiplexers. A block diagram of the comparator is shown in Figure 8-2.

FIGURE 8-1: CMCON REGISTER (ADDRESS 1Fh)

R-0 R-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

C2OUT C1OUT

CIS CM2 CM1 CM0 R = Readable bit

W =Writable bit U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7: C2OUT: Comparator 2 output

1 = C2 V

IN+ > C2 VIN–

0 = C2 V

IN+ < C2 VIN–

bit 6: C1OUT: Comparator 1 output

1 = C1 V

IN+ > C1 VIN–

0 = C1 V

IN+ < C1 VIN–

bit 5-4: Unimplemented: Read as '0' bit 3: CIS: Comparator Input Switch

When CM<2:0>: = 001: 1 = C1 V

IN– connects to RA3

0 = C1 V

IN– connects to RA0

When CM<2:0> = 010: 1 = C1 V

IN– connects to RA3

C2 V

IN– connects to RA2

0 = C1 V

IN– connects to RA0

C2 V

IN– connects to RA1

bit 2-0: CM<2:0>: Comparator mode

Figure 8-2.

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8.1 Comparator Conﬁguration

There are eight modes of operation for the comparators. The CMCON register is used to select the mode. Figure 8-2 shows the eight possible modes. The TRISA register controls the data direction of the comparator pins for each mode. If the comparator mode is

changed, the comparator output level may not be valid for the speciﬁed mode change delay shown in Table 13-2.

Note: Comparator interrupts should be disabled

during a comparator mode change otherwise a false interrupt may occur.

FIGURE 8-2: COMPARATOR I/O OPERATING MODES

VINV

IN+

Off

(Read as '0')

RA0/AN0 RA3/AN3

A A

CM<2:0> = 000

VINV

IN+

Off

(Read as '0')

RA1/AN1 RA2/AN2

A A

VINV

IN+

Off

(Read as '0')

RA0/AN0 RA3/AN3

D D

CM<2:0> = 111

VINV

IN+

Off

(Read as '0')

RA1/AN1 RA2/AN2

D D

VINV

IN+

C1OUT

RA0/AN0 RA3/AN3

A A

VINV

IN+

C2OUT

RA1/AN1

RA2/AN2

A A

CM<2:0> = 100

VINV

IN+

C1OUT

RA0/AN0 RA3/AN3

A A

VINV

IN+

C2OUT

RA1/AN1 RA2/AN2

A A

From VREF Module

VINV

IN+

C1OUT

RA0/AN0 RA3/AN3

A D

VINV

IN+

C2OUT

RA1/AN1

RA2/AN2

A A

CM<2:0> = 011

RA4 Open Drain

VINV

IN+

C1OUT

RA0/AN0

RA3/AN3

A D

VINV

IN+

C2OUT

RA1/AN1

RA2/AN2

A A

CM<2:0> = 110

VINV

IN+

Off

(Read as '0')

RA0/AN0 RA3/AN3

D D

CM<2:0> = 101

VINV

IN+

C2OUT

RA1/AN1 RA2/AN2

A A

VINV

IN+

C1OUT

RA0/AN0 RA3/AN3

A A

VINV

IN+

C2OUT

RA1/AN1 RA2/AN2

A A

CM<2:0> = 001

CIS=0 CIS=1

Comparators Reset

Two Independent Comparators

Two Common Reference Comparators

One Independent Comparator

Three Inputs Multiplexed to

Two Common Rference Comparators with Outputs

Four Inputs Multiplexed to

Comparators Off

Two Comparators

CM<2:0> = 010

CIS=0 CIS=1

A = Analog Input, Port Reads Zeros Always D = Digital Input CIS = CMCON<3>, Comparator Input Switch

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PIC16CE62X

The code example in Example 8-1 depicts the steps required to conﬁgure the comparator module. RA3 and RA4 are conﬁgured as digital output. RA0 and RA1 are conﬁgured as the V- inputs and RA2 as the V+ input to both comparators.

EXAMPLE 8-1: INITIALIZING

COMPARATOR MODULE

8.2 Comparator Operation

A single comparator is shown in Figure 8-3 along with the relationship between the analog input levels and the digital output. When the analog input at V

IN+ is less

than the analog input V

IN–, the output of the

comparator is a digital low lev el. When the analog input at V

IN+ is greater than the analog input VIN–, the output

of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 8-3 represent the uncertainty due to input offsets and response time.

FLAG_REG EQU 0X20 CLRF FLAG_REG ;Init flag register CLRF PORTA ;Init PORTA MOVF CMCON,W ;Move comparator contents to W ANDLW 0xC0 ;Mask comparator bits IORWF FLAG_REG,F ;Store bits in flag register MOVLW 0x03 ;Init comparator mode MOVWF CMCON ;CM<2:0> = 011 BSF STATUS,RP0 ;Select Bank1 MOVLW 0x07 ;Initialize data direction MOVWF TRISA ;Set RA<2:0> as inputs

;RA<4:3> as outputs ;TRISA<7:5> always read ‘0’

BCF STATUS,RP0 ;Select Bank 0 CALL DELAY 10 ;10µs delay MOVF CMCON,F ;Read CMCON to end change condition BCF PIR1,CMIF ;Clear pending interrupts BSF STATUS,RP0 ;Select Bank 1 BSF PIE1,CMIE ;Enable comparator interrupts BCF STATUS,RP0 ;Select Bank 0 BSF INTCON,PEIE ;Enable peripheral interrupts BSF INTCON,GIE ;Global interrupt enable

8.3 Comparator Reference

An external or internal reference signal may be used depending on the comparator operating mode. The analog signal that is present at V

IN– is compared to the

signal at V

IN+, and the digital output of the comparator

is adjusted accordingly (Figure 8-3).

FIGURE 8-3: SINGLE COMPARATOR

8.3.1 EXTERNAL REFERENCE SIGNAL When external voltage references are used, the

comparator module can be conﬁgured to have the comparators operate from the same or different reference sources. However, threshold detector applications may require the same reference. The reference signal must be between V

SS and VDD, and can be applied to either

pin of the comparator(s).

8.3.2 INTERNAL REFERENCE SIGNAL The comparator module also allows the selection of an

internally generated voltage reference for the comparators. Section 13, Instruction Sets, contains a detailed description of the Voltage Reference Module that provides this signal. The internal reference signal is used when the comparators are in mode CM<2:0>=010 (Figure 8-2). In this mode, the internal voltage reference is applied to the V

IN+ pin of both com-

parators.

–

VIN+ V

IN–

Output

VIN– VIN+

Output

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8.4 Comparator Response Time

Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output is guaranteed to have a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. Otherwise the maximum delay of the comparators should be used (Table 13-2 ).

8.5 Comparator Outputs

The comparator outputs are read through the CMCON register. These bits are read only. The comparator outputs may also be directly output to the RA3 and RA4 I/O pins. When the CM<2:0> = 110, multiplexors in the output path of the RA3 and RA4 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the speciﬁcations. Figure 8-4 shows the comparator output block diagram.

The TRISA bits will still function as an output enable/disable for the RA3 and RA4 pins while in this mode.

Note 1: When reading the PORT register , all pins

conﬁgured as analog inputs will read as a ‘0’. Pins conﬁgured as digital inputs will convert an analog input according to the Schmitt Trigger input speciﬁcation.

2: Analog levels on any pin that is deﬁned

as a digital input may cause the input buffer to consume more current than is speciﬁed.

FIGURE 8-4: COMPARATOR OUTPUT BLOCK DIAGRAM

To RA3 or RA4 Pin

Bus Data

RD CMCON

Set

MULTIPLEX

CMIF Bit

Port Pins

RD CMCON

NRESET

From Other Comparator

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8.6 Comparator Interrupts

The comparator interrupt ﬂag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that has occurred. The CMIF bit, PIR1<6>, is the comparator interrupt ﬂag. The CMIF bit must be reset by clearing ‘0’. Since it is also possible to write a '1' to this register, a simulated interrupt may be initiated.

The CMIE bit (PIE1<6>) and the PEIE bit (INTCON<6>) must be set to enable the interrupt. In addition, the GIE bit must also be set. If any of these bits are clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs.

The user, in the interrupt service routine, can clear the interrupt in the following manner:

a) Any read or write of CMCON. This will end the

mismatch condition.

b) Clear ﬂag bit CMIF. A mismatch condition will continue to set ﬂag bit CMIF.

Reading CMCON will end the mismatch condition, and allow ﬂag bit CMIF to be cleared.

8.7 Comparator Operation During SLEEP

When a comparator is active and the device is placed in SLEEP mode, the comparator remains active and the interrupt is functional if enabled. This interrupt will

Note: If a change in the CMCON register

(C1OUT or C2OUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF (PIR1<6>) interrupt ﬂag may not get set.

wake up the device from SLEEP mode when enabled. While the comparator is powered-up, higher sleep currents than shown in the power down current speciﬁcation will occur. Each comparator that is operational will consume additional current as shown in the comparator speciﬁcations. To minimize power consumption while in SLEEP mode, turn off the comparators, CM<2:0> = 111, before entering sleep. If the device wakes-up from sleep, the contents of the CMCON register are not affected.

8.8 Effects of a RESET

A device reset forces the CMCON register to its reset state. This forces the comparator module to be in the comparator reset mode, CM2:CM0 = 000. This ensures that all potential inputs are analog inputs. Device current is minimized when analog inputs are present at reset time. The comparators will be powered-down during the reset interval.

8.9 Analog Input Connection

Considerations

A simpliﬁed circuit for an analog input is shown in Figure 8-5. Since the analog pins are connected to a digital output, they have reverse biased diodes to V

and VSS. The analog input therefore, must be between V

SS and VDD. If the input voltage deviates from this

range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 kΩ is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current.

FIGURE 8-5: ANALOG INPUT MODEL

AIN

CPIN 5 pF

VT = 0.6V

T = 0.6V

IC < 10K

LEAKAGE

±500 nA

Legend CPIN = Input Capacitance

T = Threshold Voltage

LEAKAGE = Leakage Current At The Pin Due To Various Junctions

IC = Interconnect Resistance

S = Source Impedance

VA = Analog Voltage

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TABLE 8-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Note: x = Unknown

- = Unimplemented, read as "0"

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR / BOR

Value on

All Other

Resets

1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 0000 00-- 0000 9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000 0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 0Ch PIR1 — CMIF — — — — — — -0-- ---- -0-- ---- 8Ch PIE1 — CMIE — — — — — — -0-- ---- -0-- ---- 85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111

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PIC16CE62X

9.0 VOLTAGE REFERENCE MODULE

The Voltage Reference is a 16-tap resistor ladder network that provides a selectable voltage reference. The resistor ladder is segmented to provide two ranges of V

REF values and has a power-down function to

conserve power when the reference is not being used. The VRCON register controls the operation of the reference as shown in Figure 9-1. The block diagr am is given in Figure 9-2.

9.1 Conﬁguring the Voltage Reference

The Voltage Reference can output 16 distinct voltage levels for each range.

The equations used to calculate the output of the Voltage Reference are as follows:

if V

RR = 1: VREF = (VR<3:0>/24) x VDD

if VRR = 0: VREF = (VDD x 1/4) + (VR<3:0>/32) x VDD

The setting time of the Voltage Reference must be considered when changing the V

REF output

(Table 13-2). Example 9-1 shows an example of how to conﬁgure the Voltage Reference for an output voltage of 1.25V with V

DD = 5.0V.

FIGURE 9-1: VRCON REGISTER(ADDRESS 9Fh)

FIGURE 9-2: VOLTAGE REFERENCE BLOCK DIAGRAM

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

REN VROE VRR — VR3 VR2 VR1 VR0 R = Readable bit

W =Writable bit U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7: V

REN: VREF Enable

1 = V

REF circuit powered on

0 = V

REF circuit powered down, no IDD drain

bit 6: V

ROE: VREF Output Enable

1 = V

REF is output on RA2 pin

0 = V

REF is disconnected from RA2 pin

bit 5: V

RR: VREF Range selection

1 = Low Range

0 = High Range bit 4: Unimplemented: Read as '0' bit 3-0: V

R<3:0>: VREF value selection 0 ≤ VR [3:0] ≤ 15

when V

RR = 1: VREF = (VR<3:0>/ 24) * VDD

when VRR = 0: VREF = 1/4 * VDD + (VR<3:0>/ 32) * VDD

Note: R is deﬁned in Table 13-3.

VRR

VR0

(From VRCON<3:0>)

16-1 Analog Mux

VREN

VREF

16 Stages

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EXAMPLE 9-1: VOLTAGE REFERENCE

CONFIGURATION

9.2 V

oltage Reference Accuracy/Error

The full range of VSS to VDD cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 9-2) keep V

REF from approaching VSS or VDD.

The Voltage Reference is V

DD derived and therefore,

the V

REF output changes with ﬂuctuations in VDD. The

absolute accuracy of the Voltage Reference can be found in Table 13-3.

9.3 Operation During Sleep

When the device wakes up from sleep through an interrupt or a Watchdog Timer time-out, the contents of the VRCON register are not affected. To minimize current consumption in SLEEP mode, the Voltage Reference should be disabled.

MOVLW 0x02 ; 4 Inputs Muxed MOVWF CMCON ; to 2 comps. BSF STATUS,RP0 ; go to Bank 1 MOVLW 0x07 ; RA3-RA0 are MOVWF TRISA ; outputs MOVLW 0xA6 ; enable VREF MOVWF VRCON ; low range

; set VR<3:0>=6

BCF STATUS,RP0 ; go to Bank 0 CALL DELAY10 ; 10µs delay

9.4 Effects of a Reset

A device reset disables the Voltage Reference by clearing bit V

REN (VRCON<7>). This reset also disconnects

the reference from the RA2 pin by clearing bit V

ROE

(VRCON<6>) and selects the high voltage range by clearing bit V

RR (VRCON<5>). The VREF value select

bits, VRCON<3:0>, are also cleared.

9.5 Connection Considerations

The Voltage Reference Module operates independently of the comparator module. The output of the reference generator may be connected to the RA2 pin if the TRISA<2> bit is set and the V

ROE bit, VRCON<6>, is

set. Enabling the Voltage Reference output onto the RA2 pin with an input signal present will increase current consumption. Connecting RA2 as a digital output with V

REF enabled will also increase current consump-

tion. The RA2 pin can be used as a simple D/A output with

limited drive capability. Due to the limited drive capability, a buffer must be used in conjunction with the V oltage Reference output for external connections to V

REF. Figure 9-3 shows an example buffering

technique.

FIGURE 9-3: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

TABLE 9-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE

Note: - = Unimplemented, read as "0"

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value On

POR / BOR

Value On All Other

Resets

9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000 1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 0000 00-- 0000 85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111

VREF Output

+ –

•

VREF

Module

Voltage

Reference

Output

Impedance

(1)

RA2

Note 1: R is dependent upon the Voltage Reference Conﬁguration VRCON<3:0> and VRCON<5>.

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PIC16CE62X

10.0 SPECIAL FEATURES OF THE CPU

What sets a microcontroller apart from other processors are special circuits to deal with the needs of real time applications. The PIC16CE62X family has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection.

These are:

1. OSC selection

2. Reset

Power-on Reset (POR) Power-up Timer (PWRT) Oscillator Start-Up Timer (OST) Brown-out Reset (BOR)

3. Interrupts

4. Watchdog Timer (WDT)

5. SLEEP

6. Code protection

7. ID Locations

8. In-circuit serial programming

The PIC16CE62X has a Watchdog Timer which is controlled by conﬁguration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in reset until the crystal oscillator is stable. The other is the Power-up Ttimer (PWRT), which provides a ﬁxed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. There is also circuitry to reset the device if a brown-out occurs which provides at least a 72 ms reset. With these three functions on-chip, most applications need no external reset circuitry.

The SLEEP mode is designed to offer a very low current power-down mode. The user can wak e-up from SLEEP through external reset, Watchdog Timer wake-up or through an interrupt. Several oscillator options are also made available to allow the part to ﬁt the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of conﬁguration bits are used to select various options.

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10.1 Conﬁguration Bits

The conﬁguration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device conﬁgurations. These bits are mapped in program memory location 2007h.

The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/conﬁguration memory space (2000h – 3FFFh), which can be accessed only during programming.

FIGURE 10-1: CONFIGURATION WORD

CP1 CP0

(2)

CP1 CP0

(2)

CP1 CP0

(2)

— BODE

(1)

CP1 CP0

(2)

PWRTE

(1)

WDTE F0SC1 F0SC0

CONFIG Address REGISTER: 2007h

bit13 bit0

bit 13-8 CP1:CP0 Pairs: Code protection bits

(2)

5-4: Code protection for 2K program memory

11 = Program memory code protection off 10 = 0400h-07FFh code protected 01 = 0200h-07FFh code protected 00 = 0000h-07FFh code protected

Code protection for 1K program memory

11 = Program memory code protection off 10 =Program memory code protection on 01 = 0200h-03FFh code protected 00 = 0000h-03FFh code protected

Code protection for 0.5K program memory

11 = Program memory code protection off 10 = Program memory code protection of 01 = Program memory code protection of 00 = 0000h-01FFh code protected

bit 7: Unimplemented: Read as '1' bit 6: BODEN: Brown-out Reset Enable bit

(1)

1 = BOR enabled 0 = BOR disabled

bit 3: PWRTE: Power-up Timer Enable bit

(1)

1 = PWRT disabled 0 = PWRT enabled

bit 2: WDTE: Watchdog Timer Enable bit

1 = WDT enabled 0 = WDT disabled

bit 1-0: FOSC1:FOSC0: Oscillator Selection bits

11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator

Note 1: Enabling Bro wn-out Reset automatically enables P o wer-up Timer (PWR T) regardless of the v alue of bit PWRTE. Ensure

the Power-up Timer is enabled anytime Brown-out Reset is enabled.

2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.

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PIC16CE62X

10.2 Oscillator Conﬁgurations

10.2.1 OSCILLATOR TYPES

The PIC16CE62X can be operated in four different oscillator options. The user can program two conﬁguration bits (FOSC1 and FOSC0) to select one of these four modes:

• LP Low Power Crystal

• XT Crystal/Resonator

• HS High Speed Crystal/Resonator

• RC Resistor/Capacitor

10.2.2 CRYSTAL OSCILLATOR / CERAMIC RESONATORS

In XT, LP or HS modes a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation (Figure 10-2). The PIC16CE62X) oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers speciﬁcations. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1 pin (Figure 10-3).

FIGURE 10-2: CRYSTAL OPERATION

(OR CERAMIC RESONATOR) (HS, XT OR LP OSC CONFIGURATION)

FIGURE 10-3: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR LP OSC CONFIGURATION)

See Table 10-1 and Table 10-2 for recommended values of C1 and C2.

Note: A series resistor may be required for

AT strip cut crystals.

XTAL

OSC2

OSC1

SLEEP

To internal logic

PIC16CE62X

see Note

Clock from ext. system

PIC16CE62X

OSC1

OSC2

Open

TABLE 10-1: CERAMIC RESONATORS,

PIC16CE62X

TABLE 10-2: CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR, PIC16CE62X

1. Recommended values of C1 and C2 are identical to the ranges tested table.

2. Higher capacitance increases the stability of oscillator but also increases the start-up time.

3. Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.

4. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level speciﬁcation.

Ranges Tested:

Mode Freq OSC1 OSC2

XT 455 kHz

2.0 MHz

4.0 MHz

68 - 100 pF 15 - 68 pF 15 - 68 pF

HS 8.0 MHz

16.0 MHz

10 - 68 pF 10 - 22 pF

These values are for design guidance only. See notes at bottom of page.

Resonators Used:

455 kHz Panasonic EFO-A455K04B ± 0.3%

2.0 MHz Murata Erie CSA2.00MG ± 0.5%

4.0 MHz Murata Erie CSA4.00MG ± 0.5%

8.0 MHz Murata Erie CSA8.00MT ± 0.5%

16.0 MHz Murata Erie CSA16.00MX ± 0.5%

All resonators used did not have built-in capacitors.

Osc Type

Crystal

Freq

Cap. Range C1Cap. Range

LP 32 kHz 33 pF 33 pF

200 kHz 15 pF 15 pF

XT 200 kHz 47-68 pF 47-68 pF

1 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF

HS 4 MHz 15 pF 15 pF

8 MHz 15-33 pF 15-33 pF

20 MHz 15-33 pF 15-33 pF

These values are for design guidance only. See notes at bottom of page.

Crystals Used

32 kHz Epson C-001R32.768K-A ± 20 PPM

200 kHz STD XTL 200.000KHz ± 20 PPM

1 MHz ECS ECS-10-13-1 ± 50 PPM 4 MHz ECS ECS-40-20-1 ± 50 PPM 8 MHz EPSON CA-301 8.000M-C ± 30 PPM

20 MHz EPSON CA-301 20.000M-C ± 30 PPM

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10.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT

Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used; one with series resonance, or one with parallel resonance.

Figure 10-4 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180° phase shift that a parallel oscillator requires. The 4.7 kΩ resistor provides the negative feedback for stability. The 10 kΩ potentiometers bias the 74AS04 in the linear region. This could be used for external oscillator designs.

FIGURE 10-4: EXTERNAL PARALLEL

RESONANT CRYSTAL OSCILLATOR CIRCUIT

Figure 10-5 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180° phase shift in a series resonant oscillator circuit. The 330 kΩ resistors provide the negative feedback to bias the inverters in their linear region.

FIGURE 10-5: EXTERNAL SERIES

RESONANT CRYSTAL OSCILLATOR CIRCUIT

20 pF

+5V

20 pF

10k

4.7k

10k

74AS04

XTAL

10k

74AS04

PIC16CE62X

CLK

To other Devices

330

74AS04

PIC16CE62X

CLKIN

To other Devices

XTAL

330

74AS04

0.1 µF

10.2.4 RC OSCILLATOR For timing insensitive applications the “RC” device

option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Cext values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 10-6 shows how the R/C combination is connected to the PIC16CE62X. F or Rext values below 2.2 kΩ, the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g., 1 MΩ), the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend to keep Rext between 3 kΩ and 100 kΩ.

Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance.

See Section 14.0 for RC frequency variation from part to part due to normal process variation. The v ariation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and f or smaller C (since variation of input capacitance will affect RC frequency more).

See Section 14.0 for variation of oscillator frequency due to V

DD for given Rext/Cext values as well as

frequency variation due to operating temperature for given R, C, and V

DD values.

The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (Figure 3-2 for waveform).

FIGURE 10-6: RC OSCILLATOR MODE

OSC2/CLKOUT

Cext

Rext

PIC16CE62X

OSC1

Fosc/4

Internal Clock

VDD

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PIC16CE62X

10.3 Reset

The PIC16CE62X differentiates between various kinds of reset:

a) Power-on reset (POR) b) MCLR

reset during normal operation

c) MCLR

reset during SLEEP d) WDT reset (normal operation) e) WDT wake-up (SLEEP) f) Brown-out Reset (BOR)

Some registers are not affected in any reset condition; their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a “reset

state” on Power-on reset, on MCLR

or WDT reset and

on MCLR

reset during SLEEP. They are not aff ected b y a WDT wak e-up , since this is vie wed as the resumption of normal operation. T

O and PD bits are set or cleared differently in different reset situations as indicated in Table 10-4. These bits are used in software to determine the nature of the reset. See Table 10-6 for a full description of reset states of all registers.

A simpliﬁed block diagram of the on-chip reset circuit is shown in Figure 10-7.

The MCLR

reset path has a noise ﬁlter to detect and ignore small pulses. See Table 13-6 for pulse width speciﬁcation.

FIGURE 10-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR/

OSC1/

WDT

Module

DD rise

detect

OST/PWRT

On-chip

(1)

RC OSC

WDT

Time-out

Power-on Reset

OST

PWRT

Chip_Reset

10-bit Ripple-counter

Reset

Enable OST

Enable PWRT

SLEEP

See Table 10-3 for time-out situations.

Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.

Brown-out

Reset

BODEN

CLKIN

PP Pin

10-bit Ripple-counter

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10.4 Power-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST) and Brown-out Reset (BOR)

10.4.1 POWER-ON RESET (POR)

The on-chip POR circuit holds the chip in reset until V

DD has reached a high enough level f or proper opera-

tion. To take advantage of the POR, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for V

is required. See Electrical Speciﬁcations for details. The POR circuit does not produce internal reset when

DD declines.

When the device starts normal operation (exits the reset condition), device operating parameters (v oltage , frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met.

For additional information, refer to Application Note AN607 “Power-up Trouble Shooting”.

10.4.2 POWER-UP TIMER (PWRT)

The Power-up Timer provides a ﬁxed 72 ms (nominal) time-out on power-up only, from POR or Brown-out Reset. The Power-up Timer operates on an internal RC oscillator. The chip is kept in reset as long as PWRT is active. The PWRT delay allows the V

DD to rise to an

acceptable level. A conﬁguration bit, PW

RTE can

disable (if set) or enable (if cleared or programmed) the Power-up Timer . The P o wer-up Timer should alw ays be enabled when Brown-out Reset is enabled.

The Power-Up Time delay will vary from chip to chip and due to V

DD, temperature and process variation.

See DC parameters for details.

10.4.3 OSCILLATOR START-UP TIMER (OST) The Oscillator Start-Up Timer (OST) provides a 1024

oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP and HS modes and only on power-on reset or wake-up from SLEEP.

10.4.4 BROWN-OUT RESET (BOR) The PIC16CE62X members have on-chip Brown-out

Reset circuitry. A conﬁguration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If V

DD falls below 4.0V (refer

BVDD parameter D005) for greater than parameter

(TBOR) in Table 13-6, the brown-out situation will reset the chip. A reset is not guaranteed to occur if V

DD falls

below 4.0V for less than parameter (TBOR). The chip will remain in Brown-out Reset until V

DD rises above

DD. The Power-up Timer will no w be inv oked and will

keep the chip in reset an additional 72 ms. If V

DD drops

below BV

DD while the Power-up Timer is r unning, the

chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once V

DD rises

above BV

DD, the Pow er-Up Timer will execute a 72 ms

reset. The Power-up Timer should always be enabled when Brown-out Reset is enabled. Figure 10-8 shows typical Brown-out situations.

FIGURE 10-8: BROWN-OUT SITUATIONS

72 ms

VDD

Internal

Reset

BVDD

VDD

Internal

Reset

72 ms

<72 ms

72 ms

BVDD

Internal

Reset

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10.4.5 TIME-OUT SEQUENCE On power-up the time-out sequence is as follows: First

PWRT time-out is inv oked after POR has e xpired. Then OST is activated. The total time-out will vary based on oscillator conﬁguration and P

WRTE bit status. For

example, in RC mode with PW

RTE bit erased (PWRT disabled), there will be no time-out at all. Figure 10-9, Figure 10-10 and Figure 10-11 depict time-out sequences.

Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire . Then bringing MCLR

high will begin execution immediately (see Figure 10-10). This is useful for testing purposes or to synchronize more than one PICmicro device operating in parallel.

Table 10-5 shows the reset conditions f or some special registers, while Table 10-6 shows the reset conditions for all the registers.

10.4.6 POWER CONTROL (PCON)/STATUS REGISTER

The power control/status register, PCON (address 8Eh) has two bits.

Bit0 is BO

(Brown-out). BO is unknown on power-on-reset. It must then be set by the user and checked on subsequent resets to see if BO

= 0 indicating that a brown-out has occurred. The BO status bit is a don’t care and is not necessarily predictable if the brown-out circuit is disabled (by setting BODEN bit = 0 in the Conﬁguration word).

Bit1 is POR

(Power-on-reset). It is a ‘0’ on power-on-reset and unaffected otherwise. The user must write a ‘1’ to this bit following a power-on-reset. On a subsequent reset if POR

is ‘0’, it will indicate that

a power-on-reset must have occurred (V

DD may have

gone too low).

TABLE 10-3: TIME-OUT IN VARIOUS SITUATIONS

TABLE 10-4: STATUS/PCON BITS AND THEIR SIGNIFICANCE

Oscillator Conﬁguration

Power-up

Brown-out Reset

Wake-up

from SLEEP

PWR

TE = 0 PWRTE = 1

XT, HS, LP 72 ms + 1024 TOSC 1024 TOSC 72 ms + 1024 TOSC 1024 TOSC

RC 72 ms — 72 ms —

POR

BOR TO PD

0 X 1 1

Power-on-reset

0 X 0 X

Illegal, TO is set on POR

0 X X 0

Illegal, PD is set on POR

1 0 X X

Brown-out Reset

1 1 0 1

WDT Reset

1 1 0 0

WDT Wake-up

1 1 u u

MCLR reset during normal operation

1 1 1 0

MCLR reset during SLEEP

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TABLE 10-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS

TABLE 10-6: INITIALIZATION CONDITION FOR REGISTERS

Condition

Program

Counter

STATUS

PCON

Power-on Reset 000h

0001 1xxx ---- --0x

MCLR reset during normal operation 000h

000u uuuu ---- --uu

MCLR reset during SLEEP 000h

0001 0uuu ---- --uu

WDT reset 000h

0000 1uuu ---- --uu

WDT Wake-up PC + 1

uuu0 0uuu ---- --uu

Brown-out Reset 000h

0001 1uuu ---- --u0

Interrupt Wake-up from SLEEP PC + 1

(1)

uuu1 0uuu ---- --uu

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector

(0004h) after execution of PC+1.

• MCLR Reset during normal operation

• MCLR Reset during SLEEP

• WDT Reset

• Brown-out Reset

(1)

• Wake up from SLEEP through interrupt

• Wake up from SLEEP through WDT time-out

W -

xxxx xxxx uuuu uuuu uuuu uuuu

INDF 00h

- - -

TMR0 01h

xxxx xxxx uuuu uuuu uuuu uuuu

PCL 02h

0000 0000 0000 0000 PC + 1

(3)

STATUS 03h

0001 1xxx 000q quuu

(4)

uuuq quuu

(4)

FSR 04h

xxxx xxxx uuuu uuuu uuuu uuuu

PORTA 05h

---x xxxx ---u uuuu ---u uuuu

PORTB 06h

xxxx xxxx uuuu uuuu uuuu uuuu

CMCON 1Fh

00-- 0000 00-- 0000 uu-- uuuu

PCLATH 0Ah

---0 0000 ---0 0000 ---u uuuu

INTCON 0Bh

0000 000x 0000 000x uuuu uuuu

(2)

PIR1 0Ch

-0-- ---- -0-- ---- -u-- ----

(2)

OPTION 81h

1111 1111 1111 1111 uuuu uuuu

TRISA 85h

---1 1111 ---1 1111 ---u uuuu

TRISB 86h

1111 1111 1111 1111 uuuu uuuu

PIE1 8Ch

-0-- ---- -0-- ---- -u-- ----

PCON 8Eh

---- --0x ---- --uq

(1)

---- --uu

EEINTF 90h

uuuu u111 uuuu u111 uuuu u111

VRCON 9Fh

000- 0000 000- 0000 uuu- uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’,q = value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

4: See Table 10-5 for reset value for speciﬁc condition.

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FIGURE 10-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

FIGURE 10-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

FIGURE 10-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR

TIED TO VDD)

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWR

T TIME-OUT

OST TIME-OUT

INTERNAL RESET

VDD

MCLR

INTERNAL POR

PWR

T TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWR

T TIME-OUT

OST TIME-OUT

INTERNAL RESET

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FIGURE 10-12: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW VDD POWER-UP)

Note 1: External power-on reset circuit is required

only if V

DD power-up slope is too slow.

The diode D helps discharge the capacitor quickly when V

DD powers down.

2: < 40 kΩ is recommended to make sure

that voltage drop across R does not violate the device’s electrical speciﬁcation.

3: R1 = 100Ω to 1 kΩ will limit any current

ﬂowing into MCLR

from external capaci-

tor C in the event of MCLR

/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).

MCLR

PIC16CE62X

VDD

FIGURE 10-13: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 1

FIGURE 10-14: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 2

Note 1: This circuit will activate reset when VDD

goes below (Vz + 0.7V) where Vz = Zener voltage.

2: Internal Brown-out Reset circuitry

should be disabled when using this circuit.

VDD

33k

10k

40k

MCLR

PIC16CE62X

Note 1: This brown-out circuit is less expensive ,

albeit less accurate. Transistor Q1 turns off when V

DD is below a certain level

such that:

2: Internal brown-out detection should be

disabled when using this circuit.

3: Resistors should be adjusted for the

characteristics of the transistor.

VDD x

R1 + R2

= 0.7 V

VDD

40k

VDD

MCLR

PIC16CE62X

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10.5 Interrupts

The PIC16CE62X has 4 sources of interrupt:

• External interrupt RB0/INT

• TMR0 overﬂow interrupt

• PortB change interrupts (pins RB7:RB4)

• Comparator interrupt The interrupt control register (INTCON) records

individual interrupt requests in ﬂag bits. It also has individual and global interrupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in INTCON register. GIE is cleared on reset.

The “return from interrupt” instruction,

RETFIE, exits

interrupt routine as well as sets the GIE bit, which re-enable RB0/INT interrupts.

The INT pin interrupt, the RB port change interrupt and the TMR0 overﬂow interrupt ﬂags are contained in the INTCON register.

The peripheral interrupt ﬂag is contained in the special register PIR1. The corresponding interrupt enable bit is contained in special registers PIE1.

When an interrupt is responded to, the GIE is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of

the interrupt can be determined by polling the interrupt ﬂag bits. The interrupt ﬂag bit(s) must be cleared in software before re-enabling interrupts to avoid RB0/INT recursive interrupts.

For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs (Figure 10-16). The latency is the same for one or two cycle instructions. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt ﬂag bits. The interrupt ﬂag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. Individual interrupt ﬂag bits are set regardless of the status of their corresponding mask bit or the GIE bit.

Note 1: Individual interrupt ﬂag bits are set

regardless of the status of their corresponding mask bit or the GIE bit.

2: When an instruction that clears the GIE

bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The CPU will execute a NOP in the cycle immediately following the instruction which clears the GIE bit. The interrupts which were ignored are still pending to be serviced when the GIE bit is set again.

FIGURE 10-15: INTERRUPT LOGIC

RBIF RBIE

T0IF T0IE

INTF

INTE

GIE

PEIE

Wake-up

(If in SLEEP mode)

Interrupt to CPU

CMIE

CMIF

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10.5.1 RB0/INT INTERRUPT External interrupt on RB0/INT pin is edge triggered:

either rising if INTEDG bit (OPTION<6>) is set, or falling, if INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing the INTE control bit (INTCON<4>). The INTF bit must be cleared in software in the interrupt service routine before re-enabling this interrupt. The RB0/INT interrupt can wake-up the processor from SLEEP, if the INTE bit was set prior to going into SLEEP. The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wak e-up . See Section 10.8 for details on SLEEP and Figure 10-19 for timing of wake-up from SLEEP through RB0/INT interrupt.

10.5.2 TMR0 INTERRUPT An overﬂow (FFh → 00h) in the TMR0 register will

set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. For operation of the Timer0 module, see Section 7.0.

10.5.3 PORTB INTERRUPT An input change on PORTB <7:4> sets the RBIF

(INTCON<0>) bit. The interrupt can be enabled/disabled by setting/clearing the RBIE (INTCON<4>) bit. For operation of PORTB (Section 5.2).

10.5.4 COMPARATOR INTERRUPT See Section 8.6 for complete description of comparator

interrupts.

Note: If a change on the I/O pin should occur

when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt ﬂag may not get set.

FIGURE 10-16: INT PIN INTERRUPT TIMING

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF ﬂag (INTCON<1>)

GIE bit (INTCON<7>)

INSTR

UCTION FLOW

Instruction fetched

Instruction executed

Interrupt Latency

PC+1

0004h

0005h

Inst (0004h)

Inst (0005h)

Dummy Cycle

Inst (PC)

Inst (PC+1)

Inst (PC-1)

Inst (0004h)

Dummy Cycle

Inst (PC)

—

Note

1: INTF ﬂag is sampled here (every Q1). 2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles.

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10.6 Context Saving During Interrupts

During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to sa ve key registers during an interrupt e.g. W register and STATUS register. This will have to be implemented in software.

Example 10-1 stores and restores the STATUS and W registers. The user register, W_TEMP, must be deﬁned in both banks and must be deﬁned at the same offset from the bank base address (i.e., W_TEMP is deﬁned at 0x70 in Bank 0 and it must also be deﬁned at 0xF0 in Bank 1). The user register, STATUS_TEMP, must be deﬁned in Bank 0. The Example 10-1:

• Stores the W register

• Stores the STATUS register in Bank 0

• Executes the ISR code

• Restores the STATUS (and bank select bit register)

• Restores the W register

EXAMPLE 10-1: SAVING THE STATUS AND

W REGISTERS IN RAM

MOVWF W_TEMP ;copy W to temp register,

;could be in either bank SWAPF STATUS,W ;swap status to be saved into W BCF STATUS,RP0 ;change to bank 0 regardless

;of current bank MOVWF STATUS_TEMP ;save status to bank 0

;register

: : (ISR) :

SWAPF STATUS_TEMP,W ;swap STATUS_TEMP register

;into W, sets bank to original

;state MOVWF STATUS ;move W into STATUS register SWAPF W_TEMP,F ;swap W_TEMP SWAPF W_TEMP,W ;swap W_TEMP into W

10.7 Watchdog Timer (WDT)

The watchdog timer is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the CLKIN pin. That means that the WDT will run, even if the clock on the OSC1 and OSC2 pins of the device has been stopped, for example, by execution of a

SLEEP instruction. During normal operation, a WDT

time-out generates a device RESET. If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation. The WDT can be permanently disabled by programming the conﬁguration bit WDTE as clear (Section 10.1).

10.7.1 WDT PERIOD The WDT has a nominal time-out period of 18 ms, (with

no prescaler). The time-out periods vary with temperature, V

and process variations from part to part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to

2.3 seconds can be realized. The

CLRWDT and SLEEP instructions clear the WDT

and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET.

The T

O bit in the STATUS register will be cleared upon

a Watchdog Timer time-out.

10.7.2 WDT PROGRAMMING CONSIDERATIONS It should also be taken in account that under worst case

conditions (V

DD = Min., Temperature = Max., max.

WDT prescaler) it may take several seconds before a WDT time-out occurs.

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FIGURE 10-17: WATCHDOG TIMER BLOCK DIAGRAM

FIGURE 10-18: SUMMARY OF WATCHDOG TIMER REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

2007h Conﬁg. bits --- BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 81h OPTION

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

Legend: Shaded cells are not used by the Watchdog Timer.

Note:_ = Unimplemented location, read as “0”

+ = Reserved for future use

From TMR0 Clock Source (Figure 7-6)

To TMR0 (Figure 7-6)

Postscaler

Watchdog

Timer

U X

PSA

8 - to -1 MUX

PSA

WDT

Time-out

WDT

Enable Bit

PS<2:0>

•

Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.

MUX

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10.8 Power-Down Mode (SLEEP)

The Power-down mode is entered by executing a

SLEEP instruction.

If enabled, the Watchdog Timer will be cleared but keeps running, the PD

bit in the STATUS register is

cleared, the T

O bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before

SLEEP was executed (driving high, low, or

hi-impedance). For lowest current consumption in this mode, all I/O

pins should be either at V

DD, or VSS, with no external

circuitry drawing current from the I/O pin and the comparators and V

REF should be disabled. I/O pins that are

hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by ﬂoating inputs. The T0CKI input should also be at V

DD or VSS

for lowest current consumption. The contribution from on chip pull-ups on PORTB should be considered.

The MCLR

pin must be at a logic high level (VIHMC).

10.8.1 WAKE-UP FROM SLEEP The device can wake-up from SLEEP through one of

the following events:

1. External reset input on MCLR

2. Watchdog Timer Wake-up (if WDT was enab led)

3. Interrupt from RB0/INT pin, RB Port change, or

the Peripheral Interrupt (Comparator).

The ﬁrst event will cause a device reset. The two latter events are considered a continuation of program execution. The T

O and PD bits in the STATUS register can be used to determine the cause of device reset. PD bit, which is set on power-up is cleared when SLEEP is invoked. T

O bit is cleared if WDT Wake-up occurred.

When the

SLEEP instruction is being executed, the

next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wak e-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the

SLEEP instruction. If the GIE bit is

set (enabled), the device executes the instruction after the

SLEEP instruction and then branches to the inter-

rupt address (0004h). In cases where the execution of the instruction following

SLEEP is not desirable, the

user should have an

NOP after the SLEEP instruction.

The WDT is cleared when the device wakes-up from sleep, regardless of the source of wake-up.

Note: It should be noted that a RESET generated

by a WDT time-out does not drive MCLR pin low.

Note: If the global interrupts are disabled (GIE is

cleared), but any interrupt source has both its interrupt enable bit and the corresponding interrupt ﬂag bits set, the device will immediately wakeup from sleep. The sleep instruction is completely executed.

FIGURE 10-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

INTF ﬂag (INTCON<1>)

GIE bit (INTCON<7>)

INSTR

UCTION FLOW

Instruction fetched

Instruction executed

PC PC+1 PC+2

Inst(PC) = SLEEP

Inst(PC - 1)

Inst(PC + 1)

SLEEP

Processor in

SLEEP

Interrupt Latency

(Note 2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2 0004h 0005h

Dummy cycle

OST(2)

PC+2

Note 1: XT, HS or LP oscillator mode assumed.

2: T

OST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.

3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. 4: CLKOUT is not available in these osc modes, but shown here for timing reference.

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10.9 Code Protection

If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for veriﬁcation purposes.

10.10 ID Locations

Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code-identiﬁcation numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. Only the least signiﬁcant 4 bits of the ID locations are used.

Note: Microchip does not recommend code

protecting windowed devices.

10.11 In-Circuit Serial Programming

The PIC16CE62X microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent ﬁrmware or a custom ﬁrmware to be programmed.

The device is placed into a program/verify mode by holding the RB6 and RB7 pins low while raising the MCLR

(VPP) pin from VIL to VIHH (see programming speciﬁcation). RB6 becomes the programming clock and RB7 becomes the programming data. Both RB6 and RB7 are Schmitt Trigger inputs in this mode.

After reset, to place the device into programming/verify mode, the program counter (PC) is at location 00h. A 6-bit command is then supplied to the device. Depending on the command, 14-bits of program data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC16C6X/7X/9XX Programming Speciﬁcations (Literature #DS30228).

A typical in-circuit serial programming connection is shown in Figure 10-20.

FIGURE 10-20: TYPICAL IN-CIRCUIT SERIAL

PROGRAMMING CONNECTION

External Connector Signals

To Normal Connections

PIC16CE62X

VSS MCLR/VPP

RB6

RB7

+5V

VPP

CLK

Data I/O

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PIC16CE62X

11.0 INSTRUCTION SET SUMMARY

Each PIC16CE62X instruction is a 14-bit word divided into an OPCODE which speciﬁes the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CE62X instruction set summary in Table 11-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 11-1 shows the opcode ﬁeld descriptions.

For byte-oriented instructions, 'f' represents a ﬁle register designator and 'd' represents a destination designator. The ﬁle register designator speciﬁes which ﬁle register is to be used by the instruction.

The destination designator speciﬁes where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register . If 'd' is one , the result is placed in the ﬁle register speciﬁed in the instruction.

For bit-oriented instructions, 'b' represents a bit ﬁeld designator which selects the number of the bit affected by the operation, while 'f' represents the number of the ﬁle in which the bit is located.

For literal and control operations, 'k' represents an eight or eleven bit constant or literal value.

TABLE 11-1: OPCODE FIELD

DESCRIPTIONS

Field Description

f Register ﬁle address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit ﬁle register k Literal ﬁeld, constant data or label x Don't care location (= 0 or 1)

The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools.

d Destination select; d = 0: store result in W,

d = 1: store result in ﬁle register f. Default is d = 1

label Label name

TOS Top of Stack

PC Program Counter

PCLATH

Program Counter High Latch

GIE Global Interrupt Enable bit WDT Watchdog Timer/Counter

TO Time-out bit PD Power-down bit

dest Destination either the W register or the speciﬁed

[ ] Options

( )

Contents

→

Assigned to

< >

∈

In the set of

talics

User deﬁned term (font is courier)

The instruction set is highly orthogonal and is grouped into three basic categories:

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations All instructions are executed within one single

instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 µs. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 µs.

Table 11-1 lists the instructions recognized by the MPASM assembler.

Figure 11-1 shows the three general formats that the instructions can have.

All examples use the following format to represent a hexadecimal number:

0xhh

where h signiﬁes a hexadecimal digit.

FIGURE 11-1: GENERAL FORMAT FOR

INSTRUCTIONS

Note: To maintain upward compatibility with

future PICmicro™ products, do not use

the

OPTION and TRIS instructions.

Byte-oriented ﬁle register operations

13 8 7 6 0

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f f = 7-bit ﬁle register address

Bit-oriented ﬁle register operations

13 10 9 7 6 0

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address f = 7-bit ﬁle register address

Literal and control operations

13 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

13 11 10 0

OPCODE k (literal) k = 11-bit immediate value

General

CALL and GOTO instructions only

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TABLE 11-2: PIC16CE62X INSTRUCTION SET

Mnemonic, Operands

Description Cycles 14-Bit Opcode Status

Affected

Notes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF

ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF

f, d f, d f

f, d f, d f, d f, d f, d f, d f, d f

f, d f, d f, d f, d f, d

Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f

1 1 1 1 1 1

1(2)

1 1 1 1 1 1 1 1 1

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110

dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff

ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff

C,DC,Z Z Z Z Z Z

Z Z

C C C,DC,Z

1,2 1,2 2

1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2

1,2 1,2 1,2 1,2 1,2

BIT-ORIENTED FILE REGISTER OPERATIONS BCF

BSF BTFSC BTFSS

f, b f, b f, b f, b

Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set

1 1 (2) 1 (2)

01 01 01 01

00bb 01bb 10bb 11bb

bfff bfff bfff bfff

ffff ffff ffff ffff

1,2 1,2 3 3

LITERAL AND CONTROL OPERATIONS ADDLW

ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW

k k k

k k

Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W

11 11 10 00 10 11 11 00 11 00 00 11 11

111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010

kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk

kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk

C,DC,Z Z

O,PD

TO,PD C,DC,Z Z

Note 1: When an I/O register is modiﬁed as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is '1' for a pin conﬁgured as input and is driven low by an external device, the data will be written back with a '0'.

2: If this instruction is ex ecuted on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned

to the Timer0 Module.

3: If Program Counter (PC) is modiﬁed or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

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11.1 Instruction Descriptions

ADDLW Add Literal and W

Syntax: [

label

] ADDLW k Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Status Affected: C, DC, Z Encoding:

11 111x kkkk kkkk

Description:

The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register

. Words: 1 Cycles: 1 Example

ADDLW 0x15

Before Instruction

W = 0x10

After Instruction

W = 0x25

ADDWF Add W and f

Syntax: [

label

] ADDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (W) + (f) → (dest) Status Affected: C, DC, Z Encoding:

00 0111 dfff ffff

Description:

Add the contents of the W register

with register 'f'. If 'd' is 0 the result is

stored in the W register. If 'd' is 1 the

result is stored back in register 'f'

. Words: 1 Cycles: 1 Example

ADDWF FSR, 0

Before Instruction

W = 0x17 FSR = 0xC2

After Instruction

W = 0xD9 FSR = 0xC2

ANDLW AND Literal with W

Syntax: [

label

] ANDLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .AND. (k) → (W) Status Affected: Z Encoding:

11 1001 kkkk kkkk

Description:

The contents of W register are AND’ed with the eight bit literal 'k'. The result is placed in the W register

. Words: 1 Cycles: 1 Example

ANDLW 0x5F

Before Instruction

W = 0xA3

After Instruction

W = 0x03

ANDWF AND W with f

Syntax: [

label

] ANDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (W) .AND. (f) → (dest) Status Affected: Z Encoding:

00 0101 dfff ffff

Description:

AND the W register with register 'f'. If

'd' is 0 the result is stored in the W

back in register 'f'

. Words: 1 Cycles: 1 Example

ANDWF FSR, 1

Before Instruction

W = 0x17 FSR = 0xC2

After Instruction

W = 0x17 FSR = 0x02

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BCF Bit Clear f

Syntax: [

label

] BCF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7 Operation: 0 → (f<b>) Status Affected: None Encoding:

01 00bb bfff ffff

Description: Bit 'b' in register 'f' is cleared. Words: 1 Cycles: 1 Example

BCF FLAG_REG, 7

Before Instruction

FLAG_REG = 0xC7

After Instruction

FLAG_REG = 0x47

BSF Bit Set f

Syntax: [

label

] BSF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7 Operation: 1 → (f<b>) Status Affected: None Encoding:

01 01bb bfff ffff

Description:

Bit 'b' in register 'f' is set.

Words: 1 Cycles: 1 Example

BSF FLAG_REG, 7

Before Instruction

FLAG_REG = 0x0A

After Instruction

FLAG_REG = 0x8A

BTFSC Bit Test, Skip if Clear

Syntax: [

label

] BTFSC f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7 Operation: skip if (f<b>) = 0 Status Affected: None Encoding:

01 10bb bfff ffff

Description:

If bit 'b' in register 'f' is '0' then the next

instruction is skipped.

If bit 'b' is '0' then the next instruction

fetched during the current instruction

execution is discarded, and a NOP is

executed instead, making this a

two-cycle instruction

. Words: 1 Cycles: 1(2) Example

HERE FALSE TRUE

BTFSC GOTO

•

FLAG,1 PROCESS_CODE

Before Instruction

PC = address HERE

After Instruction

if FLAG<1> = 0, PC = address TRUE if FLAG<1>=1, PC = address FALSE

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BTFSS Bit Test f, Skip if Set

Syntax: [

label

] BTFSS f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b < 7 Operation: skip if (f<b>) = 1 Status Affected: None Encoding:

01 11bb bfff ffff

Description:

If bit 'b' in register 'f' is '1' then the next

instruction is skipped.

If bit 'b' is '1', then the next instruction

fetched during the current instruction

execution, is discarded and a NOP is

executed instead, making this a

two-cycle instruction.

Words: 1 Cycles: 1(2) Example

HERE FALSE TRUE

BTFSS GOTO

•

FLAG,1 PROCESS_CODE

Before Instruction

PC = address HERE

After Instruction

if FLAG<1> = 0, PC = address FALSE if FLAG<1> = 1, PC = address TRUE

CALL Call Subroutine

Syntax: [

label

] CALL k Operands: 0 ≤ k ≤ 2047 Operation: (PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11> Status Affected: None Encoding:

10 0kkk kkkk kkkk

Description:

Call Subroutine. First, return address

(PC+1) is pushed onto the stack. The

eleven bit immediate address is loaded

into PC bits <10:0>. The upper bits of

the PC are loaded from PCLATH.

CALL is a two-cycle instruction.

Words: 1 Cycles: 2 Example

HERE CALL THERE

Before Instruction

PC = Address HERE

After Instruction

PC = Address THERE TOS= Address HERE+1

CLRF Clear f

Syntax: [

label

] CLRF f Operands: 0 ≤ f ≤ 127 Operation: 00h → (f)

1 → Z Status Affected: Z Encoding:

00 0001 1fff ffff

Description:

The contents of register 'f' are cleared

and the Z bit is set.

Words: 1 Cycles: 1 Example

CLRF FLAG_REG

Before Instruction

FLAG_REG = 0x5A

After Instruction

FLAG_REG = 0x00 Z = 1

CLRW Clear W

Syntax: [

label

] CLRW Operands: None Operation: 00h → (W)

1 → Z Status Affected: Z Encoding:

00 0001 0xxx xxxx

Description:

W register is cleared. Zero bit (Z) is

set.

Words: 1 Cycles: 1 Example

CLRW

Before Instruction

W = 0x5A

After Instruction

W = 0x00 Z = 1

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CLRWDT Clear Watchdog Timer

Syntax: [

label

] CLRWDT Operands: None Operation: 00h → WDT

0 → WDT prescaler, 1 → T

1 → PD Status Affected: TO, PD Encoding:

00 0000 0110 0100

Description:

CLRWDT instruction resets the

Watchdog Timer. It also resets the

prescaler of the WDT. Status bits TO

and PD are set.

Words: 1 Cycles: 1 Example

CLRWDT

Before Instruction

WDT counter = ?

After Instruction

WDT counter = 0x00 WDT prescaler= 0

TO = 1 PD = 1

COMF Complement f

Syntax: [

label

] COMF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f

) → (dest) Status Affected: Z Encoding:

00 1001 dfff ffff

Description:

The contents of register 'f' are complemented. If 'd' is 0 the result is stored in W. If 'd' is 1 the result is stored back in register 'f'.

Words: 1 Cycles: 1 Example

COMF REG1,0

Before Instruction

REG1 = 0x13

After Instruction

REG1 = 0x13 W = 0xEC

DECF Decrement f

Syntax: [

label

] DECF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) - 1 → (dest) Status Affected: Z Encoding:

00 0011 dfff ffff

Description:

Decrement register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd'

is 1 the result is stored back in register

'f'

. Words: 1 Cycles: 1 Example

DECF CNT, 1

Before Instruction

CNT = 0x01 Z = 0

After Instruction

CNT = 0x00 Z = 1

DECFSZ Decrement f, Skip if 0

Syntax: [

label

] DECFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) - 1 → (dest); skip if result = 0 Status Affected: None Encoding:

00 1011 dfff ffff

Description:

The contents of register 'f' are

decremented. If 'd' is 0 the result is

placed in the W register. If 'd' is 1 the

result is placed back in register 'f'.

If the result is 0, the next instruction,

which is already fetched, is discarded. A

NOP is executed instead making it a

two-cycle instruction.

Words: 1 Cycles: 1(2) Example

HERE DECFSZ CNT, 1 GOTO LOOP CONTINUE •

•

Before Instruction

PC = address HERE

After Instruction

CNT = CNT - 1 if CNT = 0, PC = address CONTINUE if CNT ≠ 0, PC = address HERE+1

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PIC16CE62X

GOTO Unconditional Branch

Syntax: [

label

] GOTO k Operands: 0 ≤ k ≤ 2047 Operation: k → PC<10:0>

PCLATH<4:3> → PC<12:11> Status Affected: None Encoding:

10 1kkk kkkk kkkk

Description:

GOTO is an unconditional branch. The

eleven bit immediate value is loaded

into PC bits <10:0>. The upper bits of

PC are loaded from PCLATH<4:3>.

GOTO is a two-cycle instruction.

Words: 1 Cycles: 2 Example

GOTO THERE

After Instruction

PC = Address THERE

INCF Increment f

Syntax: [

label

] INCF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) + 1 → (dest) Status Affected: Z Encoding:

00 1010 dfff ffff

Description:

The contents of register 'f' are

incremented. If 'd' is 0 the result is

placed in the W register. If 'd' is 1 the

result is placed back in register 'f'.

Words: 1 Cycles: 1 Example

INCF CNT, 1

Before Instruction

CNT = 0xFF Z = 0

After Instruction

CNT = 0x00 Z = 1

INCFSZ Increment f, Skip if 0

Syntax: [

label

] INCFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) + 1 → (dest), skip if result = 0 Status Affected: None Encoding:

00 1111 dfff ffff

Description:

The contents of register 'f' are

incremented. If 'd' is 0 the result is

placed in the W register. If 'd' is 1 the

result is placed back in register 'f'.

If the result is 0, the next instruction,

which is already fetched, is discarded.

A NOP is executed instead making it

a two-cycle instruction

. Words: 1 Cycles: 1(2) Example

HERE INCFSZ CNT, 1 GOTO LOOP CONTINUE •

•

Before Instruction

PC = address HERE

After Instruction

CNT = CNT + 1 if CNT= 0, PC = address CONTINUE if CNT≠ 0, PC = address HERE +1

IORLW Inclusive OR Literal with W

Syntax: [

label

] IORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. k → (W) Status Affected: Z Encoding:

11 1000 kkkk kkkk

Description:

The contents of the W register is OR’ed with the eight bit literal 'k'. The result is placed in the W register

. Words: 1 Cycles: 1 Example

IORLW 0x35

Before Instruction

W = 0x9A

After Instruction

W = 0xBF Z = 1

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IORWF Inclusive OR W with f

Syntax: [

label

] IORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (W) .OR. (f) → (dest) Status Affected: Z Encoding:

00 0100 dfff ffff

Description:

Inclusive OR the W register with

in the W register . If 'd' is 1 the result is

placed back in register 'f'.

Words: 1 Cycles: 1 Example

IORWF RESULT, 0

Before Instruction

RESULT = 0x13 W = 0x91

After Instruction

RESULT = 0x13 W = 0x93 Z = 1

MOVLW Move Literal to W

Syntax: [

label

] MOVLW k Operands: 0 ≤ k ≤ 255 Operation: k → (W) Status Affected: None Encoding:

11 00xx kkkk kkkk

Description:

The eight bit literal 'k' is loaded into W register

. The don’t cares will assemble

as 0’s.

Words: 1 Cycles: 1 Example

MOVLW 0x5A

After Instruction

W = 0x5A

MOVF Move f

Syntax: [

label

] MOVF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) → (dest) Status Affected: Z Encoding:

00 1000 dfff ffff

Description:

The contents of register f is moved to

a destination dependant upon the

status of d. If d = 0, destination is W

ﬁle register since status ﬂag Z is

affected.

Words: 1 Cycles: 1 Example

MOVF FSR, 0

After Instruction

W = value in FSR register Z = 1

MOVWF Move W to f

Syntax: [

label

] MOVWF f Operands: 0 ≤ f ≤ 127 Operation: (W) → (f) Status Affected: None Encoding:

00 0000 1fff ffff

Description:

Move data from W register to register 'f'

. Words: 1 Cycles: 1 Example

MOVWF OPTION

Before Instruction

OPTION = 0xFF W = 0x4F

After Instruction

OPTION = 0x4F W = 0x4F

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PIC16CE62X

NOP No Operation

Syntax: [

label

] NOP Operands: None Operation: No operation Status Affected: None Encoding:

00 0000 0xx0 0000

Description:

No operation.

Words: 1 Cycles: 1 Example

NOP

OPTION Load Option Register

Syntax: [

label

] OPTION

Operands: None

Operation: (W) → OPTION Status Affected: None Encoding:

00 0000 0110 0010

Description:

The contents of the W register are loaded in the OPTION register. This instruction is supported for code compatibility with PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it.

Words: 1 Cycles: 1

Example

To maintain upward compatibility with future PICmicro™ products, do not use this instruction.

RETFIE Return from Interrupt

Syntax: [

label

] RETFIE Operands: None Operation: TOS → PC,

1 → GIE Status Affected: None Encoding:

00 0000 0000 1001

Description:

Return from Interrupt. Stack is POP ed

and Top of Stack (TOS) is loaded in

the PC. Interrupts are enabled by

setting Global Interrupt Enable bit,

GIE (INTCON<7>). This is a two-cycle

instruction.

Words: 1 Cycles: 2 Example

RETFIE

After Interrupt

PC = TOS GIE = 1

RETLW Return with Literal in W

Syntax: [

label

] RETLW k Operands: 0 ≤ k ≤ 255 Operation: k → (W);

TOS → PC Status Affected: None Encoding:

11 01xx kkkk kkkk

Description:

The W register is loaded with the eight

bit literal 'k'. The program counter is

loaded from the top of the stack (the

return address). This is a two-cycle

instruction.

Words: 1 Cycles: 2 Example

TABLE

CALL TABLE ;W contains table

;offset value

• ;W now has table

value

•

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2 ;

•

RETLW kn ; End of table

Before Instruction

W = 0x07

After Instruction

W = value of k8

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RETURN Return from Subroutine

Syntax: [

label

] RETURN Operands: None Operation: TOS → PC Status Affected: None Encoding:

00 0000 0000 1000

Description:

Return from subroutine. The stack is POPed and the top of the stack (T OS) is loaded into the program counter. This is a two cycle instruction.

Words: 1 Cycles: 2 Example

RETURN

After Interrupt

PC = TOS

RLF Rotate Left f through Carry

Syntax: [

label

] RLF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: See description below Status Affected: C Encoding:

00 1101 dfff ffff

Description:

The contents of register 'f' are rotated

one bit to the left through the Carry

Flag. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

stored back in register 'f'.

Words: 1 Cycles: 1 Example

RLF REG1,0

Before Instruction

REG1 = 1110 0110 C = 0

After Instruction

REG1 = 1110 0110 W = 1100 1100 C = 1

RRF Rotate Right f through Carry

Syntax: [

label

] RRF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: See description below Status Affected: C Encoding:

00 1100 dfff ffff

Description:

The contents of register 'f' are rotated

one bit to the right through the Carry

Flag. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Words: 1 Cycles: 1 Example

RRF REG1,0

Before Instruction

REG1 = 1110 0110 C = 0

After Instruction

REG1 = 1110 0110 W = 0111 0011 C = 0

SLEEP

Syntax: [

label

] SLEEP Operands: None Operation: 00h → WDT,

0 → WDT prescaler, 1 → T

0 → PD Status Affected: TO, PD Encoding:

00 0000 0110 0011

Description:

The power-down status bit, PD is

cleared. Time-out status bit, TO is

set. Watchdog Timer and its

prescaler are cleared.

The processor is put into SLEEP

mode with the oscillator stopped.

See Section 10.8 for more details.

Words: 1 Cycles: 1 Example: SLEEP

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PIC16CE62X

SUBLW Subtract W from Literal

Syntax: [

label

] SUBLW k Operands: 0 ≤ k ≤ 255 Operation: k - (W) → (W) Status

Affected:

C, DC, Z

Encoding: 11 110x kkkk kkkk Description:

The W register is subtracted (2’s complement method) from the eight bit literal 'k'. The result is placed in the W register.

Words: 1 Cycles: 1 Example 1: SUBLW 0x02

Before Instruction

W = 1 C = ?

After Instruction

W = 1 C = 1; result is positive

Example 2: Before Instruction

W = 2 C = ?

After Instruction

W = 0 C = 1; result is zero

Example 3: Before Instruction

W = 3 C = ?

After Instruction

W = 0xFF C = 0; result is negative

SUBWF Subtract W from f

Syntax: [

label

] SUBWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) - (W) → (dest) Status

Affected:

C, DC, Z

Encoding: 00 0010 dfff ffff Description:

Subtract (2’s complement method)

W register from register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd' is 1

the result is stored back in register 'f'.

Words: 1 Cycles: 1 Example 1: SUBWF REG1,1

Before Instruction

REG1 = 3 W = 2 C = ?

After Instruction

REG1 = 1 W = 2 C = 1; result is positive

Example 2: Before Instruction

REG1 = 2 W = 2 C = ?

After Instruction

REG1 = 0 W = 2 C = 1; result is zero

Example 3: Before Instruction

REG1 = 1 W = 2 C = ?

After Instruction

REG1 = 0xFF W = 2 C = 0; result is negative

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PIC16CE62X

DS40182A-page 76 Preliminary  1998 Microchip Technology Inc.

SWAPF Swap Nibbles in f

Syntax: [

label

] SWAPF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f<3:0>) → (dest<7:4>),

(f<7:4>) → (dest<3:0>) Status Affected: None Encoding:

1110 dfff ffff

Description:

The upper and lower nibbles of

the result is placed in W register. If 'd'

is 1 the result is placed in register 'f'.

Words: 1 Cycles: 1 Example

SWAPF REG, 0

Before Instruction

REG1 = 0xA5

After Instruction

REG1 = 0xA5 W = 0x5A

TRIS Load TRIS Register

Syntax: [

label

] TRIS f

Operands: 5 ≤ f ≤ 7

Operation: (W) → TRIS register f; Status Affected: None Encoding:

0000 0110 0fff

Description:

The instruction is supported for code

compatibility with the PIC16C5X

products. Since TRIS registers are

readable and writable, the user can

directly address them.

Words: 1 Cycles: 1 Example

To maintain upward compatibility with future PICmicro™ products, do not use this instruction.

XORLW Exclusive OR Literal with W

Syntax: [

label

] XORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Encoding: 11 1010 kkkk kkkk Description:

The contents of the W register are XOR’ed with the eight bit literal 'k'. The result is placed in the W register.

Words: 1 Cycles: 1 Example: XORLW 0xAF

Before Instruction

W = 0xB5

After Instruction

W = 0x1A

XORWF Exclusive OR W with f

Syntax: [

label

] XORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (W) .XOR. (f) → (dest) Status Affected: Z Encoding:

00 0110 dfff ffff

Description:

Exclusive OR the contents of the

W register with register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd'

is 1 the result is stored back in register

'f'.

Words: 1 Cycles: 1 Example XORWF

REG 1

Before Instruction

REG = 0xAF W = 0xB5

After Instruction

REG = 0x1A W = 0xB5

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 1998 Microchip Technology Inc. DS40182A - page 77

PIC16CE62X

12.0 DEVELOPMENT SUPPORT

12.1 Development Tools

The PICmicrο microcontrollers are supported with a full range of hardware and software dev elopment tools:

• PICMASTER



/PICMASTER CE Real-Time

In-Circuit Emulator

• ICEPIC Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator

• PRO MATE



II Universal Programmer

• PICSTART



Plus Entry-Level Prototype

Programmer

• PICDEM-1 Low-Cost Demonstration Board

• PICDEM-2 Low-Cost Demonstration Board

• PICDEM-3 Low-Cost Demonstration Board

• MPASM Assembler

• MPLAB SIM Software Simulator

• MPLAB-C17 (C Compiler)

• Fuzzy Logic Development System (

fuzzy

TECH−MP)

12.2 PICMASTER: High Performance

Universal In-Circuit Emulator with MPLAB IDE

The PICMASTER Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the PIC14C000, PIC12CXXX, PIC16C5X, PIC16CXXX and PIC17CXX families. PICMASTER is supplied with the MPLAB Integrated Development Environment (IDE), which allows editing, “make” and download, and source debugging from a single environment.

Interchangeable target probes allow the system to be easily reconﬁgured for emulation of different processors. The universal architecture of the PICMASTER allows expansion to support all new Microchip microcontrollers.

The PICMASTER Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows



3.x environment were chosen to best make these fea-

tures available to you, the end user. A CE compliant version of PICMASTER is availab le for

European Union (EU) countries.

12.3 ICEPIC: Low-Cost PICmicro™ In-Circuit Emulator

ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC12CXXX, PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers.

ICEPIC is designed to operate on PC-compatible machines ranging from 286-AT



through Pentium based machines under Windows 3.x environment. ICEPIC features real time, non-intrusive emulation.

12.4 PRO MATE II: Universal Programmer

The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. PRO MATE II is CE compliant.

The PRO MATE II has programmable V

DD and VPP

supplies which allows it to verify programmed memory at V

DD min and VDD max for maximum reliability. It has

an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices. It can also set conﬁguration and code-protect bits in this mode.

12.5 PICSTART Plus Entry Level

Development System

The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efﬁcient. PICSTART Plus is not recommended for production programming.

PICSTART Plus supports all PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923, PIC16C924 and PIC17C756 may be supported with an adapter socket. PICSTART Plus is CE compliant.

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PIC16CE62X

DS40182A - page 78  1998 Microchip Technology Inc.

12.6 PICDEM-1 Low-Cost PICmicro Demonstration Board

The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE II or PICSTART-Plus programmer, and easily test ﬁrmware. The user can also connect the PICDEM-1 board to the PICMASTER emulator and download the ﬁrmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB.

12.7 PICDEM-2 Low-Cost PIC16CXX Demonstration Board

The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test ﬁrmware. The PICMASTER emulator may also be used with the PICDEM-2 board to test ﬁrmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the f eatures include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I

C bus and separate headers for connec-

tion to an LCD module and a keypad.

12.8 PICDEM-3 Low-Cost PIC16CXXX Demonstration Board

The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and easily test ﬁrmware. The PICMASTER emulator may also be used with the PICDEM-3 board to test ﬁrmware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the f eatures include

an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplex ed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.

12.9 MPLAB™ Integrated Development Environment Software

The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains:

• A full featured editor

• Three operating modes

- editor

- emulator

- simulator

• A project manager

• Customizable tool bar and key mapping

• A status bar with project information

• Extensive on-line help

MPLAB allows you to:

• Edit your source ﬁles (either assembly or ‘C’)

• One touch assemble (or compile) and download

to PICmicro tools (automatically updates all project information)

• Debug using:

- source ﬁles

- absolute listing ﬁle

• Transfer data dynamically via DDE (soon to be

replaced by OLE)

• Run up to four emulators on the same PC

The ability to use MPLAB with Microchip’s simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools.

12.10 Assembler (MPASM)

The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It suppor ts all microcontroller series including the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX families.

MPASM offers full featured Macro capabilities, conditional assembly , and se ver al source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers.

MPASM allows full symbolic debugging from PICMASTER, Microchip’s Universal Emulator System.

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 1998 Microchip Technology Inc. DS40182A - page 79

PIC16CE62X

MPASM has the following features to assist in developing software for speciﬁc use applications.

• Provides translation of Assembler source code to object code for all Microchip microcontrollers.

• Macro assembly capability.

• Produces all the ﬁles (Object, Listing, Symbol, and special) required for symbolic debug with Microchip’s emulator systems.

• Supports Hex (default), Decimal and Octal source and listing formats.

MPASM provides a rich directive language to support programming of the PICmicro. Directives are helpful in making the development of your assemb le source code shorter and more maintainable.

12.11 Software Simulator (MPLAB-SIM)

The MPLAB-SIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PICmicro series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/ output radix can be set by the user and the execution can be performed in; single step , ex ecute until break, or in a trace mode.

MPLAB-SIM fully supports symbolic debugging using MPLAB-C and MPASM. The Software Simulator offers the low cost ﬂexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.

12.12 C Compiler (MPLAB-C17)

The MPLAB-C Code Development System is a complete ‘C’ compiler and integrated development environment for Microchip’s PIC17CXXX family of microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with other compilers.

For easier source level debugging, the compiler provides symbol information that is compatible with the MPLAB IDE memory display.

12.13 Fuzzy Logic Development System

(

fuzzy

TECH-MP)

fuzzy

TECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version,

fuzzy

TECH-MP, Edition for imple-

menting more complex systems. Both versions include Microchip’s

fuzzy

LAB demonstration board for hands-on experience with fuzzy logic systems implementation.

12.14 MP-DriveWay – Application Code

Generator

MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can visually conﬁgure all the peripherals in a PICmicro device and, with a click of the mouse, generate all the initialization and many functional code modules in C language. The output is fully compatible with Microchip’s MPLAB-C C compiler. The code produced is highly modular and allows easy integration of your o wn code. MP-DriveWay is intelligent enough to maintain your code through subsequent code generation.

12.15 SEEVAL Evaluation and Programming System

The SEEVAL SEEPROM Designer’s Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart Serials and secure serials. The Total Endurance Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can signiﬁcantly reduce time-to-market and result in an optimized system.

12.16 KEELOQ Evaluation and Programming Tools

KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters.

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PIC16CE62X

DS40182A - page 80  1998 Microchip Technology Inc.

TABLE 12-1: DEVELOPMENT TOOLS FROM MICROCHIP

PIC12C5XX PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C75X

24CXX 25CXX 93CXX

HCS200 HCS300 HCS301

Emulator Products

PICMASTER/ PICMASTER-CE In-Circuit Emulator

ü ü ü ü ü ü ü ü ü ü

ICEPIC Low-Cost In-Circuit Emulator

ü ü ü ü ü ü ü

Software Tools

MPLAB Integrated Development Environment

ü ü ü ü ü ü ü ü ü ü

MPLAB C17 Compiler

ü ü

fuzzy

TECH-MP Explorer/Edition Fuzzy Logic Dev. Tool

ü ü ü ü ü ü ü ü ü

MP-DriveWay Applications Code Generator

ü ü ü ü ü ü ü

Total Endurance Software Model

Programmers

PICSTARTPlus Low-Cost Universal Dev. Kit

ü ü ü ü ü ü ü ü ü ü

PRO MATE II Universal Programmer

ü ü ü ü ü ü ü ü ü ü ü ü

KEELOQ



Programmer

Demo Boards

SEEVAL



Designers Kit

PICDEM-1

ü ü ü ü

PICDEM-2

ü ü

PICDEM-3

KEELOQ



Evaluation Kit

 1998 Microchip Technology Inc. Preliminary DS40182A-page 81

PIC16CE62X

13.0 ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings †

Ambient Temperature under bias.............................................................................................................. -40° to +125°C

Storage Temperature................................................................................................................................. -65° to +150°C

Voltage on any pin with respect to V

SS (except VDD and MCLR)....................................................... -0.6V to VDD +0.6V

Voltage on V

DD with respect to VSS ................................................................................................................ 0 to +7.5V

Voltage on MCLR

with respect to VSS (Note 2)..................................................................................................0 to +14V

Total power Dissipation (Note 1)...............................................................................................................................1.0W

Maximum Current out of V

SS pin...........................................................................................................................300 mA

Maximum Current into V

DD pin .............................................................................................................................250 mA

Input Clamp Current, I

IK (VI <0 or VI> VDD)......................................................................................................................±20 mA

Output Clamp Current, I

OK (VO <0 or VO>VDD)...............................................................................................................±20 mA

Maximum Output Current sunk by any I/O pin........................................................................................................25 mA

Maximum Output Current sourced by any I/O pin...................................................................................................25 mA

Maximum Current sunk by PORTA and PORTB...................................................................................................200 mA

Maximum Current sourced by PORTA and PORTB..............................................................................................200 mA

Note 1: Power dissipation is calculated as follows: P

DIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)

† NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

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DS40182A-page 82 Preliminary  1998 Microchip Technology Inc.

TABLE 13-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS

AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)

OSC PIC16CE62X-04 PIC16CE62X-20 PIC16CE62X/JW

DD: 3.0V to 5.5V

DD: 3.3 mA max.

@5.5V I

PD: 2.5 µA max.

@4.0V, WDT DIS Freq: 4.0 MHz max.

VDD: 3.0V to 5.5V I

DD: 1.8 mA typ.

@5.5V I

PD: 1.0 µA typ.

@4.0V, WDT DIS Freq: 4.0 MHz max.

DD: 3.0V to 5.5V

DD: 3.3 mA max.

@5.5V I

PD: 2.5 µA max.

@4.0V, WDT DIS Freq: 4.0 MHz max.

DD: 3.0V to 5.5V

DD: 3.3 mA max.

@5.5V I

PD: 2.5 µA max.

@4.0V, WDT DIS Freq: 4.0 MHz max.

VDD: 3.0V to 5.5V I

DD: 1.8 mA typ.

@5.5V I

PD: 1.0 µA typ.

@4.0V, WDT DIS Freq: 4.0 MHz max.

DD: 3.0V to 5.5V

DD: 3.3 mA max.

@5.5V I

PD: 2.5 µA max.

@4.0V, WDT DIS Freq: 4.0 MHz max.

VDD: 4.5V to 5.5V I

DD: 3.0 mA typ.

@5.5V I

PD: 1.0 µA typ.

@4.0V, WDT DIS Freq: 4.0 MHz max.

DD: 4.5V to 5.5V

DD: 7.5 mA max.

@5.5V I

PD: 2.5 µA max.

@4.0V, WDT DIS Freq: 20 MHz max.

DD: 4.5V to 5.5V

DD: 7.5 mA max.

@5.5V I

PD: 2.5 µA max.

@4.0V, WDT DIS Freq: 20 MHz max.

DD: 3.0V to 5.5V

DD: 70 µA max.

@32 kHz, 3.0V, WDT DIS I

PD: 2.5 µA max.

@4.0 V, WDT DIS Freq: 200 kHz max.

Do not use in

LP mode

DD: 3.0V to 5.5V

DD: 70 µA max.

@32 kHz, 3.0V, WDT DIS I

PD: 2.5 µA max.

@4.0V, WDT DIS Freq: 200 kHz max.

The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX speciﬁcations. It is recommended that the user select the device type that ensures the speciﬁcations required.

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PIC16CE62X

13.1 DC CHARACTERISTICS: PIC16CE62X-04 (Commercial, Industrial, Extended)

PIC16CE62X-20 (Commercial, Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature –40°C ≤ TA ≤ +85°C for industrial and

0°C ≤ TA ≤ +70°C for commercial and

–40°C ≤ T

A ≤ +125°C for extended

Param

No.

Sym Characteristic Min Typ† Max Units Conditions

D001 D001A

VDD Supply Voltage 3.0

4.5

--5.5

5.5VV

XT, RC and LP osc conﬁguration HS osc conﬁguration

D002 VDR RAM Data Retention

Voltage (Note 1)

– 1.5* – V Device in SLEEP mode

D003 VPOR VDD start voltage to

ensure Power-on Reset

– VSS – V See section on power-on reset for

details

D004 SVDD VDD rise rate to ensure

Power-on Reset

0.05* – – V/ms See section on power-on reset for details

D005 D005A

VBOR Brown-out Reset Voltage 3.7

3.7

4.0

4.3

4.4

V BODEN conﬁguration bit is cleared

(Automotive)

D010

D010A

D013

IDD Supply Current (Note 2) –

–

1.8

3.0

3.3

7.5

µA

XT and RC osc conﬁguration FOSC = 4 MHz, VDD = 5.5V, WDT disabled (Note 4) LP osc conﬁguration, PIC16CE62X-04 only FOSC = 32 kHz, VDD = 4.0V, WDT disabled HS osc conﬁguration FOSC = 20 MHz, VDD = 5.5V, WDT disabled

D021 IPD Power Down Current (Note 3) – 1.0 2.515µAµAVDD=4.0V, WDT disabled

(125°C)

D022

D022A

D023

D023A

∆IWDT

∆IBOR

∆ICOMP

∆IVREF

WDT Current (Note 5)

Brown-out Reset Current (Note

5) Comparator Current for each Comparator (Note 5) VREF Current (Note 5)

–

6.0

20 25

150

100

200

µA µA µA

µA

VDD = 4.0V (125°C) BOR enabled, VDD = 5.0V

VDD = 4.0V

* These parameters are characterized but not tested. † Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: This is the limit to which V

DD can be lowered in SLEEP mode without losing RAM data.

2: The supply current is mainly a function of the operating v oltage and frequency. Other factors such as I/O pin loading and

switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as speciﬁed.

3: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with

the part in SLEEP mode, with all I/O pins in hi-impedence state and tied to VDD or VSS.

4: For RC osc conﬁguration, current through Rext is not included. The current through the resistor can be estimated by the

formula Ir = VDD/2Rext (mA) with Rext in kΩ.

5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the

base IDD or IPD measurement.

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DS40182A-page 84 Preliminary  1998 Microchip Technology Inc.

13.2 DC CHARACTERISTICS: PIC16CE62X-04 (Commercial, Industrial, Extended) PIC16CE62X-20 (Commercial, Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature –40˚C ≤ TA ≤ +85˚C for industrial and

0˚C ≤ TA ≤ +70˚C for commercial and

–40˚C ≤ TA ≤ +125˚C for extended

Operating voltage V

DD range as described in DC spec Table 13-1 and Table 13-2

Parm

No.

Sym

Characteristic Min Typ† Max Unit Conditions

VIL

Input Low Voltage

I/O ports

D030 D030A

with TTL buffer VSS - 0.8V

0.15V

DD = 4.5V to 5.5V

otherwise

(4)

D031

with Schmitt Trigger input VSS 0.2VDD V For entire VDD range

D032

MCLR, RA4/T0CKI,OSC1 (in RC mode)

Vss - 0.2VDD V Note1

D033

OSC1 (in XT and HS) OSC1 (in LP)

Vss - 0.3VDD

0.6VDD -

1.0

VIH

Input High Voltage

I/O ports -

D040 D040A

with TTL buffer 2.0V

0.25V

DD +

0.8V

- V

VDD

V VDD = 4.5V to 5.5V

otherwise

(4)

D041

with Schmitt Trigger input 0.8VDD VDD For entire VDD range

D042

MCLR RA4/T0CKI 0.8VDD - VDD V

D042A D043

OSC1 (XT, HS and LP) OSC1 (in RC mode)

0.7VDD

0.9VDD

- VDD V Note1

D070 IPURB

PORTB weak pull-up current 50 200 400 µA VDD = 5.0V, VPIN = VSS

D060

Input Leakage Current

(Notes 2, 3) I/O ports (Except PORTA) ±1.0 µA V

SS ≤ VPIN ≤ VDD, pin at hi-impedance

D060A

PORTA - - ±0.5 µA Vss ≤ VPIN ≤ VDD, pin at hi-impedance

D060B

RA4/T0CKI - - ±1.0 µA Vss ≤ VPIN ≤ VDD

D061

OSC1, MCLR - - ±5.0 µA Vss ≤ VPIN ≤ VDD, XT, HS and LP osc

conﬁguration

VOL

Output Low Voltage

D080

I/O ports - - 0.6 V IOL=8.5 mA, VDD=4.5V, -40° to +85°C

D080A

- - 0.6 V IOL=7.0 mA, VDD=4.5V, +125°C

D083

OSC2/CLKOUT (RC only) - - 0.6 V IOL=1.6 mA, VDD=4.5V, -40° to +85°C

- - 0.6 V I

OL=1.2 mA, VDD=4.5V, +125°C

VOH

Output High Voltage (Note 3)

D090

I/O ports (Except RA4) VDD-0.7 - - V IOH=-3.0 mA, VDD=4.5V, -40° to +85°C * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are f or design guid-

ance only and are not tested.

Note 1: In RC oscillator conﬁguration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the

PIC16CE62X be driven with external clock in RC mode.

2: The leakage current on the MCLR

pin is strongly dependent on applied voltage level. The speciﬁed levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is deﬁned as coming out of the pin. 4: The better of the two speciﬁcations may be used. For V

IL, this would be the higher voltage and for

IH, this would be the lower voltage.

62X.bk Page 84 Tuesday, March 10, 1998 3:40 PM

 1998 Microchip Technology Inc. Preliminary DS40182A-page 85

PIC16CE62X

D090A

VDD-0.7 - - V IOH=-2.5 mA,

DD=4.5V, +125°C

D092

OSC2/CLKOUT (RC only) VDD-0.7 - - V IOH=-1.3 mA, VDD=4.5V, -40° to +85°C

DD-0.7 - - V IOH=-1.0 mA, VDD=4.5V, +125°C

D150 VOD

Open-Drain High Voltage 10* V RA4 pin Capacitive Loading Specs on Output Pins

D100 COSC

OSC2 pin 15 pF In XT , HS and LP modes when external

clock used to drive OSC1.

D101 Cio

All I/O pins/OSC2 (in RC mode)

50 pF

13.2 DC CHARACTERISTICS: PIC16CE62X-04 (Commercial, Industrial, Extended) PIC16CE62X-20 (Commercial, Industrial, Extended) (Cont.)

Standard Operating Conditions (unless otherwise stated)

Operating temperature –40˚C ≤ TA ≤ +85˚C for industrial and

0˚C ≤ TA ≤ +70˚C for commercial and

–40˚C ≤ TA ≤ +125˚C for extended

Operating voltage V

DD range as described in DC spec Table 13-1 and Table 13-2

Parm

No.

Sym

Characteristic Min Typ† Max Unit Conditions

* These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are f or design guid-

ance only and are not tested.

Note 1: In RC oscillator conﬁguration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the

PIC16CE62X be driven with external clock in RC mode.

2: The leakage current on the MCLR

pin is strongly dependent on applied voltage level. The speciﬁed levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is deﬁned as coming out of the pin. 4: The better of the two speciﬁcations may be used. For V

IL, this would be the higher voltage and for

IH, this would be the lower voltage.

62X.bk Page 85 Tuesday, March 10, 1998 3:40 PM

PIC16CE62X

DS40182A-page 86 Preliminary  1998 Microchip Technology Inc.

TABLE 13-2: COMPARATOR SPECIFICATIONS

Operating Conditions: Vdd range as described in Table 12-1, -40°C<TA<+125°C. Current consumption is speciﬁed in Table 13-1.

TABLE 13-3: VOLTAGE REFERENCE SPECIFICATIONS

Operating Conditions:Vdd range as described in Table 12-1, -40°C<TA<+125°C. Current consumption is speciﬁed in Table 13-1.

Param No. Characteristics Sym Min Typ Max Units Comments

D300 Input offset voltage V

IOFF ± 5.0 ± 10 mV

D301 Input common mode voltage V

ICM 0 VDD - 1.5 V

D302 CMRR CMRR +55* db 300

Response Time

(1)

TRESP 150* 400* ns PIC16CE62X

301 Comparator Mode Change to

Output Valid

MC2OV 10* µs

* These parameters are characterized but not tested.

Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from

SS to VDD.

Param

No.

Characteristics Sym Min Typ Max Units Comments

D310 Resolution V

RES VDD/24 VDD/32 LSB

D311 Absolute Accuracy V

RAA +1/4

1/2

LSB LSB

Low Range (V

RR=1)

High Range (V

RR=0)

D312 Unit Resistor Value (R) VR

UR 2K* Ω Figure 9-2

310

Settling Time

(1)

TSET 10* µs

* These parameters are characterized but not tested.

Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.

62X.bk Page 86 Tuesday, March 10, 1998 3:40 PM

 1998 Microchip Technology Inc. Preliminary DS40182A-page 87

PIC16CE62X

13.3 Timing Parameter Symbology

The timing parameter symbols have been created with one of the following formats:

FIGURE 13-1: LOAD CONDITIONS

1. TppS2ppS

2. TppS

F Frequency T Time Lowercase subscripts (pp) and their meanings:

ck CLKOUT osc OSC1 io I/O port t0 T0CKI mc MCLR Uppercase letters and their meanings:

F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-Impedance

VDD/2

Pin Pin

VSS

RL = 464Ω C

L = 50 pF for all pins except OSC2

15 pF for OSC2 output

Load condition 1

Load condition 2

62X.bk Page 87 Tuesday, March 10, 1998 3:40 PM

PIC16CE62X

DS40182A-page 88 Preliminary  1998 Microchip Technology Inc.

13.4 Timing Diagrams and Speciﬁcations FIGURE 13-2: EXTERNAL CLOCK TIMING

TABLE 13-4: EXTERNAL CLOCK TIMING REQUIREMENTS

Parameter

No.

Sym Characteristic Min Typ† Max Units Conditions

Fos External CLKIN Frequency

(Note 1)

DC — 4 MHz XT and RC osc mode, VDD=5.0V DC — 20 MHz HS osc mode DC — 200 kHz LP osc mode

Oscillator Frequency (Note 1)

DC — 4 MHz RC osc mode, VDD=5.0V

0.1 — 4 MHz XT osc mode 1 — 20 MHz HS osc mode

DC – 200 kHz LP osc mode

1 Tosc External CLKIN Period

(Note 1)

250 — — ns XT and RC osc mode

50 — — ns HS osc mode

5 — — µs LP osc mode

Oscillator Period (Note 1)

250 — — ns RC osc mode 250 — 10,000 ns XT osc mode

50 — 1,000 ns HS osc mode

5 — — µs LP osc mode

2 TCY Instruction Cycle Time (Note 1) 1.0 Fosc/4 DC µs

TCYS=FOSC/4

3* TosL,

TosH

External Clock in (OSC1) High or Low Time

100* — — ns XT oscillator, TOSC L/H duty cycle

2* — — µs LP oscillator, T OSC L/H duty cycle

20* — — ns HS oscillator, TOSC L/H duty

cycle

4* TosR,

TosF

External Clock in (OSC1) Rise or Fall Time

25* — — ns XT oscillator 50* — — ns LP oscillator 15* — — ns HS oscillator

* These parameters are characterized but not tested. † Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Instruction cycle period (T

CY) equals four times the input oscillator time-base period. All speciﬁed values are

based on characterization data for that particular oscillator type under standard operating conditions with the device ex ecuting code. Exceeding these speciﬁed limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1 pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.

OSC1

CLKOUT

Q1 Q2

Q3 Q4 Q1

1 3 3

4 4

62X.bk Page 88 Tuesday, March 10, 1998 3:40 PM

 1998 Microchip Technology Inc. Preliminary DS40182A-page 89

PIC16CE62X

FIGURE 13-3: CLKOUT AND I/O TIMING

TABLE 13-5: CLKOUT AND I/O TIMING REQUIREMENTS

Parameter # Sym Characteristic Min Typ† Max Units

10* TosH2ckL

OSC1↑ to CLKOUT↓

(1)

— 75 200 ns

11* TosH2ckH

OSC1↑ to CLKOUT↑

(1)

— 75

200

12* TckR

CLKOUT rise time

(1)

— 35 100 ns

13* TckF

CLKOUT fall time

(1)

— 35 100 ns

14* TckL2ioV

CLKOUT ↓ to Port out valid

(1)

— — 20 ns

15* TioV2ckH

Port in valid before CLKOUT ↑

(1)

Tosc +200 ns — — ns

16* TckH2ioI

Port in hold after CLKOUT ↑

(1)

0 — — ns

17* TosH2ioV OSC1↑ (Q1 cycle) to Port out valid — 50 150 ns 18* TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid (I/O in hold

time)

100 — — ns

19* TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 — — ns 20* TioR Port output rise time — 10 40 ns 21* TioF Port output fall time — 10 40 ns 22* Tinp RB0/INT pin high or low time 25 — — ns

23 Trbp RB<7:4> change interrupt high or low time T

CY — — ns

* These parameters are characterized but not tested † Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC

22 23

Note: All tests must be do with speciﬁed capacitance loads (Figure 13-1) 50 pF on I/O pins and CLKOUT

OSC1

CLKOUT

I/O Pin (input)

I/O Pin (output)

Q2 Q3

20, 21

old value

new value

62X.bk Page 89 Tuesday, March 10, 1998 3:40 PM

PIC16CE62X

DS40182A-page 90 Preliminary  1998 Microchip Technology Inc.

FIGURE 13-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

FIGURE 13-5: BROWN-OUT RESET TIMING

TABLE 13-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER REQUIREMENTS

Parameter

No.

Sym Characteristic Min Typ† Max Units Conditions

30 TmcL MCLR Pulse Width (low) 2000 — — ns

-40

° to +85°C

31 Twdt Watchdog Timer Time-out Period

(No Prescaler)

7* 18 33* ms

VDD = 5.0V, -40° to +85°C

32 Tost Oscillation Start-up Timer Period — 1024 T

OSC — — TOSC = OSC1 period

33 Tpwrt Power-up Timer Period 28* 72 132* ms

VDD = 5.0V, -40° to +85°C

34 T

IOZ I/O hi-impedance from MCLR low — 2.0 µs

35 T

BOR Brown-out Reset Pulse Width 100* — — µs 3.7V ≤ VDD ≤ 4.3V

* These parameters are characterized but not tested. † Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

VDD

MCLR

Internal

POR

PWRT

Timeout

OSC

Timeout

Internal

RESET

Watchdog

Timer

RESET

I/O Pins

VDD

BVDD

62X.bk Page 90 Tuesday, March 10, 1998 3:40 PM

 1998 Microchip Technology Inc. Preliminary DS40182A-page 91

PIC16CE62X

FIGURE 13-6: TIMER0 CLOCK TIMING

TABLE 13-7: TIMER0 CLOCK REQUIREMENTS

Parameter

No.

Sym Characteristic Min Typ† Max Units Conditions

40 Tt0H T0CKI High Pulse Width No Prescaler 0.5 T

CY + 20* — — ns

With Prescaler 10* — — ns

41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20* — — ns

With Prescaler 10* — — ns

42 Tt0P T0CKI Period TCY + 40*

— — ns N = prescale value

(1, 2, 4, ..., 256)

* These parameters are characterized but not tested. † Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

RA4/T0CKI

TMR0

62X.bk Page 91 Tuesday, March 10, 1998 3:40 PM

PIC16CE62X

DS40182A-page 92 Preliminary  1998 Microchip Technology Inc.

13.5 EEPROM Timing TABLE 13-8: AC CHARACTERISTICS

FIGURE 13-7: BUS TIMING DATA

Parameter Symbol

STANDARD

MODE

Vcc = 4.5 - 5.5V

FAST MODE

Units Remarks

Min. Max. Min. Max.

Clock frequency F

CLK — 100 — 400 kHz

Clock high time T

HIGH 4000 — 600 — ns

Clock low time T

LOW 4700 — 1300 — ns

SDA and SCL rise time T

R — 1000 — 300 ns (Note 1)

SDA and SCL fall time T

F — 300 — 300 ns (Note 1)

START condition hold time T

HD:STA 4000 — 600 — ns After this period the ﬁrst

clock pulse is generated

START condition setup time T

SU:STA 4700 — 600 — ns Only relevant for repeated

START condition

Data input hold time T

HD:DAT 0 — 0 — ns (Note 2)

Data input setup time T

SU:DAT 250 — 100 — ns

STOP condition setup time T

SU:STO 4000 — 600 — ns

Output valid from clock T

AA — 3500 — 900 ns (Note 2)

Bus free time T

BUF 4700 — 1300 — ns Time the bus must be free

before a new transmission can start

Output fall time from V

minimum to VIL maximum

OF — 250 20 +0.1

250 ns (Note 1), CB ≤ 100 pF

Input ﬁlter spike suppression (SDA and SCL pins)

SP — 50 — 50 ns (Note 3)

Write cycle time T

WR — 10 — 10 ms Byte or Page mode

Endurance

—

10M

— 10M

— cycles

25°C, Vcc = 5.0V, Block Mode (Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undeﬁned region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

SP and VHYS speciﬁcations are due to new Schmitt trigger inputs which provide improved

noise spike suppression. This eliminates the need for a TI speciﬁcation for standard operation.

4: This parameter is not tested but guaranteed by char acterization. For endurance estimates in a speciﬁc appli-

cation, please consult the Total Endurance Model which can be obtained on our website.

SCL

SDA

OUT

HD:STA

TSU:STA

THIGH

TSU:STOTSU:DATTHD:DAT

TBUFTAA

THD:STA

TAA

TSP

TLOW

62X.bk Page 92 Tuesday, March 10, 1998 3:40 PM

 1998 Microchip Technology Inc. Preliminary DS40182A-page 93

PIC16CE62X

14.0 PACKAGING INFORMATION

Package Type: K04-010 18-Lead Ceramic Dual In-line with Window (JW) – 300 mil

* Controlling Parameter.

2 1

MIN

Window Length

Window Width

Overall Row Spacing

Radius to Radius Width

Package Width

Package Length

Tip to Seating Plane

Base to Seating Plane

Top of Lead to Seating Plane

Top to Seating Plane

Lead Thickness

Shoulder Radius

Upper Lead Width

Lower Lead Width

Number of Pins

PCB Row Spacing

Dimension Limits

Pitch

Units

E E1

A1 A2

n p

0.15

7.24

7.87

0.76

3.33

4.83

0.30

0.38

1.52

0.53

2.59

0.200

0.140

0.385

0.270

0.298

0.900

0.138

0.023

0.111

0.183

0.190

0.130

0.345

0.125

0.255

0.285

0.880

0.015

0.091

0.175

0.210

0.150

0.425

0.150

0.285

0.310

0.920

0.030

0.131

0.190

0.010

0.013

0.055

0.019

0.100

0.300

NOM

0.016

0.008

0.010

0.050

0.098

INCHES*

MAX

0.021

0.012

0.015

0.060

0.102

22.86

0.19

0.13

8.76

6.48

7.24

22.35

3.18

0.00

2.31

4.45

0.2

0.14

9.78 10.80

0.21

3.49

6.86

7.56

0.57

2.82

4.64

3.81

23.37

NOM

MILLIMETERS

MIN

0.20

0.25

1.27

0.41

2.49

MAX

0.47

0.25

0.32

1.40

2.54

7.62

62X.bk Page 93 Tuesday, March 10, 1998 3:40 PM

PIC16CE62X

DS40182A-page 94 Preliminary  1998 Microchip Technology Inc.

Package Type: K04-007 18-Lead Plastic Dual In-line (P) – 300 mil

* Controlling Parameter.

†

Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”

(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”

‡

Dimensions “D” and “E” do not include mold ﬂash or protrusions. Mold ﬂash or protrusions shall not

exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”

Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX PCB Row Spacing 0.300 7.62 Number of Pins n 18 18 Pitch p 0.100 2.54 Lower Lead Width B 0.013 0.018 0.023 0.33 0.46 0.58 Upper Lead Width B1

†

0.055 0.060 0.065 1.40 1.52 1.65 Shoulder Radius R 0.000 0.005 0.010 0.00 0.13 0.25 Lead Thickness c 0.005 0.010 0.015 0.13 0.25 0.38 Top to Seating Plane A 0.110 0.155 0.155 2.79 3.94 3.94 Top of Lead to Seating Plane A1 0.075 0.095 0.115 1.91 2.41 2.92 Base to Seating Plane A2 0.000 0.020 0.020 0.00 0.51 0.51 Tip to Seating Plane L 0.125 0.130 0.135 3.18 3.30 3.43 Package Length D

‡

0.890 0.895 0.900 22.61 22.73 22.86 Molded Package Width E

‡

0.245 0.255 0.265 6.22 6.48 6.73 Radius to Radius Width E1 0.230 0.250 0.270 5.84 6.35 6.86 Overall Row Spacing eB 0.310 0.349 0.387 7.87 8.85 9.83 Mold Draft Angle Top

5 10 15 5 10 15

Mold Draft Angle Bottom

5 10 15 5 10 15

2 1

62X.bk Page 94 Tuesday, March 10, 1998 3:40 PM

 1998 Microchip Technology Inc. Preliminary DS40182A-page 95

PIC16CE62X

Package Type: K04-072 20-Lead Plastic Shrink Small Outine (SS) – 5.30 mm

MIN

pPitch

Mold Draft Angle Bottom

Mold Draft Angle Top

Lower Lead Width

Radius Centerline

Gull Wing Radius

Shoulder Radius

Outside Dimension

Molded Package Width

Molded Package Length

Shoulder Height

Overall Pack. Height

Lead Thickness

Foot Angle

Foot Length

Standoff

Number of Pins

†

R2 L

‡

Dimension Limits

Units

0.650.026

0 0

5 5 10

0.012

0.007

0.005

0.020

0.005

0.306

0.208

0.283

0.005

0.036

0.073

0.301

0.010

0.005

0.000

0.015

0.005

0.205

0.278

0.002

0.026

0.068

0.311

0.015

0.009

0.010

0.025

0.010

4 8

0.212

0.289

0.008

0.046

0.078

0 0 5

5 10

7.65

0.25

0.13

0.00

0.38

0.13

5.20

7.07

0.05

0.66

1.73

7.907.78

0.32

0.18

0.13

0.51

0.13

0.38

0.22

0.25

0.64

0.25

5.29

7.20

0.13

1.86

0.91

5.38

7.33

0.21

1.99

1.17

NOM

INCHES

MAX NOM

MILLIMETERS*

MIN MAX

Controlling Parameter.

†

Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”

‡

Dimensions “D” and “E” do not include mold ﬂash or protrusions. Mold ﬂash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”

62X.bk Page 95 Tuesday, March 10, 1998 3:40 PM

PIC16CE62X

DS40182A-page 96 Preliminary  1998 Microchip Technology Inc.

Package Type: K04-051 18-Lead Plastic Small Outline (SO) – Wide, 300 mil

0.014

0.009

0.010

0.011

0.005

0.010

0.394

0.292

0.450

0.004

0.048

0.093

MIN

nNumber of Pins

Mold Draft Angle Bottom

Mold Draft Angle Top

Lower Lead Width

Chamfer Distance

Outside Dimension

Molded Package Width

Molded Package Length

Overall Pack. Height

Lead Thickness

Radius Centerline

Foot Angle

Foot Length

Gull Wing Radius

Shoulder Radius

Standoff

Shoulder Height

†

‡

Dimension Limits Pitch

Units

1818

0.020

0.017

0.011

0.015

0.016

0.005

0.407

0.296

0.456

0.008

0.058

0.099

0.029

0.019

0.012

0.020

0.021

0.010

0.419

0.299

0.462

0.011

0.068

0.104

0.42

0.27

0.38

0.41

0.13

0.50

10.33

7.51

11.58

0.19

1.47

2.50

0.25

0.36

0.23

0.25

0.28

0.13

10.01

7.42

11.43

0.10

1.22

2.36

0.74

4 8

0.48

0.30

0.51

0.53

0.25

10.64

7.59

11.73

0.28

1.73

2.64

INCHES*

0.050

NOM MAX

1.27

MILLIMETERS

MIN NOM MAX

2 1

Controlling Parameter.

†

Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”

‡

62X.bk Page 96 Tuesday, March 10, 1998 3:40 PM

 1998 Microchip Technology Inc. Preliminary DS40182A-page 97

PIC16CE62X

14.1 Package Marking Information

Legend: MM...M Microchip part number information

XX...X Customer speciﬁc information* AA Year code (last 2 digits of calendar year) BB Week code (week of January 1 is week ‘01’) C Facility code of the plant at which wafer is manufactured

O = Outside Vendor C = 5” Line S = 6” Line

H = 8” Line D Mask revision number E Assembly code of the plant or country of origin in which

part was assembled

Note: In the event the full Microchip part number cannot be marked on one line,

it will be carried over to the next line thus limiting the number of available characters for customer speciﬁc information.

* Standard OTP marking consists of Microchip part number, year code, week

code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Ofﬁce . For QTP devices, any special marking adders are included in QTP price.

XXXXXXXX XXXXXXXX

AABBCDE

18-Lead CERDIP Windowed

18-Lead SOIC (.300")

XXXXXXXXXXXX

AABBCDE

XXXXXXXXXXXX

XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX

AABBCDE

18-Lead PDIP

16CE625

/JW

9807 CBA

Example

-04I/S0218 9807 CDK

PIC16CE625

-04I/P423 9807CDK

Example

XXXXXXXXXX

AABBCDE

XXXXXXXXXX

20-Lead SSOP

PIC16CE625

9807 CBP

-04I/218

Example

62X.bk Page 97 Tuesday, March 10, 1998 3:40 PM

PIC16CE62X

DS40182A-page 98 Preliminary  1998 Microchip Technology Inc.

NOTES:

62X.bk Page 98 Tuesday, March 10, 1998 3:40 PM

 1998 Microchip Technology Inc. Preliminary DS40182A-page 99

PIC16CE62X

APPENDIX A: CODE FOR

ACCESSING EEPROM DATA MEMORY

To be determined. Please check our web site at www.microchip.com for code availability.

62X.bk Page 99 Tuesday, March 10, 1998 3:40 PM

PIC16CE62X

DS40182A-page 100 Preliminary  1998 Microchip Technology Inc.

NOTES:

62X.bk Page 100 Tuesday, March 10, 1998 3:40 PM

Microchip Technology Inc PIC16CE623-JW, PIC16CE624-JW, PIC16CE625-JW Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual