Microchip Technology Inc PIC16C641-04-JW, PIC16C641-04-P, PIC16C641-04-SO, PIC16C641-04E-JW, PIC16C641-04E-P Datasheet

...

Microchip Technology Inc PIC16C641-04-JW, PIC16C641-04-P, PIC16C641-04-SO, PIC16C641-04E-JW, PIC16C641-04E-P, PIC16C642-10I-SO, PIC16C642-20-JW, PIC16C642-20-P, PIC16C642-20-SO, PIC16C642-20E-JW, PIC16C642-20E-P, PIC16C642-20E-SO, PIC16C642-20I-JW, PIC16C642-20I-P, PIC16C642-20I-SO, PIC16C641-10E-P, PIC16C641-10E-SO, PIC16C641-10I-JW, PIC16C641-10I-P, PIC16C641-10I-SO, PIC16C641-20-JW, PIC16C641-20-P, PIC16C641-20-SO, PIC16C641-20E-JW, PIC16C642-04I-JW, PIC16C642-04I-SO, PIC16C642-10-JW, PIC16C642-10-P, PIC16C642-10-SO, PIC16C642-10E-P, PIC16C642-10E-SO, PIC16C642-10I-JW, PIC16C642-10I-P, PIC16C641-20E-P, PIC16C641-20E-SO, PIC16C641-20I-JW, PIC16C641-20I-P, PIC16C641-20I-SO, PIC16C642-04-JW, PIC16C642-04-P, PIC16C642-04-SO, PIC16C642-04E-JW, PIC16C642-04E-SO, PIC16C641-04E-SO, PIC16C641-04I-JW, PIC16C641-04I-P, PIC16C641-04I-SO, PIC16C641-10-JW, PIC16C641-10-P, PIC16C641-10-SO, PIC16C641-10E-JW, PIC16C661-20-P, PIC16C661-20-TQ, PIC16C661-20E-JW, PIC16C661-20E-L, PIC16C661-20E-P, PIC16C661-20E-TQ, PIC16C661-20I-JW, PIC16C661-20I-L, PIC16C662-10E-TQ, PIC16C662-10I-JW, PIC16C662-10I-L, PIC16C662-20-JW, PIC16C662-20-L, PIC16C662-20-P, PIC16C662-20E-JW, PIC16C662-20E-P, PIC16C662-20I-JW, PIC16C662-20I-L, PIC16C661-20I-P, PIC16C661-20I-TQ, PIC16C662-04-JW, PIC16C662-04-L, PIC16C662-04-P, PIC16C662-04E-JW, PIC16C662-04E-L, PIC16C662-04E-P, PIC16C662-04E-TQ, PIC16C662-04I-JW, PIC16C661-04-JW, PIC16C661-04-L, PIC16C661-04-P, PIC16C661-04-TQ, PIC16C661-04E-JW, PIC16C661-04E-L, PIC16C661-04E-P, PIC16C662-20I-P, PIC16C662-20I-TQ, PIC16C662-04I-L, PIC16C662-04I-P, PIC16C662-04I-TQ, PIC16C662-10-JW, PIC16C662-10-L, PIC16C662-10-P, PIC16C662-10-TQ, PIC16C662-10E-JW, PIC16C662-10E-L, PIC16C662-10E-P, PIC16C661-04E-TQ, PIC16C661-04I-JW, PIC16C661-04I-P, PIC16C661-10-JW, PIC16C661-10-L, PIC16C661-10-P, PIC16C661-10-TQ, PIC16C661-10E-JW, PIC16C661-10E-L, PIC16C661-10E-P, PIC16C661-10E-TQ, PIC16C661-10I-JW, PIC16C661-10I-L, PIC16C661-10I-P, PIC16C661-10I-TQ, PIC16C661-20-JW, PIC16C661-20-L Datasheet

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

PIC16C64X & PIC16C66X

8-Bit EPROM Microcontrollers with Analog Comparators

Devices included in this data sheet:

• PIC16C641

• PIC16C642

• PIC16C661

• PIC16C662

High Performance RISC CPU:

• Only 35 instructions to learn

• All single-cycle instructions (200 ns), except for program branches which are two-cycle

• Operating speed:

- DC - 20 MHz clock input

- DC - 200 ns instruction cycle

Device Program

Memory x14

Data

Memory x8

PIC16C641 2K 128 PIC16C642

4K 176 PIC16C661 2K 128 PIC16C662

4K 176

• Interrupt capability

• 8-level deep hardware stack

• Direct, Indirect and Relative addressing modes

Peripheral Features:

• Up to 33 I/O pins with individual direction control

• High current sink/source for direct LED drive

• Analog comparator module with:

- Two analog comparators

- Programmable on-chip voltage reference (V

) module

REF

- Programmable input multiplexing from device inputs and internal voltage reference

- Comparator outputs can be output signals

• Timer0: 8-bit timer/counter with 8-bit programmable prescaler

Special Microcontroller Features:

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Brown-out Reset

• Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

• Programmable code protection

• Power saving SLEEP mode

• Selectable oscillator options

• Serial in-circuit programming (via two pins)

Pin Diagrams

PDIP, SOIC, Windowed CERDIP

MCLR/VPP

RA0/AN0 RA1/AN1

RA2/AN2/V

OSC1/CLKIN

OSC2/CLKOUT

REF

RA3/AN3

RA4/T0CKI

RA5

RC0 RC1 RC2 RC3

1 2 3

PIC16C64X

4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT V

VSS RC7 RC6 RC5 RC4

PDIP, Windowed CERDIP

MCLR/VPP

RA0/AN0 RA1/AN1

RA2/AN2/V

OSC1/CLKIN

OSC2/CLKOUT

REF

RA3/AN3

RA4/T0CKI

RA5

RE0/RD

RE1/WR

RE2/CS

VDD VSS

RC0 RC1 RC2

RC3 RD0/PSP0 RD1/PSP1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

• Four user programmable ID locations

• Program Memory Parity Error checking circuitry with Parity Error Reset (PER)

• CMOS Technology:

• Low-power, high-speed CMOS EPROM technology

• Fully static design

• Wide operating voltage range: 3.0V to 6.0V

• Commercial, Industrial and Automotive temperature ranges

• Low power consumption

- < 2.0 mA @ 5.0V, 4.0 MHz

- 15 µ A typical @ 3.0V, 32 kHz

- < 1.0 µ A typical standby current @ 3.0V

40 39

38 37 36

PIC16C66X

35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT V

VSS RD7/PSP7

RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7 RC6 RC5 RC4 RD3/PSP3 RD2/PSP2

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 1



PIC16C64X & PIC16C66X

Pin Diagrams (Cont.’d)

TQFP

RC6

RC5

RC4

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3

36 3435

PIC16C66X

1819 20 212212 131415

1617

RC7 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7

VDD

RB0/INT

RB1

RB2

RB3

44 434241 40 39

1 2 3 4 5

6 7 8 9 10

RC2

RC1

33 32 31 30 29 28 27 26 25 24 23

NC RC0 OSC2/CLKOUT OSC1/CLKIN

V VDD RE2/CS RE1/WR RE0/RD RA5 RA4/T0CKI

RA4/T0CKI

RA5

RE0/RD

RE1/WR

RE2/CS

VDD VSS

OSC1/CLKIN

OSC2/CLKOUT

RC0

RB7

RB6

RB5

RB4

RA3/AN3

RA2/AN2/VREF

RA1/AN1

654321 7 8 9 10

11 12

PIC16C66X

13 14 15

16 17

181920212223242526

RD0/PSP0

RC3

RC2

RC1

RA1/AN1

RA0/AN0

MCLR

/VPP

PLCC

/VPP

RA0/AN0

MCLR

RB7

RC4

RD3/PSP3

RD2/PSP2

RD1/PSP1

RA3/AN3

RA2/AN2/V

REF

RB6

RB5

RB4

40414243

39 38 37 36 35 34 33 32 31 30 29

2728

RC6

RC5

RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7

DS30559A-page 2

Preliminary

1996 Microchip Technology Inc.



PIC16C64X & PIC16C66X

1.0 General Description..........................................................................................................................................5

2.0 PIC16C64X & PIC16C66X Device Varieties ....................................................................................................7

3.0 Architectural Overview...................................................................................................................................... 9

4.0 Memory Organization .....................................................................................................................................17

5.0 I/O Ports..........................................................................................................................................................29

6.0 Timer0 Module................................................................................................................................................ 41

7.0 Comparator Module........................................................................................................................................47

8.0 Voltage Reference Module.............................................................................................................................53

9.0 Special Features of the CPU..........................................................................................................................55

10.0 Instruction Set Summary ................................................................................................................................73

11.0 Development Support.....................................................................................................................................87

12.0 Electrical Specifications..................................................................................................................................91

13.0 Device Characterization Information.............................................................................................................103

14.0 Packaging Information..................................................................................................................................105

Appendix A: Enhancements......................................................................................................................................115

Appendix B: Compatibility.........................................................................................................................................115

Appendix C: What’s New ..........................................................................................................................................116

Appendix D: What’s Changed...................................................................................................................................116

Appendix E: PIC16/17 Microcontrollers .....................................................................................................................117

Pin Compatibility .........................................................................................................................................................125

Index ...........................................................................................................................................................................127

List of Examples.......................................................................................................................................................... 129

List of Figures..............................................................................................................................................................129

List of Tables...............................................................................................................................................................130

On-Line Support..........................................................................................................................................................131

Reader Response.......................................................................................................................................................132

PIC16C64X & PIC16C66X Product Identification System..........................................................................................135

To Our Valued Customers

We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you ﬁnd any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document.

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 3



PIC16C64X & PIC16C66X

NOTES:

DS30559A-page 4

Preliminary

1996 Microchip Technology Inc.



PIC16C64X & PIC16C66X

1.0 GENERAL DESCRIPTION

PIC16C64X & PIC16C66X devices are 28-pin and 40-pin EPROM-based members of the versatile PIC16CXXX family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers.

All PIC16/17 microcontrollers employ an advanced RISC architecture. The PIC16CXXX family has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two-stage instruction pipeline allows all instructions to execute in a single-cycle, except for program branches (which require two cycles). A total of 35 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance.

PIC16CXXX microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in its class.

The PIC16C641 has 128 bytes of RAM and the PIC16C642 has 176 bytes of RAM. Both devices have 22 I/O pins, and an 8-bit timer/counter with an 8-bit programmable prescaler. In addition, they have two analog comparators with a programmable on-chip voltage reference module. Program Memory has internal parity error detection circuitry with a Parity Error Reset. The comparator module is ideally suited for applications requiring a low-cost analog interface (e.g., battery chargers, threshold detectors, white goods controllers, etc.).

The PIC16C661 has 128 bytes of RAM and the PIC16C662 has 176 bytes of RAM. Both devices have 33 I/O pins, and an 8-bit timer/counter with an 8-bit programmable prescaler. They also have an 8-bit Parallel Slave Port. In addition, the devices have two analog comparators with a programmable on-chip voltage reference module. Program Memory has internal parity error detection circuitry with a Parity Error Reset. The comparator module is ideally suited for applications requiring a low-cost analog interface (e.g., battery chargers, threshold detectors, white goods controllers, etc.).

PIC16CXXX devices have special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) mode offers power saving. The user can wake-up the chip from SLEEP through several external and internal interrupts and resets.

A highly reliable Watchdog Timer (WDT) with its own on-chip RC oscillator provides protection against software lock-up.

A UV-erasable CERDIP-packaged version is ideal for code development while the cost-effective One-Time Programmable (OTP) version is suitable for production in any volume.

The PIC16CXXX series ﬁt perfectly in applications ranging from battery chargers to low-power remote sensors. The EPROM technology makes customization of application programs (detection levels, pulse generation, timers, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low-cost, low-power, high-performance, ease of use, and I/O ﬂexibility make the PIC16C64X & PIC16C66X very versatile.

1.1 F

Those users familiar with the PIC16C5X family of microcontrollers will realize that this is an enhanced version of the PIC16C5X architecture. Please refer to Appendix A for a detailed list of enhancements. Code written for PIC16C5X can be easily ported to the PIC16C64X & PIC16C66X (Appendix B).

1.2 De

PIC16C64X & PIC16C66X devices are supported by the complete line of Microchip Development tools, including:

• MPLAB Integrated Development Environment including MPLAB-Simulator.

• MPASM Universal Assembler and MPLAB-C Universal C compiler.

• PRO MATE II and PICSTART Plus device programmers.

• PICMASTER In-circuit Emulator System

•

fuzzy

• DriveWay Visual Programming Tool

Please refer to Section 11.0 for more details about these and other Microchip development tools.

amily and Upward Compatibility

velopment Support

TECH-MP Fuzzy Logic Development Tools

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 5



PIC16C64X & PIC16C66X

TABLE 1-1: PIC16C64X & PIC16C66X DEVICE FEATURES

Packages

Clock Memory Peripherals Features

Brown-out Reset

Voltage Range (Volts)

I/O Pins

Interrupt Sources

Parallel Slave Port

Internal Reference Voltage

Comparator(s)

Timer Module(s)

Program Memory

Data Memory (bytes)

EPROM

Maximum Frequency of Operation (MHz)

40-pin PDIP, Windowed CDIP;

44-pin PLCC, TQFP

40-pin PDIP, Windowed CDIP;

44-pin PLCC, TQFP

20 2K 128 TMR0 2 Yes - 4 22 3.0-6.0 Yes 28-pin PDIP, SOIC, Windowed CDIP

20 4K 176 TMR0 2 Yes - 4 22 3.0-6.0 Yes 28-pin PDIP, SOIC, Windowed CDIP

20 2K 128 TMR0 2 Yes Yes 5 33 3.0-6.0 Yes

DS30559A-page 6

PIC16C641

PIC16C642

Preliminary

PIC16C661

PIC16C662 20 4K 176 TMR0 2 Yes Yes 5 33 3.0-6.0 Yes

All PIC16/17 Family devices have Power-on Reset, selectable Watchdog T imer, selectable code protect, and high I/O current

capability.

All PIC16CXXX Family devices use serial programming with clock pin RB6 and data pin RB7.

1996 Microchip Technology Inc.



PIC16C64X & PIC16C66X

2.0 PIC16C64X & PIC16C66X DEVICE V ARIETIES

A variety of frequency ranges and packaging options are available. Depending on application and production requirements the proper device option can be selected using the information in the Product Identiﬁcation System page at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number.

2.1 UV Erasab

The UV erasable version, offered in CERDIP package is optimal for prototype development and pilot programs. This version can be erased and reprogrammed to any of the oscillator modes.

Microchip's PICSTART programmers both support programming of the PIC16C64X & PIC16C66X.

2.2 One-Time-Pr Devices

The availability of OTP devices is especially useful for customers who need ﬂexibility for frequent code updates and small volume applications. In addition to the program memory, the conﬁguration bits must also be programmed.

le Devices



Plus and PRO MATE

ogrammable (OTP)



2.3 Quic

k-Turnaround-Production (QTP)

Devices

Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and conﬁguration options already programmed by the factory. Certain code and prototype veriﬁcation procedures apply before production shipments are available. Please contact your Microchip Technology sales ofﬁce for more details.

2.4 Serializ Production (SQTP

Microchip offers a unique programming service where a few user-deﬁned locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential.

Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number.

ed Quick-Turnaround-

vices

) De

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 7



PIC16C64X & PIC16C66X

NOTES:

DS30559A-page 8

Preliminary

1996 Microchip Technology Inc.



PIC16C64X & PIC16C66X

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC16C64X & PIC16C66X devices can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16C64X & PIC16C66X use a Harvard architecture in which program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched from the same memory. Separating program and data memory further allows instructions to be sized differently than an 8-bit wide data word. Instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (35) execute in a single cycle (200 ns @ 20 MHz) except for program branches, which require two cycles.

The PIC16C641 and PIC16C661 both address 2K x 14 on-chip program memory while the PIC16C642 and PIC16C662 address 4K x 14. All program memory is internal.

PIC16C64X & PIC16C66X devices can directly or indirectly address their register ﬁles or data memory. All special function registers including the program counter are mapped in the data memory. These devices have an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC16C64X & PIC16C66X simple yet efﬁcient. In addition, the learning curve is reduced signiﬁcantly.

PIC16C64X & PIC16C66X devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register ﬁle.

The ALU is 8-bits wide and capable of addition, subtraction, shift, and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a ﬁle register or an immediate constant. In single operand instructions, the operand is either the W register or a ﬁle register.

The W register is an 8-bit working register used for ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a Bo respectively, bit in subtraction. See the SUBLW and

SUBWF instructions for examples.

rrow and Digit Borrow out bit,

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 9



PIC16C64X & PIC16C66X

FIGURE 3-1: PIC16C641/642 BLOCK DIAGRAM

PIC16C641 has 2K x 14 Program Memory and 128 x 8 RAM PIC16C642 has 4K x 14 Program Memory and 176 x 8 RAM

Program

Bus

OSC1/CLKIN OSC2/CLKOUT

EPROM

Program

Memory

Instruction reg

Instruction

Decode &

Control

Timing

Generation

Program Counter

8 Level Stack

Direct Addr

Power-up

Oscillator

Start-up Timer

Power-on

Watchdog

Brown-out

Parity Error

MCLR

(13-bit)

Timer

Reset

Timer

Reset

VDD, VSS

RAM Bank

Select

Data Bus

RAM

File

Registers

Addr MUX

STATUS reg

ALU

W reg

FSR reg

MUX

Indirect

Addr

Voltage

Reference

Comparator

Timer0

PORTA

PORTB

RA0/AN0 RA1/AN1 RA2/AN2/VREF RA3/AN3

RA4/T0CKI

RA5

RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7

DS30559A-page 10

Preliminary

PORTC

RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7

1996 Microchip Technology Inc.



PIC16C64X & PIC16C66X

FIGURE 3-2: PIC16C661/662 BLOCK DIAGRAM

PIC16C661 has 2K x 14 Program Memory and 128 x 8 RAM PIC16C662 has 4K x 14 Program Memory and 176 x 8 RAM

Program

Bus

OSC1/CLKIN OSC2/CLKOUT

EPROM

Program

Memory

Instruction reg

Instruction Decode &

Control

Timing

Generation

Program Counter

8 Level Stack

Direct Addr

Power-up

Oscillator

Start-up Timer

Power-on

Watchdog

Brown-out

Parity Error

MCLR

(13-bit)

Timer

Reset

Timer

Reset

VDD, VSS

RAM Bank

Select

RE0/RD

Data Bus

RAM

File

Registers

Addr MUX

STATUS reg

ALU

W reg

FSR reg

MUX

Parallel

Slave

Port

PORTE

Indirect

Addr

Voltage

Reference

Comparator

Timer0

PORTA

PORTB

PORTC

RA0/AN0 RA1/AN1 RA2/AN2/VREF RA3/AN3

RA4/T0CKI

RA5

RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7

RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7

1996 Microchip Technology Inc.

RE1/WR

RE2/CS

Preliminary

PORTD

RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7

DS30559A-page 11



PIC16C64X & PIC16C66X

TABLE 3-1: PIC16C641/642 PINOUT DESCRIPTION

Name Pin #

I/O/P Type

Buffer

Type

Description

OSC1/CLKIN 9 I ST/CMOS Oscillator crystal input or external clock source input. OSC2/CLKOUT 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal

oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.

MCLR

1 I/P ST Master clear (reset) input or programming voltage input. This pin is

an active low reset to the device.

PORTA is a bi-directional I/O port. RA0/AN0 2 I/O ST Analog comparator input. RA1/AN1 3 I/O ST Analog comparator input. RA2/AN2/V

REF

4 I/O ST Analog comparator input or V

REF

output. RA3/AN3 5 I/O ST Analog comparator input or comparator output. RA4/T0CKI 6 I/O ST Can be selected to be the clock input to the Timer0 timer/counter

or a comparator output. Output is open drain type.

RA5 7 I/O ST

PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

RB0/INT 21 I/O

TTL/ST

(1)

RB0 can also be selected as an external interrupt pin.

RB1 22 I/O TTL RB2 23 I/O TTL RB3 24 I/O TTL RB4 25 I/O TTL Interrupt on change pin. RB5 26 I/O TTL Interrupt on change pin. RB6 27 I/O

RB7 28 I/O

TTL/ST TTL/ST

(2) (2)

Interrupt on change pin. Serial programming clock. Interrupt on change pin. Serial programming data.

PORTC is a bi-directional I/O port. RC0 11 I/O ST RC1 12 I/O ST RC2 13 I/O ST RC3 14 I/O ST RC4 15 I/O ST RC5 16 I/O ST RC6 17 I/O ST RC7 18 I/O ST V

8,19 P — Ground reference for logic and I/O pins.

20 P — Positive supply for logic and I/O pins.

Legend: O = output I/O = input/output P = power

I = input — = not used ST = Schmitt Trigger input TTL = TTL input

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

DS30559A-page 12

Preliminary

1996 Microchip Technology Inc.



PIC16C64X & PIC16C66X

TABLE 3-2: PIC16C661/662 PINOUT DESCRIPTION

Name

OSC1/CLKIN 13 30 14 I ST/CMOS Oscillator crystal input or external clock source

OSC2/CLKOUT 14 31 15 O — Oscillator crystal output. Connects to crystal or reso-

MCLR

RA0/AN0 2 19 3 I/O ST Analog comparator input. RA1/AN1 3 20 4 I/O ST Analog comparator input. RA2/AN2/V RA3/AN3 5 22 6 I/O ST Analog comparator input or comparator output. RA4/T0CKI 6 23 7 I/O ST Can be selected to be the clock input to the

RA5 7 24 8 I/O ST

RB0/INT 33 8 36 I/O

RB1 34 9 37 I/O TTL RB2 35 10 38 I/O TTL RB3 36 11 39 I/O TTL RB4 37 14 41 I/O TTL Interrupt on change pin. RB5 38 15 42 I/O TTL Interrupt on change pin. RB6 39 16 43 I/O

RB7 40 17 44 I/O

RC0 15 32 16 I/O ST RC1 16 35 18 I/O ST RC2 17 36 19 I/O ST RC3 18 37 20 I/O ST RC4 23 42 25 I/O ST RC5 24 43 26 I/O ST RC6 25 44 27 I/O ST RC7 26 1 29 I/O ST Legend: O = output I/O = input/output P = power

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when conﬁgured as a general purpose I/O and a TTL input when used

in the Parallel Slave Port Mode (for interfacing to a microprocessor port).

DIP Pin #

REF

QFP Pin #

1 18 2 I/P ST Master clear (reset) input or programming voltage

4 21 5 I/O ST Analog comparator input or V

I = input — = not used ST = Schmitt Trigger input TTL = TTL input

PLCC Pin #

I/O/P Type

Buffer

Type

TTL/ST

Description

input.

nator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.

input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port.

output.

REF

Timer0 timer/counter or a comparator output. Output is open drain type.

PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

(1)

(2)

RB0 can also be selected as an external interrupt pin.

Interrupt on change pin. Serial programming clock.

Interrupt on change pin. Serial programming data.

PORTC is a bi-directional I/O port.

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 13



PIC16C64X & PIC16C66X

Name

DIP Pin #

QFP Pin #

PLCC Pin #

I/O/P Type

Buffer

Type

Description

PORTD can be a bi-directional I/O port or parallel

slave port for interfacing to a microprocessor bus. RD0/PSP0 19 38 21 I/O ST/TTL RD1/PSP1 20 39 22 I/O ST/TTL RD2/PSP2 21 40 23 I/O ST/TTL RD3/PSP3 22 41 24 I/O ST/TTL RD4/PSP4 27 2 30 I/O ST/TTL RD5/PSP5 28 3 31 I/O ST/TTL RD6/PSP6 29 4 32 I/O ST/TTL RD7/PSP7 30 5 33 I/O ST/TTL

(3) (3) (3) (3) (3) (3) (3) (3)

PORTE is a bi-directional I/O port. RE0/RD RE1/WR RE2/CS V

8 25 9 I/O ST/TTL 9 26 10 I/O ST/TTL

10 27 11 I/O ST/TTL 12,31 6,29 13,34 P — Ground reference for logic and I/O pins. 11,32 7,28 12,35 P — Positive supply for logic and I/O pins.

NC — 12,13,

33,34

1,17

28,40

— — Not Connected.

(3) (3) (3)

RE0/RD

read control for parallel slave port. RE1/WR write control for parallel slave port. RE2/CS

select control for parallel slave port.

Legend: O = output I/O = input/output P = power

I = input — = not used ST = Schmitt Trigger input TTL = TTL input

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when conﬁgured as a general purpose I/O and a TTL input when used

in the Parallel Slave Port Mode (for interfacing to a microprocessor port).

DS30559A-page 14

Preliminary

1996 Microchip Technology Inc.



PIC16C64X & PIC16C66X

3.1 Cloc

king Scheme/Instruction Cycle

The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3, and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution ﬂow is shown in Figure 3-3.

FIGURE 3-3: CLOCK/INSTRUCTION CYCLE

Q2 Q3 Q4

OSC1

Q1 Q2 Q3

Q4 PC

OSC2/CLKOUT

(RC mode)

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

3.2 Instruction Flo

w/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3, and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO ) then two cycles are required to complete the instruction (Example 3-1).

A fetch cycle begins with the program counter (PC) incrementing in Q1.

In the execution cycle, the fetched instruction is latched into the “Instruction Register (IR)” in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).

Q2 Q3 Q4

Execute INST (PC) Fetch INST (PC+2)

Q2 Q3 Q4

Execute INST (PC+1)

Internal phase clock

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Tcy0 Tcy1 Tcy2 Tcy3 Tcy4 Tcy5

1. MOVLW 55h

2. MOVWF PORTB

3. CALL SUB_1

4. BSF PORTA, BIT3 (Forced NOP)

5. Instruction @ address SUB_1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “ﬂushed” from the pipeline while the new instruction is being fetched and then executed.

1996 Microchip Technology Inc.

Fetch 1 Execute 1

Fetch 2 Execute 2

Preliminary

Fetch 3 Execute 3

Fetch 4 Flush

Fetch SUB_1 Execute SUB_1

DS30559A-page 15

PIC16C64X & PIC16C66X

NOTES:



DS30559A-page 16

Preliminary

1996 Microchip Technology Inc.



PIC16C64X & PIC16C66X

4.0 MEMORY ORGANIZATION

4.1 Pr

The PIC16C64X & PIC16C66X have a 13-bit program counter capable of addressing an 8K x 14 program memory space. For the PIC16C641 and PIC16C661 only the ﬁrst 2K x 14 (0000h - 07FFh) is physically implemented. For the PIC16C642 and PIC16C662 only the ﬁrst 4K x 14 (0000h - 0FFh) is physically implemented. Accessing a location above the 2K or 4K boundary will cause a wrap-around. The reset vector is at 0000h and the interrupt vector is at 0004h (Figure 41 and Figure 4-2). See Section 4.4 for Program Memory paging.

FIGURE 4-1: PIC16C641/661 PROGRAM

CALL, RETURN RETFIE, RETLW

ogram Memory Organization

MEMORY MAP AND STACK

PC<12:0>

Stack Level 1

Stack Level 2

Stack Level 8

Reset Vector

0000h

FIGURE 4-2: PIC16C642/662 PROGRAM

MEMORY MAP AND STACK

PC<12:0>

CALL, RETURN RETFIE, RETLW

Stack Level 1

Stack Level 2

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

Page0

User Memory Space

On-chip Program

Memory

Page1

0000h

0004h 0005h

07FFh 0800h

0FFFh 1000h

Interrupt Vector

User Memory Space

On-chip Program

Memory

TEST

Conﬁguration Word

TEST

0004h 0005h

07FFh 0800h

1FFFh 2000h

2007h

3FFFh

TEST

Conﬁguration Word

TEST

1FFFh 2000h

2007h

3FFFh

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 17



PIC16C64X & PIC16C66X

4.2 D

The data memory (Figure 4-4) is partitioned into two banks which contain the general purpose registers and the special function registers. Bank 0 is selected when bit RP0 (STATUS<5>) is cleared. Bank 1 is selected when the RP0 bit is set. The Special Function Registers are located in the ﬁrst 32 locations of each Bank. Register locations A0h-EFh (Bank 1) are general purpose registers implemented as static RAM. Some special function registers are mapped in Bank 1.

4.2.1 GENERAL PURPOSE REGISTER FILE The register ﬁle is organized as 176 x 8 for the

PIC16C642/662, and 128 x8 for the PIC16C641/661. Each is accessed either directly, or indirectly through the File Select Register FSR (Section 4.5).

ata Memory Organization

FIGURE 4-3: PIC16C641/661 DATA

MEMORY MAP

File

Address

00h 01h 02h 03h 04h 05h 06h 07h 08h

09h 0Ah 0Bh 0Ch 0Dh 0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h 1Ah 1Bh 1Ch 1Dh 1Eh

1Fh

20h

INDF

TMR0

PCL

STATUS

FSR PORTA PORTB

PORTC

PORTD

PORTE

PCLATH INTCON

PIR1

CMCON

General Purpose Register

(1)

(2) (2)

INDF

OPTION

PCL

STATUS

FSR TRISA TRISB TRISC

TRISD TRISE

PCLATH INTCON

PIE1

PCON

VRCON

General Purpose Register

(1)

(2) (2)

File

Address

80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh

A0h

BFh C0h

DS30559A-page 18

Preliminary

Mapped

7Fh

Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

2: Not implemented on the PIC16C641.

Bank 0 Bank 1

in Page 0

1996 Microchip Technology Inc.

EFh

F0h

FFh



PIC16C64X & PIC16C66X

FIGURE 4-4: PIC16C642/662 DATA

MEMORY MAP

File

Address

00h 01h 02h 03h 04h 05h 06h 07h 08h

09h 0Ah 0Bh 0Ch 0Dh 0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h 1Ah 1Bh 1Ch 1Dh 1Eh

1Fh

20h

(1)

INDF

TMR0

PCL

STATUS

FSR

PORTA PORTB PORTC TRISC

PORTD

PORTE

(2) (2)

PCLATH INTCON

PIR1

CMCON

(1)

INDF

OPTION

PCL

STATUS

FSR TRISA TRISB

TRISD TRISE

PCLATH INTCON

PIE1

PCON

VRCON

(2) (2)

File

Address

80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh

A0h

4.2.2 SPECIAL FUNCTION REGISTERS The special function registers are registers used by the

CPU and Peripheral Modules for controlling the desired operation of the device (T able 4-1). These registers are static RAM.

The special function registers can be classiﬁed into two sets (core and peripheral). The special function registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature.

General Purpose Register

in Bank 0

7Fh

Note 1: Not a physical register.

1996 Microchip Technology Inc.

Bank 0 Bank 1

Unimplemented data memory loca-

tions, read as '0'.

2: Not implemented on the PIC16C642.

General Purpose Register

Mapped

EFh F0h

FFh

Preliminary

DS30559A-page 19



PIC16C64X & PIC16C66X

TABLE 4-1: SPECIAL FUNCTION REGISTERS

Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bank 0

00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 01h TMR0 Timer0 Module’s Register 02h PCL Program Counter's (PC) Least Signiﬁcant Byte 03h STATUS IRP 04h FSR Indirect data memory address pointer 05h PORTA 06h PORTB PORTB Data Latch when written: PORTB pins when read 06h PORTC PORTC Data Latch when written: PORTC pins when read 06h PORTD 06h PORTE 0Ah PCLATH 0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0Ch PIR1 PSPIF 0Dh-1Eh 1Fh CMCON C2OUT C1OUT

Bank 1

80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 81h OPTION RBPU 82h PCL Program Counter's (PC) Least Signiﬁcant Byte 83h STATUS IRP 84h FSR Indirect data memory address pointer 85h TRISA 86h TRISB PORTB Data Direction Register 86h TRISC PORTC Data Direction Register 86h TRISD 86h TRISE 8Ah PCLATH 8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x 8Ch PIE1 PSPIE 8Dh 8Eh PCON MPEEN 8Fh-9Eh 9Fh VRCON VREN VROE VRR

Legend: - = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented

Note 1: Other (non power-up) resets include MCLR

2: The IRP and RP1 bits are reserved, always maintain these bits clear. 3: The PORTD, PORTE, TRISD, and TRISE registers are not implemented on the PIC16C641/642. 4: Bits PSPIE and PSPIF are reserved on the PIC16C641/642, always maintain these bits clear.

(3) (3)

Unimplemented

(3)

Unimplemented

(2)

— — PORTA Data Latch when written: PORTA pins when read

PORTD Data Latch when written: PORTD pins when read

— — — — Write buffer for upper 5 bits of program counter

(4)

(2)

— — PORTA Data Direction Register

PORTD Data Direction Register

IBF OBF IBOV PSPMODE

— — — Write buffer for upper 5 bits of program counter

(4)

(2)

RP1

— — — — RE2 RE1 RE0 ---- -xxx ---- -uuu

CMIF

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

RP1

CMIE

— — — — PER POR BOR

RP0 T

— — — — — — 00-- ---- 00-- ----

— — CIS CM2 CM1 CM0 00-- 0000 00-- 0000

(2)

RP0 TO PD ZDCC

— — — — — — 00-- ---- 00-- ----

Reset and Watchdog Timer Reset during normal operation.

O PD ZDCC

— TRISE2 TRISE1 TRISE0 0000 -111 0000 -111

— VR3 VR2 VR1 VR0 000- 0000 000- 0000

POR, BOR,

PER

xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu

--xx 0000 --xu 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

---0 0000 ---0 0000 0000 000x 0000 000u

—

0000 0000 0000 0000 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu

--11 1111 --11 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111

---0 0000 ---0 0000

—

u--- -qqq u--- -uuu

—

Value on

all other

resets

—

(1)

DS30559A-page 20

Preliminary

1996 Microchip Technology Inc.



PIC16C64X & PIC16C66X

4.2.2.1 STATUS REGISTER The STATUS register, shown in Figure 4-5, contains

the arithmetic status of the ALU, the RESET status, and the bank select bits for data memory.

The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the T writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000uu1uu (where u = unchanged).

O and PD bits are not

It is recommended, therefore, that only BCF, BSF,

SWAPF, and MOVWF instructions are used to alter the

STATUS register because these instructions do not affect any status bit. For other instructions, not affecting any status bits, see the “Instruction Set Summary.”

Note 1: The IRP and RP1 bits (ST A TUS<7:6>) are

reserved on the PIC16C64X & PIC16C66X and should be maintained clear. Use of these bits as general purpose R/W bits is NOT recommended, since this may affect upward compatibility with future products.

Note 2: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

FIGURE 4-5: STATUS REGISTER (ADDRESS 03h, 83h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD Z DC C R = Readable bit

bit7 bit0

bit 7: IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) Bit IRP is reserved on the PIC16C64X & PIC16C66X, always maintain this bit clear.

bit 6-5: RP1:RP0 : Register Bank Select bits (used for direct addressing)

= Bank 3 (180h - 1FFh) = Bank 2 (100h - 17Fh) = Bank 1 (80h - FFh)

= Bank 0 (00h - 7Fh) Each bank is 128 bytes. Bit RP1 is reserved on the PIC16C64X & PIC16C66X, always maintain this bit clear.

bit 4: T

bit 3: PD

bit 2: Z: Zero bit

bit 1: DC: Digit carry/borrow

bit 0: C: Carry/borrow

: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred

: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

bit (ADDWF , ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result

bit (ADDWF , ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most signiﬁcant bit of the result occurred 0 = No carry-out from the most signiﬁcant bit of the result occurred Note: For borrow second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.

the polarity is reversed. A subtraction is executed by adding the two’s complement of the

W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 21

PIC16C64X & PIC16C66X

4.2.2.2 OPTION REGISTER The OPTION register is a readable and writable

register which contains various control bits to conﬁgure the TMR0/WDT prescaler, the external RB0/INT interrupt, TMR0, and the weak pull-ups on PORTB.

FIGURE 4-6: OPTION REGISTER (ADDRESS 81h)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU

bit7 bit0

bit 7: RBPU

bit 6: INTEDG: Interrupt Edge Select bit

bit 5: T0CS: TMR0 Clock Source Select bit

bit 4: T0SE: TMR0 Source Edge Select bit

bit 3: PSA: Prescaler Assignment bit

bit 2-0: PS2:PS0: Prescaler Rate Select bits

INTEDG T0CS T0SE PSA PS2 PS1 PS0 R= Readable bit

: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values

1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin

1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT)

1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin

1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

Bit Value TMR0 Rate WDT Rate

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Note: To achieve a 1:1 prescaler assignment for

TMR0, assign the prescaler to the WDT.

W= Writable bit U= Unimplemented bit, read as ‘0’

- n= Value at POR reset

DS30559A-page 22 Preliminary  1996 Microchip Technology Inc.

PIC16C64X & PIC16C66X

4.2.2.3 INTCON REGISTER The INTCON register is a readable and writable

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).

FIGURE 4-7: INTCON REGISTER (ADDRESS 0Bh, 8Bh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R= Readable bit

bit7 bit0

bit 7: GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts 0 = Disables all interrupts

bit 6: PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts

bit 5: T0IE: TMR0 Overﬂow Interrupt Enable bit

1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt

bit 4: INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt

bit 3: RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt

bit 2: T0IF: TMR0 Overﬂow Interrupt Flag bit

1 = TMR0 register overﬂowed (must be cleared in software) 0 = TMR0 register did not overﬂow

bit 1: INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur

bit 0: RBIF: RB Port Change Interrupt Flag bit

1 = When at least one of the RB7:RB4 pins changed state (See Section 5.2 to clear interrupt) 0 = None of the RB7:RB4 pins have changed state

W= Writable bit U= Unimplemented bit, read as ‘0’

- n= Value at POR reset

 1996 Microchip Technology Inc. Preliminary DS30559A-page 23

PIC16C64X & PIC16C66X

4.2.2.4 PIE1 REGISTER This register contains the individual enable bits for the

comparator and Parallel Slave Port interrupts.

FIGURE 4-8: PIE1 REGISTER (ADDRESS 8Ch)

R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

(1)

PSPIE

bit7 bit0

bit 7: PSPIE

bit 6: CMIE: Comparator Interrupt Enable bit

bit 5-0: Unimplemented: Read as '0'

CMIE — — — — — — R= Readable bit

(1)

: Parallel Slave Port Read/Write Interrupt Enable bit

1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt

1 = Enables the Comparator interrupt 0 = Disables the Comparator interrupt

W= Writable bit U= Unimplemented bit, read as ‘0’

- n= Value at POR reset

Note 1: Bit PSPIE is reserved on the PIC16C641/642, always maintain this bit clear.

DS30559A-page 24 Preliminary  1996 Microchip Technology Inc.

PIC16C64X & PIC16C66X

4.2.2.5 PIR1 REGISTER This register contains the individual ﬂag bits for the

comparator and Parallel Slave Port interrupts.

Note: Interrupt ﬂag bits get set when an interrupt

FIGURE 4-9: PIR1 REGISTER (ADDRESS 0Ch)

R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

(1)

PSPIF

bit7 bit0

bit 7: PSPIF

bit 6: CMIF: Comparator Interrupt Flag bit

bit 5-0: Unimplemented: Read as '0'

CMIF — — — — — — R= Readable bit

(1)

: Parallel Slave Port Interrupt Flag bit

1 = A read or write operation has taken place (must be cleared in software) 0 = No read or write operation has taken place

1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed

condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt ﬂag bits are clear prior to enabling an interrupt.

W= Writable bit U= Unimplemented bit, read as ‘0’

- n= Value at POR reset

Note 1: Bit PSPIF is reserved on the PIC16C641/642, always maintain this bit clear.

 1996 Microchip Technology Inc. Preliminary DS30559A-page 25

PIC16C64X & PIC16C66X

4.2.2.6 PCON REGISTER The PCON register contains ﬂag bits to differentiate

between a Power-on Reset (POR), an external MCLR reset, WDT reset, Brown-out Reset (BOR), and Parity Error Reset (PER). The PCON register also contains a status bit, MPEEN, which reﬂects the value of the MPEEN bit in Conﬁguration Word. See Table 9-4 for status of these bits on various resets.

Note: BOR is unknown on Power-on Reset. It

FIGURE 4-10: PCON REGISTER (ADDRESS 8Eh)

R-U U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-u MPEEN bit7 bit0

bit 7: MPEEN: Memory Parity Error Circuitry Status bit

bit 6-3: Unimplemented: Read as '0' bit 2: PER

bit 1: POR

bit 0: BOR

— — — —PER POR BOR R= Readable bit

Reﬂects the value of Conﬁguration Word bit, MPEEN

: Memory Parity Error Reset Status bit 1 = No error occurred 0 = Program memory fetch parity error occurred (must be set in software after a Parity Error Reset occurs)

: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

must then be set by the user and checked on subsequent resets to see if BOR cleared, indicating a brown-out has occurred. The BOR care” and is not necessarily predictable if the brown-out circuit is disabled (by programming the BODEN bit in the Conﬁguration word).

W= Writable bit U= Unimplemented bit, read as ‘0’

- n= Value at POR reset

status bit is a “don't

DS30559A-page 26 Preliminary  1996 Microchip Technology Inc.

PIC16C64X & PIC16C66X

4.3 PCL and PCLATH

The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is readable and writable. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any reset, the PC is cleared. Figure 4-11 shows the two situations for the loading of the PC. The upper example in the ﬁgure shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH). The lower example in the ﬁgure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> → PCH).

FIGURE 4-11: LOADING OF PC IN

DIFFERENT SITUATIONS

PCH PCL

12 8 7 0

PCLATH<4:0>

PCLATH

PCH PCL

12 11 10 0

PCLATH<4:3>

PCLATH

4.3.1 COMPUTED GOTO A computed GOTO is accomplished by adding an

offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note

“Implementing a Table Read”

(AN556).

Instruction with PCL as Destination

ALU result

GOTO, CALL

Opcode <10:0>

4.3.2 STACK PIC16C64X & PIC16C66X devices have an 8 level

deep x 13-bit wide hardware stack (Figure 4-2). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the ﬁrst push. The tenth push overwrites the second push (and so on).

Note 1: There are no status bits to indicate stack

overﬂow or stack underﬂow conditions.

Note 2: There are no instructions mnemonics

called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt address.

4.4 Program Memory Paging

PIC16C642 and PIC16C662 devices have 4K of program memory, but the CALL and GOTO instructions only have an 11-bit address range. This 11-bit address range allows a branch within a 2K program memory page size. To allow CALL and GOTO instructions to address the entire 4K program memory address range, there must be another bit to specify the program memory page. This paging bit comes from the PCLATH<3> bit (Figure 4-11). When doing a CALL or GOTO instruction, the user must ensure that this page select bit (PCLATH<3>) is programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<3> bit is not required for the return instructions (which POPs the address from the stack).

Note: The PIC16C64X & PIC16C66X ignore the

PCLATH<4> bit, which is used for program memory pages 2 and 3 (1000h - 1FFFh). The use of PCLATH<4> as a general purpose read/write bit is not recommended since this may affect upward compatibility with future products.

 1996 Microchip Technology Inc. Preliminary DS30559A-page 27

PIC16C64X & PIC16C66X

4.5 Indirect Addressing, INDF, and FSR Registers

The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the ﬁle select register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register indirectly results in a nooperation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-12. However, bit IRP is not used in the PIC16C64X & PIC16C66X.

FIGURE 4-12: DIRECT/INDIRECT ADDRESSING

(1)

RP1 RP0 6

bank select location select

from opcode

00h

00 01 10 11

A simple program to clear RAM location 20h-2Fh using indirect addressing is shown in Example 4-1.

EXAMPLE 4-1: INDIRECT ADDRESSING

movlw 0x20 ;initialize pointer movwf FSR ;to RAM NEXT clrf INDF ;clear INDF register incf FSR ;inc pointer btfss FSR,4 ;all done? goto NEXT ;no goto next ;yes continue CONTINUE:

Indirect AddressingDirect Addressing

(1)

IRP

bank select

00h

FSR register

location select

Data

not used

Memory

7Fh

Bank 0 Bank 1 Bank 2 Bank 3

For memory map detail see Figure 4-3 and Figure 4-4. Note 1: Bits RP1 and IRP are reserved, always maintain these bits clear.

7Fh

DS30559A-page 28 Preliminary  1996 Microchip Technology Inc.



PIC16C64X & PIC16C66X

5.0 I/O PORTS

The PIC16C641 and PIC16C642 have three ports, PORTA, PORTB, and PORTC. PIC16C661 and PIC16C662 devices have ﬁve ports, PORTA through PORTE. Some pins for these I/O ports are multiplexed with alternate functions for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.

5.1 POR

PORTA is a 6-bit wide latch. RA4 is a Schmitt Trigger input and an open drain output. Pin RA4 is multiplexed with the T0CKI clock input. All other RA port pins have Schmitt Trigger input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers) which can conﬁgure these pins as input or output.

Setting a bit in the TRISA register puts the corresponding output driver in a hi-impedance mode. Clearing a bit in the TRISA register puts the contents of the output latch on the selected pin.

Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modiﬁed, and then written to the port data latch.

The PORTA pins are multiplexed with comparator and voltage reference functions. The operation of these pins are selected by control bits in the CMCON (comparator control register) register and the VRCON (voltage reference control) register. When selected as comparator inputs, these pins will read as '0's.

TA and TRISA Registers

FIGURE 5-1: BLOCK DIAGRAM OF

RA1:RA0 PINS

Data bus

WR Port

Data Latch

WR TRIS

TRIS Latch

RD PORT

To Comparator

Note: I/O pins have protection diodes to VDD and VSS.

Note: On reset, the TRISA register is set to all

TRISA controls the direction of the RA pins, even when they are being used as comparator inputs. The user must make sure to keep the pins conﬁgured as inputs when using them as comparator inputs.

The RA2 pin will also function as the output for the voltage reference. When in this mode, the V a very hi-impedance output. The user must set the TRISA<2> bit and use hi-impedance loads.

In one of the comparator modes deﬁned by the CMCON register, pins RA3 and RA4 become outputs of the comparators. The TRISA<4:3> bits must be cleared to enable outputs to use this function.

VDD

Analog

Input Mode

Schmitt Trigger

RD TRIS

inputs. The digital inputs are disabled and the comparator inputs are forced to ground to reduce excess current consumption.

VSS

Input Buffer

I/O Pin

pin is

REF

1996 Microchip Technology Inc.

EXAMPLE 5-1: INITIALIZING PORTA

CLRF PORTA ;Initialize PORTA by ;clearing output latches MOVLW 0x07 ;Turn comparators off, MOVWF CMCON ;enable pins for I/O BSF STATUS, RP0 ;Select bank1 MOVLW 0x1F ;Value to initialize ;data direction MOVWF TRISA ;Set RA<4:0> as inputs ;TRISA<7:5> are clear

Preliminary

DS30559A-page 29



PIC16C64X & PIC16C66X

FIGURE 5-2: BLOCK DIAGRAM OF RA2 PIN

Data bus

WR Port

Data Latch

WR TRIS

TRIS Latch

RD TRIS

Analog

Input Mode

Schmitt Trigger

Input Buffer

VDD

VSS

RA2 Pin

RD PORT

To Comparator

VROE

VREF

Note: I/O pin has protection diodes to VDD and VSS.

FIGURE 5-3: BLOCK DIAGRAM OF RA3 PIN

Data bus

WR Port

WR TRIS

Data Latch

TRIS Latch

RD TRIS

Comparator Output

Comparator Mode = 110

Analog

Input Mode

Schmitt Trigger

Input Buffer

VDD P

VSS

RA3 Pin

RD PORT

To Comparator

DS30559A-page 30

Preliminary

1996 Microchip Technology Inc.



PIC16C64X & PIC16C66X

FIGURE 5-4: BLOCK DIAGRAM OF RA4 PIN

Data bus

WR Port

WR TRIS

Data Latch

TRIS Latch

RD TRIS

Comparator Output

Comparator Mode = 110

Schmitt Trigger

Input Buffer

VSS

RA4 Pin

RD PORT

TMR0 Clock Input

TABLE 5-1: PORTA FUNCTIONS

Name Bit #

RA0/AN0 bit0 ST Input/output or comparator input. RA1/AN1 bit1 ST Input/output or comparator input. RA2/AN2/V

REF

bit2 ST Input/output or comparator input or V RA3/AN3 bit3 ST Input/output or comparator input/output. RA4/T0CKI bit4 ST Input/output or external clock input for TMR0 or comparator output. Out-

RA5 bit5 ST Input/output. Legend: ST = Schmitt Trigger input

Buffer

Type

put is open drain type.

Function

REF

output.

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

05h PORTA 85h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 0000 00-- 0000 9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

— — RA5 RA4 RA3 RA2 RA1 RA0 --xx 0000 --uu 0000

POR,

BOR

Value on

all other

resets

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 31



PIC16C64X & PIC16C66X

5.2 POR

TB and TRISB Registers

PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a bit in the TRISB register puts the corresponding output driver in a hi-impedance mode. Clearing a bit in the TRISB register puts the contents of the output latch on the selected pin(s).

Reading PORTB register reads the status of the pins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modiﬁed, and then written to the port data latch.

Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is done by clearing the RBPU

(OPTION<7>) bit. The weak pull-up is automatically turned off when the port pin is conﬁgured as an output. The pull-ups are disabled on a Power-on Reset.

Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins conﬁgured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin conﬁgured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RBIF interrupt (ﬂag latched in (INTCON<0>)).

FIGURE 5-5: BLOCK DIAGRAM OF

RB7:RB4 PINS

TTL Input Buffer

VDD

weak pull-up

I/O pin

ST Buffer

(1)

RBPU

Data bus

WR Port

WR TRIS

(2)

Data Latch

TRIS Latch

This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear ﬂag bit RBIF. A mismatch condition will continue to set ﬂag bit RBIF.

Reading PORTB will end the mismatch condition, and allow ﬂag bit RBIF to be cleared.

This interrupt on mismatch feature, together with software conﬁgurable pull-ups on these four pins allow easy interface to a keypad and make it possible for wake-up on key-depression. (See AN552 in the Microchip

Embedded Control Handbook

The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.

FIGURE 5-6: BLOCK DIAGRAM OF

RB3:RB0 PINS

TTL Input Buffer

weak

pull-up

I/O pin

RD Port

(1)

RBPU

Data bus

WR Port

WR TRIS

RB0/INT

(2)

Data Latch

RD TRIS

RD Port

ST Buffer

RD TRIS

Set RBIF

From other RB7:RB4 pins

RB7:RB6 in serial programming mode

Note 1: I/O pins have diode protection to VDD and VSS.

2: TRISB = '1' enables weak pull-up if RBPU

(OPTION<7>).

DS30559A-page 32

RD Port

Latch

= '0'

RD Port

Preliminary

Note 1: I/O pins have diode protection to VDD and VSS.

2: TRISB = '1' enables weak pull-up if RBPU

(OPTION<7>).

1996 Microchip Technology Inc.

= '0'



PIC16C64X & PIC16C66X

EXAMPLE 5-2: INITIALIZING PORTB

CLRF PORTB ; Initialize PORTB by ; clearing output ; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISB ; Set RB<3:0> as inputs ; RB<5:4> as outputs ; RB<7:6> as inputs

TABLE 5-3: PORTB FUNCTIONS

Name Bit # Buffer Type Function

RB0/INT bit0

TTL/ST

RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable

RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable

RB6 bit6

RB7 bit7

TTL/ST

Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

(1)

Input/output or external interrupt input. Internal software programmable weak pull-up.

weak pull-up.

(2)

Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming clock pin.

(2)

Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming data pin.

TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111 81h OPTION RBPU Legend: x = unknown, u = unchanged, shaded cells are not used by PORTB.

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

POR,

BOR

Value on

all other

resets

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 33

PIC16C64X & PIC16C66X



5.3 POR

TC and TRISC Registers

PORTC is an 8-bit bi-directional port. Each pin is individually conﬁgurable as an input or output through the TRISC register. PORTC pins have Schmitt Trigger input buffers.

EXAMPLE 5-3: INITIALIZING PORTC

CLRF PORTC ; Initialize PORTC by ; clearing output ; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISC ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs

FIGURE 5-7: PORTC BLOCK DIAGRAM (IN

I/O PORT MODE)

Data bus

WR PORT

Data Latch

WR TRIS

TRIS Latch

RD PORT

Note 1: I/O pins have protection diodes to VDD and VSS.

RD TRIS

Schmitt Trigger input buffer

I/O pin

(1)

TABLE 5-5: PORTC FUNCTIONS

Name Bit# Buffer Type Function

RC0 RC1

bit0

ST Input/output

bit1 ST Input/output

RC2 bit2 ST Input/output RC3 bit3 ST Input/output RC4 bit4 ST Input/output RC5 bit5 ST Input/output

RC6 RC7

bit6 ST Input/output bit7 ST Input/output

Legend: ST = Schmitt Trigger input

TABLE 5-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged.

POR, BOR

Value on all

other resets

DS30559A-page 34

Preliminary

1996 Microchip Technology Inc.



PIC16C64X & PIC16C66X

5.4 POR

TD and TRISD Registers

(PIC16C661 and PIC16C662 only)

PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually conﬁgurable as an input or output.

PORTD can be conﬁgured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL.

FIGURE 5-8: PORTD BLOCK DIAGRAM (IN

I/O PORT MODE)

Data bus

WR PORT

WR TRIS

TRIS Latch

RD PORT

Note 1: I/O pins have protection diodes to VDD and VSS.

Data Latch

RD TRIS

Schmitt Trigger input buffer

I/O pin

(1)

TABLE 5-7: PORTD FUNCTIONS

Name Bit# Buffer Type Function

RD0/PSP0 bit0 ST/TTL RD1/PSP1 bit1 ST/TTL RD2/PSP2 bit2 ST/TTL RD3/PSP3 bit3 ST/TTL RD4/PSP4 bit4 ST/TTL RD5/PSP5 bit5 ST/TTL RD6/PSP6 bit6 ST/TTL RD7/PSP7 bit7 ST/TTL

(1) (1) (1) (1) (1) (1) (1) (1)

Input/output port pin or parallel slave port bit0 Input/output port pin or parallel slave port bit1 Input/output port pin or parallel slave port bit2 Input/output port pin or parallel slave port bit3 Input/output port pin or parallel slave port bit4 Input/output port pin or parallel slave port bit5 Input/output port pin or parallel slave port bit6 Input/output port pin or parallel slave port bit7

Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode.

TABLE 5-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu 88h TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111 89h TRISE

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD.

IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 0000 -111

POR,

BOR

Value on all

other resets

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 35

PIC16C64X & PIC16C66X

5.5 PORTE and TRISE Register

(PIC16C661 and PIC16C662 only)

PORTE has three pins RE0/RD, RE1/WR, and RE2/ CS

, which are individually conﬁgurable as inputs or

outputs. These pins have Schmitt Trigger input buf fers. I/O PORTE becomes control inputs for the micropro-

cessor port when bit PSPMODE (TRISE<4>) is set. In this mode, the user must make sure that the TRISE<2:0> bits are set (pins are conﬁgured as digital inputs). In this mode the input buffers are TTL.

Figure 5-9 shows the TRISE register, which also controls the parallel slave port operation.

FIGURE 5-9: TRISE REGISTER (ADDRESS 89h)

R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 R = Readable bit

bit7 bit0

bit 7: IBF: Input Buffer Full Status bit

1 = A word has been received and waiting to be read by the CPU 0 = No word has been received

bit 6: OBF: Output Buffer Full Status bit

1 = The output buffer still holds a previously written word 0 = The output buffer has been read

bit 5: IBOV: Input Buffer Overﬂow Detect bit (in microprocessor mode)

1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overﬂow occurred

bit 4: PSPMODE: Parallel Slave Port Mode Select bit

1 = Parallel slave port mode

0 = General purpose I/O mode bit 3: Unimplemented: Read as '0' bit 2: TRISE2: Direction control bit for pin RE2/CS

1 = Input

0 = Output bit 1: TRISE1: Direction control bit for pin RE1/WR

1 = Input

0 = Output bit 0: TRISE0: Direction control bit for pin RE0/RD

1 = Input

0 = Output

W = Writable bit U = Unimplemented bit,

- n = Value at POR reset

read as ‘0’

DS30559A-page 36 Preliminary  1996 Microchip Technology Inc.

PIC16C64X & PIC16C66X

FIGURE 5-10: PORTE BLOCK DIAGRAM (IN I/O PORT MODE)

Data Bus

WR PORT

WR TRIS

RD PORT

Note: I/O pins have protection diodes to VDD and VSS.

Data Latch

TRIS Latch

TABLE 5-9: PORTE FUNCTIONS

RD TRIS

I/O pin

Schmitt Trigger input buffer

Name Bit# Buffer Type Function

RE0/RD

bit0 ST/TTL

(1)

Input/output port pin or read control input in parallel slave port mode:

RD 1 = Not a read operation 0 = Read operation. Reads PORTD register (if chip selected)

RE1/WR

bit1 ST/TTL

(1)

Input/output port pin or write control input in parallel slave port mode:

WR 1 = Not a write operation 0 = Write operation. Writes PORTD register (if chip selected)

RE2/CS

bit2 ST/TTL

(1)

Input/output port pin or chip select control input in parallel slave port mode:

CS 1 = Device is not selected 0 = Device is selected

Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode.

TABLE 5-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

09h PORTE 89h TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 0000 -111

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.

— — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu

POR,

BOR

Value on all

other resets

 1996 Microchip Technology Inc. Preliminary DS30559A-page 37

PIC16C64X & PIC16C66X

5.6 I/O Programming Considerations

5.6.1 BI-DIRECTIONAL I/O PORTS Any instruction which writes, operates internally as a

read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs deﬁned. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used as a bi-directional I/O pin (e.g., bit0) and it is deﬁned as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch may now be unknown.

Reading the port register reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read-modify-write instructions (e.g., BCF, BSF, etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch.

Example 5-4 shows the effect of two sequential read-modify-write instructions on an I/O port.

A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin (“wired-or”, “wired-and”). The resulting high output currents may damage the chip.

EXAMPLE 5-4: READ-MODIFY-WRITE

INSTRUCTIONS ON AN I/O PORT

;Initial PORT settings: PORTB<7:4> Inputs ; PORTB<3:0> Outputs ;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry ; ; PORT latch PORT pins ; ---------- -------- BCF PORTB, 7 ; 01pp pppp 11pp pppp BCF PORTB, 6 ; 10pp pppp 11pp pppp BCF STATUS, RP1 ; BSF STATUS, RP0 ; BCF TRISB, 7 ; 10pp pppp 11pp pppp BCF TRISB, 6 ; 10pp pppp 10pp pppp ; ;Note that the user may have expected the ;pin values to be 00pp ppp. The 2nd BCF ;caused RB7 to be latched as the pin value ;(high).

5.6.2 SUCCESSIVE OPERATIONS ON I/O PORTS

The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-11). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that ﬁle to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with an NOP or another instruction not accessing this I/O port.

FIGURE 5-11: SUCCESSIVE I/O OPERATION

PC + 3

NOP

Note: This example shows a write to PORTB

followed by a read from PORTB. Note that: data setup time = (0.25TCY - TPD) where TCY = instruction cycle

TPD = propagation delay

Therefore, at higher clock frequencies, a write followed by a read may be problematic.

NOP

Q1 Q2

Instruction

fetched

RB7:RB0

Instruction

executed

DS30559A-page 38 Preliminary  1996 Microchip Technology Inc.

MOVWF PORTB

PC PC + 1 PC + 2

write to PORTB

Q1 Q2

MOVF PORTB,W

MOVWF PORTB

write to PORTB

Q1 Q2

Port pin sampled here

TPD

MOVF PORTB,W

PIC16C64X & PIC16C66X

5.7 Parallel Slave Port (PIC16C661 and PIC16C662 only)

PORTD operates as an 8-bit wide parallel slave port, or as a microprocessor port when control bit PSPMODE (TRISE<4>) is set. In slave mode it is asynchronously readable and writable by the external world through R

D control input pin (RE0/RD) and WR control input pin

(RE1/WR It can directly interface to an 8-bit microprocessor data

bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting PSPMODE enables port pin RE0/RD to be the WR input and RE2/CS to be the CS (chip select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be conﬁgured as inputs (set).

There are actually two 8-bit latches, one for data-out (from the PIC16/17) and one for data input. The user writes 8-bit data to PORTD data latch and reads data from the port pin latch (note that they have the same address). In this mode, the TRISD register is ignored since the microprocessor is controlling the direction of data ﬂow.

Input Buffer Full Status Flag bit IBF (TRISE<7>) is set if a received word is waiting to be read by the CPU. Once the PORTD input latch is read, bit IBF is cleared. IBF is a read only status bit. Output Buffer Full Status Flag bit OBF (TRISE<6>) is set if a word written to PORTD latch is waiting to be read by the external bus. Once the PORTD output latch is read by the microprocessor, bit OBF is cleared. Input Buffer Overﬂow Status ﬂag bit IBOV (TRISE<5>) is set if a second write to the microprocessor port is attempted when the previous word has not been read by the CPU (the ﬁrst word is retained in the buffer).

When not in Parallel Slave Port mode, bits IBF and OBF are held clear. However, if ﬂag bit IBOV was previously set, it must be cleared in software.

to be the RD input, RE1/WR

An interrupt is generated and latched into ﬂag bit PSPIF (PIR1<7>) when a read or a write operation is completed. Flag bit PSPIF must be cleared by user software. The interrupt can be disabled by clearing the interrupt enable bit PSPIE (PIE1<7>).

FIGURE 5-12: PORTD AND PORTE AS A

PARALLEL SLAVE PORT

Data bus

WR PORT

RD PORT

One bit of PORTD

Set interrupt ﬂag

PSPIF (PIR1<7>)

Note: I/O pins have protection diodes to VDD and VSS.

TTL

Read

Chip Select

Write

TTL

RDx pin

TABLE 5-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT

Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

08h PORTD PSP7 PSP6 PSP5 PSP4 PSP3 PSP2 PSP1 PSP0 xxxx xxxx uuuu uuuu 09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 89h TRISE IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 0000 -111 0000 -111 0Ch PIR1 PSPIF 8Ch PIE1 PSPIE

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by the PSP. Note 1: These bits are reserved on the PIC16C641/642, always maintain these bits clear.

 1996 Microchip Technology Inc. Preliminary DS30559A-page 39

(1)

CMIF — — — — — — 00-- ---- 00-- ----

(1)

CMIE — — — — — — 00-- ---- 00-- ----

POR,

BOR

Value on all

other resets

PIC16C64X & PIC16C66X

NOTES:

DS30559A-page 40 Preliminary  1996 Microchip Technology Inc.



PIC16C64X & PIC16C66X

6.0 TIMER0 MODULE

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

- Read and write capability

- Interrupt on overﬂow from FFh to 00h

• 8-bit software programmable prescaler

• Internal or external clock select

- Edge select for external clock

Figure 6-1 is a simpliﬁed block diagram of the Timer0 module.

Timer mode is selected by clearing bit T0CS (OPTION<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two instruction cycles (Figure 6-2 and Figure 6-3). The user can work around this by writing an adjusted value to the TMR0 register.

Counter mode is selected by setting bit T0CS. In this mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the source edge select bit T0SE

(OPTION<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.2.

The prescaler is mutually exclusively shared between the Timer0 module and the W atchdog Timer. The prescaler assignment is controlled in software by control bit PSA (OPTION<3>). Clearing bit PSA will assign the prescaler to the Timer0 module. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, …, 1:256 are selectable. Section 6.3 details the operation of the prescaler.

6.1 T

imer0 Interrupt

The TMR0 interrupt is generated when the register (TMR0) overﬂows from FFh to 00h. This overﬂow sets interrupt ﬂag bit T0IF (INTCON<2>). The interrupt can be masked by clearing enable bit T0IE (INTCON<5>). Flag bit T0IF must be cleared in software by the Timer0 interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot wake the processor from SLEEP since the timer is shut off during SLEEP. Figure 6-4 displays the Timer0 interrupt timing.

FIGURE 6-1: TIMER0 BLOCK DIAGRAM

RA4/T0CKI pin

Note 1: Bits, T0CS, T0SE, PSA, and PS2, PS1, PS0 are (OPTION<5:0).

FOSC/4

T0SE

2: The prescaler is shared with Watchdog Timer (refer to Figure 6-6 for detailed diagram).

T0CS

Programmable

Prescaler

PS2, PS1, PS0

PSA

PSout

Sync with

Internal

clocks

(2 cycle delay)

FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER

PC (Program Counter)

Instruction

Fetch

TMR0

Instruction Executed

Q1 Q2 Q3 Q4

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

MOVWF TMR0

T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0 executed

Read TMR0 reads NT0

PSout

Data bus

TMR0 reg

Read TMR0 reads NT0 + 1

Set bit T0IF on overﬂow

Read TMR0 reads NT0 + 2

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 41



PIC16C64X & PIC16C66X

FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

PC (Program Counter)

Instruction

Fetch

TMR0

Instruction Execute

Q1 Q2 Q3 Q4

PC-1

T0 NT0+1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

MOVWF TMR0

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

T0+1

Write TMR0 executed

Read TMR0 reads NT0

FIGURE 6-4: TIMER0 INTERRUPT TIMING

Q2Q1 Q3 Q4Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT(3)

Timer0

T0IF bit (INTCON<2>)

GIE bit (INTCON<7>)

INSTRUCTION

LOW

FEh

FFh 00h 01h 02h

NT0

Read TMR0 reads NT0

Read TMR0 reads NT0 + 1

Instruction fetched

Instruction executed

Note 1: Interrupt ﬂag bit T0IF is sampled here (every Q1).

Inst (PC)

Inst (PC-1)

2: Interrupt latency = 4Tcy where Tcy = instruction cycle time. 3: CLKOUT is available only in RC oscillator mode.

PC +1 PC +1 0004h 0005h

Inst (PC+1)

Inst (PC)

Inst (0004h) Inst (0005h)

Inst (0004h)Dummy cycle Dummy cycle

DS30559A-page 42

Preliminary

1996 Microchip Technology Inc.



PIC16C64X & PIC16C66X

6.2 Using

When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (T incrementing of Timer0 after synchronization.

6.2.1 EXTERNAL CLOCK SYNCHRONIZATION

When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-5). Therefore, it is necessary for T0CKI to be high for at least 2T osc (and a small RC delay of 20 ns) and low for at least 2T osc (and a small RC delay of 20 ns). Refer to the electrical speciﬁcation of the desired device.

Timer0 with External Clock

OSC

). Also, there is a delay in the actual

When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4Tosc (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41, and 42 in the electrical speciﬁcation of the desired device.

6.2.2 TIMER0 INCREMENT DELAY Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 6-5 shows the delay from the external clock edge to the timer incrementing.

FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

External Clock Input or Prescaler output

External Clock/Prescaler Output after sampling

Increment Timer0 (Q4)

(2)

(1)

(3)

Small pulse misses sampling

Timer0

Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).

Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max. 2: External clock if no prescaler selected, prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs.

T0 T0 + 1 T0 + 2

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 43



PIC16C64X & PIC16C66X

6.3 Prescaler

An 8-bit counter is available as a prescaler for the Timer0 module or as a postscaler for the Watchdog Timer (WDT), respectively (Figure 6-6). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that the prescaler may be used by either the Timer0 module or the Watchdog Timer, but not both. Thus, a prescaler assignment for

The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,

BSF 1,x ) will clear the prescaler count. When

assigned to Watchdog Timer, a CLRWDT instruction will clear the prescaler count along with the Watchdog Timer. The prescaler is not readable or writable.

the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa.

FIGURE 6-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

CLKOUT (=Fosc/4)

RA4/T0CKI

T0SE

T0CS

M U

PSA

SYNC

Cycles

Data Bus

TMR0 reg

Set ﬂag bit T0IF

on Overﬂow

Watchdog

Timer

WDT Enable bit

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).

PSA

8-bit Prescaler

8 - to - 1MUX

M U X

WDT

Time-out

PS2:PS0

PSA

DS30559A-page 44

Preliminary

1996 Microchip Technology Inc.



PIC16C64X & PIC16C66X

6.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con-

trol, i.e., it can be changed “on the ﬂy” during program execution.

Note: T o avoid an unintended device RESET, the

following instruction sequence (shown in Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This precaution must be followed even if the WDT is disabled.

EXAMPLE 6-1: CHANGING PRESCALER

(TIMER0 → WDT)

BCF STATUS, RP0 ;Bank 0 CLRF TMR0 ;Clear TMR0 & Prescaler BSF STATUS, RP0 ;Bank 1 CLRWDT ;Clears WDT MOVLW b'xxxx1xxx' ;Select new prescale MOVWF OPTION_REG ;value & WDT BCF STATUS, RP0 ;Bank 0

To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 6-2.

EXAMPLE 6-2: CHANGING PRESCALER

(WDT → TIMER0)

CLRWDT ;Clear WDT and ;prescaler BSF STATUS, RP0 ;Bank 1 MOVLW b'xxxx0xxx' ;Select TMR0, new ;prescale value and MOVWF OPTION_REG ;clock source BCF STATUS, RP0 ;Bank 0

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0

Value on:

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

01h TMR0 Timer0 module’s register 0Bh/8Bh INTCON GIE 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 85h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.

PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

POR,

BOR

xxxx xxxx uuuu uuuu

Value on all other resets

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 45



PIC16C64X & PIC16C66X

NOTES:

DS30559A-page 46

Preliminary

1996 Microchip Technology Inc.



PIC16C64X & PIC16C66X

7.0 COMPARATOR MODULE

The comparator module contains two analog comparators. The inputs to the comparators are

The CMCON register, shown in Figure 7-1, controls the comparator input and output multiplexers. A block diagram of the comparator is shown in Figure 7-2.

multiplexed with pins RA0 through RA4. The on-chip Voltage Reference (Section 8.0) can also be an input to the comparators.

FIGURE 7-1: CMCON REGISTER

(ADDRESS 1Fh)

R-0 R-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

C2OUT C1OUT

— — CIS CM2 CM1 CM0 R =Readable bit

bit7 bit0

bit 7: C2OUT : Comparator 2 output

1 = C2 V 0 = C2 V

+ > C2 V + < C2 V

– –

bit 6: C1OUT : Comparator 1 output

1 = C1 V 0 = C1 V

+ > C1 V

+ < C1 V

–

bit 5-4: Unimplemented: Read as '0' bit 3: CIS : Comparator Input Switch

W =Writable bit U =Unimplemented bit, read as ‘0’

- n =Value at POR reset

When CM2:CM0: = 001 : Then: 1 = C1 V 0 = C1 V

– connects to RA3

– connects to RA0

When CM2:CM0 = 010 : Then: 1 = C1 V C2 V 0 = C1 V C2 V

– connects to RA3

– connects to RA2 – connects to RA0

– connects to RA1

bit 2-0: CM2:CM0 : Comparator mode

Figure 7-2 shows the comparator modes and CM2:CM0 bit settings.

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 47



PIC16C64X & PIC16C66X

7.1 Comparator Conﬁ

guration

mode is changed, the comparator output level may not be valid for the speciﬁed mode change delay shown

There are eight modes of operation for the

in Table 12-2.

comparators. The CMCON register is used to select the mode. Figure 7-2 shows the eight possible modes. The TRISA register controls the data direction of the comparator pins for each mode. If the comparator

FIGURE 7-2: COMPARATOR I/O OPERATING MODES

Comparators Reset (POR Default Value) CM2:CM0 = 000

RA0/AN0 RA3/AN3

RA1/AN1 RA2/AN2

VIN-

VINV

IN+

A A

Off (Read as '0')

Off

Two Independent Comparators CM2:CM0 = 100

RA0/AN0 RA3/AN3

RA1/AN1 RA2/AN2

VIN-

VINV

IN+

A A

C1OUT

C2OUT

(Read as '0')

Comparators Off CM2:CM0 = 111

RA0/AN0 RA3/AN3

RA1/AN1 RA2/AN2

Four Inputs Multiplexed to Two Comparators CM2:CM0 = 010

RA0/AN0 RA3/AN3

RA1/AN1 RA2/AN2

Note: Comparator interrupts should be disabled

during a comparator mode change otherwise a false interrupt may occur.

VIN-

(Read as '0')

VINV

IN+

Off

(Read as '0')

Off

C1OUT

C2OUT

IN+

VIN-

IN+

CIS = 0

CIS = 1

CIS = 0

CIS = 1

Two Common Reference Comparators CM2:CM0 = 011

RA0/AN0 RA3/AN3

RA1/AN1 RA2/AN2

VIN-

VINV

IN+

A A

C1OUT

C2OUT

One Independent Comparator CM2:CM0 = 101

RA0/AN0 RA3/AN3

RA1/AN1 RA2/AN2

VIN-

(Read as '0')

VINV

IN+

A A

Off

C2OUT

A = Analog Input, port reads zeros always. D = Digital Input. CIS (CMCON<3>) is the Comparator Input Switch.

From VREF Module

Two Common Reference Comparators with Outputs CM2:CM0 = 110

RA0/AN0 RA3/AN3

RA1/AN1 RA2/AN2

VIN-

IN+

VIN-

IN+

C1OUT

C2OUT

RA4 Open Drain

Three Inputs Multiplexed to Two Comparators CM2:CM0 = 001

RA0/AN0 RA3/AN3

RA1/AN1 RA2/AN2

CIS = 0

CIS = 1

A A

VINV

IN+

C1OUT

C2OUT

DS30559A-page 48

Preliminary

1996 Microchip Technology Inc.



PIC16C64X & PIC16C66X

The code example in Example 7-1 depicts the steps required to conﬁgure the comparator module. RA3 and RA4 are conﬁgured as digital outputs. RA0 and RA1 are conﬁgured as the V- inputs and RA2 as the V+ input to both comparators.

EXAMPLE 7-1: INITIALIZING THE

COMPARATOR MODULE

FLAG_REG EQU 0x20 CLRF FLAG_REG ;Init Flag Register CLRF PORTA ;Init PORTA ANDLW 0xC0 ;Mask Comp bits IORWF FLAG_REG,F ;Bits to Flag_Reg MOVLW 0x03 ;Init Comp Mode MOVWF CMCON ;CM2:CM0 = 011 BSF STATUS,RP0 ;Select Bank 1 MOVLW 0x07 ;Init Data direction MOVWF TRISA ;RA<2:0> to inputs ;RA<4:3> to outputs ;TRISA<7:5> read '0' BCF STATUS,RP0 ;Select Bank 0 CALL DELAY_10 µ s ;10 µ s delay MOVF CMCON,F ;Read CMCON to end ;change condition BCF PIR1,CMIF ;Clear Pending Ints BSF STATUS,RP0 ;Select Bank 1 BSF PIE1,CMIE ;Enable Comp Ints BCF STATUS,RP0 ;Select Bank 0 BSF INTCON,PEIE ;Enable Periph Ints BSF INTCON,GIE ;Global Int enable

7.2 Comparator Operation

A single comparator is shown in Figure 7-3 along with the relationship between the analog input levels and the digital output. When the analog input at V than the analog input V

–, the output of the comparator is a digital low level. When the analog input at V greater than the analog input V

–, the output of the

comparator is a digital high level. The shaded areas of the output of the comparator in Figure 7-3 represents the uncertainty due to input offsets and response time.

+ is less

+ is

7.3 Comparator Ref

erence

An external or internal reference signal may be used depending on the comparator operating mode. The analog signal that is present at V signal at V

+, and the digital output of the comparator

– is compared to the

is adjusted accordingly (Figure 7-3).

FIGURE 7-3: SINGLE COMPARATOR

VINV

IN+

VIN-

IN+

Output

7.3.1 EXTERNAL REFERENCE SIGNAL When external voltage references are used, the

comparator module can be conﬁgured to have the comparators operate from the same or different reference sources. However, threshold detector applications may require the same reference. The reference signal must be between V

and V

, and can be applied to either

pin of the comparator(s).

7.3.2 INTERNAL REFERENCE SIGNAL The comparator module also allows the selection of an

internally generated voltage reference for the comparators. Section 8.0, contains a detailed description of the Voltage Reference Module that provides this signal. The internal reference signal is used when the comparators are in mode CM2:CM0 = 010 (Figure 7-2). In this mode, the internal voltage reference is applied to the V

+ pin of both comparators.

Output

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 49

PIC16C64X & PIC16C66X

7.4 Comparator Response Time

Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output is guaranteed to have a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. Otherwise, the maximum delay of the comparators should be used (Table 12-2 and Table 12-3).

7.5 Comparator Outputs

The comparator outputs are read through the CMCON register. These bits are read only. The comparator outputs may also be directly output to the RA3 and RA4 I/O pins. When CM2:CM0 = 110, multiplexors in the output path of the RA3 and RA4 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the speciﬁcations. Figure 7-4 shows the comparator output block diagram.

The TRISA bits will still function as an output enable/ disable for the RA3 and RA4 pins while in this mode.

Note 1: When reading the PORTA register , all pins

conﬁgured as analog inputs will read as a ‘0’. Pins conﬁgured as digital inputs will convert an analog input according to the Schmitt Trigger input speciﬁcation.

Note 2: Analog levels on any pin that is deﬁned as

a digital input may cause the input buffer to consume more current than is speciﬁed.

FIGURE 7-4: COMPARATOR OUTPUT BLOCK DIAGRAM

To RA3 or RA4 pin To Data Bus

RD CMCON

Set CMIF bit

From other Comparator

Port Pins

MULTIPLEX

RD CMCON

NRESET

DS30559A-page 50 Preliminary  1996 Microchip Technology Inc.

PIC16C64X & PIC16C66X

7.6 Comparator Interrupts

The comparator interrupt ﬂag is set whenever there is a change in the output value of either comparator. User software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that has occurred. The CMIF bit (PIR1<6>), is the comparator interrupt ﬂag and must be cleared in user software.

To enable the Comparator interrupt the following bits must be set:

• CMIE (PIE1<6>)

• PEIE (INTCON<6>)

• GIE (INTCON<7>) The user, in the interrupt service routine, can clear the

interrupt in the following manner: a) Any read or write of CMCON. This will end the

mismatch condition.

b) Clear ﬂag bit CMIF. A mismatch condition will continue to set ﬂag bit CMIF.

Reading CMCON will end the mismatch condition, and allow ﬂag bit CMIF to be cleared.

7.7 Comparator Operation During SLEEP

When a comparator is active and the device is placed in SLEEP mode, the comparator remains active and the interrupt is functional if enabled. This interrupt will wake up the device from SLEEP mode when enabled. While the comparator is powered up, higher sleep currents than shown in the power-down current speciﬁcation will occur. Each comparator that is operational will consume additional current as shown in the comparator speciﬁcations. To minimize power consumption while in SLEEP mode, turn off the

comparators, CM2:CM0 = 111, before entering sleep. If the device wakes up from sleep, the contents of the CMCON register are not affected.

7.8 Effects of a RESET

A device reset forces the CMCON register to its reset state. This forces the comparator module to be in the comparator reset mode, CM2:CM0 = 000. This ensures that all potential inputs are analog inputs. Device current is minimized when analog inputs are present at reset time. The comparators will be powered down during the reset interval.

7.9 Analog Input Connection Considerations

A simpliﬁed circuit for an analog input is shown in Figure 7-5. Since the analog pins are connected to a digital output, they have reverse biased diodes to V and VSS. The analog input therefore, must be between V

SS and VDD. If the input voltage deviates from this

range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 kΩ is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current.

FIGURE 7-5: ANALOG INPUT MODEL

AIN

CPIN

5 pF

Legend CPIN = Input Capacitance

T = Threshold Voltage

LEAKAGE = Leakage Current at the pin due to various junctions

IC = Interconnect Resistance

S = Source Impedance

A = Analog Voltage

 1996 Microchip Technology Inc. Preliminary DS30559A-page 51

VT = 0.6V

T = 0.6V

LEAKAGE

I ±500 nA

C < 10k

PIC16C64X & PIC16C66X

TABLE 7-1: REGISTERS ASSOCIATED WITH THE COMPARATOR MODULE

Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 0000 00-- 0000 9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000 0Bh/8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1

8Ch PIE1 85h TRISA

Note 1: These bits are reserved on the PIC16C641/642, always maintain these bits clear.

(1)

PSPIF PSPIE

— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

CMIF — — — — — — 00-- ---- 00-- ----

(1)

CMIE — — — — — — 00-- ---- 00-- ----

POR,

BOR

Value on

all other

resets

DS30559A-page 52 Preliminary  1996 Microchip Technology Inc.



PIC16C64X & PIC16C66X

8.0 VOLTAGE REFERENCE MODULE

The VRCON register, shown in Figure 8-1, controls the operation of the Voltage Reference Module. The block

diagram is given in Figure 8-2. The Voltage Reference is a 16-tap resistor ladder network that provides a selectable voltage reference. The resistor ladder is segmented to provide two ranges of V

values and has a power-down function to

REF

conserve power when the reference module is not being used.

FIGURE 8-1: VRCON REGISTER (ADDRESS 9Fh)

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 VREN VROE VRR

bit7 bit0

bit 7: VREN: V

1 = V 0 = V

bit 6: VROE: V

1 = V 0 = V

bit 5: VRR: V

REF

Enable

circuit powered up

REF

circuit powered down, no I

REF

Output Enable

is output on RA2 pin

REF

is disconnected from RA2 pin

REF

Range selection

REF

1 = Low Range

0 = High Range bit 4: Unimplemented: Read as '0' bit 3-0: VR3:VR0 : V

REF

value selection 0 ≤ VR3:VR0 ≤ 15

When: VRR = 1

Then: V

REF

= (VR3:VR0/ 24) • V

— VR3 VR2 VR1 VR0 R =Readable bit

drain

W =Writable bit U =Unimplemented bit, read as ‘0’

- n =Value at POR reset

When: VRR = 0

Then: V

REF

= 1/4 • V

+ (VR3:VR0/ 32) • V

FIGURE 8-2: VOLTAGE REFERENCE BLOCK DIAGRAM

16 Stages

VREN

VREF

Note: R is deﬁned in Table 12-3.

16-1 Analog Mux

VR3 VR2 VR1 VR0

VRR

(From VRCON<3:0>)

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 53



PIC16C64X & PIC16C66X

8.1 Conﬁ

guring the Voltage Reference

The Voltage Reference Module can output 16 distinct voltage levels for each range.

The equations used to calculate the output of the Voltage Reference are as follows:

If VRR = 1 Then V

= (VR3:VR0/24) • V

REF

If VRR = 0 Then V

REF

= (V

• 1/4) + (VR3:VR0/32) • V

The settling time of the Voltage Reference must be considered when changing the V

REF

output (T able 12-2). Example 8-1 shows an example of how to conﬁgure the Voltage Reference for an output voltage of 1.25V with V

= 5.0V.

EXAMPLE 8-1: VOLTAGE REFERENCE

CONFIGURATION

MOVLW 0x02 ; 4 inputs muxed MOVWF CMCON ; to 2 comparators BSF STATUS,RP0 ; Select Bank 1 MOVLW 0x07 ; RA3:RA0 to outputs MOVWF TRISA ; MOVLW 0xA6 ; enable Vref low MOVWF VRCON ; range, VR3:VR0 = 6 BCF STATUS,RP0 ; Select Bank 0 CALL DELAY_10 µ s ; 10 µ s delay

8.2 V

The full range of V the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 8-2) keep V The Voltage Reference is V

oltage Reference Accuracy/Error

to V

cannot be realized due to

from approaching V

REF

derived and therefore,

or V

the V

output changes with ﬂuctuations in V

REF

. The absolute accuracy of the Voltage Reference can be found in Table 12-3.

8.3 Operation During Sleep

When the device wakes up from sleep through an interrupt or a Watchdog T imer time-out, the contents of the VRCON register are not affected. To minimize current consumption in SLEEP mode, the Voltage Reference Module should be disabled.

8.4 Eff

ects of a Reset

A device reset disables the V oltage Reference by clearing bit VREN (VRCON<7>). This reset also disconnects the reference from the RA2 pin by clearing bit VROE (VRCON<6>) and selects the high voltage range by clearing bit VRR (VRCON<5>). The V

REF

value select bits, VRCON<3:0>, are also cleared.

8.5 Connection Considerations

The Voltage Reference Module operates independently of the comparator module. The output of the reference generator may be connected to the RA2 pin if the TRISA<2> bit is set and bit VROE is set. Enabling the Voltage Reference output onto the RA2 pin with an input signal present will increase current consumption. Connecting RA2 as a digital output with V will also increase current consumption.

The RA2 pin can be used as a simple D/A output with limited drive capability. Due to the limited drive capability, a buf fer must be used in conjunction with the

Voltage Reference output for external connections to V

REF

. Figure 8-3 shows an example buffering

technique.

REF

enabled

FIGURE 8-3: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

PIC16C662

(1)

Pin RA2

VREF Module

VREF output Voltage Reference Output Impedance

Note 1: R is dependent upon the Voltage Reference Conﬁguration VRCON<3:0> and VRCON<5>.

TABLE 8-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE

Value On

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

9Fh VRCON VREN VROE VRR 1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 0000 00-- 0000 85h TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

DS30559A-page 54

— VR3 VR2 VR1 VR0 000- 0000 000- 0000

Preliminary

POR,

BOR

1996 Microchip Technology Inc.

Value on

all other

resets



PIC16C64X & PIC16C66X

9.0 SPECIAL FEATURES OF THE CPU

What sets apart a microcontroller from other processors are special circuits to deal with the needs of real-time applications. The PIC16C64X & PIC16C66X families have a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection.

These are:

1. Oscillator selection

2. Resets

Power-on Reset (POR) Power-up Timer (PWRT) Oscillator Start-up Timer (OST) Brown-out Reset (BOR) Parity Error Reset (PER)

3. Interrupts

4. Watchdog Timer (WDT)

5. SLEEP

6. Code protection

7. ID Locations

8. In-circuit serial programming

The PIC16C64X & PIC16C66X has a Watchdog Timer which is enabled by a conﬁguration bit (WDTE). It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a ﬁxed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. Circuitry has been provided for checking program memory parity with a reset when an error is indicated. There is also circuitry to reset the device if a brown-out occurs which provides at least a 72 ms reset. With these three functions on-chip, most applications need no external reset circuitry.

SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external reset, Watchdog Timer wake-up or through an interrupt. Several oscillator options are also made available to allow the part to ﬁt the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of conﬁguration bits are used to select various options.

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 55



PIC16C64X & PIC16C66X

9.1 C

onﬁguration Bits

The user will note that address 2007h is beyond the user program memory space. In fact, it belongs

The conﬁguration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device conﬁgurations. These bits are mapped in

to the special test/conﬁguration memory space (2000h–3FFFh), which can be accessed only during programming.

program memory location 2007h.

FIGURE 9-1: CONFIGURATION WORD

CP1 CP0 CP1 CP0 CP1 CP0 MPEEN BODEN CP1 CP0 PWR bit13 bit0 bit 13-8

5-4: 11 = Code protection off

bit 7: MPEEN : Memory Parity Error Enable

bit 6: BODEN : Brown-out Reset Enable bit

bit 3: PWR

bit 2: WDTE : Watchdog Timer Enable bit

bit 1-0: FOSC1:FOSC0 : Oscillator Selection bits

Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of bit PWR

CP1:CP0: Code protection bits

= Upper half of program memory code protected = Upper 3/4th of program memory code protected = All memory is code protected

1 = Memory Parity Checking is enabled 0 = Memory Parity Checking is disabled

1 = BOR enabled 0 = BOR disabled

: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled

1 = WDT enabled 0 = WDT disabled

= RC oscillator = HS oscillator = XT oscillator = LP oscillator

Power-up Timer is enabled anytime Brown-out Reset is enabled.

2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.

(2)

(1)

TE WDTE FOSC1 FOSC0 CONFIG Address

TE. Ensure the

DS30559A-page 56

Preliminary

1996 Microchip Technology Inc.



PIC16C64X & PIC16C66X

9.2 Oscillator Conﬁ

gurations

9.2.1 OSCILLATOR TYPES The PIC16CXXX can be operated in four different

oscillator modes. The user can program two conﬁguration bits (FOSC1 and FOSC0) to select one of these four modes:

• LP Low Power Crystal

• XT Crystal/Resonator

• HS High Speed Crystal/Resonator

• RC Resistor/Capacitor

9.2.2 CRYSTAL OSCILLATOR / CERAMIC RESONATORS

In XT, LP or HS modes a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation (Figure 9-2). The PIC16CXXX oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers speciﬁcations. When in XT , LP or HS modes, the device can have an external clock source to drive the OSC1 pin (Figure 9-3).

FIGURE 9-2: CRYSTAL OPERATION

(OR CERAMIC RESONATOR) (HS, XT OR LP OSC CONFIGURATION)

OSC1

XTAL

see Note

OSC2

To internal logic SLEEP

PIC16CXXX

See Table 9-1 or Table 9-2 for recommended values of C1 and C2.

Note: A series resistor may be required for

AT strip cut crystals.

FIGURE 9-3: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR LP OSC CONFIGURATION)

clock from ext. system

Open

OSC1

PIC16CXXX

OSC2

TABLE 9-1: CAPACITOR SELECTION

FOR CERAMIC RESONATORS (PRELIMINARY)

Ranges tested:

Mode Freq OSC1

XT 455 kHz

2.0 MHz

4.0 MHz

HS 8.0 MHz

16.0 MHz

Note: Recommended values of C1 and C2 are identical

to the ranges tested table. Higher capacitance increases the stability of the oscillator but also increases the start-up time. These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components.

22 - 100 pF 15 - 68 pF 15 - 68 pF

10 - 68 pF 10 - 22 pF

Resonators used:

455 kHz Panasonic EFO-A455K04B ± 0.3%

2.0 MHz Murata Erie CSA2.00MG

4.0 MHz Murata Erie CSA4.00MG

8.0 MHz Murata Erie CSA8.00MT

0.5%

16.0 MHz Murata Erie CSA16.00MX ± 0.5%

All resonators used did not have built-in capacitors.

TABLE 9-2: CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR (PRELIMINARY)

Mode Freq OSC1 OSC2

LP 32 kHz

200 kHz

XT 100 kHz

2 MHz 4 MHz

HS 8 MHz

10 MHz 20 MHz

Higher capacitance increases the stability of the oscillator but also increases the start-up time. These values are for design guidance only. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level speciﬁcation. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.

32.768 kHz Epson C-001R32.768K-A ± 20 PPM 100 kHz Epson C-2 100.00 KC-P ± 20 PPM 200 kHz STD XTL 200.000 kHz

2.0 MHz ECS ECS-20-S-2

4.0 MHz ECS ECS-40-S-4

10.0 MHz ECS ECS-100-S-4

20.0 MHz ECS ECS-200-S-4

68 - 100 pF

15 - 30 pF

68 - 150 pF

15 - 30 pF 15 - 30 pF

15 - 30 pF 15 - 30 pF 15 - 30 pF

Crystals used:

68 - 100 pF

15 - 30 pF

150 - 200 pF

15 - 30 pF 15 - 30 pF

15 - 30 pF 15 - 30 pF 15 - 30 pF

20 PPM 50 PPM 50 PPM 50 PPM 50 PPM

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 57



PIC16C64X & PIC16C66X

9.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT

Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with series resonance, or one with parallel resonance.

Figure 9-4 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 k Ω resistor provides the negative feedback for stability. The 10 k Ω potentiometer biases the 74AS04 in the linear region. This could be used for external oscillator designs.

FIGURE 9-4: EXTERNAL PARALLEL

RESONANT CRYSTAL OSCILLATOR CIRCUIT

+5V

10k

4.7k

74AS04

10k

XTAL

10k

20 pF

Figure 9-5 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180-degree phase shift in a series resonant oscillator circuit. The 330 k Ω resistors provide the negative feedback to bias the inverters in their linear region.

74AS04

To Other Devices

PIC16CXXX

CLKIN

FIGURE 9-5: EXTERNAL SERIES

RESONANT CRYSTAL OSCILLATOR CIRCUIT

To Other

74AS04

Devices

PIC16CXXX

CLKIN

330 kΩ

74AS04

330 kΩ

74AS04

0.1 µF XTAL

9.2.4 RC OSCILLATOR For timing insensitive applications the “RC” device

option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Cext values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 9-6 shows how the R/C combination is connected to the PIC16CXXX. For Rext values below 2.2 k Ω , the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g. 1 M Ω ), the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend to keep Rext between 3 k Ω and 100 k Ω .

Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance.

See characterization data for desired device for RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more).

See characterization data for desired device for variation of oscillator frequency due to V

for given Rext/ Cext values as well as frequency variation due to operating temperature for given R, C, and V

values.

The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (see Figure 3-3 for waveform).

FIGURE 9-6: RC OSCILLATOR MODE

VDD

Rext

Cext

VSS

Fosc/4

OSC1

OSC2/CLKOUT

Internal

clock

PIC16CXXX

DS30559A-page 58

Preliminary

1996 Microchip Technology Inc.



PIC16C64X & PIC16C66X

9.3 Reset

state” on Power-on reset, M Brown-out Reset, Parity Error Reset, and on MCLR

The PIC16CXXX differentiates between various kinds of reset:

a) Power-on reset (POR) b) MCLR c) MCLR

reset during normal operation

reset during SLEEP d) WDT reset (normal operation) e) Brown-out Reset (BOR) f) Parity Error Reset (PER)

Some registers are not affected in any reset condition; their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a “reset

reset during SLEEP. They are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. T

O and PD bits are set or cleared differently in different reset situations as indicated in T able 9-4. These bits are used in software to determine the nature of the reset. See Table 9-6 for a full description of reset states of all registers.

A simpliﬁed block diagram of the on-chip reset circuit is shown in Figure 9-7.

The MCLR

reset path has a noise ﬁlter to detect and ignore small pulses. See Table 12-6 for pulse width speciﬁcation.

FIGURE 9-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR/

PP Pin

Program

Memory

Parity

WDT

Module

DD rise

detect

Brown-out

Reset

MPEEN

SLEEP

WDT Time-out

Power-on Reset

BODEN

CLR, WDT reset,

OST/PWRT

OST

10-bit Ripple-counter

OSC1/ CLKIN

On-chip

RC OSC

PWRT

(1)

10-bit Ripple-counter

Enable PWRT

Enable OST

See Table 9-3 for time-out situations.

Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.

Chip_Reset

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 59

PIC16C64X & PIC16C66X



9.4 P

ower-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST), Brown-out Reset (BOR), and Parity Error Reset (PER)

9.4.1 POWER-ON RESET (POR) A Power-on Reset pulse is generated on-chip when

rise is detected (in the range of 1.6V to 1.8V). To take advantage of the POR, just tie the MCLR directly (or through a resistor) to V

eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for V is required. See Electrical Speciﬁcations for details.

When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met.

For additional information, refer to Application Note AN607 “

Pow er-up Trouble Shooting.

”

9.4.2 POWER-UP TIMER (PWRT) The Power-up Timer provides a ﬁxed 72 ms (nominal)

delay on power-up only, from POR or BOR. The Power-up Timer operates on an internal RC oscillator. The chip is kept in reset as long as PWRT is active. The PWRT delay allows V A conﬁguration bit, PW

to rise to an acceptable level.

RTE can disable (if set) or enable (if cleared or programmed) the Power-up Timer . The Power-up Timer should always be enabled when Brown-out Reset is enabled.

. This will

The power-up time delay will vary from chip to chip due to V

, temperature, and process variations. See DC

parameters for details.

9.4.3 OSCILLATOR START-UP TIMER (OST) The Oscillator Start-Up Timer (OST) provides a 1024

oscillator cycle (from OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP, and HS modes and only on Power-on Reset or wake-up from SLEEP.

9.4.4 BROWN-OUT RESET (BOR) PIC16C64X & PIC16C66X devices have on-chip

Brown-out Reset circuitry. A conﬁguration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If V

falls below 4.0V

(Parameter D005 in ES section) for greater than parameter 35 in T able 12-6, the brown-out situation will reset the chip. A reset is not guaranteed to occur if V

falls below 4.0V for less than parameter 35. The chip will remain in Brown-out Reset until V

. The Power-up Timer will now be invoked and will keep the chip in reset an additional 72 ms. If V below BV

while the Power-up Timer is running, the

rises above

drops

chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once V above BV

, the Power-up Timer will execute a 72 ms

rises

time delay. The Power-up Timer should always be enabled when Brown-out Reset is enabled. Figure 9-8 shows typical Brown-out situations.

FIGURE 9-8: BROWN-OUT SITUATIONS

Internal

Reset

Internal

Reset

Internal

Reset

72 ms

<72 ms

72 ms

BVDD Max.

DD Min.

BVDD Max.

DD Min.

BVDD Max.

DD Min.

DS30559A-page 60

Preliminary

1996 Microchip Technology Inc.

PIC16C64X & PIC16C66X



9.4.5 PARITY ERROR RESET (PER) PIC16C64X & PIC16C66X devices have on-chip parity

bits that can be used to verify the contents of program memory. Parity bits may be useful in applications in order to increase overall reliability of a system.

There are two parity bits for each word of Program Memory. The parity bits are computed on alternating bits of the program word. One computation is performed using even parity, the other using odd parity. As a program executes, the parity is veriﬁed. The even parity bit is XOR’d with the even bits in the program memory word. The odd parity bit is negated and XOR’d with the odd bits in the program memory word. When an error is detected, a reset is generated and the PER ﬂag bit in the PCON register is set. This indication can allow software to act on a failure. However, there is no indication of the program memory location of the failure of the Program Memory. This ﬂag can only be cleared in software or by a POR.

The parity array is user selectable during programming. Bit7 of the conﬁguration word located at address 2007h can be programmed (read as '0') to disable parity checking. If left unprogrammed (read as '1'), parity checking is enabled.

9.4.6 TIME-OUT SEQUENCE

9.4.7 POWER CONTROL/STATUS REGISTER (PCON)

The power control/status register, PCON (address 8Eh) has four bits. See Figure 4-10 for register.

Bit0 is BOR Power-on-reset. It must initially be set by the user and checked on subsequent resets to see if BOR indicating that a Brown-out Reset has occurred. The BOR ily predictable if the brown-out circuit is disabled (by clearing the BODEN bit in the Conﬁguration word).

Bit1 is POR Power-on Reset and is unaffected otherwise. The user set this bit following a Power-on Reset. On subsequent resets if POR Reset must have occurred.

Bit2 is PER Error Reset and must be set by user software. It will also be set on a Power-on Reset.

Bit7 is MPEEN (Memory Parity Error Enable). This bit reﬂects the status of the MPEEN bit in conﬁguration word. It is unaffected by any reset or interrupt.

(Brown-out Reset). BOR is unknown on a

= '0'

status bit is a “don’t care” bit and is not necessar-

(Power-on Reset). It is cleared on a

is ‘0’, it will indicate that a Power-on

(Parity Error Reset). It is cleared on a Parity

On power-up, the time-out sequence is as follows: First PWRT time-out is invoked after POR has expired. Then the OST is activated. The total time-out will vary based on oscillator conﬁguration and P example, in RC mode with the PWR disabled), there will be no time-out at all. Figure 9-9, Figure 9-10 and Figure 9-11 depict time-out sequences.

Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR (Figure 9-10). This is useful for testing purposes or to synchronize more than one device operating in parallel.

Table 9-5 shows the reset conditions for some special registers, while Table 9-6 shows the reset conditions for all the registers.

high will begin execution immediately

WRTE bit status. For

TE bit set (PWRT

TABLE 9-3: TIME-OUT IN VARIOUS SITUATIONS

Power-up

Oscillator Conﬁguration

TE = 0 PWRTE = 1

PWR

XT, HS, LP 72 ms + 1024 T

OSC

1024 T

OSC

Brown-out Reset

72 ms + 1024 T

OSC

Wake-up

from SLEEP

1024 T

OSC

RC 72 ms — 72 ms —

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 61

PIC16C64X & PIC16C66X

TABLE 9-4: STATUS BITS AND THEIR SIGNIFICANCE

PER POR BOR TO PD

10x11Power-on Reset x0x0xIllegal, T x0xx0Illegal, PD 11011Brown-out Reset 11101WDT Reset 11100WDT Wake-up 111uuMCLR 11110MCLR 01111Parity Error Reset 00xxxIllegal, PER 0x0xxIllegal, PER

O is set on POR

is set on POR

reset during normal operation reset during SLEEP

is set on POR is set on BOR

TABLE 9-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS

Condition

Power-on Reset 000h 0001 1xxx u--- -10x MCLR

reset during normal operation 000h 000u uuuu u--- -uuu

Program Counter

STATUS

PCON

MCLR

reset during SLEEP 000h 0001 0uuu u--- -uuu WDT reset 000h 0000 1uuu u--- -uuu WDT Wake-up PC + 1 uuu0 0uuu u--- -uuu Brown-out Reset 000h 0001 1uuu u--- -uu0 Parity Error Reset 000h 0001 1uuu 1--- -0uu Interrupt Wake-up from SLEEP

Legend: Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the inter-

u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.

rupt vector (0004h) after execution of PC+1.

PC + 1

(1)

uuu1 0uuu u--- -uuu

DS30559A-page 62

Preliminary  1996 Microchip Technology Inc.

PIC16C64X & PIC16C66X

TABLE 9-6: INITIALIZATION CONDITION FOR REGISTERS

Wake up from SLEEP through:

- interrupt

- WDT time-out

Power-on Reset

Brown-out Reset

Parity Error Reset

MCLR Reset during:

- normal operation

- SLEEP or WDT Reset

W- xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h -- TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h 0000 0000 0000 0000

STATUS 03h 0001 1xxx

000q quuu

(3)

uuuq quuu

PC + 1

(2)

(3)

FSR 04h xxxx xxxx uuuu uuuu uuuu uuuu PORTA 05h --xx 0000 --xu 0000 --uu uuuu PORTB 06h xxxx xxxx uuuu uuuu uuuu uuuu PORTC 07h xxxx xxxx uuuu uuuu uuuu uuuu

PORTD PORTE

(4)

08h xxxx xxxx uuuu uuuu uuuu uuuu 09h ---- -xxx ---- -uuu ---- -uuu

CMCON 1Fh 00-- 0000 00-- 0000 uu-- uuuu PCLATH 0Ah ---0 0000 ---0 0000 ---u uuuu INTCON 0Bh 0000 000x 0000 000u

PIR1 0Ch 00-- ---- 00-- ----

uuuu uuuu uu-- ----

(1)

OPTION 81h 1111 1111 1111 1111 uuuu uuuu TRISA 85h --11 1111 --11 1111 --uu uuuu TRISB 86h 1111 1111 1111 1111 uuuu uuuu TRISC 87h 1111 1111 1111 1111 uuuu uuuu

TRISD TRISE

(4)

88h 1111 1111 1111 1111 uuuu uuuu 89h 0000 -111 0000 -111 uuuu -uuu

PIE1 8Ch 00-- ---- 00-- ---- uu-- ---- PCON 8Eh u--- -qqq u--- -uuu u--- -uuu VRCON 9Fh 000- 0000 000- 0000 uuu- uuuu Legend:

u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’,q = value depends on condition.

Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h). 3: See Table 9-5 for reset value for speciﬁc condition. 4: These registers are associated with the Parallel Slave Port and are not implemented on the PIC16C641/642.

 1996 Microchip Technology Inc. Preliminary DS30559A-page 63

PIC16C64X & PIC16C66X

FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

VDD

MCLR

INTERNAL POR

TPWRT

PWR

T TIME-OUT

OST TIME-OUT

INTERNAL RESET

FIGURE 9-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

VDD

TOST

MCLR

INTERNAL POR

TPWRT

T TIME-OUT

PWR

OST TIME-OUT

INTERNAL RESET

FIGURE 9-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR

VDD

MCLR

INTERNAL POR

TPWRT

PWR

T TIME-OUT

TOST

TIED TO VDD)

OST TIME-OUT

INTERNAL RESET

DS30559A-page 64 Preliminary  1996 Microchip Technology Inc.

PIC16C64X & PIC16C66X

FIGURE 9-12: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW VDD POWER-UP)

VDD

Note 1: External power-on reset circuit is required

only if V

MCLR

DD power-up slope is too slow.

PIC16CXXX

The diode D helps discharge the capacitor quickly when V

DD powers down.

2: R < 40 kΩ is recommended to make sure

that voltage drop across R does not violate the device’s electrical speciﬁcation.

3: R1 = 100Ω to 1 kΩ will limit any current

ﬂowing into MCLR from external capacitor C in the event of MCLR/

VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).

FIGURE 9-14: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 2

VDD

Note 1: This brown-out circuit is less expensive,

albeit less accurate. Transistor Q1 turns off when V

DD is below a certain level

such that:

VDD •

R1 + R2

2: Internal Brown-out Reset circuitry

should be disabled when using this circuit.

3: Resistors should be adjusted for the

characteristics of the transistor.

40k

VDD

MCLR

PIC16CXXX

= 0.7 V

FIGURE 9-13: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 1

VDD

33k

10k

40k

Note 1: This circuit will activate reset when VDD

goes below (Vz + 0.7V) where Vz = Zener voltage.

2: Internal Brown-out Reset circuitry

should be disabled when using this circuit.

3: Resistors should be adjusted for the

characteristics of the transistor.

MCLR

PIC16CXXX

 1996 Microchip Technology Inc. Preliminary DS30559A-page 65

PIC16C64X & PIC16C66X

9.5 Interrupts

The PIC16C641 and PIC16C642 have four sources of interrupt, while the PIC16C661 and PIC16C662 have five sources:

• External interrupt RB0/INT

• TMR0 overﬂow interrupt

• PORTB change interrupts (pins RB7:RB4)

• Comparator interrupt

• Parallel Slave Port interrupt (PIC16C661/662) The interrupt control register, (INTCON), records

individual core interrupt requests in ﬂag bits. It also has various individual enable bits and the global interrupt enable bit.

The global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in INTCON register. GIE is cleared on reset.

The “return from interrupt” instruction, the interrupt routine as well as sets the GIE bit, which allows any pending interrupt to execute.

Those interrupts associated with the “core” have their ﬂag and enable bits in the INTCON register. The core interrupts are: RB0/INT pin interrupt, the RB port change interrupt, and the TMR0 overﬂow interrupt. The INTCON register also contains the Peripheral Interrupt Enable bit, PEIE. Bit PEIE will enable/mask the peripheral interrupts (CM and PSP) from vectoring when bit PEIE is set/cleared.

Flag bits PSPIF and CMIF are contained in special function register PIR1. The corresponding interrupt enable bits (PSPIE and CMIE) are contained in special function register PIE1.

RETFIE, exits

When an interrupt is responded to, the GIE is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt ﬂag bits. The interrupt ﬂag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts.

For external interrupt events, such as the RB0/INT or Port RB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs (Figure 9-16). The latency is the same for one or two cycle instructions. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt ﬂag bits. The interrupt ﬂag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. Individual interrupt ﬂag bits are set regardless of the status of their corresponding mask bit or the GIE bit.

Note 1: Individual interrupt ﬂag bits are set regard-

less of the status of their corresponding mask bit or the GIE bit.

Note 2: When an instruction that clears the GIE bit

is executed, any interrupts that were pending for execution in the next cycle are ignored. The CPU will execute a NOP in the cycle immediately following the instruction which clears the GIE bit. The interrupts which were ignored are still pending to be serviced when the GIE bit is set again.

FIGURE 9-15: INTERRUPT LOGIC

T0IF T0IE

INTF

INTE

RBIF RBIE

GIE

CMIF

CMIE

(1)

PSPIF

(1)

PSPIE

Note 1: The Parallel Slave Port is implemented on the PIC16C661 and PIC16C662 only.

DS30559A-page 66 Preliminary  1996 Microchip Technology Inc.

PEIE

Wake-up (If in SLEEP mode)

Interrupt to CPU

PIC16C64X & PIC16C66X

9.5.1 RB0/INT INTERRUPT The external interrupt on the RB0/INT pin is edge trig-

gered: either rising if bit INTEDG (OPTION<6>) is set, or falling, if bit INTEDG is clear. When a valid edge appears on the RB0/INT pin, ﬂag bit INTF (INTCON<1>) is set. This interrupt can be enabled/disabled by setting/clearing enable bit INTE (INTCON<4>). The INTF bit must be cleared in software in the interrupt service routine before re-enabling this interrupt. The RB0/INT interrupt can wake-up the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of the GIE bit decides whether or not the processor branches to the interrupt vector following wake-up. See Section 9.8 for details on SLEEP and Figure 9-19 for timing of wake-up from SLEEP through RB0/INT interrupt.

9.5.2 TMR0 INTERRUPT An overﬂow (FFh → 00h) in the TMR0 register will

set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. For operation of the Timer0 module, see Section 6.0.

FIGURE 9-16: RB0/INT PIN INTERRUPT TIMING

9.5.3 PORTB INTERRUPT An input change on any bit of PORTB<7:4> sets ﬂag bit

RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<4>). For operation of PORTB (Section 5.2).

9.5.4 COMPARATOR INTERRUPT See Section 7.6 for complete description of the com-

parator interrupt.

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF ﬂag (INTCON<1>)

GIE bit (INTCON<7>)

INSTRUCTION FLOW

Instruction fetched

Instruction executed

Note

Inst (PC-1)

1: INTF ﬂag is sampled here (every Q1). 2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles.

Inst (PC)

PC+1

Inst (PC+1)

Inst (PC)

Interrupt Latency

PC+1

—

Dummy Cycle

0004h

Inst (0004h)

Dummy Cycle

0005h

Inst (0005h)

Inst (0004h)

 1996 Microchip Technology Inc. Preliminary DS30559A-page 67

PIC16C64X & PIC16C66X

9.6 Context Saving During Interrupts

During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt e.g. W register and STATUS register. This will have to be implemented in software.

Example 9-1 stores and restores the STATUS and W registers. The user register, W_TEMP, must be deﬁned in both banks and must be deﬁned at the same offset from the bank base address (i.e., W_TEMP is deﬁned at 0x70 - 0x7F in Bank 0). The user register, STATUS_TEMP, must be deﬁned in Bank 0.

Example 9-1:

• Stores the W register regardless of current bank

• Stores the STATUS register in Bank 0

• Executes the ISR code

• Restores the STATUS (and bank select bit register)

• Restores the W register

EXAMPLE 9-1: SAVING THE STATUS AND W REGISTERS IN RAM

MOVWF W_TEMP ; Copy W to a Temporary Register regardless of current bank SWAPF STATUS,W ; Swap STATUS nibbles and place into W register BCF STATUS,RP0 ; Change to Bank 0 regardless of current bank MOVWF STATUS_TEMP ; Save STATUS to a Temporary register in Bank 0 : : (Interrupt Service Routine) : SWAPF STATUS_TEMP,W ; Swap original STATUS register value into W (restores original bank) MOVWF STATUS ; Restore STATUS register from W register SWAPF W_TEMP,F ; Swap W_Temp nibbles and return value to W_Temp SWAPF W_TEMP,W ; Swap W_Temp to W to restore original W value without affecting STATUS

DS30559A-page 68 Preliminary  1996 Microchip Technology Inc.

PIC16C64X & PIC16C66X

9.7 Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components. The block diagram is shown in Figure 9-17. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. This means that the WDT will run, even if the clock on the OSC1 and OSC2 pins has been stopped, for example, by execution of a

SLEEP

instruction. During normal operation, a WDT time-out generates a device RESET. If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation, this is known as a WDT wake-up. The WDT can be permanently disabled by clearing conﬁguration bit WDTE (Section 9.1).

9.7.1 WDT PERIOD The WDT has a nominal time-out period of 18 ms, (with

no prescaler). The time-out period varies with temperature, V

and process variations from part to part (see DC specs). If longer time-outs are desired, a prescaler with a division ratio of up to 1:128 can be assigned to

FIGURE 9-17: WATCHDOG TIMER BLOCK DIAGRAM

From TMR0 Clock Source (Figure 7-6)

the WDT, under software control, by writing to the OPTION register. Thus, time-out periods of up to 2.3 seconds can be realized.

The

CLRWDT and SLEEP instructions clear the WDT and

the postscaler (if assigned to the WDT) and prevent it from timing out and generating a device RESET.

The T

O bit in the ST ATUS register will be cleared upon a Watchdog Timer time-out (WDT Reset and WDT wake-up).

9.7.2 WDT PROGRAMMING CONSIDERATIONS It should also be taken in account that under worst case

conditions (V

DD = Min., Temperature = Max., max.

WDT prescaler) it may take several seconds before a WDT time-out occurs.

Note: When the prescaler is assigned to the

WDT, always execute a CLRWDT instruction before changing the prescale value, otherwise a WDT reset may occur.

WDT Timer

WDT

Enable Bit

Note: PSA and PS2:PS0 are bits in the OPTION register.

U X

PSA

Postscaler

8 - to - 1 MUX

MUX

WDT

Time-out

PS2:PS0

To TMR0 (Figure 7-6)

PSA

FIGURE 9-18: SUMMARY OF WATCHDOG TIMER REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

2007h Conﬁg. bits 81h OPTION

MPEEN BODEN

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

(1)

CP1 CP0 PWRTE

Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Figure 9-1 for details of the operation of these bits.

(1)

WDTE FOSC1 FOSC0

 1996 Microchip Technology Inc. Preliminary DS30559A-page 69

PIC16C64X & PIC16C66X

9.8 Power-Down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP instruction.

If enabled, the Watchdog Timer will be cleared but keeps running, the PD cleared, the T

O bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the

SLEEP instruction was executed (driving

high, low, or hi-impedance). For lowest current consumption in this mode, all I/O

pins should be either at V circuitry drawing current from the I/O pin and the comparators and V

REF module should be disabled. I/O pins

that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by ﬂoating inputs. The T0CKI input should also be at V or VSS for lowest current consumption. The contribution from on chip pull-ups on PORTB should be considered.

The MCLR

pin must be at a logic high level (VIHMC).

9.8.1 WAKE-UP FROM SLEEP The device can wake-up from SLEEP through one of

the following events:

1. Any device reset

2. Watchdog Timer Wake-up (if WDT was enabled)

3. Interrupt from RB0/INT pin, RB Port change, or

the Comparator.

The ﬁrst event will reset the device upon wake-up. However the latter two events will wake the device and then resume program execution. The T the STATUS register can be used to determine the cause of device reset. The PD power-up is cleared when SLEEP is invoked. The T bit is cleared if WDT wake-up occurred.

bit in the STATUS register is

DD, or VSS, with no external

O and PD bits in

bit, which is set on

When the

SLEEP instruction is being executed, the

next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the

SLEEP instruction. If the GIE bit is

set (enabled), the device executes the instruction after the

SLEEP instruction and then branches to the inter-

rupt address (0004h). In cases where the execution of the instruction following user should have an

SLEEP is not desirable, the

NOP after the SLEEP instruction.

9.8.2 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit and interrupt ﬂag set, one of the following events will occur:

• If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as an NOP. Therefore, the WDT and WDT postscaler will not be cleared, the T be set and PD

bit will not be cleared.

O bit will not

• If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the T

O bit will be set and the PD bit will

be cleared.

Even if the ﬂag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD

bit. If the PD bit is set, the SLEEP instruction

was executed as an NOP. To ensure that the WDT is clear, a CLRWDT instruction

should be executed before a SLEEP instruction.

FIGURE 9-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

OST(2)

CLKOUT(4)

INT pin

INTF ﬂag (INTCON<1>)

GIE bit (INTCON<7>)

INSTRUCTION FLOW

Instruction fetched

Instruction executed

Note 1: XT, HS or LP oscillator mode assumed.

2: T 3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. 4: CLKOUT is not available in these osc modes, but shown here for timing reference.

DS30559A-page 70 Preliminary  1996 Microchip Technology Inc.

PC PC+1 PC+2

Inst(PC) = SLEEP

Inst(PC - 1)

OST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.

Inst(PC + 1)

SLEEP

Processor in

SLEEP

Interrupt Latency

(Note 2)

PC+2

Inst(PC + 2)

Inst(PC + 1)

PC + 2 0004h 0005h

Inst(0004h)

Dummy cycle

Inst(0005h)

Inst(0004h)

PIC16C64X & PIC16C66X

9.9 Code Protection

If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for veriﬁcation purposes.

Note: Microchip does not recommend code

protecting windowed devices.

9.10 ID Locations

Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code-identiﬁcation numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. Only the least signiﬁcant 4 bits of the ID locations are used.

9.11 In-Circuit Serial Programming

The PIC16CXX microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent ﬁrmware or a custom ﬁrmware to be programmed.

The device is placed into a program/verify mode by holding the RB6 and RB7 pins low while raising the MCLR

(VPP) pin from VIL to VIHH (see programming speciﬁcation). RB6 becomes the programming clock and RB7 becomes the programming data. Both RB6 and RB7 are Schmitt Trigger inputs in this mode.

After reset, to place the device into programming/verify mode, the program counter (PC) is at location 00h. A 6-bit command is then supplied to the device. Depending on the command, 14-bits of program data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC16C6X/7X Programming Speciﬁcations (Literature #DS30228).

A typical in-circuit serial programming connection is shown in Figure 9-20.

FIGURE 9-20: TYPICAL IN-CIRCUIT SERIAL

PROGRAMMING CONNECTION

To Normal

External Connector Signals

+5V

VPP

CLK

Data I/O

Connections

To Normal Connections

PIC16CXX

V VSS MCLR/VPP

RB6

RB7

VDD

 1996 Microchip Technology Inc. Preliminary DS30559A-page 71

PIC16C64X & PIC16C66X

NOTES:

DS30559A-page 72 Preliminary  1996 Microchip Technology Inc.



•

PIC16C64X & PIC16C66X

10.0 INSTRUCTION SET SUMMARY

Each PIC16CXX instruction is a 14-bit word divided into an OPCODE which speciﬁes the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 10-2 lists byte-oriented , bit-ori-

ented , and literal and control operations. Table 10-1

shows the opcode ﬁeld descriptions. For byte-oriented instructions, 'f' represents a ﬁle reg-

ister designator and 'd' represents a destination designator. The ﬁle register designator speciﬁes which ﬁle register is to be used by the instruction.

The destination designator speciﬁes where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register. If 'd' is one, the result is placed in the ﬁle register speciﬁed in the instruction.

For bit-oriented instructions, 'b' represents a bit ﬁeld designator which selects the number of the bit affected by the operation, while 'f' represents the number of the ﬁle in which the bit is located.

For literal and control operations, 'k' represents an eight or eleven bit constant or literal value.

TABLE 10-1: OPCODE FIELD

DESCRIPTIONS

Field Description

Register ﬁle address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit ﬁle register Literal ﬁeld, constant data or label Don't care location (= 0 or 1)

The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools.

Destination select; d = 0: store result in W, d = 1: store result in ﬁle register f. Default is d = 1

label Label name

TOS Top of Stack

Program Counter

PCLATH

Program Counter High Latch

GIE Global Interrupt Enable bit WDT Watchdog Timer/Counter

Time-out bit Power-down bit

dest Destination either the W register or the speciﬁed

[ ] Options

Contents

( )

Assigned to

→

< >

In the set of

∈

User deﬁned term (font is courier)

talics

Byte-oriented operations

• Bit-oriented operations

• Literal and control operations All instructions are executed within one single instruc-

tion cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 µ s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 µ s.

Table 10-2 lists the instructions recognized by the MPASM assembler.

Figure 10-1 shows the three general formats that the instructions can have.

Note: To maintain upward compatibility with

future PIC16CXX products, do not use

the

OPTION and TRIS instructions.

All examples use the following format to represent a hexadecimal number:

0xhh

where h signiﬁes a hexadecimal digit.

FIGURE 10-1: GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented ﬁle register operations

13 8 7 6 0

OPCODE d f (FILE #)

d = 0 for destination W d = 1 for destination f f = 7-bit ﬁle register address

Bit-oriented ﬁle register operations

13 10 9 7 6 0

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address f = 7-bit ﬁle register address

Literal and control operations General

13 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

CALL and GOTO instructions only

13 11 10 0

OPCODE k (literal)

k = 11-bit immediate value

The instruction set is highly orthogonal and is grouped into three basic categories:

1996 Microchip Technology Inc. DS30559A-page 73



PIC16C64X & PIC16C66X

10.1 Special Functi

on Registers as

Source/Destination

The PIC16C64X & PIC16C66X’s orthogonal instruction set allows read and write of all ﬁle registers, including special function registers. There are some special situations the user should be aware of:

10.1.1 STATUS AS DESTINATION If an instruction writes to STATUS, the Z, C, and DC bits

may be set or cleared as a result of the instruction and overwrite the original data bits written. For example, executing CLRF STATUS will clear register STATUS, and then set the Z bit leaving 0000 0100b in the register.

10.1.2 PCL AS SOURCE OR DESTINATION Read, write or read-modify-write on PCL may have the

following results: Read PC: PCL → dest Write PCL: PCLATH → PCH;

8-bit destination value → PCL

Read-Modify-Write: PCL → ALU operand

PCLATH → PCH; 8-bit result → PCL

Where PCH = program counter high byte (not an addressable register), PCLATH = Program counter high holding latch, dest = destination, WREG or f.

10.1.3 BIT MANIPULATION All bit manipulation instructions are done by ﬁrst read-

ing the entire register, operating on the selected bit and writing the result back (read-modify-write). The user should keep this in mind when operating on special function registers, such as ports.

DS30559A-page 74

1996 Microchip Technology Inc.

TABLE 10-2: INSTRUCTION SET



PIC16C64X & PIC16C66X

Mnemonic, Operands

BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF

ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF

BIT-ORIENTED FILE REGISTER OPERATIONS BCF

BSF BTFSC BTFSS

LITERAL AND CONTROL OPERATIONS ADDLW

ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW

Note 1: When an I/O register is modiﬁed as a function of itself ( e.g., MOVF PORTB, 1 ), the value used will be that value present

on the pins themselves. For example, if the data latch is '1' for a pin conﬁgured as input and is driven low by an external device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned

to the Timer0 Module.

3: If Program Counter (PC) is modiﬁed or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

Description Cycles 14-Bit Opcode Status

MSb LSb

f, d

Add W and f

f, d

AND W with f

Clear f

Clear W

f, d

Complement f

f, d

Decrement f

f, d

Decrement f, Skip if 0

f, d

Increment f

f, d

Increment f, Skip if 0

f, d

Inclusive OR W with f

f, d

Move f

Move W to f

No Operation

f, d

Rotate Left f through Carry

f, d

Rotate Right f through Carry

f, d

Subtract W from f

f, d

Swap nibbles in f

f, d

Exclusive OR W with f

f, b

Bit Clear f

f, b

Bit Set f

f, b

Bit Test f, Skip if Clear

f, b

Bit Test f, Skip if Set

Add literal and W

AND literal with W

Call subroutine

Clear Watchdog Timer

Go to address

Inclusive OR literal with W

Move literal to W

Return from interrupt

Return with literal in W

Return from Subroutine

Go into standby mode

Subtract W from literal

Exclusive OR literal with W

1 1 1 1 1 1

1(2)

1 1 1 1 1 1 1 1 1

1 1 (2) 1 (2)

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

01 01 01 01

11 11 10 00 10 11 11 00 11 00 00 11 11

0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110

00bb 01bb 10bb 11bb

111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010

dfff dfff lfff 0000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff

bfff bfff bfff bfff

kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk

ffff ffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff

ffff ffff ffff ffff

kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk

Affected

C,DC,Z Z Z Z Z Z

Z Z

C C C,DC,Z

C,DC,Z Z

PD C,DC,Z Z

Notes

1,2 1,2 2

1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2

1,2 1,2 1,2 1,2 1,2

1,2 1,2 3 3

1996 Microchip Technology Inc. DS30559A-page 75

PIC16C64X & PIC16C66X



10.2 Instruction Descriptions

ADDLW Add Literal and W

Syntax: [ Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Status Affected: C, DC, Z Encoding: Description:

Words: 1 Cycles: 1 Example

ADDWF Add W and f

Syntax: [ Operands: 0 ≤ f ≤ 127

Operation: (W) + (f) → (dest) Status Affected: C, DC, Z Encoding: Description:

Words: 1 Cycles: 1 Example

label

] ADDLW k

11 111x kkkk kkkk

The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register

ADDLW 0x15

Before Instruction

W = 0x10

After Instruction

W = 0x25

label

] ADDWF f,d

d ∈ [0,1]

00 0111 dfff ffff

Add the contents of the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'

ADDWF FSR, 0

Before Instruction

W = 0x17 FSR = 0xC2

After Instruction

W = 0xD9 FSR = 0xC2

ANDLW And Literal with W

Syntax: [ Operands: 0 ≤ k ≤ 255 Operation: (W) .AND. (k) → (W) Status Affected: Z Encoding: Description:

Words: 1 Cycles: 1 Example

ANDWF AND W with f

Syntax: [ Operands: 0 ≤ f ≤ 127

Operation: (W) .AND. (f) → (dest) Status Affected: Z Encoding: Description:

Words: 1 Cycles: 1 Example

label

] ANDLW k

11 1001 kkkk kkkk

The contents of W register are AND’ed with the eight bit literal 'k'. The result is placed in the W register

ANDLW 0x5F

Before Instruction

W = 0xA3

After Instruction

W = 0x03

label

] ANDWF f,d

d ∈ [0,1]

00 0101 dfff ffff

AND the W register with register 'f'. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'

ANDWF FSR, 1

Before Instruction

W = 0x17 FSR = 0xC2

After Instruction

W = 0x17 FSR = 0x02

DS30559A-page 76

1996 Microchip Technology Inc.

PIC16C64X & PIC16C66X

BCF Bit Clear f

label

Syntax: [

] BCF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7 Operation: 0 → (f<b>) Status Affected: None Encoding:

01 00bb bfff ffff

Description: Bit 'b' in register 'f' is cleared. Words: 1 Cycles: 1 Example

BCF FLAG_REG, 7

Before Instruction

FLAG_REG = 0xC7

After Instruction

FLAG_REG = 0x47

BSF Bit Set f

label

Syntax: [

] BSF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7 Operation: 1 → (f<b>) Status Affected: None Encoding: Description:

01 01bb bfff ffff

Bit 'b' in register 'f' is set.

Words: 1 Cycles: 1 Example

BSF FLAG_REG, 7

Before Instruction

FLAG_REG = 0x0A

After Instruction

FLAG_REG = 0x8A

BTFSC Bit Test, Skip if Clear

label

Syntax: [

] BTFSC f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7 Operation: skip if (f<b>) = 0 Status Affected: None Encoding: Description:

01 10bb bfff ffff

If bit 'b' in register 'f' is '0' then the next

instruction is skipped.

If bit 'b' is '0' then the next instruction

fetched during the current instruction

execution is discarded, and a NOP is

executed instead, making this a 2 cycle

instruction

. Words: 1 Cycles: 1(2) Example

HERE FALSE TRUE

BTFSC GOTO

•

FLAG,1 PROCESS_CODE

Before Instruction

PC = address HERE

After Instruction

if FLAG<1> = 0,

PC = address TRUE

if FLAG<1>=1,

PC = address FALSE

 1996 Microchip Technology Inc. DS30559A-page 77

PIC16C64X & PIC16C66X

BTFSS Bit Test f, Skip if Set

label

Syntax: [

] BTFSS f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b < 7 Operation: skip if (f<b>) = 1 Status Affected: None Encoding: Description:

01 11bb bfff ffff

If bit 'b' in register 'f' is '1' then the next

instruction is skipped.

If bit 'b' is '1', then the next instruction

fetched during the current instruction

execution, is discarded and a NOP is

executed instead, making this a 2 cycle

instruction.

Words: 1 Cycles: 1(2) Example

HERE FALSE TRUE

BTFSC GOTO

•

FLAG,1 PROCESS_CODE

Before Instruction

PC = address HERE

After Instruction

if FLAG<1> = 0, PC = address FALSE if FLAG<1> = 1, PC = address TRUE

CLRF Clear f

label

Syntax: [

] CLRF f Operands: 0 ≤ f ≤ 127 Operation: 00h → (f)

1 → Z Status Affected: Z Encoding: Description:

00 0001 1fff ffff

The contents of register 'f' are cleared

and the Z bit is set.

Words: 1 Cycles: 1 Example

CLRF FLAG_REG

Before Instruction

After Instruction

FLAG_REG = 0x5A

FLAG_REG = 0x00 Z=1

CALL Call Subroutine

label

Syntax: [

] CALL k Operands: 0 ≤ k ≤ 2047 Operation: (PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11> Status Affected: None Encoding: Description:

10 0kkk kkkk kkkk

Call Subroutine. First, return address

(PC+1) is pushed onto the stack. The

eleven bit immediate address is loaded

into PC bits <10:0>. The upper bits of

the PC are loaded from PCLATH.

CALL is a two cycle instruction.

Words: 1 Cycles: 2 Example

HERE CALL THERE

Before Instruction

PC = Address HERE

After Instruction

PC = Address THERE TOS= Address HERE+1

CLRW Clear W

label

Syntax: [

] CLRW Operands: None Operation: 00h → (W)

1 → Z Status Affected: Z Encoding: Description:

00 0001 0000 0011

W register is cleared. Zero bit (Z) is

set.

Words: 1 Cycles: 1 Example

CLRW

Before Instruction

After Instruction

W = 0x5A

W = 0x00 Z=1

DS30559A-page 78  1996 Microchip Technology Inc.

PIC16C64X & PIC16C66X

CLRWDT Clear Watchdog Timer

label

Syntax: [

] CLRWDT Operands: None Operation: 00h → WDT

0 → WDT prescaler,

1 → T

1 → PD Status Affected: TO, PD Encoding: Description:

00 0000 0110 0100

CLRWDT instruction resets the Watch-

dog Timer. It also resets the prescaler

of the WDT. Status bits TO and PD

are set.

Words: 1 Cycles: 1 Example

CLRWDT

Before Instruction

WDT counter = ?

After Instruction

WDT counter = 0x00 WDT prescaler= 0

TO =1 PD =1

DECF Decrement f

label

Syntax: [

] DECF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) - 1 → (dest) Status Affected: Z Encoding: Description:

00 0011 dfff ffff

Decrement register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd'

is 1 the result is stored back in register

'f'

. Words: 1 Cycles: 1 Example

DECF CNT, 1

Before Instruction

CNT = 0x01 Z=0

After Instruction

CNT = 0x00 Z=1

COMF Complement f

label

Syntax: [

] COMF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f

) → (dest) Status Affected: Z Encoding: Description:

00 1001 dfff ffff

The contents of register 'f' are complemented. If 'd' is 0 the result is stored in W. If 'd' is 1 the result is stored back in register 'f'.

Words: 1 Cycles: 1 Example

COMF REG1,0

Before Instruction

REG1 = 0x13

After Instruction

REG1 = 0x13 W = 0xEC

DECFSZ Decrement f, Skip if 0

label

Syntax: [

] DECFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) - 1 → (dest); skip if result = 0 Status Affected: None Encoding: Description:

00 1011 dfff ffff

The contents of register 'f' are decre-

mented. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

If the result is 0, the next instruction,

which is already fetched, is discarded. A

NOP is executed instead making it a two

cycle instruction.

Words: 1 Cycles: 1(2) Example

HERE DECFSZ CNT, 1 GOTO LOOP CONTINUE •

•

Before Instruction

PC = address HERE

After Instruction

CNT = CNT - 1 if CNT = 0, PC = address CONTINUE if CNT ≠ 0, PC = address HERE+1

 1996 Microchip Technology Inc. DS30559A-page 79

PIC16C64X & PIC16C66X

GOTO Unconditional Branch

label

Syntax: [

] GOTO k Operands: 0 ≤ k ≤ 2047 Operation: k → PC<10:0>

PCLATH<4:3> → PC<12:11> Status Affected: None Encoding: Description:

10 1kkk kkkk kkkk

GOTO is an unconditional branch. The

eleven bit immediate value is loaded

into PC bits <10:0>. The upper bits of

PC are loaded from PCLATH<4:3>.

GOTO is a two cycle instruction.

Words: 1 Cycles: 2 Example

GOTO THERE

After Instruction

PC = Address THERE

INCFSZ Increment f, Skip if 0

label

Syntax: [

] INCFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) + 1 → (dest), skip if result = 0 Status Affected: None Encoding: Description:

00 1111 dfff ffff

The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed

in the W register. If 'd' is 1 the result is

placed back in register 'f'.

If the result is 0, the next instruction,

which is already fetched, is discarded.

A NOP is executed instead making it a

two cycle instruction

. Words: 1 Cycles: 1(2) Example

HERE INCFSZ CNT, 1 GOTO LOOP CONTINUE •

•

Before Instruction

PC = address HERE

After Instruction

CNT = CNT + 1 if CNT= 0, PC = address CONTINUE if CNT≠ 0, PC = address HERE +1

INCF Increment f

label

Syntax: [

] INCF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) + 1 → (dest) Status Affected: Z Encoding: Description:

00 1010 dfff ffff

The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed

in the W register. If 'd' is 1 the result is

placed back in register 'f'.

Words: 1 Cycles: 1 Example

INCF CNT, 1

Before Instruction

CNT = 0xFF Z=0

After Instruction

CNT = 0x00 Z=1

IORLW Inclusive OR Literal with W

label

Syntax: [

] IORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. k → (W) Status Affected: Z Encoding: Description:

11 1000 kkkk kkkk

The contents of the W register is OR’ed with the eight bit literal 'k'. The result is placed in the W register

Words: 1 Cycles: 1 Example

IORLW 0x35

Before Instruction

W = 0x9A

After Instruction

W = 0xBF Z=1

DS30559A-page 80  1996 Microchip Technology Inc.

PIC16C64X & PIC16C66X

IORWF Inclusive OR W with f

label

Syntax: [

] IORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (W) .OR. (f) → (dest) Status Affected: Z Encoding: Description:

00 0100 dfff ffff

Inclusive OR the W register with regis-

ter 'f'. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Words: 1 Cycles: 1 Example

IORWF RESULT, 0

Before Instruction

RESULT = 0x13 W = 0x91

After Instruction

RESULT = 0x13 W = 0x93 Z=1

MOVLW Move Literal to W

label

Syntax: [

] MOVLW k Operands: 0 ≤ k ≤ 255 Operation: k → (W) Status Affected: None Encoding: Description:

11 00xx kkkk kkkk

The eight bit literal 'k' is loaded into W register

. The don’t cares will assemble

as 0’s.

Words: 1 Cycles: 1 Example

MOVLW 0x5A

After Instruction

W = 0x5A

MOVF Move f

label

Syntax: [

] MOVF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) → (dest) Status Affected: Z Encoding: Description:

00 1000 dfff ffff

The contents of register f is moved to

a destination dependant upon the sta-

tus of d. If d = 0, destination is W reg-

ister. If d = 1, the destination is ﬁle

ﬁle register since status ﬂag Z is

affected.

Words: 1 Cycles: 1 Example

MOVF FSR, 0

After Instruction

W = value in FSR register Z= 1

MOVWF Move W to f

label

Syntax: [

] MOVWF f Operands: 0 ≤ f ≤ 127 Operation: (W) → (f) Status Affected: None Encoding: Description:

00 0000 1fff ffff

Move data from W register to register 'f'

. Words: 1 Cycles: 1 Example

MOVWF OPTION

Before Instruction

OPTION = 0xFF W = 0x4F

After Instruction

OPTION = 0x4F W = 0x4F

 1996 Microchip Technology Inc. DS30559A-page 81

PIC16C64X & PIC16C66X

NOP No Operation

label

Syntax: [

] NOP Operands: None Operation: No operation Status Affected: None Encoding: Description:

00 0000 0xx0 0000

No operation.

Words: 1 Cycles: 1 Example

NOP

OPTION Load Option Register

Syntax: [

label

] OPTION

Operands: None

Operation: (W) → OPTION Status Affected: None Encoding: Description:

00 0000 0110 0010

The contents of the W register are loaded in the OPTION register. This instruction is supported for code compatibility with PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it.

Words: 1 Cycles: 1

Example

To maintain upward compatibility with future PIC16CXX products, do not use this instruction.

RETFIE Return from Interrupt

label

Syntax: [

] RETFIE Operands: None Operation: TOS → PC,

1 → GIE Status Affected: None Encoding: Description:

00 0000 0000 1001

Return from Interrupt. Stack is POPed

and Top of Stack (TOS) is loaded in

the PC. Interrupts are enabled by set-

ting Global Interrupt Enable bit, GIE

(INTCON<7>). This is a two cycle

instruction.

Words: 1 Cycles: 2 Example

RETFIE

After Interrupt

PC = TOS GIE = 1

RETLW Return with Literal in W

label

Syntax: [

] RETLW k Operands: 0 ≤ k ≤ 255 Operation: k → (W);

TOS → PC Status Affected: None Encoding: Description:

11 01xx kkkk kkkk

The W register is loaded with the eight

bit literal 'k'. The program counter is

loaded from the top of the stack (the

return address). This is a two cycle

instruction.

Words: 1 Cycles: 2 Example

CALL TABLE ;W contains table

;offset value

• ;W now has table value

•

TABLE

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2 ;

•

RETLW kn ; End of table

Before Instruction

W = 0x07

After Instruction

W = value of k8

DS30559A-page 82  1996 Microchip Technology Inc.

PIC16C64X & PIC16C66X

RETURN Return from Subroutine

label

Syntax: [

] RETURN Operands: None Operation: TOS → PC Status Affected: None Encoding: Description:

00 0000 0000 1000

Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction.

Words: 1 Cycles: 2 Example

RETURN

After Interrupt

PC = TOS

RRF Rotate Right f through Carry

label

Syntax: [

] RRF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: See description below Status Affected: C Encoding: Description:

00 1100 dfff ffff

The contents of register 'f' are rotated

one bit to the right through the Carry

Flag. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Words: 1 Cycles: 1 Example

RRF REG1,0

Before Instruction

REG1 = 1110 0110 C =0

After Instruction

REG1 = 1110 0110 W = 0111 0011 C =0

RLF Rotate Left f through Carry

label

Syntax: [

] RLF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: See description below Status Affected: C Encoding: Description:

00 1101 dfff ffff

The contents of register 'f' are rotated

one bit to the left through the Carry

Flag. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

stored back in register 'f'.

Words: 1 Cycles: 1 Example

RLF REG1,0

Before Instruction

REG1 = 1110 0110 C =0

After Instruction

REG1 = 1110 0110 W = 1100 1100 C =1

SLEEP

Syntax: [

label

] SLEEP Operands: None Operation: 00h → WDT,

0 → WDT prescaler,

1 → T

0 → PD Status Affected: TO, PD Encoding: Description:

00 0000 0110 0011

The power-down status bit, PD is

cleared. Time-out status bit, TO is

set. Watchdog Timer and its pres-

caler are cleared.

The processor is put into SLEEP

mode with the oscillator stopped.

See Power-Down Mode (SLEEP) for

more details.

Words: 1 Cycles: 1 Example: SLEEP

 1996 Microchip Technology Inc. DS30559A-page 83

PIC16C64X & PIC16C66X

SUBLW Subtract W from Literal

label

Syntax: [

] SUBLW k Operands: 0 ≤ k ≤ 255 Operation: k - (W) → (W) Status

C, DC, Z

Affected: Encoding: 11 110x kkkk kkkk Description:

The W register is subtracted (2’s complement method) from the eight bit literal 'k'. The result is placed in the W register.

Words: 1 Cycles: 1 Example 1: SUBLW 0x02

Before Instruction

W= 1 C=?

After Instruction

W= 1 C = 1; result is positive

Example 2: Before Instruction

W= 2 C=?

After Instruction

W= 0 C = 1; result is zero

Example 3: Before Instruction

W= 3 C=?

After Instruction

W = 0xFF C = 0; result is negative

SUBWF Subtract W from f

label

Syntax: [

] SUBWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) - (W) → (dest) Status

C, DC, Z Affected:

Encoding: 00 0010 dfff ffff Description:

Subtract (2’s complement method) W reg-

ister from register 'f'. If 'd' is 0 the result is

stored in the W register. If 'd' is 1 the

result is stored back in register 'f'.

Words: 1 Cycles: 1 Example 1: SUBWF REG1,1

Before Instruction

REG1 = 3 W=2 C=?

After Instruction

REG1 = 1 W=2 C = 1; result is positive

Example 2: Before Instruction

REG1 = 2 W=2 C=?

After Instruction

REG1 = 0 W=2 C = 1; result is zero

Example 3: Before Instruction

REG1 = 1 W=2 C=?

After Instruction

REG1 = 0xFF W=2 C = 0; result is negative

DS30559A-page 84  1996 Microchip Technology Inc.

PIC16C64X & PIC16C66X

SWAPF Swap Nibbles in f

label

Syntax: [

] SWAPF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f<3:0>) → (dest<7:4>),

(f<7:4>) → (dest<3:0>)

Status Affected: None

Encoding: Description:

The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0 the result is placed in W register. If 'd' is 1 the result is placed in register 'f'.

1110 dfff ffff

Words: 1 Cycles: 1 Example

SWAPF REG, 0

Before Instruction

REG1 = 0xA5

After Instruction

REG1 = 0xA5 W = 0x5A

XORLW Exclusive OR Literal with W

Syntax: [

label

] XORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Encoding: 11 1010 kkkk kkkk Description:

The contents of the W register are XOR’ed with the eight bit literal 'k'. The result is placed in the W register.

Words: 1 Cycles: 1 Example: XORLW 0xAF

Before Instruction

W = 0xB5

After Instruction

W = 0x1A

TRIS Load TRIS Register

Syntax: [

label

] TRIS f

Operands: 5 ≤ f ≤ 7

Operation: (W) → TRIS register f; Status Affected: None Encoding: Description:

0000 0110 0fff

The instruction is supported for code compatibility with the PIC16C5X products. Since TRIS registers are readable and writable, the user can directly address them.

Words: 1 Cycles: 1

Example

To maintain upward compatibility with future PIC16CXX products, do not use this instruction.

XORWF Exclusive OR W with f

label

Syntax: [

] XORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (W) .XOR. (f) → (dest) Status Affected: Z Encoding: Description:

00 0110 dfff ffff

Exclusive OR the contents of the W

result is stored in the W register. If 'd'

is 1 the result is stored back in register

'f'.

Words: 1 Cycles: 1 Example XORWF

REG 1

Before Instruction

REG = 0xAF W = 0xB5

After Instruction

REG = 0x1A W = 0xB5

 1996 Microchip Technology Inc. DS30559A-page 85

PIC16C64X & PIC16C66X

NOTES:

DS30559A-page 86  1996 Microchip Technology Inc.



−

PIC16C64X & PIC16C66X

11.0 DEVELOPMENT SUPPORT

11.1 De

The PIC16/17 microcontrollers are supported with a full range of hardware and software development tools:

• PICMASTER/PICMASTER CE Real-Time In-Circuit Emulator

• ICEPIC Low-Cost PIC16C5X and PIC16CXX In-Circuit Emulator

• PRO MATE

• PICSTART Programmer

• PICDEM-1 Low-Cost Demonstration Board

• PICDEM-2 Low-Cost Demonstration Board

• PICDEM-3 Low-Cost Demonstration Board

• MPASM Assembler

• MPLAB-SIM Software Simulator

• MPLAB-C (C Compiler)

• Fuzzy logic development system (fuzzyTECH

11.2 PICMASTER:

velopment Tools



II Universal Programmer



Plus Entry-Level Prototype



High Performance Universal In-Circuit Emulator with MPLAB IDE

MP)

11.3 I

CEPIC: Low-cost PIC16CXX In-Cir cuit

Emulator

ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC16C5X and PIC16CXX families of 8-bit OTP microcontrollers.

ICEPIC is designed to operate on PC-compatible machines ranging from 286-AT based machines under Windows 3.x environment. ICEPIC features real time, non-intrusive emulation.

11.4 PR

The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode.

The PRO MATE II has programmable V supplies which allows it to verify programmed memory at V

an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC16C5X, PIC16CXX, PIC17CXX and PIC14000 devices. It can also set conﬁguration and code-protect bits in this mode.

O MATE II: Universal Programmer

min and V

max for maximum reliability. It has



through Pentium 

and V

The PICMASTER Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXX and PIC17CXX families. PICMASTER is supplied with the MPLAB  Integrated Development Environment (IDE), which allows editing, “make” and download, and source debugging from a single environment.

Interchangeable target probes allow the system to be easily reconﬁgured for emulation of different processors. The universal architecture of the PICMASTER allows expansion to support all new Microchip microcontrollers.

The PICMASTER Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows ment were chosen to best make these features available to you, the end user.

A CE compliant version of PICMASTER is available for European Union (EU) countries.



3.x environ-

11.5 P

ICSTART Plus Entry Level

Development System

The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efﬁcient. PICST ART Plus is not recommended for production programming.

PICSTART Plus supports all PIC12C5XX, PIC14000, PIC16C5X, PIC16CXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923 and PIC16C924 may be supported with an adapter socket.

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 87



PIC16C64X & PIC16C66X

11.6 PICDEM-1

Low-Cost PIC16/17

Demonstration Board

The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE II or PICSTART-16B programmer, and easily test ﬁrmware. The user can also connect the PICDEM-1 board to the PICMASTER emulator and download the ﬁrmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB.

11.7 PICDEM-2

Low-Cost PIC16CXX

Demonstration Board

The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTAR T-16C, and easily test ﬁrmware. The PICMASTER emulator may also be used with the PICDEM-2 board to test ﬁrmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I tion to an LCD module and a keypad.

11.8 PICDEM-3

C bus and separate headers for connec-

Low-Cost PIC16CXX

Demonstration Board

The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and easily test ﬁrmware. The PICMASTER emulator may also be used with the PICDEM-3 board to test ﬁrmware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include

an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals. PICDEM3 will be available in the 3rd quarter of 1996.

11.9 MPLAB Integrated De

velopment

Environment Software

The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains:

• A full featured editor

• Three operating modes

- editor

- emulator

- simulator

• A project manager

• Customizable tool bar and key mapping

• A status bar with project information

• Extensive on-line help MPLAB allows you to:

• Edit your source ﬁles (either assembly or ‘C’)

• One touch assemble (or compile) and download to PIC16/17 tools (automatically updates all project information)

• Debug using:

- source ﬁles

- absolute listing ﬁle

• Transfer data dynamically via DDE (soon to be replaced by OLE)

• Run up to four emulators on the same PC

The ability to use MPLAB with Microchip’s simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools.

11.10 Assemb

The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXX, and PIC17CXX families.

MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers.

ler (MPASM)

DS30559A-page 88

Preliminary

1996 Microchip Technology Inc.





PIC16C64X & PIC16C66X

MPASM allows full symbolic debugging from the Microchip Universal Emulator System (PICMASTER).

MPASM has the following features to assist in developing software for speciﬁc use applications.

• Provides translation of Assembler source code to object code for all Microchip microcontrollers.

• Macro assembly capability.

• Produces all the ﬁles (Object, Listing, Symbol, and special) required for symbolic debug with Microchip’s emulator systems.

• Supports Hex (default), Decimal and Octal source and listing formats.

MPASM provides a rich directive language to support programming of the PIC16/17. Directives are helpful in making the development of your assemble source code shorter and more maintainable.

11.11 S

The MPLAB-SIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PIC16/17 series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode.

MPLAB-SIM fully supports symbolic debugging using MPLAB-C and MPASM. The Software Simulator offers the low cost ﬂexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.

11.12 C Compiler (

The MPLAB-C Code Development System is a complete ‘C’ compiler and integrated development environment for Microchip’s PIC16/17 family of microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with other compilers.

For easier source level debugging, the compiler provides symbol information that is compatible with the MPLAB IDE memory display (PICMASTER emulator software versions 1.13 and later).

oftware Simulator (MPLAB-SIM)

MPLAB-C)

Both versions include Microchip’s stration board for hands-on experience with fuzzy logic systems implementation.

11.14 MP-DriveW

fuzzy

LAB  demon-

– Application Code

Generator

MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can visually conﬁgure all the peripherals in a PIC16/17 device and, with a click of the mouse, generate all the initialization and many functional code modules in C language. The output is fully compatible with Microchip’s MPLAB-C C compiler. The code produced is highly modular and allows easy integration of your own code. MP-DriveWay is intelligent enough to maintain your code through subsequent code generation.



11.15 SEEV

aluation and

Programming System

The SEEVAL SEEPROM Designer ’s Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart Serials  and secure serials. The Total Endurance  Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can signiﬁcantly reduce time-to-market and result in an optimized system.

11.16 T

rueGauge



Intellig

ent Battery

Management

The TrueGauge development tool supports system development with the MTA11200B TrueGauge Intelligent Battery Management IC. System design veriﬁcation can be accomplished before hardware prototypes are built. User interface is graphically-oriented and measured data can be saved in a ﬁle for exporting to Microsoft Excel.



11.17 K

aluation and

Programming Tools

evaluation and programming tools support

Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters.

11.13 Fuzzy Logic De

(

fuzzy

TECH-MP)

fuzzy

TECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, menting more complex systems.

1996 Microchip Technology Inc.

velopment System

fuzzy

TECH-MP, edition for imple-

Preliminary

DS30559A-page 89











PIC16C64X & PIC16C66X

TABLE 11-1: DEVELOPMENT TOOLS FROM MICROCHIP

Plus

Dev. Kit

Universal

Low-Cost

PICSTART

Lite

Dev. Kit

Ultra Low-Cost

PICSTART

Microchip

II Universal

Programmer

****PRO MATE



ICEPIC /

*** PICMASTER

-MP

fuzzyTECH

MP-DriveWay C

MPLAB

— DV007003 — DV003001

Emulator

In-Circuit

Low-Cost

Emulator

In-Circuit

EM167101

PICMASTER-CE

Dev . T ool

Fuzzy Logic

Explorer/Edition

Code

Generator

Applications

Compiler

— DV007003 — DV003001

EM167201 DV007003 DV162003 DV003001

EM147101

EM167015/

—- DV007003 — DV003001

EM167113

EM167101

EM167033/

DV005002

EM167205 DV007003 DV162003 DV003001

EM167203 DV007003 DV162002 DV003001

N/A

EM167103

EM167021/

EM167025/

DV005002

EM167202 DV007003 DV162003 DV003001

EM167204 DV007003 DV162002 DV003001

EM167109

EM167103

EM167023/

EM167025/

DV005002

—- DV007003 DV162002 DV003001

EM167205 DV007003 DV162003 DV003001

EM167105

EM167027/

— DV007003 DV162003 DV003001

EM167105

EM167027/

DV005002

— DV007003 DV162002 DV003001

— DV007003 DV162003 DV003001

EM167103

EM167107

EM167029/

DV005002

— DV007003 DV162003 DV003001

EM167206 DV007003 DV162003 DV003001

EM167107

EM167029/

DV005002

— DV007003 — DV003001

EM167111

EM177107

EM167031/

EM177007/

DV005002

***All PICMASTER and PICMASTER-CE ordering part numbers above include

PRO MATE II programmer

****PRO MATE socket modules are ordered separately. See development systems

ordering guide for speciﬁc ordering part numbers

Designers Kit Hopping Code Security Programmer Kit Hopping Code Security Eval/Demo Kit

Development Kit SEEVAL

N/A DV243001 N/A N/A

Integrated

Environment

Development

Product ** MPLAB

PIC12C508, 509 SW007002 SW006005 — — EM167015/

DS30559A-page 90

SW007002 SW006005 SW006006 DV005001/

PIC14000 SW007002 SW006005 — — EM147001/

PIC16C52, 54, 54A,

55, 56, 57, 58A

PIC16C61 SW007002 SW006005 SW006006 DV005001/

PIC16C554, 556, 558 SW007002 SW006005 — DV005001/

SW007002 SW006005 SW006006 DV005001/

PIC16C62, 62A,

64, 64A

PIC16C620, 621, 622 SW007002 SW006005 SW006006 DV005001/

SW007002 SW006005 SW006006 DV005001/

PIC16C63, 65, 65A,

SW007002 SW006005 — — EM167035/

PIC16C71 SW007002 SW006005 SW006006 DV005001/

662*

PIC16C710, 711 SW007002 SW006005 SW006006 DV005001/

73, 73A, 74, 74A

PIC16C641, 642, 661,

Preliminary

PIC16C72 SW007002 SW006005 SW006006 — EM167025/

PIC16F83 SW007002 SW006005 SW006006 DV005001/

PIC16C84 SW007002 SW006005 SW006006 DV005001/

PIC16F84 SW007002 SW006005 SW006006 DV005001/

SW007002 SW006005 SW006006 DV005001/

Product TRUEGAUGE

PIC16C923, 924* SW007002 SW006005 SW006006 DV005001/

PIC17C42,

42A, 43, 44

*Contact Microchip Technology for availability date

**MPLAB Integrated Development Environment includes MPLAB-SIM Simulator and

MPASM Assembler

1996 Microchip Technology Inc.

All 2 wire and 3 wire

Serial EEPROM's

MTA11200B DV114001 N/A N/A N/A

HCS200, 300, 301 * N/A N/A PG306001 DM303001



)

†

PIC16C64X & PIC16C66X

12.0 ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings †

Ambient Temperature under bias............................................................................................................. –40 ° to +125 ° C

Storage Temperature ............................................................................................................................... –65 ° to +150 ° C

(except V

Voltage on any pin with respect to V Voltage on V Voltage on MCLR

with respect to V

................................................................................................................ 0 to +7.5V

(Note 2) .................................................................................................0 to +14V

Total power Dissipation (Note 1) ...............................................................................................................................1.0W

Maximum Current out of V Maximum Current into V Input Clamp Current, I Output Clamp Current, I

pin ..........................................................................................................................300 mA

pin .............................................................................................................................250 mA

<0 or V

(Vo <0 or Vo>V

> V

.......................................................................................................................± 20 mA

Maximum Output Current sunk by any I/O pin........................................................................................................25 mA

Maximum Output Current sourced by any I/O pin...................................................................................................25 mA

Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 2)...................................................200 mA

Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 2)..............................................200 mA

Maximum current sunk by PORTC and PORTD (combined) (Note 2)..................................................................200 mA

Maximum current sourced by PORTC and PORTD (combined) (Note 2).............................................................200 mA

Note 1: Power dissipation is calculated as follows: P Note 2: PORTD and PORTE are not implemented on the PIC16C641 and PIC16C642.

and MCLR

) .....................................................–0.3V to V

+ 0.3V

................................................................................................................± 20 mA

= V

x {I

DIS

- ∑ I

} + ∑ {(V

-V

) x I

} + ∑ (V

l x I

NOTICE : Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

TABLE 12-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS

AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)

PIC16C641-04

OSC

RC V

XT V

PIC16C642-04 PIC16C661-04 PIC16C662-04

: 4.0V to 6.0V

: 5 mA max. @ 5.5V

I I

: 21 µ A max. @ 4.0V

Freq: 4.0 MHz max.

: 4.0V to 6.0V

: 5 mA max. @ 5.5V

I I

: 21 µ A max. @ 4.0V

Freq: 4.0 MHz max. V

: 4.5V to 5.5V

: 13.5 mA typ. @ 5.5V

I I

: 1.5 µ A typ. @ 4.5V

Freq: 4.0 MHz max. V

: 4.0V to 6.0V

: 52.5 µ A typ. @

32 kHz, 4.0V

: 0.9 µ A typ. @ 4.0V

Freq: 200 kHz max.

The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX speciﬁcations. It is recommended that the user select the device type that ensures the speciﬁcations required.

PIC16C641-10 PIC16C642-10 PIC16C661-10 PIC16C662-10

: 4.5V to 5.5V

: 2.7 mA typ. @ 5.5V

I I

: 1.5 µ A typ. @ 4.0V

Freq: 4.0 MHz max. V

: 4.5V to 5.5V

: 2.7 mA typ. @ 5.5V

I I

: 1.5 µ A typ. @ 4.0V

Freq: 4.0 MHz max. V

: 4.5V to 5.5V

: 30 mA max. @ 5.5V

I I

: 1.5 µ A typ. @ 4.5V

Freq: 10 MHz max. Do not use in LP mode Do not use in LP mode V

PIC16C641-20 PIC16C642-20 PIC16C661-20 PIC16C662-20

: 4.5V to 5.5V

: 2.7 mA typ. @ 5.5V

I I

: 1.5 µ A typ. @ 4.0V

Freq: 4.0 MHz max. V

: 4.5V to 5.5V

: 2.7 mA typ. @ 5.5V

I I

: 1.5 µ A typ. @ 4.0V

Freq: 4.0 MHz max. V

: 4.5V to 5.5V

: 30 mA max. @ 5.5V

I I

: 1.5 µ A typ. @ 4.5V

Freq: 20 MHz max.

PIC16LC641-04 PIC16LC642-04 PIC16LC661-04 PIC16LC662-04

: 3.0V to 6.0V

: 2.0 mA typ. @ 3.0V

I I

: 0.9 µ A typ. @ 3.0V

Freq: 4.0 MHz max. V

: 3.0V to 6.0V

: 2.0 mA typ. @ 3.0V

I I

: 0.9 µ A typ. @ 3.0V

Freq: 4.0 MHz max. Do not use in HS mode V

: 3.0V to 6.0V

: 48 µ A max. @

32 kHz, 3.0V

: 5.0 µ A max. @ 3.0V

Freq: 200 kHz max.

JW Devices

: 4.0V to 6.0V

: 5 mA max. @ 5.5V

I I

: 21 µ A max. @ 4.0V

Freq: 4.0 MHz Max. V

: 4.0V to 6.0V

: 5 mA max. @ 5.5V

I I

: 21 µ A max. @ 4.0V

Freq: 4.0 MHz max.

: 4.5V to 5.5V

: 30 mA max. @ 5.5V

I I

: 1.5 µ A typ. @ 4.5V

Freq: 10 MHz max.

: 3.0V to 6.0V

: 48 µ A max. @

32 kHz, 3.0V

: 5.0 µ A max. @ 3.0V

Freq: 200 kHz max.

1996 Microchip Technology Inc.

Preliminary

DS30559A-page 91



≤

PIC16C64X & PIC16C66X

12.1 DC Characteristics: PIC16C641/642/661/662-04 (Commercial, Industrial, Automotive) PIC16C641/642/661/662-10 (Commercial, Industrial, Automotive) PIC16C641/642/661/662-20 (Commercial, Industrial, Automotive)

Standard Operating Conditions (unless otherwise stated) Operating temperature –40 ° C ≤ T

0 ° C ≤ T –40 ° C ≤ T

Param

Sym Characteristic Min Typ† Max Units Conditions

No.

D001

Supply Voltage 4.0

D001A D002* V D003 V

DR POR

RAM Data Retention Voltage V

start voltage to

(1)

1.5 – – V Device in SLEEP mode

ensure internal Power-on Reset signal

D004* S

VDD

rise rate to ensure internal

Power-on Reset signal

D005 V

D010 I

BOR

Brown-out Reset Voltage 3.7

Supply Current

(2)

D010A – 35 70 µA LP osc conﬁguration,

D013 – 13.5 30 mA HS osc conﬁguration

Module Differential Current

(5)

D015 ∆IBOR Brown-out Reset Current – 350 425 µA BODEN bit is clear, VDD = 5.0V D016 ∆I

COMP Comparator Current for

each Comparator D017 ∆I D021 ∆I

D021 I

VREF VREF Current – – 300 µAVDD = 4.0V WDT WDT Current –

Power-down Current

(3)

* These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: This is the limit to which V

DD can be lowered in SLEEP mode without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all I

DD measurements in active operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to V MCLR

= VDD; WDT enabled/disabled as speciﬁed.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to V

4: For RC osc conﬁguration, current through Rext is not included. The current through the resistor can be

estimated by the formula Ir = V

DD/2Rext (mA) with Rext in kΩ.

5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be

added to the base I

DD or IPD measurement.

+85 ° C for industrial,

A A

+70 ° C commercial, and

+125 ° C automotive

––6.0

4.5

–V

5.5VV

– V See section on Power-on Reset for

XT, RC and LP osc conﬁguration HS osc conﬁguration

details

0.05 – – V/ms See section on Power-on Reset for details

4.0

3.7

4.0

4.3

4.4VV

BODEN conﬁguration bit is clear Automotive

– 2.7 5 mA XT and RC osc conﬁguration

OSC = 4 MHz, VDD = 5.5V,

WDT disabled

(4)

PIC16C64X & PIC16C66X-04 only F

OSC = 32 kHz, VDD = 4.0V,

WDT disabled

OSC = 20 MHz, VDD = 5.5V,

WDT disabled

– – 100 µAVDD = 4.0V

6.0–2025µAµAVDD = 4.0V

– –

1.5

–

2.52124µAµA

Automotive VDD = 4.0V, WDT disabled

Automotive

DD,

DD or VSS.

≤

DS30559A-page 92

Preliminary

1996 Microchip Technology Inc.

PIC16C64X & PIC16C66X

12.2 DC Characteristics: PIC16LC641/642/661/662-04 (Commercial, Industrial)

Standard Operating Conditions (unless otherwise stated)

Param

No. D001 V D002* V

D003 V

D004* S

D005 V D010

Operating temperature –40°C ≤ T

0°C ≤ T

Sym Characteristic Min Typ† Max Units Conditions

DD Supply Voltage 3.0 – 6.0 V XT, RC, and LP osc conﬁguration DR RAM Data Retention

Voltage

POR VDD start voltage to

(1)

ensure internal Power-on Reset signal

VDD VDD rise rate to ensure internal

Power-on Reset signal

BOR Brown-out Reset Voltage 3.7 4.0 4.3 V BODEN conﬁguration bit is clear

Supply Current

(2)

A ≤ +85°C for industrial and A ≤ +70°C commercial

1.5 – – V Device in SLEEP mode

–VSS – V See section on Power-on Reset for

details

0.05 – – V/ms See section on Power-on Reset for details

–

2.0

3.848mAµAXT and RC osc conﬁguration F

OSC = 4.0 MHz, VDD = 3.0V,

WDT disabled

(4)

D010A

–

22.5

LP osc conﬁguration F

OSC = 32 kHz, VDD = 3.0V,

WDT disabled

Module Differential Current

(5)

D015 ∆IBOR Brown-out Reset Current – 350 425 µA BODEN bit is clear, VDD = 5.0V D016 ∆I

COMP Comparator Current for

– – 100 µAVDD = 3.0V

each Comparator D017 ∆I D021 ∆I D021 I

VREF VREF Current – – 300 µAVDD = 3.0V WDT WDT Current – 6.0 20 µAVDD = 3.0V

Power-down Current

(3)

– 0.9 5 µAVDD = 3.0V, WDT disabled

* These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: This is the limit to which V

DD can be lowered in SLEEP mode without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all I OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to V MCLR

= VDD; WDT enabled/disabled as speciﬁed.

DD measurements in active operation mode are:

DD,

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to V

DD or VSS.

4: For RC osc conﬁguration, current through Rext is not included. The current through the resistor can be

estimated by the formula Ir = V

DD/2Rext (mA) with Rext in kΩ.

5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be

added to the base I

DD or IPD measurement.

 1996 Microchip Technology Inc. Preliminary DS30559A-page 93

PIC16C64X & PIC16C66X

12.3 DC Characteristics: PIC16C641/661 (Commercial, Industrial, Automotive) PIC16C642/662 (Commercial, Industrial, Automotive) PIC16LC641/661 (Commercial, Industrial) PIC16LC642/662 (Commercial, Industrial)

Standard Operating Conditions (unless otherwise stated) Operating temperature –40°C ≤ T

0°C ≤ T –40°C ≤ T

Param

Operating voltage V

Sym Characteristic Min Typ

DD range as described in DC spec Section 12.1 and 12.2

No.

IL Input Low Voltage

I/O ports

D030 with TTL buffer V

D031 with Schmitt Trigger input V D032 MCLR

, RA4/T0CKI,OSC1 (in

RC mode)

D033 OSC1 (XT and HS modes) Vss - 0.3VDD V

OSC1 (LP modes) Vss - 0.6V

IH Input High Voltage

I/O ports D040 with TTL buffer 2.0 - V D041 with Schmitt Trigger input 0.25V

D042 MCLR D043

D043A

RA4/T0CKI 0.8VDD -VDD V

OSC1 (XT, HS, LP modes)

OSC1 (RC mode) D070 IPURB PORTB weak pull-up current 50 200 400 µAVDD = 5.0V, VPIN = VSS

IIL

Input Leakage Current

(2,3)

I/O ports (Except PORTA)

D060 PORTA - - ±0.5 µA Vss ≤ V

D061 RA4/T0CKI - - ±1.0 µA Vss ≤ V D063 OSC1, MCLR --±5.0 µA Vss ≤ VPIN ≤ VDD, XT, HS and LP

OL Output Low Voltage

D080 I/O ports - - 0.6 V I

D083 OSC2/CLKOUT - - 0.6 V I

(RC only) - - 0.6 V I

* These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and

are not tested.

Note 1: In RC oscillator conﬁguration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the

PIC16C64X & PIC16C66X be driven with external clock in RC mode.

2: The leakage current on the MCLR

pin is strongly dependent on applied voltage level. The speciﬁed levels repre-

sent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is deﬁned as coming out of the pin.

A ≤ +85°C for industrial, A ≤ +70°C commercial, and A ≤ +125°C automotive

Max Unit Conditions

†

VSS

SS - 0.2VDD V

0.15VDD

0.8V

Vss - 0.2VDD V

DD-1.0 V

DD V

-VDD V

to 0.8V

0.7V

0.9VDD

VDD

--±1.0 µAV

- - 0.6 V I

VVFor entire V

4.5V ≤ V

(1)

SS ≤ VPIN ≤ VDD,

DD range

DD ≤ 5.5V

pin at hi-impedance

PIN ≤ VDD,

pin at hi-impedance

PIN ≤ VDD

osc conﬁguration

OL = 8.5 mA, VDD = 4.5V,

-40° to +85°C

OL = 7.0 MA, VDD = 4.5V, +125°C OL = 1.6 mA, VDD = 4.5V,

-40° to +85°C

OL = 1.2 mA, VDD = 4.5V, +125°C

DS30559A-page 94 Preliminary  1996 Microchip Technology Inc.

PIC16C64X & PIC16C66X

Standard Operating Conditions (unless otherwise stated) Operating temperature –40°C ≤ T

0°C ≤ T –40°C ≤ T

Param

Operating voltage V

Sym Characteristic Min Typ

DD range as described in DC spec Section 12.1 and 12.2

No.

VOH

Output High Voltage

(3)

D090 I/O ports (Except RA4) VDD-0.7 - - V IOH = -3.0 mA, VDD = 4.5V,

D092 OSC2/CLKOUT V

(RC only)

Capacitive Loading Specs on Output Pins

D100 C

D101 C

OSC2 OSC2 pin - - 15 pF In XT, HS and LP modes when

IO All I/O pins/OSC2 (in RC mode) - - 50 pF

* These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and

are not tested.

Note 1: In RC oscillator conﬁguration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the

PIC16C64X & PIC16C66X be driven with external clock in RC mode.

2: The leakage current on the MCLR

pin is strongly dependent on applied voltage level. The speciﬁed levels repre-

sent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is deﬁned as coming out of the pin.

A ≤ +85°C for industrial, A ≤ +70°C commercial, and A ≤ +125°C automotive

Max Unit Conditions

†

-40° to +85°C

DD-0.7 - - V IOH = -2.5 mA,

DD = 4.5V, +125°C

DD-0.7 - - V IOH = -1.3 mA, VDD=4.5V,

-40° to +85°C

DD-0.7 - - V IOH = -1.0 mA,

DD = 4.5V, +125°C

external clock used to drive OSC1.

 1996 Microchip Technology Inc. Preliminary DS30559A-page 95

PIC16C64X & PIC16C66X

TABLE 12-2: COMPARATOR SPECIFICATIONS

Operating Conditions: 3.0V < VDD < 6.0V, -40˚C < T A < +125˚C, unless otherwise stated. Current consumption is spec- iﬁed in Table 12-1.

Characteristics Sym Min Typ Max Units Comments

Input offset voltage - ± 5.0 ± 10 mV Input common mode voltage* 0 - V CMRR* 35 - - db

Response Time

Comparator Mode Change to Output Valid*

* These parameters are characterized but not tested.

Note 1: Response time measured with one comparator input at (V

(1)*

SS to VDD.

- 150 400

-- 10µs

TABLE 12-3: VOLTAGE REFERENCE SPECIFICATIONS

Operating Conditions: 3.0V < VDD < 6.0V , -40°C < TA < +125°C, unless otherwise stated. Current consumption is speciﬁed in Table 12-1.

DD - 1.5 V

nsnsPIC16C64X/66X

600

DD - 1.5)/2 while the other input transitions from

PIC16LC64X/66X

Characteristics Sym Min Typ Max Units Comments

Resolution V Absolute Accuracy -

Unit Resistor Value (R)* - 2k - Ω Settling Time

* These parameters are characterized but not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.

(1)*

DD/24 - VDD/32 LSb

- - 10 µs

1/4 1/2

LSb LSb

Low Range (VRR = 1) High Range (VRR = 0)

Figure 8-2

DS30559A-page 96 Preliminary  1996 Microchip Technology Inc.

PIC16C64X & PIC16C66X

12.4 Timing Parameter Symbology

The timing parameter symbols have been created with one of the following formats:

1. TppS2ppS

2. TppS T F Frequency T Time Lowercase subscripts (pp) and their meanings: pp ck CLKOUT osc OSC1 io I/O port t0 T0CKI mc MCLR Uppercase letters and their meanings: S F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-Impedance

FIGURE 12-1: LOAD CONDITIONS

Load condition 1

VDD/2

Pin Pin

RL = 464Ω

L = 50 pF for all pins except OSC2

15 pF for OSC2 output

Load condition 2

VSS

 1996 Microchip Technology Inc. Preliminary DS30559A-page 97

PIC16C64X & PIC16C66X

12.5 Timing Diagrams and Speciﬁcations

FIGURE 12-2: EXTERNAL CLOCK TIMING

OSC1

CLKOUT

Q1 Q2

133

Q3 Q4 Q1

TABLE 12-4: EXTERNAL CLOCK TIMING REQUIREMENTS

Param

No.

1 Tosc External CLKIN Period

3* TosL,

4* TosR,

* These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only

Note 1: Instruction cycle period (T

Sym Characteristic Min Typ† Max Units Conditions

(1)

Fosc External CLKIN Frequency

DC — 4 MHz XT and RC osc mode,

DD = 5.0V

DC — 20 MHz HS osc mode DC — 200 kHz LP osc mode

Oscillator Frequency

(1)

DC — 4 MHz RC osc mode, VDD = 5.0V

0.1 — 4 MHz XT osc mode 4 — 20 MHz HS osc mode 5 – 200 kHz LP osc mode

(1)

250 — — ns XT and RC osc mode

50 — — ns HS osc mode

5——µs LP osc mode

Oscillator Period

(1)

250 — — ns RC osc mode 250 — 10,000 ns XT osc mode

50 — 250 ns HS osc mode

5——µs LP osc mode

CY Instruction Cycle Time

External Clock in (OSC1)

TosH

High or Low Time

(1)

200 — DC ns TCY = FOSC/4 100 — — ns XT osc mode

2.5 — — µs LP osc mode

15 — — ns HS osc mode

TosF

External Clock in (OSC1) Rise or Fall Time

— — 25 ns XT osc mode — — 50 ns LP osc mode — — 15 ns HS osc mode

and are not tested.

CY) equals four times the input oscillator time-base period. All speciﬁed values are

based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these speciﬁed limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices.

DS30559A-page 98 Preliminary  1996 Microchip Technology Inc.

FIGURE 12-3: CLKOUT AND I/O TIMING

PIC16C64X & PIC16C66X

OSC1

CLKOUT

I/O Pin (input)

I/O Pin (output)

Note: See Figure 12-1 for load conditions.

old value

20, 21

22 23

Q2 Q3

new value

TABLE 12-5: CLKOUT AND I/O TIMING REQUIREMENTS

Parameter

No.

10* TosH2ckL OSC1↑ to CLKOUT↓ — 75 200 ns Note 1 11* TosH2ckH OSC1↑ to CLKOUT↑ — 75 200 ns Note 1 12* TckR CLKOUT rise time — 35 100 ns Note 1 13* TckF CLKOUT fall time — 35 100 ns Note 1 14* TckL2ioV CLKOUT ↓ to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT ↑ TOSC + 200 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT ↑ 0 — — ns Note 1 17* TosH2ioV OSC1↑ (Q1 cycle) to

18* TosH2ioI OSC1↑ (Q2 cycle) to

19* TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 — — ns 20* TioR Port output rise time PIC16C64X/66X — 10 40 ns

21* TioF Port output fall time PIC16C64X/66X — 10 40 ns

22††* Tinp INT pin high or low time T 23††* Trbp RB7:RB4 change INT high or low time TCY ——ns

Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.

Sym Characteristic Min Typ† Max Units Conditions

— 50 150 ns

Port out valid

PIC16C64X/66X 100 — — ns Port input invalid (I/O in hold time)

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance

only and are not tested.

†† These parameters are asynchronous events not related to any internal clock edges.

PIC16LC64X/66X 200 — — ns

PIC16LC64X/66X — — 80 ns

CY ——ns

 1996 Microchip Technology Inc. Preliminary DS30559A-page 99

PIC16C64X & PIC16C66X

FIGURE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP

TIMER TIMING

VDD

MCLR

Internal

POR

PWRT

Timeout

OSC

Timeout

Internal

RESET Parity

Error Reset

Watchdog

Timer

RESET

I/O Pins

FIGURE 12-5: BROWN-OUT RESET TIMING

VDD

BVDD

TABLE 12-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,

AND BROWN-OUT RESET REQUIREMENTS

Parameter

No.

30 TmcL MCLR Pulse Width (low) 2 — — µsVDD = 5V, -40˚C to +125˚C

31* Twdt Watchdog Timer Time-out Period

32 Tost Oscillation Start-up Timer Period — 1024TOSC ——TOSC = OSC1 period

33* Tpwrt Power up Timer Period 28 72 132 ms VDD = 5V, -40˚C to +125˚C

34 TIOZ I/O Hi-impedance from MCLR Low

35 TBOR Brown-out Reset pulse width 100 — — µsVDD ≤ BVDD (D005) 36 TPER Parity Error Reset — TBD — µs

* These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not

Sym Characteristic Min Typ† Max Units Conditions

71833msVDD = 5V, -40˚C to +125˚C

(No Prescaler)

— — 2.1 µs

or Watchdog Timer Reset

tested.

DS30559A-page 100 Preliminary  1996 Microchip Technology Inc.

Microchip Technology Inc PIC16C641-04-JW, PIC16C641-04-P, PIC16C641-04-SO, PIC16C641-04E-JW, PIC16C641-04E-P Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Devices included in this data sheet:

High Performance RISC CPU:

Peripheral Features:

Special Microcontroller Features:

Pin Diagrams

Table of Contents

1.0 GENERAL DESCRIPTION

2.0 PIC16C64X & PIC16C66X DEVICE V ARIETIES

3.0 ARCHITECTURAL OVERVIEW

4.0 MEMORY ORGANIZATION

4.3 PCL and PCLATH

4.4 Program Memory Paging

4.5 Indirect Addressing, INDF, and FSR Registers

5.0 I/O PORTS

5.6 I/O Programming Considerations

5.7 Parallel Slave Port (PIC16C661 and PIC16C662 only)

6.0 TIMER0 MODULE

6.2.1 EXTERNAL CLOCK SYNCHRONIZATION

6.3 Prescaler

7.0 COMPARATOR MODULE

7.2 Comparator Operation

7.4 Comparator Response Time

7.5 Comparator Outputs

7.6 Comparator Interrupts

7.7 Comparator Operation During SLEEP

7.8 Effects of a RESET

7.9 Analog Input Connection Considerations

8.0 VOLTAGE REFERENCE MODULE

8.3 Operation During Sleep

8.5 Connection Considerations

9.0 SPECIAL FEATURES OF THE CPU

9.2.2 CRYSTAL OSCILLATOR / CERAMIC RESONATORS

9.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT

Reset

9.4.6 TIME-OUT SEQUENCE

9.4.7 POWER CONTROL/STATUS REGISTER (PCON)

9.5 Interrupts

9.6 Context Saving During Interrupts

9.7 Watchdog Timer (WDT)

9.8 Power-Down Mode (SLEEP)

9.9 Code Protection

9.10 ID Locations

9.11 In-Circuit Serial Programming

10.0 INSTRUCTION SET SUMMARY

10.2 Instruction Descriptions

11.0 DEVELOPMENT SUPPORT

12.0 ELECTRICAL SPECIFICATIONS

12.4 Timing Parameter Symbology