Microchip Technology Inc PIC16C54-RC-P, PIC16C54-RC-SS, PIC16C54-RCI-P, PIC16C54-RCI-SO, PIC16C54-RCI-SS Datasheet

M



1998 Microchip Technology Inc.

Preliminary

DS30453B-page 1

PIC16C5X

Devices Included in this Data Sheet:

• PIC16C52

• PIC16C54s

• PIC16CR54s

• PIC16C55s

• PIC16C56s

• PIC16CR56s

• PIC16C57s

• PIC16CR57s

• PIC16C58s

• PIC16CR58s

High-Performance RISC CPU:

• Only 33 single word instructions to learn

• All instructions are single cycle (200 ns) except for
program branches which are two-cycle

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

Note: The letter "s" used following the part

numbers throughout this document
indicate plural, meaning there is more
than one part variety for the indicated
device.

Device Pins I/O

EPROM/

ROM

RAM

PIC16C52 18 12 384 25
PIC16C54 18 12 512 25
PIC16C54A 18 12 512 25
PIC16C54B 18 12 512 25
PIC16C54C 18 12 512 25
PIC16CR54A 18 12 512 25
PIC16CR54B 18 12 512 25
PIC16CR54C 18 12 512 25
PIC16C55 28 20 512 24
PIC16C55A 28 20 512 24
PIC16C56 18 12 1K 25
PIC16C56A 18 12 1K 25
PIC16CR56A 18 12 1K 25
PIC16C57 28 20 2K 72
PIC16C57C 28 20 2K 72
PIC16CR57B 28 20 2K 72
PIC16CR57C 28 20 2K 72
PIC16C58A 18 12 2K 73
PIC16C58B 18 12 2K 73
PIC16CR58A 18 12 2K 73
PIC16CR58B 18 12 2K 73

• 12-bit wide instructions

• 8-bit wide data path

• Seven or eight special function hardware registers

• Two-level deep hardware stack

• Direct, indirect and relative addressing modes for
data and instructions

Peripheral Features:

• 8-bit real time clock/counter (TMR0) with 8-bit
programmable prescaler

• Power-On Reset (POR)

• Device Reset Timer (DRT)

• Watchdog Timer (WDT) with its own on-chip
RC oscillator for reliable operation

• Programmable code-protection

• Power saving SLEEP mode

• Selectable oscillator options:

- RC: Low-cost RC oscillator

- XT: Standard crystal/resonator

- HS: High-speed crystal/resonator

- LP: Power saving, low-frequency crystal

CMOS Tec hnology:

• Low-power, high-speed CMOS EPROM/ROM
technology

• Fully static design

• Wide-operating voltage and temperature range:

- EPROM Commercial/Industrial 2.0V to 6.25V

- ROM Commercial/Industrial 2.0V to 6.25V

- EPROM Extended 2.5V to 6.0V

- ROM Extended 2.5V to 6.0V

• Low-power consumption

- < 2 mA typical @ 5V, 4 MHz

- 15 µA typical @ 3V, 32 kHz

- < 0.6 µA typical standby current

(with WDT disabled) @ 3V, 0°C to 70°C

Note: In this document, figure and table titles

refer to all varieties of the part number
indicated, (i.e., The title "Figure 14-1:
Load Conditions - PIC16C54A", also
refers to PIC16LC54A and PIC16LV54A
parts).

EPROM/ROM-Based 8-Bit CMOS Microcontroller Series

PIC16C5X

DS30453B-page 2

Preliminary



1998 Microchip Technology Inc.

Pin Diagrams

PDIP, SOIC, Windowed CERDIP

PIC16CR54s

PIC16C58s

PIC16CR58s

PIC16C54s

RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
V

DD

VDD
RB7
RB6
RB5
RB4

RA2
RA3

T0CKI

MCLR

/VPP

VSS

VSS
RB0
RB1
RB2
RB3

•1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

SSOP

PIC16C56s

PIC16CR56s

PIC16CR54s

PIC16C58s

PIC16CR58s

PIC16C54s

PIC16C56s

PIC16CR56s

RA2
RA3

T0CKI

MCLR

/VPP

VSS

RB0
RB1
RB2
RB3

•1
2
3
4
5
6
7
8
9

10

18
17
16
15
14
13
12

11

RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
V

DD

RB7
RB6
RB5
RB4

PIC16C52s

28
27
26
25
24
23
22
21
20
19
18
17
16
15

•1
2
3
4
5
6
7
8
9
10
11
12
13
14

PDIP, SOIC, Windowed CERDIP

PIC16C57s

PIC16C55s

MCLR/VPP
OSC1/CLKIN
OSC2/CLKOUT
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RB7
RB6
RB5

T0CKI

V

DD

VSS

RA0
RA1
RA2
RA3
RB0
RB1
RB2
RB3
RB4

•1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

PIC16C57s

SSOP

PIC16C55s

VDD

VSS

PIC16CR57s

PIC16CR57s

T0CKI

V

DD

N/C
V

SS

N/C
RA0
RA1
RA2
RA3
RB0
RB1
RB2
RB3
RB4

MCLR

/VPP
OSC1/CLKIN
OSC2/CLKOUT

RC7
RC6
RC5

RC4
RC3

RC2
RC1

RC0
RB7
RB6

RB5



1998 Microchip Technology Inc.

Preliminary

DS30453B-page 3

PIC16C5X

Device Differences

Note 1:

If you change from this device to another device, please verify oscillator characteristics in your application.

Note 2:

In PIC16LV58A, MCLR

Filter = Yes

Device

Voltage
Range

Oscillator

Selection

(Program)

Oscillator

Process

Technology

(Microns)

ROM

Equivalent

MCLR

Filter

PIC16C52 3.0-6.25 User See Note 1 0.9 — No
PIC16C54 2.5-6.25 Factory See Note 1 1.2 PIC16CR54A No
PIC16C54A 2.0-6.25 User See Note 1 0.9 — No
PIC16C54B 2.5-5.5 User See Note 1 0.7 PIC16CR54B Yes
PIC16C54C 2.5-5.5 User See Note 1 0.7 PIC16CR54C Yes
PIC16C55 2.5-6.25 Factory See Note 1 1.7 — No
PIC16C55A 2.5-5.5 User See Note 1 0.7 — Yes
PIC16C56 2.5-6.25 Factory See Note 1 1.7 — No
PIC16C56A 2.5-5.5 User See Note 1 0.7 PIC16CR56A Yes
PIC16C57 2.5-6.25 Factory See Note 1 1.2 — No
PIC16C57C 2.5-5.5 User See Note 1 0.7 PIC16CR57C Yes
PIC16C58A 2.0-6.25 User See Note 1 0.9 PIC16CR58A

No

(2)

PIC16C58B 2.5-5.5 User See Note 1 0.7 PIC16CR58B Yes
PIC16CR54A 2.5-6.25 Factory See Note 1 1.2 N/A Yes
PIC16CR54B 2.5-5.5 Factory See Note 1 0.7 N/A Yes
PIC16CR54C 2.5-5.5 Factory See Note 1 0.7 N/A Yes
PIC16CR56A 2.5-5.5 Factory See Note 1 0.7 N/A Yes
PIC16CR57B 2.5-6.25 Factory See Note 1 0.9 N/A Yes
PIC16CR57C 2.5-5.5 Factory See Note 1 0.7 N/A Yes
PIC16CR58A 2.5-6.25 Factory See Note 1 0.9 N/A Yes
PIC16CR58B 2.5-5.5 Factory See Note 1 0.7 N/A Yes

PIC16C5X

DS30453B-page 4

Preliminary



1998 Microchip Technology Inc.

Table of Contents

1.0 General Description.............................................................................................................................................5

2.0 PIC16C5X Device Varieties.................................................................................................................................7

3.0 Architectural Overview.........................................................................................................................................9

4.0 Memory Organization ........................................................................................................................................15

5.0 I/O Ports.............................................................................................................................................................25

6.0 Timer0 Module and TMR0 Register...................................................................................................................27

7.0 Special Features of the CPU.............................................................................................................................31

8.0 Instruction Set Summary ...................................................................................................................................43

9.0 Development Support........................................................................................................................................55

10.0 Electrical Characteristics - PIC16C52................................................................................................................59

11.0 Electrical Characteristics - PIC16C54/55/56/57.................................................................................................67

12.0 DC and AC Characteristics - PIC16C54/55/56/57.............................................................................................81

13.0 Electrical Characteristics - PIC16CR54A...........................................................................................................89

14.0 Electrical Characteristics - PIC16C54A...........................................................................................................103

15.0 Electrical Characteristics - PIC16CR57B.........................................................................................................117

16.0 Electrical Characteristics - PIC16C58A...........................................................................................................131

17.0 Electrical Characteristics - PIC16CR58A.........................................................................................................145

18.0 DC and AC Characteristics - PIC16C54A/CR57B/C58A/CR58A ....................................................................159

19.0 Electrical Characteristics -

PIC16C54B/C54C/CR54B/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B....................................171

20.0 DC and AC Characteristics -

PIC16C54B/C54C/CR54B/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B....................................183

21.0 Packaging Information.....................................................................................................................................195

Appendix A: Compatibility ...........................................................................................................................................207

Index .........................................................................................................................................................................209

On-Line Support..........................................................................................................................................................211

PIC16C5X Product Identification System....................................................................................................................213

PIC16C54/55/56/57 Product Identification System.....................................................................................................214

To Our Valued Customers

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.

Errata

An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended
workarounds. As de vice/documentation issues become known to us , we will publish an err ata sheet. The err ata will specify the revi­sion of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip .com

• Your local Microchip sales office (see last page)

• The Microchip Corporate Literature Center; U.S. FAX: [phone]
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit-

erature number) you are using.

Corrections to this Data Sheet

We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure
that this document is correct. However, we realize that w e may have missed a few things. If you find any information that is missing
or appears in error, please:

• Fill out and mail in the reader response form in the back of this data sheet.

• E-mail us at [e-mail].
We appreciate your assistance in making this a better document.



1998 Microchip Technology Inc.

Preliminary

DS30453B-page 5

PIC16C5X

1.0 GENERAL DESCRIPTION

The PIC16C5X from Microchip Technology is a family
of low-cost, high performance, 8-bit, fully static,
EPROM/ ROM-based CMOS microcontrollers. It
employs a RISC architecture with only 33 single
word/single cycle instructions. All instructions are sin­gle cycle (200 ns) except for program branches which
take two cycles. The PIC16C5X delivers performance
an order of magnitude higher than its competitors in the
same price category. The 12-bit wide instructions are
highly symmetrical resulting in 2:1 code compression
over other 8-bit microcontrollers in its class. The easy
to use and easy to remember instruction set reduces
development time significantly.

The PIC16C5X products are equipped with special fea­tures that reduce system cost and power requirements.
The Power-On Reset (POR) and Device Reset Timer
(DRT) eliminate the need for external reset circuitry.
There are four oscillator configurations to choose from,
including the power-saving LP (Low Power) oscillator
and cost saving RC oscillator. Power saving SLEEP
mode, Watchdog Timer and code protection features
improve system cost, power and reliability.

The UV erasable CERDIP packaged versions are ideal
for code development, while the cost-effective One
Time Programmable (OTP) versions are suitable for
production in any volume. The customer can take full
advantage of Microchip’s price leadership in OTP
microcontrollers while benefiting from the OTP’s
flexibility.

The PIC16C5X products are supported by a
full-featured macro assembler , a softw are simulator , an
in-circuit emulator, a ‘C’ compiler, fuzzy logic support
tools, a low-cost development programmer, and a full
featured programmer. All the tools are supported on
IBM



PC and compatible machines.

1.1 Applications

The PIC16C5X series fits perfectly in applications rang­ing from high-speed automotive and appliance motor
control to low-power remote transmitters/receivers,
pointing devices and telecom processors. The EPROM
technology makes customizing application programs
(transmitter codes, motor speeds, receiver frequen­cies, etc.) extremely fast and convenient. The small
footprint packages, for through hole or surface mount­ing, make this microcontroller series perfect for applica­tions with space limitations. Low-cost, low-power, high
performance, ease of use and I/O flexibility make the
PIC16C5X series very versatile even in areas where no
microcontroller use has been considered before (e.g.,
timer functions, replacement of “glue” logic in larger
systems, coprocessor applications).

PIC16C5X

DS30453B-page 6

Preliminary



1998 Microchip Technology Inc.

TABLE 1-1: PIC16C5X FAMILY OF DEVICES

PIC16C52

PIC16C54s PIC16CR54s PIC16C55s PIC16C56s

Clock

Maximum Frequency
of Operation (MHz)

42020 2020

Memory

EPROM Program Memory
(x12 words)

384 512 — 512 1K

ROM Program Memory
(x12 words)

— — 512 — —

RAM Data Memory (bytes) 25 25 25 24 25

Peripherals

Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0

Features

I/O Pins 12 12 12 20 12
Number of Instructions 33 33 33 33 33
Packages 18-pin DIP,

SOIC

18-pin DIP,
SOIC;
20-pin SSOP

18-pin DIP,
SOIC;
20-pin SSOP

28-pin DIP,
SOIC;
28-pin SSOP

18-pin DIP,
SOIC;
20-pin SSOP

All PICmicro™ Family de vices ha v e Power-on Reset, selectable W atchdog Timer (except PIC16C52), selectable code
protect and high I/O current capability.

PIC16CR56s

PIC16C57s PIC16CR57s PIC16C58s PIC16CR58s

Clock

Maximum Frequency
of Operation (MHz)

20 20 20 20 20

Memory

EPROM Program Memory
(x12 words)

— 2K — 2K —

ROM Program Memory
(x12 words)

1K — 2K — 2K

RAM Data Memory (bytes) 25 72 72 73 73

Peripherals

Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0

Features

I/O Pins 12 20 20 12 12
Number of Instructions 33 33 33 33 33
Packages 18-pin DIP,

SOIC;
20-pin SSOP

28-pin DIP,
SOIC;
28-pin SSOP

28-pin DIP,
SOIC;
28-pin SSOP

18-pin DIP,
SOIC;
20-pin SSOP

18-pin DIP,
SOIC;
20-pin SSOP

All PICmicro™ Family de vices ha v e Power-on Reset, selectable W atchdog Timer (except PIC16C52), selectable code
protect and high I/O current capability.



1998 Microchip Technology Inc.

Preliminary

DS30453B-page 7

PIC16C5X

2.0 PIC16C5X DEVICE VARIETIES

A variety of frequency ranges and packaging options
are available. Depending on application and
production requirements, the proper device option can
be selected using the information in this section. When
placing orders, please use the PIC16C5X Product
Identification System at the back of this data sheet to
specify the correct part number.

For the PIC16C5X family of devices, there are four
device types, as indicated in the device number:

1.C, as in PIC16C54. These devices have
EPROM program memory and operate over the
standard voltage range.

2.

LC

, as in PIC16LC54A. These devices have
EPROM program memory and operate over an
extended voltage range.

3.LV, as in PIC16LV54A. These devices have
EPROM program memory and operate over a

2.0V to 3.8V range.

4.

CR

, as in PIC16CR54A. These devices have
ROM program memory and operate over the
standard voltage range.

5.

LCR

, as in PIC16LCR54B. These devices have
ROM program memory and operate over an
extended voltage range.

2.1 U

V Erasable Devices (EPROM)

The UV erasable versions, offered in CERDIP
packages, are optimal for prototype development and
pilot programs

UV erasable devices can be programmed for any of
the four oscillator configurations. Microchip's
PICSTART



and PRO MATE programmers both
support programming of the PIC16C5X. Third party
programmers also are available; refer to the Third
Party Guide for a list of sources.

2.2 One-Time-Pr

ogrammable (OTP)

Devices

The availability of OTP devices is especially useful for
customers expecting frequent code changes and
updates.

The OTP devices, packaged in plastic packages,
permit the user to program them once. In addition to
the program memory, the configuration bits must be
programmed.

2.3 Quic

k-Turnaround-Production (QTP)

Devices

Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who choose not to program a
medium to high quantity of units and whose code
patterns have stabilized. The devices are identical to
the OTP devices but with all EPROM locations and
configuration bit options already programmed by the
factory. Certain code and prototype verification
procedures apply before production shipments are
available. Please contact your Microchip Technology
sales office for more details.

2.4 Serializ

ed
Quick-Turnaround-Production
(SQTP ) Devices

Microchip offers the unique programming service
where a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential. The devices are identical to the OTP
devices but with all EPROM locations and
configuration bit options already programmed by the
factory.

Serial programming allows each device to have a
unique number which can serve as an entry code,
password or ID number.

2.5 Read Onl

y Memory (ROM) Devices

Microchip offers masked ROM versions of several of
the highest volume parts, giving the customer a low
cost option for high volume, mature products.

SM

PIC16C5X

DS30453B-page 8

Preliminary



1998 Microchip Technology Inc.

NOTES:



1998 Microchip Technology Inc.

Preliminary

DS30453B-page 9

PIC16C5X

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC16C5X family can be
attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16C5X uses a Harvard architecture in
which program and data are accessed on separate
buses. This improves bandwidth over traditional von
Neumann architecture where program and data are
fetched on the same bus. Separating program and
data memory further allows instructions to be sized
differently than the 8-bit wide data word. Instruction
opcodes are 12-bits wide making it possible to have all
single word instructions. A 12-bit wide program
memory access bus fetches a 12-bit instruction in a
single cycle. A two-stage pipeline overlaps fetch and
execution of instructions. Consequently, all instructions
(33) execute in a single cycle (200ns @ 20MHz)
except for program branches.

The PIC16C52 addresses 384 x 12 of program
memory, the PIC16C54s/CR54s and PIC16C55s
address 512 x 12 of program memory, the
PIC16C56s/CR56s address 1K X 12 of program
memory, and the PIC16C57s/CR57s and
PIC16C58s/CR58s address 2K x 12 of program
memory. All program memory is internal.

The PIC16C5X can directly or indirectly address its
register files and data memory. All special function
registers including the program counter are mapped in
the data memory. The PIC16C5X has a highly
orthogonal (symmetrical) instruction set that makes it
possible to carry out any operation on any register
using any addressing mode. This symmetrical nature
and lack of ‘special optimal situations’ make
programming with the PIC16C5X simple yet efficient.
In addition, the learning curve is reduced significantly.

The PIC16C5X device contains an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.

The ALU is 8-bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the W (working) register. The
other operand is either a file register or an immediate
constant. In single operand instructions, the operand
is either the W register or a file register.

The W register is an 8-bit working register used for
ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC),
and Zero (Z) bits in the STATUS register. The C and
DC bits operate as a borr

ow and digit borrow out bit,

respectively, in subtraction. See the

SUBWF

and

ADDWF

instructions for examples.
A simplified block diagram is shown in Figure 3-1, with

the corresponding device pins described in Table 3-1.

PIC16C5X

DS30453B-page 10

Preliminary



1998 Microchip Technology Inc.

FIGURE 3-1: PIC16C5X SERIES BLOCK DIAGRAM

WDT TIME

OUT

8

STACK 1
ST ACK 2

EPROM/ROM

384 X 12 TO

2048 X 12

INSTRUCTION

REGISTER

INSTRUCTION

DECODER

WA TCHDOG

TIMER

CONFIGURA TION W ORD

OSCILLA T OR/

TIMING &

CONTROL

GENERAL
PURPOSE
REGISTER

FILE

(SRAM)

24, 25, 72 or

73 Bytes

WDT/TMR0

PRESCALER

OPTION REG.

“OPTION”

“SLEEP”

“CODE

PROTECT”

“OSC

SELECT”

DIRECT ADDRESS

TMR0

FROM W

FROM W

“TRIS 5”

“TRIS 6”

“TRIS 7”

FSR

TRISA PORTA

TRISB

PORTC

TRISC

PORTB

FROM W

T0CKI

PIN

9-11

9-11

12

12

8

W

4

4

4

DATA BUS

8

8

8

8

8

8

8

ALU

STATUS

FROM W

CLKOUT

8

9

6

5

5-7

OSC1 OSC2 MCLR

LITERALS

PC

“DISABLE”

2

RA3:RA0 RB7:RB0

RC7:RC0

(28-Pin

Devices Only)

DIRECT RAM

ADDRESS



1998 Microchip Technology Inc.

Preliminary

DS30453B-page 11

PIC16C5X

TABLE 3-1: PINOUT DESCRIPTION - PIC16C52, PIC16C54s, PIC16CR54s, PIC16C56s,

PIC16CR56s, PIC16C58s, PIC16CR58s

Name

DIP, SOIC

No.

SSOP

No.

I/O/P
Type

Input

Levels

Description

RA0
RA1
RA2
RA3

17
18

1
2

19
20

1
2

I/O
I/O
I/O
I/O

TTL
TTL
TTL
TTL

Bi-directional I/O port

RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7

6
7
8

9
10
11
12
13

7
8

9
10
11
12
13
14

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL

Bi-directional I/O port

T0CKI 3 3 I ST Clock input to Timer0. Must be tied to V

SS

or V

DD,

if not in

use, to reduce current consumption.

MCLR

/V

PP

4 4 I ST Master clear (reset) input/programming voltage input. This

pin is an active low reset to the device. Voltage on the
MCLR

/V

PP

pin must not exceed VDD to avoid unintended

entering of programming mode.

OSC1/CLKIN 16 18 I ST Oscillator crystal input/external clock source input.

OSC2/CLKOUT 15 17 O — Oscillator crystal output. Connects to crystal or resonator in

crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.

V

DD

14 15,16 P — Positive supply for logic and I/O pins.

V

SS

5 5,6 P — Ground reference for logic and I/O pins.

Legend: I = input, O = output, I/O = input/output,

P = power, — = Not Used, TTL = TTL input,
ST = Schmitt Trigger input

PIC16C5X

DS30453B-page 12

Preliminary



1998 Microchip Technology Inc.

TABLE 3-2: PINOUT DESCRIPTION - PIC16C55s, PIC16C57s, PIC16CR57s

Name

DIP, SOIC

No.

SSOP

No.

I/O/P
Type

Input

Levels

Description

RA0
RA1
RA2
RA3

6
7
8
9

5
6
7
8

I/O
I/O
I/O
I/O

TTL
TTL
TTL
TTL

Bi-directional I/O port

RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7

10
11
12
13
14
15
16
17

9
10
11
12
13
15
16
17

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL

Bi-directional I/O port

RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7

18
19
20
21
22
23
24
25

18
19
20
21
22
23
24
25

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL

Bi-directional I/O port

T0CKI 1 2 I ST Clock input to Timer0. Must be tied to V

SS

or VDD if not in use

to reduce current consumption.

MCLR

28 28 I ST Master clear (reset) input. This pin is an active low reset to the

device.

OSC1/CLKIN 27 27 I ST Oscillator crystal input/external clock source input.

OSC2/CLKOUT 26 26 O — Oscillator crystal output. Connects to crystal or resonator in

crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.

V

DD

2 3,4 P — Positive supply for logic and I/O pins.

V

SS

4 1,14 P — Ground reference for logic and I/O pins.

N/C 3,5 — — — Unused, do not connect

Legend: I = input, O = output, I/O = input/output,

P = power, — = Not Used,
TTL = TTL input, ST = Schmitt Trigger input



1998 Microchip Technology Inc.

Preliminary

DS30453B-page 13

PIC16C5X

3.1 Cloc

king Scheme/Instruction Cycle

The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter is incremented every Q1, and the
instruction is fetched from program memory and
latched into instruction register in Q4. It is decoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow is shown in
Figure 3-2 and Example 3-1.

3.2 Instruction Flo

w/Pipelining

An Instruction Cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g.,

GOTO

)
then two cycles are required to complete the
instruction (Example 3-1).

A fetch cycle begins with the program counter (PC)
incrementing in Q1.

In the execution cycle, the fetched instruction is
latched into the Instruction Register (IR) in cycle Q1.
This instruction is then decoded and executed during
the Q2, Q3, and Q4 cycles. Data memory is read
during Q2 (operand read) and written during Q4
(destination write).

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Q1

Q2 Q3 Q4

Q1

Q2 Q3 Q4

Q1

Q2 Q3 Q4

OSC1

Q1
Q2
Q3

Q4

PC

OSC2/CLKOUT

(RC mode)

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

Execute INST (PC) Fetch INST (PC+2)

Execute INST (PC+1)

Internal
phase
clock

All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

1. MOVLW 55H

Fetch 1 Execute 1

2. MOVWF PORTB

Fetch 2 Execute 2

3. CALL SUB_1

Fetch 3 Execute 3

4. BSF PORTA, BIT3

Fetch 4 Flush

Fetch SUB_1 Execute SUB_1

PIC16C5X

DS30453B-page 14 Preliminary  1998 Microchip Technology Inc.

NOTES:

 1998 Microchip Technology Inc. Preliminary DS30453B-page 15

PIC16C5X

4.0 MEMORY ORGANIZATION

PIC16C5X memory is organized into program memory
and data memory. For devices with more than 512
bytes of program memory, a paging scheme is used.
Program memory pages are accessed using one or
two STATUS register bits. For devices with a data
memory register file of more than 32 registers, a
banking scheme is used. Data memory banks are
accessed using the File Selection Register (FSR).

4.1 Program Memory Organization

The PIC16C52 has a 9-bit Program Counter (PC)
capable of addressing a 384 x 12 program memory
space (Figure 4-1). The PIC16C54s, PIC16CR54s and
PIC16C55s have a 9-bit Program Counter (PC)
capable of addressing a 512 x 12 program memory
space (Figure 4-2). The PIC16C56s and PIC16CR56s
have a 10-bit Program Counter (PC) capable of
addressing a 1K x 12 program memory space
(Figure 4-3). The PIC16CR57s, PIC16C58s and
PIC16CR58s have an 11-bit Program Counter capab le
of addressing a 2K x 12 program memory space
(Figure 4-4). Accessing a location above the physically
implemented address will cause a wraparound.

The reset vector for the PIC16C52 is at 17Fh. A NOP
at the reset vector location will cause a restart at
location 000h. The reset vector for the PIC16C54s,
PIC16CR54s and PIC16C55s is at 1FFh. The reset
vector for the PIC16C56s and PIC16CR56s is at
3FFh. The reset vector for the PIC16C57s,
PIC16CR57s, PIC16C58s, and PIC16CR58s is at
7FFh.

FIGURE 4-1: PIC16C52 PROGRAM

MEMORY MAP AND STACK

PC<8:0>

Stack Level 1
Stack Level 2

User Memory

Space

9

000h

Reset Vector

On-chip Program

Memory

17Fh

CALL, RETLW

FIGURE 4-2: PIC16C54s/CR54s/C55s

PROGRAM MEMORY MAP
AND STACK

FIGURE 4-3: PIC16C56s/CR56s

PROGRAM MEMORY MAP
AND STACK

PC<8:0>

Stack Level 1
Stack Level 2

User Memory

Space

CALL, RETLW

9

000h

1FFh

Reset Vector

0FFh
100h

On-chip
Program
Memory

PC<9:0>

Stack Level 1
Stack Level 2

User Memory

Space

10

000h

1FFh

Reset Vector

0FFh
100h

On-chip Program

Memory (Page 0)

On-chip Program
Memory (Page 1)

200h
2FFh

300h

3FFh

CALL, RETLW

PIC16C5X

DS30453B-page 16 Preliminary  1998 Microchip Technology Inc.

FIGURE 4-4: PIC16C57s/CR57s/C58s/

CR58s PROGRAM MEMORY
MAP AND STACK

PC<10:0>

Stack Level 1
Stack Level 2

User Memory

Space

11

000h

1FFh

Reset Vector

0FFh
100h

On-chip Program

Memory (Page 0)

On-chip Program
Memory (Page 1)

On-chip Program
Memory (Page 2)

On-chip Program
Memory (Page 3)

200h

3FFh

2FFh
300h

400h

5FFh

4FFh
500h

600h

7FFh

6FFh
700h

CALL, RETLW

 1998 Microchip Technology Inc. Preliminary DS30453B-page 17

PIC16C5X

4.2 Data Memory Organization

Data memory is composed of registers, or bytes of
RAM. Therefore, data memory for a device is specified
by its register file. The register file is divided into two
functional groups: special function registers and
general purpose registers.

The special function registers include the TMR0
register, the Program Counter (PC), the Status
Register, the I/O registers (ports), and the File Select
Register (FSR). In addition, special purpose registers
are used to control the I/O port configuration and
prescaler options.

The general purpose registers are used for data and
control information under command of the instructions.

For the PIC16C52, PIC16C54s, PIC16CR54s,
PIC16C56s and PIC16CR56s, the register file is
composed of 7 special function registers and 25
general purpose registers (Figure 4-5).

For the PIC16C55s, the register file is composed of 8
special function registers and 24 general purpose
registers.

For the PIC16C57s and PIC16CR57s, the register file
is composed of 8 special function registers, 24 general
purpose registers and up to 48 additional general
purpose registers that may be addressed using a
banking scheme (Figure 4-6).

For the PIC16C58s and PIC16CR58s, the register file
is composed of 7 special function registers, 25 general
purpose registers and up to 48 additional general
purpose registers that may be addressed using a
banking scheme (Figure 4-7).

4.2.1 GENERAL PURPOSE REGISTER FILE
The register file is accessed either directly or indirectly

through the file select register FSR (Section 4.7).

FIGURE 4-5: PIC16C52, PIC16C54s,

PIC16CR54s, PIC16C55s,
PIC16C56s, PIC16CR56s
REGISTER FILE MAP

File Address

00h
01h
02h
03h
04h
05h
06h
07h

1Fh

INDF

(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

General

Purpose

Registers

Note 1: Not a physical register. See Section 4.7

2: PIC16C55s only, others are a general

purpose register.

0Fh
10h

PORTC

(2)

PIC16C5X

DS30453B-page 18 Preliminary  1998 Microchip Technology Inc.

FIGURE 4-6: PIC16C57s/CR57s REGISTER FILE MAP

FIGURE 4-7: PIC16C58s/CR58s REGISTER FILE MAP

File Address

00h
01h
02h
03h
04h
05h
06h
07h

1Fh

INDF

(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

0Fh

10h

Bank 0 Bank 1 Bank 2 Bank 3

3Fh

30h

20h

2Fh

5Fh

50h

40h

4Fh

7Fh

70h

60h

6Fh

General
Purpose
Registers

General
Purpose
Registers

General
Purpose
Registers

General
Purpose
Registers

General
Purpose
Registers

PORTC

08h

Addresses map back to
addresses in Bank 0.

Note 1: Not a physical register. See Section 4.7

FSR<6:5> 00 01 10 11

File Address

00h
01h
02h
03h
04h
05h
06h

07h

1Fh

INDF

(1)

TMR0

PCL

STATUS

FSR
PORTA
PORTB

0Fh

10h

Bank 0 Bank 1 Bank 2 Bank 3

3Fh

30h

20h

2Fh

5Fh

50h

40h

4Fh

7Fh

70h

60h

6Fh

General
Purpose
Registers

General
Purpose
Registers

General
Purpose
Registers

General
Purpose
Registers

General
Purpose
Registers

Addresses map back to
addresses in Bank 0.

Note 1: Not a physical register. See Section 4.7

FSR<6:5> 00 01 10 11

 1998 Microchip Technology Inc. Preliminary DS30453B-page 19

PIC16C5X

4.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by

the CPU and peripheral functions to control the
operation of the device (Table 4-1).

The special registers can be classified into two sets.
The special function registers associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section for each peripheral feature.

TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-On

Reset

Value on

MCLR and

WDT Reset

N/A TRIS I/O control registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111
N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler --11 1111 --11 1111
00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu
01h TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu

02h

(1)

PCL Low order 8 bits of PC 1111 1111 1111 1111
03h STATUS PA2 PA1 PA0 TO PD ZDCC0001 1xxx 000q quuu
04h FSR Indirect data memory address pointer 1xxx xxxx 1uuu uuuu
05h PORTA — — — — RA3 RA2 RA1 RA0 ---- xxxx ---- uuuu
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu

07h

(2)

PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
Legend: Shaded boxes = unimplemented or unused, – = unimplemented, read as '0' (if applicable)

x = unknown, u = unchanged, q = see the tables in Section 7.7 for possible values.

Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.5

for an explanation of how to access these bits.

2: File address 07h is a general purpose register on the PIC16C52, PIC16C54s, PIC16CR54s, PIC16C56s, PIC16CR56s,

PIC16C58s and PIC16CR58s.

PIC16C5X

DS30453B-page 20 Preliminary  1998 Microchip Technology Inc.

4.3 STATUS Register

This register contains the arithmetic status of the ALU,
the RESET status, and the page preselect bits for
program memories larger than 512 words.

The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to
the device logic. Further more, the T

O and PD bits are

not writable. Therefore, the result of an instruction with
the STATUS register as destination may be different
than intended.

For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF and
MOVWF instructions be used to alter the STATUS
register because these instructions do not affect the Z,
DC or C bits from the STATUS register. For other
instructions, which do affect STATUS bits, see
Section 8.0, Instruction Set Summary.

FIGURE 4-8: STATUS REGISTER (ADDRESS:03h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

PA2 PA1 PA0 TO PD Z DC C R = Readable bit

W = Writable bit

- n = Value at POR reset

bit7 6 5 4 3 2 1 bit0

bit 7: PA2: This bit unused at this time.

Use of the PA2 bit as a general purpose read/write bit is not recommended, since this may affect upward
compatibility with future products.

bit 6-5: PA1:PA0: Program page preselect bits (PIC16C56s/CR56s)(PIC16C57s/CR57s)(PIC16C58s/CR58s)

00 = Page 0 (000h - 1FFh) - PIC16C56s/CR56s, PIC16C57s/CR57s, PIC16C58s/CR58s
01 = Page 1 (200h - 3FFh) - PIC16C56s/CR56s, PIC16C57s/CR57s, PIC16C58s/CR58s
10 = Page 2 (400h - 5FFh) - PIC16C57s/CR57s, PIC16C58s/CR58s
11 = Page 3 (600h - 7FFh) - PIC16C57s/CR57s, PIC16C58s/CR58s
Each page is 512 words.
Using the PA1:PA0 bits as general purpose read/write bits in devices which do not use them for program
page preselect is not recommended since this may affect upward compatibility with future products.

bit 4: T

O: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred

bit 3: PD: Power-down bit

1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction

bit 2: Z: Zero bit

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

bit 1: DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions)

ADDWF

1 = A carry from the 4th low order bit of the result occurred
0 = A carry from the 4th low order bit of the result did not occur

SUBWF

1 = A borrow from the 4th low order bit of the result did not occur
0 = A borrow from the 4th low order bit of the result occurred

bit 0: C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)

ADDWF SUBWF RRF or RLF

1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively
0 = A carry did not occur 0 = A borrow occurred

 1998 Microchip Technology Inc. Preliminary DS30453B-page 21

PIC16C5X

4.4 OPTION Register

The OPTION register is a 6-bit wide, write-only
register which contains various control bits to
configure the Timer0/WDT prescaler and Timer0.

By executing the OPTION instruction, the contents of
the W register will be transferred to the OPTION
register. A RESET sets the OPTION<5:0> bits.

FIGURE 4-9: OPTION REGISTER

U-0 U-0 W-1 W-1 W-1 W-1 W-1 W-1

— — T0CS T0SE PSA PS2 PS1 PS0 W = Writable bit

U = Unimplemented bit

- n = Value at POR reset

bit7 6 5 4 3 2 1 bit0

bit 7-6: Unimplemented.
bit 5: T0CS: Timer0 clock source select bit

1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)

bit 4: T0SE: Timer0 source edge select bit

1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin

bit 3: PSA: Prescaler assignment bit

1 = Prescaler assigned to the WDT (not implemented on PIC16C52)
0 = Prescaler assigned to Timer0

bit 2-0: PS2:PS0: Prescaler rate select bits

000
001
010
011
100
101
110
111

1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256

1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128

Bit Value Timer0 Rate WDT Rate (not implemented on PIC16C52)

PIC16C5X

DS30453B-page 22 Preliminary  1998 Microchip Technology Inc.

4.5 Program Counter

As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.

For a GOTO instruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The PC Latch (PCL) is
mapped to PC<7:0> (Figure 4-10 and Figure 4-11).

For the PIC16C56s, PIC16CR56s, PIC16C57s,
PIC16CR57s, PIC16C58s and PIC16CR58s, a page
number must be supplied as well. Bit5 and bit6 of the
STATUS register provide page information to bit9 and
bit10 of the PC (Figure 4-11 and Figure 4-12).

For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC again are
provided by the instruction word. However, PC<8>
does not come from the instruction word, but is always
cleared (Figure 4-10 and Figure 4-11).

Instructions where the PCL is the destination, or
Modify PCL instructions, include MOVWF PC, ADDWF
PC, and BSF PC,5.

For the PIC16C56s, PIC16CR56s, PIC16C57s,
PIC16CR57s, PIC16C58s and PIC16CR58s, a page
number again must be supplied. Bit5 and bit6 of the
STATUS register provide page information to bit9 and
bit10 of the PC (Figure 4-11 and Figure 4-12).

Note: Because PC<8> is cleared in the CALL

instruction, or any Modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any pro­gram memory page (512 words long).

FIGURE 4-10: LOADING OF PC

BRANCH INSTRUCTIONS ­PIC16C52, PIC16C54s,
PIC16CR54s, PIC16C55s

FIGURE 4-11: LOADING OF PC

BRANCH INSTRUCTIONS ­PIC16C56s/PIC16CR56s

PC

87 0

PCL

PC

87 0

PCL

Reset to '0'

Instruction Word

Instruction Word

GOTO Instruction

CALL or Modify PCL Instruction

PA1:PA0

2

STATUS

PC

87 0

PCL

910

PA1:PA0

2

STATUS

PC

87 0

PCL

910

Instruction Word

Reset to ‘0’

Instruction Word

70

70

GOTO Instruction

CALL or Modify PCL Instruction

 1998 Microchip Technology Inc. Preliminary DS30453B-page 23

PIC16C5X

FIGURE 4-12: LOADING OF PC

BRANCH INSTRUCTIONS ­PIC16C57s/PIC16CR57s, AND
PIC16C58s/PIC16CR58s

PA1:PA0

2

STATUS

PC

87 0

PCL

910

PA1:PA0

2

STATUS

PC

87 0

PCL

910

Instruction Word

Reset to ‘0’

Instruction Word

70

70

GOTO Instruction

CALL or Modify PCL Instruction

4.5.1 PAGING CONSIDERATIONS –
PIC16C56

s/CR56s, PIC16C57s/CR57s AND

PIC16C58

s/CR58s

If the Program Counter is pointing to the last address
of a selected memory page, when it increments it will
cause the program to continue in the next higher page.
However, the page preselect bits in the STATUS
register will not be updated. Therefore, the next GOTO,
CALL, or Modify PCL instruction will send the program
to the page specified by the page preselect bits (PA0
or PA1:PA0).

For example, a NOP at location 1FFh (page 0)
increments the PC to 200h (page 1). A GOTO xxx at
200h will return the program to address 0xxh on page
0 (assuming that PA1:PA0 are clear).

To prevent this, the page preselect bits must be
updated under program control.

4.5.2 EFFECTS OF RESET

The Program Counter is set upon a RESET, which
means that the PC addresses the last location in the
last page i.e., the reset vector.

The STATUS register page preselect bits are cleared
upon a RESET, which means that page 0 is
pre-selected.

Therefore, upon a RESET, a GOTO instruction at the
reset vector location will automatically cause the
program to jump to page 0.

4.6 Stack

PIC16C5X devices have a 9-bit, 10-bit or 11-bit wide,
two-level hardware push/pop stack (Figure 4-2,
Figure 4-1, and Figure 4-3 respectively).

A CALL instruction will

push

the current value of stack
1 into stack 2 and then push the current program
counter value, incremented by one, into stac k level 1. If
more than two sequential CALL’s are executed, only
the most recent two return addresses are stored.

A RETLW instruction will

pop

the contents of stack level
1 into the program counter and then copy stack level 2
contents into level 1. If more than two sequential
RETLW’s are executed, the stack will be filled with the
address previously stored in level 2. Note that the
W register will be loaded with the literal value specified
in the instruction. This is particularly useful for the
implementation of data look-up tables within the
program memory.

For the RETLW instruction, the PC is loaded with the
Top Of Stack (TOS) contents. All of the devices
covered in this data sheet have a two-level stack. The
stack has the same bit width as the device PC.

PIC16C5X

DS30453B-page 24 Preliminary  1998 Microchip Technology Inc.

4.7 Indirect Data Addressing; INDF and
FSR Registers

The INDF register is not a physical register.
Addressing INDF actually addresses the register
whose address is contained in the FSR register (FSR
is a

pointer

). This is indirect addressing.

EXAMPLE 4-1: INDIRECT ADDRESSING

• Register file 05 contains the value 10h

• Register file 06 contains the value 0Ah

• Load the value 05 into the FSR register

• A read of the INDF register will return the value

of 10h

• Increment the value of the FSR register by one

(FSR = 06h)

• A read of the INDR register now will return the

value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).

A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 4-2.

EXAMPLE 4-2: HOW TO CLEAR RAM

USING INDIRECT
ADDRESSING

movlw 0x10 ;initialize pointer
movwf FSR ; to RAM

NEXT clrf INDF ;clear INDF register

incf FSR,F ;inc pointer
btfsc FSR,4 ;all done?
goto NEXT ;NO, clear next

CONTINUE

: ;YES, continue

The FSR is either a 5-bit (PIC16C52, PIC16C54s,
PIC16CR54s, PIC16C55s), 6-bit (PIC16C56s,
PIC16CR56s), or 7-bit (PIC16C57s, PIC16CR57s,
PIC16C58s, PIC16CR58s) wide register. It is used in
conjunction with the INDF register to indirectly address
the data memory area.

The FSR<4:0> bits are used to select data memory
addresses 00h to 1Fh.

PIC16C52, PIC16C54s, PIC16CR54s, PIC16C55s:

These do not use banking. FSR<6:5> are
unimplemented and read as '1's.

PIC16C57s, PIC16CR57s, PIC16C58s,
PIC16CR58s: FSR<6:5> are the bank select bits and

are used to select the bank to be addressed (00 =
bank 0, 01 = bank 1, 10 = bank 2, 11 = bank 3).

FIGURE 4-13: DIRECT/INDIRECT ADDRESSING

Note 1: For register map detail see Section 4.2.

bank

location select

location select

bank select

Indirect Addressing

Direct Addressing

Data
Memory

(1)

0Fh
10h

Bank 0 Bank 1 Bank 2 Bank 3

0

4

5

6

(FSR)

1000 01 11

00h

1Fh 3Fh 5Fh 7Fh

(opcode) 04

5

6

(FSR)

Addresses map back
to addresses in Bank 0.

 1998 Microchip Technology Inc. Preliminary DS30453B-page 25

PIC16C5X

5.0 I/O PORTS

As with any other register, the I/O registers can be
written and read under program control. Ho wever, read
instructions (e.g., MOVF PORTB,W) always read the I/O
pins independent of the pin’s input/output modes. On
RESET, all I/O ports are defined as input (inputs are at
hi-impedance) since the I/O control registers (TRISA,
TRISB, TRISC) are all set.

5.1 PORTA

PORTA is a 4-bit I/O register. Only the low order 4 bits
are used (RA3:RA0). Bits 7-4 are unimplemented and
read as '0's.

5.2 PORTB

PORTB is an 8-bit I/O register (PORTB<7:0>).

5.3 PORTC

PORTC is an 8-bit I/O register for PIC16C55s,
PIC16C57s and PIC16CR57s.

PORTC is a general purpose register for PIC16C52,
PIC16C54s, PIC16CR54s, PIC16C56s, PIC16C58s
and PIC16CR58s.

5.4 TRIS Registers

The output driver control registers are loaded with the
contents of the W register by executing the TRIS f
instruction. A '1' from a TRIS register bit puts the
corresponding output driver in a hi-impedance mode.
A '0' puts the contents of the output data latch on the
selected pins, enabling the output buffer.

The TRIS registers are “write-only” and are set (output
drivers disabled) upon RESET.

Note: A read of the ports reads the pins, not the

output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.

5.5 I/O Interfacing

The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All ports may be used for both input and
output operation. For input operations these ports are
non-latching. Any input must be present until read by
an input instruction (e.g., MOVF PORTB, W). The
outputs are latched and remain unchanged until the
output latch is rewritten. To use a port pin as output,
the corresponding direction control bit (in TRISA,
TRISB) must be cleared (= 0). For use as an input, the
corresponding TRIS bit must be set. Any I/O pin can
be programmed individually as input or output.

FIGURE 5-1: EQUIVALENT CIRCUIT

FOR A SINGLE I/O PIN

Note 1: I/O pins have protection diodes to VDD and VSS.

Data
Bus

QD

Q

CK

QD

Q

CK

P

N

WR
Port

TRIS ‘f’

Data

TRIS

RD Port

VSS

VDD

I/O
pin

(1)

W
Reg

Latch

Latch

Reset

TABLE 5-1: SUMMARY OF PORT REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-On

Reset

Value on

MCLR and

WDT Reset

N/A TRIS I/O control registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111
05h PORTA — — — — RA3 RA2 RA1 RA0 ---- xxxx ---- uuuu
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
Legend: Shaded boxes = unimplemented, read as ‘0’,

– = unimplemented, read as '0', x = unknown, u = unchanged

PIC16C5X

DS30453B-page 26 Preliminary  1998 Microchip Technology Inc.

5.6 I/O Programming Considerations

5.6.1 BI-DIRECTIONAL I/O PORTS

Some instructions operate internally as read followed
by write operations. The BCF and BSF instructions, for
example, read the entire port into the CPU, execute
the bit operation and re-write the result. Caution must
be used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSF operation on bit5 of PORTB will cause
all eight bits of PORTB to be read into the CPU, bit5 to
be set and the PORTB value to be written to the output
latches. If another bit of PORTB is used as a
bi-directional I/O pin (say bit0) and it is defined as an
input at this time, the input signal present on the pin
itself would be read into the CPU and rewritten to the
data latch of this particular pin, overwriting the
previous content. As long as the pin stays in the input
mode, no problem occurs. However, if bit0 is switched
into output mode later on, the content of the data latch
may now be unknown.

Example 5-1 shows the effect of two sequential
read-modify-write instructions (e.g., BCF, BSF , etc.) on
an I/O port.

A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage the
chip.

EXAMPLE 5-1: READ-MODIFY-WRITE

INSTRUCTIONS ON AN
I/O PORT

;Initial PORT Settings
; PORTB<7:4> Inputs
; PORTB<3:0> Outputs
;PORTB<7:6> have external pull-ups and are
;not connected to other circuitry
;
; PORT latch PORT pins
; ---------- ---------­ BCF PORTB, 7 ;01pp pppp 11pp pppp
BCF PORTB, 6 ;10pp pppp 11pp pppp
MOVLW 03Fh ;
TRIS PORTB ;10pp pppp 10pp pppp
;
;Note that the user may have expected the pin
;values to be 00pp pppp. The 2nd BCF caused
;RB7 to be latched as the pin value (High).

5.6.2 SUCCESSIVE OPERATIONS ON I/O
PORTS

The actual write to an I/O port happens at the end of
an instruction cycle, whereas for reading, the data
must be valid at the beginning of the instruction cycle
(Figure 5-2). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should
allow the pin voltage to stabilize (load dependent)
before the next instruction, which causes that file to be
read into the CPU, is executed. Otherwise, the
previous state of that pin may be read into the CPU
rather than the new state. When in doubt, it is better to
separate these instructions with a NOP or another
instruction not accessing this I/O port.

FIGURE 5-2: SUCCESSIVE I/O OPERATION

PC PC + 1 PC + 2

PC + 3

Q1 Q2

Q3

Q4

Q1 Q2

Q3

Q4

Q1 Q2

Q3

Q4

Q1 Q2

Q3

Q4

Instruction

fetched

RB7:RB0

MOVWF PORTB

NOP

Port pin
sampled here

NOP

MOVF PORTB,W

Instruction

executed

MOVWF PORTB

(Write to

PORTB)

NOP

MOVF PORTB,W

This example shows a write
to PORTB followed by a read
from PORTB.

(Read

PORTB)

Port pin
written here

 1998 Microchip Technology Inc. Preliminary DS30453B-page 27

PIC16C5X

6.0 TIMER0 MODULE AND
TMR0 REGISTER

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

- Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

- Edge select for external clock

Figure 6-1 is a simplified block diagram of the Timer0
module, while Figure 6-2 shows the electrical structure
of the Timer0 input.

Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 6-3 and Figure 6-4).
The user can work around this by writing an adjusted
value to the TMR0 register.

Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
incrementing edge is determined by the source edge
select bit T0SE (OPTION<4>). Clearing the T0SE bit
selects the rising edge. Restrictions on the external
clock input are discussed in detail in Section 6.1.

The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit PSA (OPTION<3>). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is
not readable or writable. When the prescaler is
assigned to the Timer0 module, prescale v alues of 1:2,
1:4,..., 1:256 are selectable. Section 6.2 details the
operation of the prescaler.

A summary of registers associated with the Timer0
module is found in Table 6-1.

FIGURE 6-1: TIMER0 BLOCK DIAGRAM

FIGURE 6-2: ELECTRICAL STRUCTURE OF T0CKI PIN

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.

2: The prescaler is shared with the Watchdog Timer (Figure 6-6).

T0CKI

T0SE

(1)

0

1

1

0

pin

T0CS

(1)

FOSC/4

Programmable

Prescaler

(2)

Sync with

Internal

Clocks

TMR0 reg

PSout

(2 cycle delay)

PSout

Data bus

8

PSA

(1)

PS2, PS1, PS0

(1)

3

Sync

VSS

VSS

RIN

Schmitt T rigger

N

Input Buffer

T0CKI

pin

Note 1: ESD protection circuits

(1)

(1)

PIC16C5X

DS30453B-page 28 Preliminary  1998 Microchip Technology Inc.

FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

FIGURE 6-4: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-On

Reset

Value on

MCLR and

WDT Reset

01h TMR0 Timer0 - 8-bit real-time clock/counter xxxx xxxx uuuu uuuu
N/A OPTION

— — T0CS T0SE PSA PS2 PS1 PS0 --11 1111 --11 1111

Legend: Shaded cells: Unimplemented bits,

- = unimplemented, x = unknown, u = unchanged,

PC-1

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC
(Program
Counter)

Instruction
Fetch

Timer0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0

T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2

MOVWF TMR0

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0
executed

Read TMR0
reads NT0

Read TMR0
reads NT0

Read TMR0
reads NT0

Read TMR0
reads NT0 + 1

Read TMR0
reads NT0 + 2

Instruction
Executed

PC-1

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC
(Program
Counter)

Instruction

Fetch

Timer0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 NT0+1

MOVWF TMR0

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0
executed

Read TMR0
reads NT0

Read TMR0
reads NT0

Read TMR0
reads NT0

Read TMR0
reads NT0

Read TMR0
reads NT0 + 1

T0+1

NT0

Instruction
Execute

T

0

 1998 Microchip Technology Inc. Preliminary DS30453B-page 29

PIC16C5X

6.1 Using Timer0 with an External Clock

When an external clock input is used for Timer0, it
must meet certain requirements. The external clock
requirement is due to internal phase clock (T

OSC)

synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.

6.1.1 EXTERNAL CLOCK SYNCHRONIZATION

When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-5). Therefore, it is necessary for T0CKI to be
high for at least 2T

OSC (and a small RC delay of 20 ns)

and low for at least 2T

OSC (and a small RC delay of

20 ns). Refer to the electrical specification of the
desired device.

When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4T

OSC (and a small RC delay of

40 ns) divided by the prescaler value. The only
requirement on T0CKI high and low time is that they
do not violate the minimum pulse width requirement of
10 ns. Refer to parameters 40, 41 and 42 in the
electrical specification of the desired device.

6.1.2 TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 6-5 shows the
delay from the external clock edge to the timer
incrementing.

FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK

Increment Timer0 (Q4)

External Clock Input or

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Timer0

T0 T0 + 1 T0 + 2

Small pulse
misses sampling

External Clock/Prescaler

Output After Sampling

(3)

Note 1:

2:
3:

Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max.
External clock if no prescaler selected, Prescaler output otherwise.
The arrows indicate the points in time where sampling occurs.

Prescaler Output (2)

(1)

PIC16C5X

DS30453B-page 30 Preliminary  1998 Microchip Technology Inc.

6.2 Prescaler

An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer (WDT) (WDT postscaler not implemented on
PIC16C52), respectively (Section 6.1.2). For simplicity,
this counter is being referred to as “prescaler”
throughout this data sheet. Note that the prescaler
may be used by either the Timer0 module or the WDT,
but not both. Thus, a prescaler assignment for the
Timer0 module means that there is no prescaler for
the WDT, and vice-versa.

The PSA and PS2:PS0 bits (OPTION<3:0>) determine
prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1,x, etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the WDT. The prescaler is neither readable
nor writable. On a RESET, the prescaler contains all
'0's.

6.2.1 SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control

(i.e., it can be changed “on the fly” during program
execution). To avoid an unintended device RESET, the

following instruction sequence (Example 6-1) must be
executed when changing the prescaler assignment from
Timer0 to the WDT.

EXAMPLE 6-1: CHANGING PRESCALER

(TIMER0→WDT)

1.CLRWDT ;Clear WDT

2.CLRF TMR0 ;Clear TMR0 & Prescaler

3.MOVLW '00xx1111’b ;These 3 lines (5, 6, 7)

4.OPTION ; are required only if
; desired

5.CLRWDT ;PS<2:0> are 000 or 001

6.MOVLW '00xx1xxx’b ;Set Postscaler to

7.OPTION ; desired WDT rate

To change prescaler from the WDT to the Timer0
module, use the sequence shown in Example 6-2. This
sequence must be used even if the WDT is disabled. A
CLRWDT instruction should be executed bef ore switching
the prescaler.

EXAMPLE 6-2: CHANGING PRESCALER

(WDT→TIMER0)

CLRWDT ;Clear WDT and

;prescaler

MOVLW 'xxxx0xxx' ;Select TMR0, new

;prescale value and
;clock source

OPTION

FIGURE 6-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

T0CKI

T0SE

pin

TCY ( = Fosc/4)

Sync

2

Cycles

TMR0 reg

8-bit Prescaler

8 - to - 1MUX

M

MUX

Watchdog

Timer

PSA

0

1

0

1

WDT

Time-Out

PS2:PS0

8

Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.

PSA

WDT Enable bit

0

1

0

1

Data Bus

8

PSA

T0CS

M
U

X

M

U
X

U
X

WDT not implemented on PIC16C52.