Microchip Technology Inc PIC16C505T-20I-SL, PIC16C505-20E-SL, PIC16C505-20I-JW, PIC16C505-20I-P, PIC16C505-20I-SL Datasheet

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PIC16C505

14-Pin, 8-Bit CMOS Microcontroller

Device included in this Data Sheet:

PIC16C505

High-Performance RISC CPU:

• Only 33 instructions to learn

• Operating speed:

- DC - 20 MHz clock input

- DC - 200 ns instruction cycle

Device

Program Data

Memory

PIC16C505 1024 x 12 72 x 8

• Direct, indirect and relative addressing modes for data and instructions

• 12 bit wide instructions

• 8 bit wide data path

• 2-level deep hardware stack

• Eight special function hardware registers

• Direct, indirect and relative addressing modes for data and instructions

• All single cycle instructions (200 ns) except for program branches which are two-cycle

Peripheral Features:

• 11 I/O pins with individual direction control

• 1 input pin

• High current sink/source for direct LED drive

• Timer0: 8-bit timer/counter with 8-bit programmable prescaler

FIGURE 1: PIN DIAGRAM:

PDIP, SOIC, Ceramic Side Brazed

Special Microcontroller Features:

• In-Circuit Serial Programming (ICSP™)

• Power-on Reset (POR)

• Device Reset Timer (DRT)

• Watchdog Timer (WDT) with dedicated on-chip RC oscillator for reliable operation

• Programmable Code Protection

• Internal weak pull-ups on I/O pins

• Wake-up from Sleep on pin change

• Power-saving Sleep mode

• Selectable oscillator options:

- INTRC: Precision internal 4 MHz oscillator

- EXTRC: External low-cost RC oscillator

- XT: Standard crystal/resonator

- HS: High speed crystal/resonator

- LP: Power saving, low frequency

crystal

CMOS Technology:

• Low-power, high-speed CMOS EPROM technology

• Fully static design

• Wide operating voltage range (2.5V to 5.5V)

• Wide temperature ranges

- Commercial: 0˚C to +70˚C

- Industrial: -40˚C to +85˚C

- Extended: -40˚C to +125˚C

- < 1.0 µA typical standby current @ 5V

• Low power consumption

- < 2.0 mA @ 5V, 4 MHz

- 15 µA typical @ 3.0V, 32 kHz for TMR0 run-

ning in SLEEP mode

- < 1.0 µA typical standby current @ 5V

RB5/OSC1/CLKIN

RB4/OSC2/CLKOUT

RB3/MCLR/V

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1998 Microchip Technology Inc.

VDD

RC5/T0CKI

RC4 RC3

PIC16C505

V RB0 RB1 RB2 RC0 RC1 RC2

Preliminary

DS40192A-page 1

PIC16C505

TABLE OF CONTENTS

1.0 General Description..................................................................................................................................................................... 3

2.0 PIC16C505 Device Varieties....................................................................................................................................................... 5

3.0 Architectural Overview ................................................................................................................................................................ 7

4.0 Memory Organization................................................................................................................................................................ 11

5.0 I/O Port...................................................................................................................................................................................... 19

6.0 Timer0 Module and TMR0 Register .......................................................................................................................................... 23

7.0 Special Features of the CPU..................................................................................................................................................... 27

8.0 Instruction Set Summary........................................................................................................................................................... 39

9.0 Development Support................................................................................................................................................................ 51

10.0 Electrical Characteristics - PIC16C505 ..................................................................................................................................... 55

11.0 DC and AC Characteristics - PIC16C505.................................................................................................................................. 65

12.0 Packaging Information............................................................................................................................................................... 69

INDEX.................................................................................................................................................................................................. 73

PIC16C505 Product Identification System........................................................................................................................................... 77

To Our Valued Customers

We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you ﬁnd any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document.

DS40192A-page 2

Preliminary

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PIC16C505

1.0 GENERAL DESCRIPTION

The PIC16C505 from Microchip Technology is a lowcost, high performance, 8-bit, fully static, EPROM/ ROM-based CMOS microcontroller. It employs a RISC architecture with only 33 single word/single cycle instructions. All instructions are single cycle (1 µs) except for program branches which take two cycles. The PIC16C505 delivers performance an order of magnitude higher than its competitors in the same price category. The 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. The easy to use and easy to remember instruction set reduces development time signiﬁcantly.

The PIC16C505 product is equipped with special features that reduce system cost and power requirements. The Power-On Reset (POR) and Device Reset Timer (DRT) eliminate the need for external reset circuitry. There are five oscillator conﬁgurations to choose from, including INTRC internal oscillator mode and the power-saving LP (Low Power) oscillator. Power saving SLEEP mode, Watchdog Timer and code protection features improve system cost, power and reliability.

The PIC16C505 is available in the cost-effective OneTime-Programmable (OTP) version, which is suitable for production in any volume. The customer can take full advantage of Microchip’s price leadership in OTP microcontrollers while beneﬁting from the OTP’s ﬂexibility.

The PIC16C505 product is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a ‘C’ compiler, a low-cost development programmer, and a full featured programmer. All the tools are supported on IBM



PC and compatible machines.

1.1 Applications

The PIC16C505 ﬁts perfectly in applications ranging from personal care appliances and security systems to low-power remote transmitters/receivers. The EPROM technology makes customizing application programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages, for through hole or surface mounting, make this microcontroller perfect for applications with space limitations. Low-cost, low-power, high performance, ease of use and I/O ﬂexibility make the PIC16C505 very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, replacement of “glue” logic and PLD’s in larger systems, coprocessor applications).

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Preliminary

DS40192A-page 3

PIC16C505

TABLE 1-1: PIC16C505 DEVICE

PIC16C505

Clock

Memory

Peripherals

Features

The PIC16C505 device has Power-on Reset, selectable Watchdog Timer, selectable code protect, high I/O current capability and precision internal oscillator. The PIC16C505 device uses serial programming with data pin RB0 and clock pin RB1.

Maximum Frequency of Operation (MHz)

EPROM Program Memory 1024 Data Memory (bytes) 72 Timer Module(s) TMR0 Wake-up from SLEEP on

pin change I/O Pins 11 Input Pins 1 Internal Pull-ups Yes In-Circuit Serial Programming Yes Number of Instructions 33 Packages 14-pin DIP, SOIC, JW

Yes

DS40192A-page 4

Preliminary

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PIC16C505

2.0 PIC16C505 DEVICE VARIETIES

A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC16C505 Product Identiﬁcation System at the back of this data sheet to specify the correct part number.

2.1 UV Erasab

The UV erasable version, offered in ceramic side brazed package, is optimal for prototype development and pilot programs.

The UV erasable version can be erased and reprogrammed to any of the conﬁguration modes.

Note:

Please note that erasing the device will also erase the pre-programmed internal calibration value for the inter nal oscillator. The calibration value must be saved prior to erasing the part.

Microchip's PICSTAR T grammers all support programming of the PIC16C505. Third party programmers also are available; refer to the

Microchip Third Party Guide

2.2 One-Time-Pr Devices

The availability of OTP devices is especially useful for customers who need the ﬂexibility for frequent code updates or small volume applications.

The OTP devices, pac kaged in plastic packages permit the user to program them once. In addition to the program memory, the conﬁguration bits must also be programmed.

le Devices



PLUS and PRO MATE pro-

for a list of sources.

ogrammable (OTP)

2.3 Quic

k-Turnaround-Production (QTP)

Devices

Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices b ut with all EPROM locations and fuse options already programmed by the factory. Certain code and prototype veriﬁcation procedures do apply before production shipments are availab le. Please contact your local Microchip Technology sales ofﬁce for more details.

2.4 Serializ

Microchip offers a unique programming service where a few user-deﬁned locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential.

Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number.

ed Quick-Turnaround

Production (SQTP

vices

) De

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Preliminary

DS40192A-page 5

PIC16C505

NOTES:

DS40192A-page 6

Preliminary

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1998 Microchip Technology Inc.

PIC16C505

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC16C505 can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16C505 uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12-bits wide, making it possible to have all single word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a single cycle (200ns @ 20MHz) except for program branches.

The PIC16C505 addresses 1K x 12 of program memory. All program memory is internal.

The PIC16C505 can directly or indirectly address its register ﬁles and data memory. All special function registers, including the program counter, are mapped in the data memory. The PIC16C505 has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC16C505 simple yet efﬁcient. In addition, the learning curve is reduced signiﬁcantly.

The PIC16C505 device contains an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register ﬁle.

The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the W (working) register. The other operand is either a ﬁle register or an immediate constant. In single operand instructions, the operand is either the W register or a ﬁle register.

The W register is an 8-bit working register used for ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borr respectively, in subtraction. See the instructions for examples.

A simpliﬁed block diagram is shown in Figure 3-1, with the corresponding device pins described in Table 3-1.

ow and digit borrow out bit,

SUBWF

and

ADDWF

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Preliminary

DS40192A-page 7

PIC16C505

FIGURE 3-1: PIC16C505 BLOCK DIAGRAM

Program Counter

STACK1 STACK2

Direct Addr

Device Reset

Timer

Power-on

Reset

Watchdog

Timer

Internal RC

OSC

OSC1/CLKIN

OSC2

Program

Bus

EPROM 1K x 12

Program

Memory

Instruction reg

Instruction

Decode &

Control

Timing

Generation

Data Bus

Registers

RAM Addr

Addr MUX

RAM

72 bytes

File

5-7

FSR reg

STATUS reg

MUX

ALU

W reg

Timer0

Indirect

Addr

PORTB

PORTC

RB0 RB1 RB2 RB3/MCLR/Vpp RB4/OSC2/CLKOUT RB5/OSC1/CLKIN

RC0 RC1 RC2 RC3 RC4 RC5/T0CKI

MCLR

Vdd, Vss

DS40192A-page 8

Preliminary

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PIC16C505

TABLE 3-1: PIC16C505 PINOUT DESCRIPTION

DIP

Name

RB0 13 13 I/O TTL/ST Bi-directional I/O port/ serial programming data. Can

RB1 12 12 I/O TTL/ST Bi-directional I/O port/ serial programming clock. Can

RB2 11 11 I/O TTL Bi-directional I/O port. RC0 10 10 I/O TTL Bi-directional I/O port. RC1 9 9 I/O TTL Bi-directional I/O port. RC2 8 8 I/O TTL Bi-directional I/O port. RC3 7 7 I/O TTL Bi-directional I/O port. RC4 6 6 I/O TTL Bi-directional I/O port. RC5/T0CKI 5 5 I/O ST Bi-directional I/O port. Can be conﬁgured as T0CKI.

RB3/MCLR

RB4/OSC2/CLKOUT 3 3 I/O TTL Bi-directional I/O port/oscillator crystal output. Con-

RB5/OSC1/CLKIN 2 2 I/O TTL/ST Bidirectional IO port/oscillator crystal input/external

DD SS

Legend: I = input, O = output, I/O = input/output, P = power, — = not used, TTL = TTL input, ST = Schmitt Trigger input

Pin #

SOIC Pin #

4 4 I TTL Input port/master clear (reset) input/programming volt-

1 1 P — Positive supply for logic and I/O pins

14 14 P — Ground reference for logic and I/O pins

I/O/P Type

Buffer

Type

be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. This buffer is a Schmitt Trigger input when used in serial programming mode.

age input. When conﬁgured as MCLR active low reset to the device. Voltage on MCLR must not exceed V Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. Weak pullup only when conﬁgured as RB3.

nections to crystal or resonator in crystal oscillator mode (XT and LP modes only, RB4 in other modes). Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. In EXTRC and INTRC modes, the pin output can be conﬁgured to CLKOUT, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate.

clock source input (RB5 in Internal RC mode only, OSC1 in all other oscillator modes). TTL input when RB5, ST input in external RC oscillator mode.

Description

during normal device operation.

, this pin is an

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Preliminary

DS40192A-page 9

PIC16C505

3.1 Cloc

king Scheme/Instruction Cycle

The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter is incremented every Q1, and the instruction is fetched from program memory and latched into instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution ﬂow is shown in Figure 3-2 and Example 3-1.

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

Q2 Q3 Q4

OSC1

Q1 Q2 Q3 Q4 PC

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

3.2 Instruction Flo

w/Pipelining

An Instruction Cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., then two cycles are required to complete the instruction (Example 3-1).

A fetch cycle begins with the program counter (PC) incrementing in Q1.

In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).

Q2 Q3 Q4

Execute INST (PC) Fetch INST (PC+2)

Q2 Q3 Q4

Execute INST (PC+1)

Internal phase clock

GOTO

)

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

1. MOVLW 03H

2. MOVWF PORTB

3. CALL SUB_1

4. BSF PORTB, BIT1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “ﬂushed” from the pipeline while the new instruction is being fetched and then executed.

DS40192A-page 10

Fetch 1 Execute 1

Fetch 2 Execute 2

Preliminary

Fetch 3 Execute 3

Fetch 4 Flush

Fetch SUB_1 Execute SUB_1

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1998 Microchip Technology Inc.

PIC16C505

4.0 MEMORY ORGANIZATION

PIC16C505 memory is organized into program memory and data memory. For the PIC16C505, a paging scheme is used. Program memory pages are accessed using one STATUS register bit. Data memory banks are accessed using the File Select Register (FSR).

4.1 Pr

The PIC16C505 devices have a 12-bit Program Counter (PC).

The 1K x 12 (0000h-03FFh) for the PIC16C505 are physically implemented. Refer to Figure 4-1. Accessing a location above this boundary will cause a wrap-around within the ﬁrst 1K x 12 space. The effective reset vector is at 0000h, (see Figure 4-1). Location 03FFh (PIC16C505) contains the internal clock oscillator calibration value. This value should never be overwritten.

ogram Memory Organization

FIGURE 4-1: PROGRAM MEMORY MAP

AND STACK FOR THE PIC16C505

CALL, RETLW

PC<11:0>

Stack Level 1 Stack Level 2

Reset Vector (note 1)

Space

User Memory

On-chip Program

Memory

1024 Word

Note 1: Address 0000h becomes the

effective reset vector. Location 03FFh (PIC16C505) contains the MOVLW XX INTERNAL RC oscillator calibration value.

0000h

01FFh 0200h

03FFh 0400h

7FFh

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Preliminary

DS40192A-page 11

PIC16C505

4.2 Data Memor

y Organization

Data memory is composed of registers, or bytes of RAM. Therefore, data memory for a device is speciﬁed by its register ﬁle. The register ﬁle is divided into two functional groups: special function registers and general purpose registers.

The special function registers include the TMR0 register, the Program Counter (PC), the Status Register, the I/O registers (ports), and the File Select Register (FSR). In addition, special purpose registers are used to control the I/O port conﬁguration and prescaler options.

The general purpose registers are used for data and control information under command of the instructions.

FIGURE 4-2: PIC16C505 REGISTER FILE MAP

FSR<6:5> 00 01

File Address

00h 01h 02h 03h 04h 05h 06h

07h 08h

0Fh

10h

1Fh

Note 1: Not a physical register.

(1)

INDF

TMR0

PCL

STATUS

FSR

OSCCAL

PORTB PORTC

General Purpose Registers

Bank 0

20h

2Fh 30h

General Purpose Registers

3Fh

Bank 1

For the PIC16C505, the register ﬁle is composed of 8 special function registers, 24 general purpose registers, and 48 general purpose registers that may be addressed using a banking scheme (Figure 4-2).

4.2.1 GENERAL PURPOSE REGISTER FILE The general purpose register ﬁle is accessed either

directly or indirectly through the ﬁle select register FSR (Section 4.8).

40h

Addresses map back to addresses in Bank 0.

4Fh

50h

General Purpose Registers

5Fh

Bank 2

60h

6Fh

70h

General Purpose Registers

7Fh

Bank 3

DS40192A-page 12

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PIC16C505

4.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (Table 4-1).

The special registers can be classiﬁed into two sets. The special function registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature.

TABLE 4-1: SPECIAL FUNCTION REGISTER (SFR) SUMMARY

Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00h INDF Uses contents of FSR to address data memory (not a physical register) 01h TMR0 8-bit real-time clock/counter

(1)

02h 03h STATUS RBWUF 04h 05h OSCCAL CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 N/A TRISB N/A TRISC N/A OPTION RBWU 06h PORTB 07h PORTC

Legend: Shaded cellls not used by Port Registers, read as ‘0’, — = unimplemented, read as ‘0’, x = unknown, u = unchanged.

PCL Low order 8 bits of PC

— PAO TO PD Z DC C

FSR

Indirect data memory address pointer

— — I/O control registers — — I/O control registers

RBPU TOCS TOSE PSA PS2 PS1 PS0 — — RB5 RB4 RB3 RB2 RB1 RB0 — — RC5 RC4 RC3 RC2 RC1 RC0

— —

Power-On

Reset

xxxx xxxx uuuu uuuu uuuu uuuu xxxx xxxx uuuu uuuu uuuu uuuu 1111 1111 1111 1111 1111 1111 0001 1xxx 000q quuu 100q quuu 110x xxxx 11uu uuuu 11uu uuuu 1000 00-- uuuu uu-- uuuu uu--

--11 1111 --11 1111 --11 1111

--11 1111 --11 1111 --11 1111 1111 1111 1111 1111 1111 1111

--xx xxxx --uu uuuu --uu uuuu

Value on

CLR and

WDT Reset

Value on Wake-up on Pin Change

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PIC16C505

4.3 S

TATUS Register

This register contains the arithmetic status of the ALU, the RESET status, and the page preselect bit.

The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the T

O and PD bits are

For example, bits and set the Z bit. This leaves the STATUS register as

000u u1uu

It is recommended, therefore, that only MOVWF instructions be used to alter the STATUS register because these instructions do not affect the Z, DC or C bits from the STATUS register. For other instructions, which do affect STATUS bits, see Instruction Set Summary.

not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

FIGURE 4-3: STATUS REGISTER (ADDRESS:03h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

RBWUF

bit7 6 5 4 3 2 1 bit0 bit 7: RBWUF: IO reset bit

bit 6: Unimplemented bit 5: PA0: Program page preselect bits

bit 4: TO: Time-out bit

bit 3: PD: Power-down bit

bit 2: Z: Zero bit

bit 1: DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions)

bit 0: C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)

—

1 = Reset due to wake-up from SLEEP on pin change 0 = After power up or other reset

1 = Page 1 (200h - 3FFh) 0 = Page 0 (000h - 1FFh) Each page is 512 bytes. Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is not recommended since this may affect upward compatibility with future products.

1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

ADDWF

1 = A carry from the 4th low order bit of the result occurred 0 = A carry from the 4th low order bit of the result did not occur

SUBWF

1 = A borrow from the 4th low order bit of the result did not occur 0 = A borrow from the 4th low order bit of the result occurred

ADDWF SUBWF RRF or RLF

1 = A carry occurred 1 = A borrow did not occur Load bit with LSB or MSB, respectively 0 = A carry did not occur 0 = A borrow occurred

PA0 TO PD Z DC C R = Readable bit

CLRF STATUS

will clear the upper three

(where u = unchanged).

W = Writable bit

- n = Value at POR reset

BCF

, BSF and

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Preliminary

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PIC16C505

4.4 OPTION Register

The OPTION register is a 8-bit wide, write-only register which contains various control bits to conﬁgure the Timer0/WDT prescaler and Timer0.

Note: If TRIS bit is set to ‘0’, the wake-up on

change and pull-up functions are disabled for that pin; i.e., note that TRIS overrides OPTION control of RBPU

By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A RESET sets the OPTION<7:0> bits.

FIGURE 4-4: OPTION REGISTER

W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1

RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 W = Writable bit

bit7 6 5 4 3 2 1 bit0

bit 7: RBWU

bit 6: RBPU: Enable weak pull-ups (RB0, RB1, RB3, RB4)

bit 5: T0CS: Timer0 clock source select bit

bit 4: T0SE: Timer0 source edge select bit

bit 3: PSA: Prescaler assignment bit

bit 2-0: PS2:PS0: Prescaler rate select bits

: Enable wake-up on pin change (RB0, RB1, RB3, RB4) 1 = Disabled 0 = Enabled

1 = Disabled 0 = Enabled

1 = Transition on T0CKI pin 0 = Transition on internal instruction cycle clock, Fosc/4

1 = Increment on high to low transition on the T0CKI pin 0 = Increment on low to high transition on the T0CKI pin

1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0

Bit Value Timer0 Rate WDT Rate

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

U = Unimplemented bit

- n = Value at POR reset Reference Table 4-1 for other resets.

and RBWU.

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PIC16C505

4.5 OSCCAL Register

The Oscillator Calibration (OSCCAL) register is used to calibrate the internal 4 MHz oscillator. It contains six bits for ﬁne calibration.

FIGURE 4-5: OSCCAL REGISTER (ADDRESS 05h)PIC16C505

R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 — — R = Readable bit

bit7 bit0

bit 7-4: CAL<5:0>: Fine calibration

W = Writable bit U = Unimplemented bit,

- n = Value at POR reset

read as ‘0’

DS40192A-page 16 Preliminary  1998 Microchip Technology Inc.

PIC16C505

4.6 Program Counter

As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC.

For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. The PC Latch (PCL) is mapped to PC<7:0>. Bit 5 of the STATUS register provides page information to bit 9 of the PC (Figure 4-

6). For a CALL instruction, or any instruction where the

PCL is the destination, bits 7:0 of the PC again are provided by the instruction word. However, PC<8> does not come from the instruction word, but is always cleared (Figure 4-6).

Instructions where the PCL is the destination, or Modify PCL instructions, include MOVWF PC, ADDWF PC, and BSF PC,5.

Note: Because PC<8> is cleared in the CALL

instruction, or any Modify PCL instruction, all subroutine calls or computed jumps are limited to the ﬁrst 256 locations of any program memory page (512 words long).

FIGURE 4-6: LOADING OF PC

BRANCH INSTRUCTIONS -

PIC16C505

GOTO Instruction

910

8 7 0

PCL

4.6.1 EFFECTS OF RESET The Program Counter is set upon a RESET, which

means that the PC addresses the last location in the last page i.e., the oscillator calibration instruction. After executing MOVLW XX, the PC will roll over to location 00h, and begin executing user code.

The STATUS register page preselect bits are cleared upon a RESET, which means that page 0 is preselected.

Therefore, upon a RESET, a GOTO instruction will automatically cause the program to jump to page 0 until the value of the page bits is altered.

4.7 Stack

PIC16C505 devices have a 12-bit wide hardware push/pop stack.

push

A CALL instruction will 1 into stack 2 and then push the current program counter value, incremented by one, into stac k level 1. If more than two sequential CALL’s are executed, only the most recent two return addresses are stored.

A RETLW instruction will 1 into the program counter and then copy stack level 2 contents into level 1. If more than two sequential RETLW’s are executed, the stack will be filled with the address previously stored in level 2. Note that the W register will be loaded with the literal value speciﬁed in the instruction. This is particularly useful for the implementation of data look-up tables within the program memory.

the current value of stack

pop

the contents of stack level

Instruction Word

PA0

7 0

STATUS

CALL or Modify PCL Instruction

 1998 Microchip Technology Inc. Preliminary DS40192A-page 17

8 7 0

910

Instruction Word

Reset to ‘0’

PA0

7 0

STATUS

PCL

PIC16C505

4.8 Indirect Data Addressing; INDF and FSR Registers

The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a

pointer

). This is indirect addressing.

EXAMPLE 4-1: INDIRECT ADDRESSING

• Register ﬁle 07 contains the value 10h

• Register ﬁle 08 contains the value 0Ah

• Load the value 07 into the FSR register

• A read of the INDF register will return the value

of 10h

• Increment the value of the FSR register by one

(FSR = 08)

• A read of the INDR register now will return the

value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected).

A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 4-2.

FIGURE 4-7: DIRECT/INDIRECT ADDRESSING

Direct Addressing

(FSR)

6 5 4 (opcode) 0

EXAMPLE 4-2: HOW TO CLEAR RAM

USING INDIRECT ADDRESSING

movlw 0x10 ;initialize pointer movwf FSR ; to RAM

NEXT clrf INDF ;clear INDF register

incf FSR,F ;inc pointer btfsc FSR,4 ;all done? goto NEXT ;NO, clear next

CONTINUE

: ;YES, continue

The FSR is a 5-bit wide register. It is used in conjunction with the INDF register to indirectly address the data memory area.

The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh.

The device uses FSR6:5 to select between banks 0:3.

Indirect Addressing

6 5 4 (FSR) 0

bank select location select

Data Memory(1)

00h

0Fh 10h

00 01 10 11

1Fh 3Fh 5Fh 7Fh

Bank 0 Bank 1 Bank 2 Bank 3

Addresses map back to addresses in Bank 0.

bank location select

Note 1: For register map detail see Section 4.2.

DS40192A-page 18 Preliminary  1998 Microchip Technology Inc.

PIC16C505

5.0 I/O PORT

As with any other register, the I/O register can be written and read under program control. However, read instructions (e.g., MOVF PORTB,W) always read the I/O pins independent of the pin’s input/output modes. On RESET, all I/O ports are deﬁned as input (inputs are at hi-impedance) since the I/O control registers are all set.

5.1 PORTB

PORTB is an 8-bit I/O register. Only the low order 6 bits are used (RB5:RB0). Bits 7 and 6 are unimplemented and read as '0's. Please note that RB3 is an input only pin. The conﬁguration word can set several I/O’s to alternate functions. When acting as alternate functions the pins will read as ‘0’ during port read. Pins RB0, RB1, RB3 and RB4 can be conﬁgured with weak pull-ups and also with wake-up on change. The wake-up on change and weak pull-up functions are not pin selectable. If pin 4 is conﬁgured as MCLR weak pull-up is always off and wake-up on change for this pin is not enabled.

5.2 PORTC

PORTC is an 8-bit I/O register. Only the low order 6 bits are used (RC5:RC0). Bits 7 and 6 are unimplemented and read as ‘0’s.

5.3 TRIS Registers

The output driver control register is loaded with the contents of the W register by executing the TRIS f instruction. A '1' from a TRIS register bit puts the corresponding output driver in a hi-impedance mode. A '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. The exceptions are RB3 which is input only and RC5 which may be controlled by the option register, see Figure 4-

4. Note: A read of the ports reads the pins, not the

output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low.

The TRIS registers are “write-only” and are set (output drivers disabled) upon RESET.

5.4 I/O Interfacing

The equivalent circuit for an I/O port pin is shown in Figure 5-1. All port pins, except RB3 which is input only, may be used for both input and output operations. For input operations these ports are nonlatching. Any input must be present until read by an input instruction (e.g., MOVF PORTB,W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit in TRIS must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin (except RB3) can be programmed individually as input or output.

FIGURE 5-1: EQUIVALENT CIRCUIT

FOR A SINGLE I/O PIN

Data Bus

WR Port

W Reg

TRIS ‘f’

Note 1: I/O pins have protection diodes to VDD and VSS.

TRIS Latch

Reset

Data Latch

VDD

RD Port

VSS

I/O pin

(1)

 1998 Microchip Technology Inc. Preliminary DS40192A-page 19

PIC16C505

TABLE 5-1: SUMMARY OF PORT REGISTERS

Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

N/A TRISB — — I/O control registers N/A TRISC — — I/O control registers N/A OPTION RBWU RBPU TOCS TOSE PSA PS2 PS1 PS0 03h STATUS RBWUF — PAO TO PD Z DC C 06h PORTB — — RB5 RB4 RB3 RB2 RB1 RB0 07h PORTC — — RC5 RC4 RC3 RC2 RC1 RC0

Legend: Shaded cellls not used by Port Registers, read as ‘0’, — = unimplemented, read as ‘0’, x = unknown, u = unchanged.

5.5 I/O Programming Considerations

EXAMPLE 5-1: READ-MODIFY-WRITE

5.5.1 BI-DIRECTIONAL I/O PORTS Some instructions operate internally as read followed

by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU, bit5 to be set and the PORTB value to be written to the output latches. If another bit of PORTB is used as a bidirectional I/O pin (say bit0) and it is deﬁned as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input

;Initial PORTB Settings ; PORTB<5:3> Inputs ; PORTB<2:0> Outputs ; ; PORTB latch PORTB pins ; ---------- --------- BCF PORTB, 5 ;--01 -ppp --11 pppp BCF PORTB, 4 ;--10 -ppp --11 pppp MOVLW 007h ; TRIS PORTB ;--10 -ppp --11 pppp ; ;Note that the user may have expected the pin ;values to be --00 pppp. The 2nd BCF caused ;RB5 to be latched as the pin value (High).

5.5.2 SUCCESSIVE OPERATIONS ON I/O

mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch may now be unknown.

Example 5-1 shows the effect of two sequential readmodify-write instructions (e.g., BCF, BSF , etc.) on an I/ O port.

A pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin (“wired-or”, “wiredand”). The resulting high output currents may damage the chip.

The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-2). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that ﬁle to be read into the CPU, is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to

Power-On

Reset

--11 1111 --11 1111 --11 1111

--11 1111 --11 1111 --11 1111 1111 1111 1111 1111 1111 1111 0001 1xxx 000q quuu 100q quuu

--xx xxxx --uu uuuu --uu uuuu

INSTRUCTIONS ON AN I/O PORT

PORTS

Value on

MCLR and

WDT Reset

Value on Wake-up on Pin Change

separate these instructions with a NOP or another instruction not accessing this I/O port.

DS40192A-page 20 Preliminary  1998 Microchip Technology Inc.

FIGURE 5-2: SUCCESSIVE I/O OPERATION

PIC16C505

Instruction

fetched

RB5:RB0

Instruction

executed

Q1 Q2

PC PC + 1 PC + 2

MOVWF PORTB

Q1 Q2

MOVF PORTB,W

MOVWF PORTB

Port pin written here

(Write to

PORTB)

Q1 Q2

NOP

Port pin sampled here

MOVF PORTB,W

(Read

PORTB)

Q1 Q2

PC + 3

NOP

This example shows a write to PORTB followed by a read from PORTB.

Data setup time = (0.25 TCY – TPD) where: TCY = instruction cycle.

TPD = propagation delay

Therefore, at higher clock frequencies, a write followed by a read may be problematic.

NOP

 1998 Microchip Technology Inc. Preliminary DS40192A-page 21

PIC16C505

NOTES:

DS40192A-page 22 Preliminary  1998 Microchip Technology Inc.

PIC16C505

6.0 TIMER0 MODULE AND TMR0 REGISTER

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

- Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

- Edge select for external clock

Figure 6-1 is a simpliﬁed block diagram of the Timer0 module.

Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two cycles (Figure 6-2 and Figure 6-3). The user can work around this by writing an adjusted value to the TMR0 register.

FIGURE 6-1: TIMER0 BLOCK DIAGRAM

RC5/T0CKI

T0SE

FOSC/4

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.

2: The prescaler is shared with the Watchdog Timer (Figure 6-5).

T0CS

(1)

Programmable

Prescaler

PS2, PS1, PS0

Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.1.

The prescaler may be used by either the Timer0 module or the Watchdog Timer, but not both. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale v alues of 1:2, 1:4,..., 1:256 are selectable. Section 6.2 details the operation of the prescaler.

A summary of registers associated with the Timer0 module is found in Table 6-1.

Data bus

PSout

(2)

(1)

PSA

(1)

Sync with

Internal

Clocks

(2 cycle delay)

PSout

Sync

TMR0 reg

 1998 Microchip Technology Inc. Preliminary DS40192A-page 23

PIC16C505

FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

PC (Program Counter)

Instruction Fetch

Timer0

Instruction Executed

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC-1

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

MOVWF TMR0

T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0 executed

Read TMR0 reads NT0

Read TMR0 reads NT0 + 1

Read TMR0 reads NT0 + 2

FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

PC (Program Counter)

Instruction Fetch

Timer0

Instruction Execute

Q1 Q2 Q3 Q4

T0 NT0+1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC-1

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

MOVWF TMR0

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

T0+1

Write TMR0 executed

Read TMR0 reads NT0

NT0

Read TMR0 reads NT0

Read TMR0 reads NT0 + 1

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0

Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Power-On

Reset

01h TMR0 Timer0 - 8-bit real-time clock/counter xxxx xxxx uuuu uuuu N/A OPTION

RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 N/A TRISB I/O control registers --11 1111 --11 1111 --11 1111 N/A TRISC

Legend: Shaded cells not used by Timer0,

I/O control registers --11 1111 --11 1111 --11 1111

- = unimplemented, x = unknown, u = unchanged,

Value on

MCLR and

WDT Reset

Value on Wake-up on Pin Change

uuuu uuuu

1111 1111

DS40192A-page 24 Preliminary  1998 Microchip Technology Inc.

PIC16C505

6.1 Using Timer0 with an External Clock

When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (T synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization.

6.1.1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-4). Therefore, it is necessary for T0CKI to be high for at least 2T and low for at least 2T

OSC (and a small RC delay of 20 ns)

OSC (and a small RC delay of

20 ns). Refer to the electrical speciﬁcation of the desired device.

OSC)

When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4T 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical speciﬁcation of the desired device.

6.1.2 TIMER0 INCREMENT DELAY Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 6-4 shows the delay from the external clock edge to the timer incrementing.

FIGURE 6-4: TIMER0 TIMING WITH EXTERNAL CLOCK

External Clock Input or Prescaler Output (2)

External Clock/Prescaler Output After Sampling

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(3)

(1)

OSC (and a small RC delay of

Small pulse misses sampling

Increment Timer0 (Q4)

Timer0

Note 1:

Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max.

External clock if no prescaler selected, Prescaler output otherwise.

The arrows indicate the points in time where sampling occurs.

 1998 Microchip Technology Inc. Preliminary DS40192A-page 25

T0 T0 + 1 T0 + 2

PIC16C505

6.2 Prescaler

An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer (WDT), respectively (Section 7.6). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT, and vice-versa.

The PSA and PS2:PS0 bits (OPTION<3:0>) determine prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,x, etc.) will clear the prescaler. When assigned to WDT , a CLRWDT instruction will clear the prescaler along with the WDT. The prescaler is neither readable nor writable. On a RESET, the prescaler contains all '0's.

EXAMPLE 6-1: CHANGING PRESCALER

1.CLRWDT ;Clear WDT

2.CLRF TMR0 ;Clear TMR0 & Prescaler

3.MOVLW '00xx1111’b; ;These 3 lines (5, 6, 7)

4.OPTION ; are required only if

5.CLRWDT ;PS<2:0> are 000 or 001

6.MOVLW '00xx1xxx’b ;Set Postscaler to

7.OPTION ; desired WDT rate

To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 6-2. This sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before switching the prescaler.

EXAMPLE 6-2: CHANGING PRESCALER

CLRWDT ;Clear WDT and

MOVLW 'xxxx0xxx' ;Select TMR0, new

6.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control

OPTION

(i.e., it can be changed “on the ﬂy” during program execution). To avoid an unintended device RESET, the following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT.

FIGURE 6-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

TCY ( = Fosc/4)

RC5/T0CKI

M U

Sync

Cycles

(TIMER0→WDT)

; desired

(WDT→TIMER0)

;prescaler

;prescale value and ;clock source

Data Bus

TMR0 reg

T0SE

Watchdog

Timer

WDT Enable bit

Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.

DS40192A-page 26 Preliminary  1998 Microchip Technology Inc.

U X

PSA

T0CS

8-bit Prescaler

8 - to - 1MUX

MUX

WDT

Time-Out

PSA

PS2:PS0

PSA

PIC16C505

7.0 SPECIAL FEATURES OF THE CPU

What sets a microcontroller apart from other processors are special circuits to deal with the needs of real-time applications. The PIC16C505 family of microcontrollers has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These features are:

• Oscillator selection

• Reset

- Power-On Reset (POR)

- Device Reset Timer (DRT)

- Wake-up from SLEEP on pin change

• Watchdog Timer (WDT)

• SLEEP

• Code protection

• ID locations

• In-circuit Serial Programming

• Clock Out

The PIC16C505 has a Watchdog Timer which can be shut off only through conﬁguration bit WDTE. It runs off of its own RC oscillator for added reliability. If using HS, XT or LP selectable oscillator options, there is always an 18 ms (nominal) delay provided by the Device Reset Timer (DRT), intended to keep the chip in reset until the crystal oscillator is stable. If using INTRC or EXTRC there is an 18 ms delay only on V power-up. With this timer on-chip, most applications need no external reset circuitry.

The SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through a change on input pins or through a Watchdog Timer time-out. Several oscillator options are also made available to allow the part to ﬁt the application, including an internal 4 MHz oscillator. The EXTRC oscillator option saves system cost while the LP crystal option saves power. A set of conﬁguration bits are used to select various options.

7.1 Conﬁguration Bits

The PIC16C505 conﬁguration word consists of 6 bits. Conﬁguration bits can be programmed to select various device conﬁgurations. Three bits are for the selection of the oscillator type, one bit is the Watchdog Timer enable bit, and one bit is the MCLR One bit is the code protection bit (Figure 7-1).

FIGURE 7-1: CONFIGURATION WORD FOR PIC16C505

enable bit.

CP CP CP CP CP CP MCLRE CP WDTE FOSC2 FOSC1 FOSC0 Register: CONFIG

bit11 10 9 8 7 6 5 4 3 2 1 bit0

bit 11-6, 4: CP Code Protection bits bit 5: MCLRE: RB3/MCLR pin function select

1 = RB3/MCLR pin function is MCLR 0 = RB3/MCLR pin function is digital I/O, MCLR internally tied to VDD

bit 3: WDTE: Watchdog timer enable bit

1 = WDT enabled 0 = WDT disabled

bit 2-0: FOSC1:FOSC0: Oscillator Selection bits

111 = external RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin 110 = external RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin 101 = internal RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin 100 = internal RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin 011 = invalid selection 010 = HS oscillator 001 = XT oscillator 000 = LP oscillator

Note 1: 03FFh is always uncodeprtotected on the PIC16C505. This location contains the

MOVLWxx calibration instruction for the INTRC.

Note 2: Refer to the PIC16C505 Programming Speciﬁcations to determine how to access the con-

ﬁguration word. This register is not user addressable during device operation.

 1998 Microchip Technology Inc. Preliminary DS40192A-page 27

(1)(2)

Address

(2)

: 0FFFh

PIC16C505

7.2 Oscillator Conﬁgurations

7.2.1 OSCILLATOR TYPES The PIC16C505 can be operated in four different

oscillator modes. The user can program three conﬁguration bits (FOSC2:FOSC0) to select one of these four modes:

• LP: Low Power Crystal

• XT: Crystal/Resonator

• HS: High Speed Crystal/Resonator

• INTRC: Internal 4 MHz Oscillator

• EXTRC: External Resistor/Capacitor

7.2.2 CRYSTAL OSCILLATOR / CERAMIC RESONATORS

In HS, XT or LP modes, a crystal or ceramic resonator is connected to the RB5/OSC1/CLKIN and RB4/ OSC2/CLKOUT pins to establish oscillation (Figure 7-

2). The PIC16C505 oscillator design requires the use

of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers speciﬁcations. When in HS, XT or LP modes, the device can have an external clock source drive the RB5/OSC1/CLKIN pin (Figure 7-3).

FIGURE 7-2: CRYSTAL OPERATION (OR

CERAMIC RESONATOR) (HS, XT OR LP OSC CONFIGURATION)

(1)

Note 1: See Capacitor Selection tables for

recommended values of C1 and C2.

2: A series resistor (RS) may be required for

A T strip cut crystals.

3: RF varies with the crystal chosen

(approx. value = 10 MΩ).

XTAL

OSC1

OSC2

(2)

(3)

PIC16C505

SLEEP

To internal

logic

TABLE 7-1: CAPACITOR SELECTION

FOR CERAMIC RESONATORS

- PIC16C505

Osc

Resonator

Type

XT 4.0 MHz 30 pF 30 pF

HS 16 MHz 10-47 pF 10-47 pF

These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components.

Freq

Cap. RangeC1Cap. Range

TABLE 7-2: CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR

- PIC16C505

Osc

Resonator

Type

LP 32 kHz XT 200 kHz

HS 20 MHz 15-47 pF 15-47 pF

Note 1: For V These values are for design guidance only. Rs may

be required in XT mode to avoid overdriving crystals with low drive level speciﬁcation. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.

Freq

1 MHz 4 MHz

DD > 4.5V, C1 = C2 ≈ 30 pF is

recommended.

Cap.Range

(1)

15 pF 15 pF

47-68 pF

15 pF 15 pF

Cap. Range

47-68 pF

15 pF 15 pF

FIGURE 7-3: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR LP OSC CONFIGURATION)

Clock from ext. system

Open

DS40192A-page 28 Preliminary  1998 Microchip Technology Inc.

OSC1

PIC16C505

OSC2

PIC16C505

7.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT

Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance.

Figure 7-4 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 kΩ resistor provides the negative feedback for stability. The 10 kΩ potentiometers bias the 74AS04 in the linear region. This circuit could be used for external oscillator designs.

FIGURE 7-4: EXTERNAL PARALLEL

RESONANT CRYSTAL OSCILLATOR CIRCUIT

+5V

10k

4.7k

74AS04

XTAL

10k

20 pF

Figure 7-5 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator circuit. The 330 Ω resistors provide the negative feedback to bias the inverters in their linear region.

10k

74AS04

To Other Devices

PIC16C505

CLKIN

FIGURE 7-5: EXTERNAL SERIES

RESONANT CRYSTAL OSCILLATOR CIRCUIT

To Other

74AS04

Devices

PIC16C505

CLKIN

330

74AS04

330

74AS04

0.1 µF XTAL

7.2.4 EXTERNAL RC OSCILLATOR For timing insensitive applications, the RC device

option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Cext values. The user also needs to take into account variation due to tolerance of external R and C components used.

Figure 7-6 shows how the R/C combination is connected to the PIC16C505. For Rext values below

2.2 kΩ, the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g., 1 MΩ) the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping Rext between 3 kΩ and 100 kΩ.

Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance.

The Electrical Speciﬁcations sections show RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more).

Also, see the Electrical Speciﬁcations sections for variation of oscillator frequency due to V

DD for given

Rext/Cext values as well as frequency variation due to operating temperature for given R, C, and V

DD values.

FIGURE 7-6: EXTERNAL RC OSCILLATOR

MODE

VDD

Rext

Cext

FOSC/4

OSC1

OSC2/CLKOUT

Internal clock

PIC16C505

 1998 Microchip Technology Inc. Preliminary DS40192A-page 29

PIC16C505

7.2.5 INTERNAL 4 MHz RC OSCILLATOR The internal RC oscillator provides a ﬁxed 4 MHz (nom-

inal) system clock at VDD = 5V and 25°C, see “Electrical Speciﬁcations” section for information on variation over voltage and temperature..

In addition, a calibration instruction is programmed into the last address of memory which contains the calibration value for the internal RC oscillator. This location is always uncode protected regardless of the code protect settings. This value is programmed as a MOVLW XX instruction where XX is the calibration value, and is placed at the reset vector. This will load the W register with the calibration value upon reset and the PC will then roll over to the users program at address 0x000. The user then has the option of writing the value to the OSCCAL Register (05h) or ignoring it.

OSCCAL, when written to with the calibration value, will “trim” the internal oscillator to remove process variation from the oscillator frequency. .

Note: Please note that erasing the device will

also erase the pre-programmed internal calibration value for the inter nal oscillator. The calibration value must be read prior to erasing the part. so it can be reprogrammed correctly later.

For the PIC16C505, only bits <7:2> of OSCCAL are implemented.

7.3 RESET

The device differentiates between various kinds of reset:

a) Power on reset (POR) b) MCLR c) MCLR d) WDT time-out reset during normal operation e) WDT time-out reset during SLEEP f) Wake-up from SLEEP on pin change

Some registers are not reset in any way; they are unknown on POR and unchanged in any other reset. Most other registers are reset to “reset state” on pow eron reset (POR), on MCLR change reset during normal operation. They are not affected by a WDT reset during SLEEP or MCLR during SLEEP, since these resets are viewed as resumption of normal operation. The exceptions to this are T differently in different reset situations. These bits are used in software to determine the nature of reset. See Table 7-3 for a full description of reset states of all registers.

reset during normal operation reset during SLEEP

, WDT or wake-up on pin

reset

O, PD, and RBWUF bits. They are set or cleared

DS40192A-page 30 Preliminary  1998 Microchip Technology Inc.

PIC16C505

TABLE 7-3: RESET CONDITIONS FOR REGISTERS

Reset

MCLR

W — qqqq xxxx (1) qqqq uuuu (1)

INDF 00h xxxx xxxx uuuu uuuu

TMR0 01h xxxx xxxx uuuu uuuu

PC 02h 1111 1111 1111 1111

STATUS 03h 0001 1xxx ?00? ?uuu (2)

FSR 04h 110x xxxx 11uu uuuu

OSCCAL 05h 1000 00-- uuuu uu--

PORTB 06h --xx xxxxx --uu uuuu PORTC 07h --xx xxxxx --uu uuuu

OPTION — 1111 1111 1111 1111

TRISB — --11 1111 --11 1111 TRISC — --11 1111 --11 1111

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, ? = value depends on condition.

Note 1: Bits <7:4> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory. Note 2: See Table 7-7 for reset value for speciﬁc conditions

TABLE 7-4: RESET CONDITION FOR SPECIAL REGISTERS

STATUS Addr: 03h PCL Addr: 02h

Power on reset 0001 1xxx 1111 1111

reset during normal operation 000u uuuu 1111 1111

MCLR

reset during SLEEP 0001 0uuuu 1111 1111

MCLR WDT reset during SLEEP 0000 0uuu 1111 1111 WDT reset normal operation 0000 1uuu 1111 1111 Wake-up from SLEEP on pin change 1001 0uuu 1111 1111 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’.

WDT time-out

Wake-up on Pin Change

 1998 Microchip Technology Inc. Preliminary DS40192A-page 31

PIC16C505

7.3.1 MCLR ENABLE This conﬁguration bit when unprogrammed (left in the

‘1’ state) enables the exter nal MCLR programmed, the MCLR V

DD, and the pin is assigned to be a I/O. See Figure 7-

function is tied to the internal

function. When

FIGURE 7-7: MCLR SELECT

RBWU

RB3/MCLR/VPP

7.4 P

ower-On Reset (POR)

The PIC16C505 family incorporates on-chip Power-On Reset (POR) circuitry which provides an internal chip reset for most power-up situations.

A Power-on Reset pulse is generated on-chip when V

DD rise is detected (in the range of 2.3V - 2.8V). To

take advantage of the internal POR, program the RB3/ MCLR

/VPP pin as MCLR and tie directly to VDD or program the pin as RB3. An internal weak pull-up resistor is implemented using a transistor. Refer to Table 10-6 for the pull-up resistor ranges. This will eliminate external RC components usually needed to create a Poweron Reset. A maximum rise time for V See Electrical Speciﬁcations for details.

When the device starts normal operation (exits the reset condition), device operating parameters (voltage , frequency , temperature, ...) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating parameters are met.

A simpliﬁed block diagram of the on-chip Power-On Reset circuit is shown in Figure 7-8.

WEAK PULL-UP

MCLRE

INTERNAL MCLR

DD is speciﬁed.

The Power-On Reset circuit and the Device Reset Timer (Section 7.5) circuit are closely related. On power-up, the reset latch is set and the DRT is reset. The DRT timer begins counting once it detects MCLR to be high. After the time-out period, which is typically 18 ms, it will reset the reset latch and thus end the onchip reset signal.

A power-up example where MCLR shown in Figure 7-9. V

DD is allowed to rise and

stabilize before bringing MCLR actually come out of reset T

is held low is

high. The chip will

DRT msec after MCLR

goes high. In Figure 7-10, the on-chip Power-On Reset feature is

being used (MCLR pin is programmed to be RB3.). The V

and VDD are tied together or the

DD is stable

before the start-up timer times out and there is no problem in getting a proper reset. However, Figure 711 depicts a problem situation where V

DD rises too

slowly. The time between when the DRT senses that MCLR

is high and when MCLR (and VDD) actually reach their full value, is too long. In this situation, when the start-up timer times out, V V

DD (min) value and the chip is, therefore, not

DD has not reached the

guaranteed to function correctly. For such situations, we recommend that external RC circuits be used to achieve longer POR delay times (Figure 7-10).

Note: When the device starts normal operation

(exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be meet to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met.

For additional information refer to Application Notes “

Power-Up Considerations”

Trouble Shooting

” - AN607.

- AN522 and “

Power-up

DS40192A-page 32 Preliminary  1998 Microchip Technology Inc.

PIC16C505

FIGURE 7-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Power-Up

VDD

RB3/MCLR/VPP

Detect

POR (Power-On Reset)

Pin Change

SLEEP

Wake-up on pin change

MCLRE

On-Chip

DRT OSC

WDT Time-out

8-bit Asynch

Ripple Counter

(Start-Up Timer)

FIGURE 7-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR

VDD

MCLR

INTERNAL POR

DRT TIME-OUT

INTERNAL RESET

FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR

VDD

MCLR

INTERNAL POR

TDRT

RESET

S Q

CHIP RESET

PULLED LOW)

TDRT

TIED TO VDD): FAST VDD RISE TIME

DRT TIME-OUT

INTERNAL RESET

 1998 Microchip Technology Inc. Preliminary DS40192A-page 33

PIC16C505

FIGURE 7-11: TIME-OUT SEQUENCE ON POWER -UP (MCLR TIED TO VDD): SLOW VDD RISE TIME

VDD

MCLR

INTERNAL POR

DRT TIME-OUT

INTERNAL RESET

When VDD rises slowly, the TDRT time-out expires long before VDD has reached its ﬁnal value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min.

TDRT

7.5 Device Reset Timer (DRT)

In the PIC16C505, the DRT runs any time the device is powered up. DRT runs from RESET and varies based on oscillator selection (see Table 7-5.)

The Device Reset Timer (DRT) provides a ﬁxed 18 ms nominal time-out on reset. The DRT operates on an internal RC oscillator. The processor is kept in RESET as long as the DRT is active. The DRT delay allows V

DD to rise above VDD min., and for the oscillator to

stabilize. Oscillator circuits based on crystals or ceramic

resonators require a certain time after power-up to establish a stable oscillation. The on-chip DRT keeps the device in a RESET condition for approximately 18 ms after MCLR level. Thus, programming RB3/MCLR and using an external RC network connected to the MCLR

input is not required in most cases, allowing for savings in cost-sensitive and/or space restricted applications, as well as allowing the use of the RB3/ MCLR

/VPP pin as a general purpose input. The Device Reset time delay will vary from chip to chip

due to V AC parameters for details.

The DRT will also be triggered upon a W atchdog Timer time-out (only in HS, XT and LP modes). This is particularly impor tant for applications using the WDT to wake from SLEEP mode automatically.

has reached a logic high (VIHMCLR)

/VPP as MCLR

DD, temperature, and process variation. See

7.6 Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the external RC oscillator of the RB5/OSC1/CLKIN pin and the internal 4 MHz oscillator. That means that the WDT will run even if the main processor clock has been stopped, for example, by execution of a SLEEP instruction. During normal operation or SLEEP, a WDT reset or wake-up reset generates a device RESET.

The T

O bit (STATUS<4>) will be cleared upon a

Watchdog Timer reset. The WDT can be permanently disabled by

programming the conﬁguration bit WDTE as a '0' (Section 7.1). Refer to the PIC16C505 Programming Speciﬁcations to determine how to access the conﬁguration word.

TABLE 7-5: DRT (DEVICE RESET TIMER

PERIOD)

Oscillator

Conﬁguration

IntRC & ExtRC

HS, XT & LP 18 ms (typical) 18 ms (typical)

POR Reset

18 ms (typical) 300 µs (typi-

Subsequent

Resets

cal)

DS40192A-page 34 Preliminary  1998 Microchip Technology Inc.

PIC16C505

7.6.1 WDT PERIOD The WDT has a nominal time-out period of 18 ms,

(with no prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT (under software control) by writing to the OPTION register. Thus, a time-out period of a nominal 2.3 seconds can be realized. These periods vary with temperature, V

DD and part-to-

part process variations (see DC specs). Under worst case conditions (V

DD = Min., Temperature

= Max., max. WDT prescaler), it may take several seconds before a WDT time-out occurs.

FIGURE 7-12: WATCHDOG TIMER BLOCK DIAGRAM

From Timer0 Clock Source (Figure 6-5)

Watchdog

Timer

WDT Enable

Conﬁguration Bit

Note: T0CS, T0SE, PSA, PS2:PS0

are bits in the OPTION register.

U X

PSA

7.6.2 WDT PROGRAMMING CONSIDERATIONS The CLRWDT instruction clears the WDT and the

postscaler, if assigned to the WDT, and prevents it from timing out and generating a device RESET.

The SLEEP instruction resets the WDT and the postscaler, if assigned to the WDT. This gives the maximum SLEEP time before a WDT wake-up reset.

Postscaler

8 - to - 1 MUX

MUX

WDT

Time-out

PS2:PS0

To Timer0 (Figure 6-4)

PSA

TABLE 7-6: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Value on

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

N/A OPTION RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: Shaded boxes = Not used by Watchdog Timer, — = unimplemented, read as '0', u = unchanged

 1998 Microchip Technology Inc. Preliminary DS40192A-page 35

Power-On

Reset

Value on

MCLR and

WDT Reset

Value on Wake-up on Pin Change

1111 1111

PIC16C505

7.7 Time-Out Sequence, Power Down, and Wake-up from SLEEP Status Bits (TO/PD/RBWUF)

The TO, PD, and RBWUF bits in the STATUS register can be tested to determine if a RESET condition has been caused by a power-up condition, a MCLR Watchdog Timer (WDT) reset, or a MCLR

or WDT

reset.

TABLE 7-7: TO/PD/RBWUF STATUS

AFTER RESET

RBWUF TO PD RESET caused by

0 0 0

WDT wake-up from SLEEP

0 0 1

WDT time-out (not from SLEEP)

0 1 0

MCLR wake-up from SLEEP

0 1 1 0 u u 1 1 0

Power-up MCLR not during SLEEP Wake-up from SLEEP on

pin change

Legend: Legend: u = unchanged

Note 1: The TO, PD, and RBWUF bits main-

tain their status (u) until a reset occurs. A low-pulse on the MCLR input does not change the TO, PD, and RBWUF status bits.

These STATUS bits are only affected by events listed in Table 7-8.

TABLE 7-8: EVENTS AFFECTING TO/PD

STATUS BITS

Event RBWUF TO PD Remarks

Power-up WDT Time-out

SLEEP instruction CLRWDT

instruction Wake-up from

SLEEP on pin change

Legend: u = unchanged A WDT time-out will occur regardless of the status of the TO bit. A SLEEP instruction will be executed, regardless of the status of the PD bit. Table 7-7 reﬂects the status of TO and PD after the corresponding event.

Table 7-4 lists the reset conditions for the special function registers, while Table 7-3 lists the reset conditions for all the registers.

0 1 1 0 0 u

u 1 0 u 1 1

1 1 0

No effect on PD

7.8 Reset on Brown-Out

A brown-out is a condition where device power (VDD) dips below its minimum value, but not to z ero, and then recovers. The device should be reset in the event of a brown-out.

To reset PIC16C505 devices when a brown-out occurs, external brown-out protection circuits may be built, as shown in Figure 7-13 and Figure 7-14.

FIGURE 7-13: BROWN-OUT PROTECTION

CIRCUIT 1

VDD

40k*

MCLR

PIC16C505

33k

10k

This circuit will activate reset when VDD goes below Vz +

0.7V (where Vz = Zener voltage). *Refer to Figure 7-7 and Table 10-6 for internal weak pull-

up on MCLR.

FIGURE 7-14: BROWN-OUT PROTECTION

CIRCUIT 2

VDD

40k

VDD

MCLR

PIC16C505

= 0.7V

This brown-out circuit is less expensive, although less accurate. Transistor Q1 turns off when V is below a certain level such that:

VDD •

R1 + R2

*Refer to Figure 7-7 and Table 10-6 for internal weak pull-up on MCLR.

DS40192A-page 36 Preliminary  1998 Microchip Technology Inc.

PIC16C505

7.9 Power-Down Mode (SLEEP)

A device may be powered down (SLEEP) and later powered up (Wake-up from SLEEP).

7.9.1 SLEEP The Power-Down mode is entered by executing a

SLEEP instruction. If enabled, the Watchdog Timer will be cleared but

keeps running, the T bit (STATUS<3>) is cleared and the oscillator driver is turned off. The I/O por ts maintain the status they had before the SLEEP instruction was executed (driving high, driving low, or hi-impedance).

It should be noted that a RESET generated by a WDT time-out does not drive the MCLR

For lowest current consumption while powered down, the T0CKI input should be at V MCLR

/VPP pin must be at a logic high level (VIHMC) if

MCLR

is enabled.

7.9.2 WAKE-UP FROM SLEEP The device can wake-up from SLEEP through one of

the following events:

1. An external reset input on RB3/MCLR when conﬁgured as MCLR

2. A Watchdog Timer time-out reset (if WDT was enabled).

3. A change on input pin RB0, RB1, RB3 or RB4 when wake-up on change is enabled.

These events cause a device reset. The T RBWUF bits can be used to determine the cause of device reset. The T occurred (and caused wake-up). The PD set on power-up, is cleared when SLEEP is invoked. The RBWUF bit indicates a change in state while in SLEEP at pins RB0, RB1, RB3 or RB4 (since the last ﬁle or bit operation on RB port).

Caution: Right before entering SLEEP, read the

The WDT is cleared when the device wakes from sleep, regardless of the wake-up source.

input pins. When in SLEEP, wake up occurs when the values at the pins change from the state they were in at the last reading. If a wake-up on change occurs and the pins are not read before reentering SLEEP, a wake up will occur immediately even if no pins change while in SLEEP mode.

O bit (STATUS<4>) is set, the PD

pin low.

DD or VSS and the RB3/

/VPP pin,

O, PD, and

O bit is cleared if a WDT time-out

bit, which is

7.10 Program Veriﬁcation/Code Protection

If the code protection bit has not been programmed, the on-chip program memory can be read out for veriﬁcation purposes.

The ﬁrst 64 locations and the last location (OSCCAL) can be read regardless of the code protection bit setting.

7.11 ID Locations

Four memory locations are designated as ID locations where the user can store checksum or other codeidentiﬁcation numbers. These locations are not accessible during normal execution but are readable and writable during program/verify.

Use only the lower 4 bits of the ID locations and always program the upper 8 bits as '0's.

 1998 Microchip Technology Inc. Preliminary DS40192A-page 37

PIC16C505

7.12 In-Circuit Serial Programming

The PIC16C505 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent ﬁrmware or a custom ﬁrmware to be programmed.

The device is placed into a program/verify mode by holding the RB1 and RB0 pins low while raising the MCLR

(VPP) pin from VIL to VIHH (see programming speciﬁcation). RB1 becomes the programming clock and RB0 becomes the programming data. Both RB1 and RB0 are Schmitt Trigger inputs in this mode.

After reset, a 6-bit command is then supplied to the device. Depending on the command, 14-bits of program data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC16C505 Programming Speciﬁcations.

A typical in-circuit serial programming connection is shown in Figure 7-15.

FIGURE 7-15: TYPICAL IN-CIRCUIT SERIAL

PROGRAMMING CONNECTION

To Normal

External Connector Signals

+5V

VPP

CLK

Data I/O

Connections

To Normal Connections

PIC16C505

V VSS MCLR/VPP

RB1

RB0

DS40192A-page 38 Preliminary  1998 Microchip Technology Inc.

PIC16C505

8.0 INSTRUCTION SET SUMMARY

Each PIC16C505 instruction is a 12-bit word divided into an OPCODE, which speciﬁes the instruction type, and one or more operands which further specify the operation of the instruction. The PIC16C505 instruction set summary in Table 8-2 groups the instructions into byte-oriented, bit-oriented, and literal and control operations. Table 8-1 shows the opcode ﬁeld descriptions.

For byte-oriented instructions, 'f' represents a ﬁle register designator and 'd' represents a destination designator. The ﬁle register designator is used to specify which one of the 32 file registers is to be used by the instruction.

The destination designator speciﬁes where the result of the operation is to be placed. If 'd' is '0', the result is placed in the W register. If 'd' is '1', the result is placed in the ﬁle register speciﬁed in the instruction.

For bit-oriented instructions, 'b' represents a bit ﬁeld designator which selects the number of the bit affected by the operation, while 'f' represents the number of the ﬁle in which the bit is located.

For literal and control operations, 'k' represents an 8 or 9-bit constant or literal value.

TABLE 8-1: OPCODE FIELD

Field Description

f Register ﬁle address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit ﬁle register k Literal ﬁeld, constant data or label

label Label name

TOS Top of Stack

PC Program Counter

WDT Watchdog Timer Counter

TO PD Power-Down bit

dest

[ ]

( )

→

< >

∈

talics

DESCRIPTIONS

Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools.

Destination select;

d = 0 (store result in W) d = 1 (store result in ﬁle register 'f')

Default is d = 1

Time-Out bit

Destination, either the W register or the speciﬁed register ﬁle location

Options Contents Assigned to Register bit ﬁeld In the set of User deﬁned term (font is courier)

All instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 µs. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 µs.

Figure 8-1 shows the three general formats that the instructions can have. All examples in the ﬁgure use the following format to represent a hexadecimal number:

0xhhh

where 'h' signiﬁes a hexadecimal digit.

FIGURE 8-1: GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented ﬁle register operations

11 6 5 4 0

OPCODE d f (FILE #)

d = 0 for destination W d = 1 for destination f f = 5-bit ﬁle register address

Bit-oriented ﬁle register operations

11 8 7 5 4 0

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address f = 5-bit ﬁle register address

Literal and control operations (except GOTO)

11 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

Literal and control operations - GOTO instruction

11 9 8 0

OPCODE k (literal)

k = 9-bit immediate value

 1998 Microchip Technology Inc. Preliminary DS40192A-page 39

PIC16C505

TABLE 8-2: INSTRUCTION SET SUMMARY

1 1 1 1 1 1

1 1

1 1 1 1 1 1 1 1

1 1

1 2 1 2 1 1 1 2 1 1 1

12-Bit Opcode

11df

0001

01df

0001

011f

0000

0100

0000

01df

0010

11df

0000

11df

0010

10df

0010

11df

0011

00df

0001

00df

0010

001f

0000

01df

0011

00df

0011

10df

0000

10df

0011

10df

0001

bbbf

0100

bbbf

0101

bbbf

0110

bbbf

0111

kkkk

1110

kkkk

1001

0000

kkkk

101k

kkkk

1101

kkkk

1100

0000

kkkk

1000

0000

kkkk

1111

ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff

ffff ffff ffff ffff

kkkk kkkk 0100 kkkk kkkk kkkk 0010 kkkk 0011 0fff kkkk

Status

Affected NotesMSb LSb

C,DC,Z

Z Z Z Z Z

None

Z None None

C,DC,Z

None

None None None None

Z None

O, PD

None

Z None None None

O, PD

None

1,2,4

Mnemonic,

Operands Description Cycles

Add W and f

ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF

BIT-ORIENTED FILE REGISTER OPERATIONS BCF

BSF BTFSC BTFSS

LITERAL AND CONTROL OPERATIONS ANDLW

CALL CLRWDT GOTO IORLW MOVLW OPTION RETLW SLEEP TRIS XORLW

Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except f or GOTO .

f,d

AND W with f

f,d

Clear f

Clear W

–

Complement f

f, d

Decrement f

f, d

Decrement f, Skip if 0

f, d

Increment f

f, d

Increment f, Skip if 0

f, d

Inclusive OR W with f

f, d

Move f

f, d

Move W to f

No Operation

–

Rotate left f through Carry

f, d

Rotate right f through Carry

f, d

Subtract W from f

f, d

Swap f

f, d

Exclusive OR W with f

f, d

Bit Clear f

f, b

Bit Set f

f, b

Bit Test f, Skip if Clear

f, b

Bit Test f, Skip if Set

f, b

AND literal with W

Call subroutine

Clear Watchdog Timer

Unconditional branch

Inclusive OR Literal with W

Move Literal to W

Load OPTION register

–

Return, place Literal in W

Go into standby mode

–

Load TRIS register

Exclusive OR Literal to W

(Section 4.6)

2: When an I/O register is modiﬁed as a function of itself (e.g. MOVF PORTB, 1), the v alue used will be that v alue

present on the pins themselves. For example, if the data latch is '1' for a pin conﬁgured as input and is driven low by an external device, the data will be written bac k with a '0'.

3: The instruction TRIS f, where f = 6 causes the contents of the W register to be written to the tristate latches of

PORTB. A '1' forces the pin to a hi-impedance state and disables the output buffers .

4: If this instruction is executed on the TMR0 register (and, where applicab le , d = 1), the prescaler will be cleared

(if assigned to TMR0).

1(2) 1(2)

1 (2) 1 (2)

2,4

2,4 2,4 2,4 2,4 2,4 2,4 1,4

2,4 2,4

DS40192A-page 40 Preliminary  1998 Microchip Technology Inc.

PIC16C505

ADDWF Add W and f

label

Syntax: [

] ADDWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (W) + (f) → (dest) Status Affected: C, DC, Z Encoding: Description:

0001 11df ffff

Add the contents of the W register and

in the W register. If 'd' is '1' the result is

stored back in register 'f'

Words: 1 Cycles: 1 Example:

ADDWF FSR, 0

Before Instruction

W = 0x17 FSR = 0xC2

After Instruction

W = 0xD9 FSR = 0xC2

ANDLW And literal with W

label

Syntax: [

] ANDLW k Operands: 0 ≤ k ≤ 255 Operation: (W).AND. (k) → (W) Status Affected: Z Encoding: Description:

1110 kkkk kkkk

The contents of the W register are AND’ed with the eight-bit literal 'k'. The result is placed in the W register

Words: 1 Cycles: 1 Example:

ANDLW 0x5F

Before Instruction

W = 0xA3

After Instruction

W = 0x03

ANDWF AND W with f

label

Syntax: [

] ANDWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (W) .AND. (f) → (dest) Status Affected: Z Encoding: Description:

0001 01df ffff

The contents of the W register are

AND’ed with register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd' is

'1' the result is stored back in register 'f'

. Words: 1 Cycles: 1 Example:

ANDWF FSR, 1

Before Instruction

W = 0x17 FSR = 0xC2

After Instruction

W = 0x17 FSR = 0x02

BCF Bit Clear f

label

Syntax: [

] BCF f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7 Operation: 0 → (f<b>) Status Affected: None Encoding:

Description: Words: 1

0100 bbbf ffff

Bit 'b' in register 'f' is cleared.

Cycles: 1 Example:

BCF FLAG_REG, 7

Before Instruction

FLAG_REG = 0xC7

After Instruction

FLAG_REG = 0x47

 1998 Microchip Technology Inc. Preliminary DS40192A-page 41

PIC16C505

BSF Bit Set f

label

Syntax: [

] BSF f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7 Operation: 1 → (f<b>) Status Affected: None Encoding: Description:

0101 bbbf ffff

Bit 'b' in register 'f' is set.

Words: 1 Cycles: 1 Example:

BSF FLAG_REG, 7

Before Instruction

FLAG_REG = 0x0A

After Instruction

FLAG_REG = 0x8A

BTFSC Bit Test f, Skip if Clear

label

Syntax: [

] BTFSC f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7 Operation: skip if (f<b>) = 0 Status Affected: None Encoding: 0110 Description:

If bit 'b' in register 'f' is 0 then the next

instruction is skipped.

If bit 'b' is 0 then the next instruction

fetched during the current instruction

execution is discarded, and an NOP is

executed instead, making this a 2 cycle

instruction.

bbbf ffff

Words: 1 Cycles: 1(2) Example:

FALSE

TRUE

BTFSC GOTO

•

FLAG,1 PROCESS_CODE

HERE

•

Before Instruction

PC = address (HERE)

After Instruction

if FLAG<1> = 0, PC = address (TRUE); if FLAG<1> = 1, PC = address(FALSE)

BTFSS Bit Test f, Skip if Set

label

Syntax: [

] BTFSS f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b < 7 Operation: skip if (f<b>) = 1 Status Affected: None Encoding: Description:

0111 bbbf ffff

If bit 'b' in register 'f' is '1' then the next

instruction is skipped.

If bit 'b' is '1', then the next instruction

fetched during the current instruction

execution, is discarded and an NOP is

executed instead, making this a 2 cycle

instruction.

Words: 1 Cycles: 1(2) Example:

HERE BTFSS FLAG,1

FALSE GOTO PROCESS_CODE

TRUE •

•

Before Instruction

PC = address (HERE)

After Instruction

If FLAG<1> = 0, PC = address (FALSE); if FLAG<1> = 1, PC = address (TRUE)

DS40192A-page 42 Preliminary  1998 Microchip Technology Inc.

PIC16C505

CALL Subroutine Call

label

Syntax: [

] CALL k Operands: 0 ≤ k ≤ 255 Operation: (PC) + 1→ Top of Stack;

k → PC<7:0>; (STATUS<6:5>) → PC<10:9>;

0 → PC<8> Status Affected: None Encoding: Description:

1001 kkkk kkkk

Subroutine call. First, return address

(PC+1) is pushed onto the stack. The

eight bit immediate address is loaded

into PC bits <7:0>. The upper bits

PC<10:9> are loaded from STA-

TUS<6:5>, PC<8> is cleared. CALL is a

two cycle instruction.

Words: 1 Cycles: 2 Example:

HERE CALL THERE

Before Instruction

PC = address (HERE)

After Instruction

PC = address (THERE) TOS= address (HERE + 1)

CLRF Clear f

label

Syntax: [

] CLRF f Operands: 0 ≤ f ≤ 31 Operation: 00h → (f);

1 → Z Status Affected: Z Encoding: Description:

0000 011f ffff

The contents of register 'f' are cleared

and the Z bit is set.

Words: 1 Cycles: 1 Example:

CLRF FLAG_REG

Before Instruction

FLAG_REG = 0x5A

After Instruction

FLAG_REG = 0x00 Z = 1

CLRW Clear W

label

Syntax: [

] CLRW Operands: None Operation: 00h → (W);

1 → Z Status Affected: Z Encoding: Description:

0000 0100 0000

The W register is cleared. Zero bit (Z)

is set.

Words: 1 Cycles: 1 Example:

CLRW

Before Instruction

W = 0x5A

After Instruction

W = 0x00 Z = 1

CLRWDT Clear Watchdog Timer

label

Syntax: [

] CLRWDT Operands: None Operation: 00h → WDT;

0 → WDT prescaler (if assigned);

1 → T

1 → PD Status Affected: TO, PD Encoding: Description:

0000 0000 0100

The CLRWDT instruction resets the

WDT. It also resets the prescaler , if the

prescaler is assigned to the WDT and

not Timer0. Status bits TO and PD are

set.

Words: 1 Cycles: 1 Example:

CLRWDT

Before Instruction

WDT counter = ?

After Instruction

WDT counter = 0x00 WDT prescale = 0 TO = 1 PD = 1

 1998 Microchip Technology Inc. Preliminary DS40192A-page 43

PIC16C505

COMF Complement f

label

Syntax: [

] COMF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f

) → (dest) Status Affected: Z Encoding: Description:

0010 01df ffff

The contents of register 'f' are complemented. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.

Words: 1 Cycles: 1 Example:

COMF REG1,0

Before Instruction

REG1 = 0x13

After Instruction

REG1 = 0x13 W = 0xEC

DECF Decrement f

label

Syntax: [

] DECF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (f) – 1 → (dest) Status Affected: Z Encoding: Description:

0000 11df ffff

Decrement register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd' is

1 the result is stored back in register 'f'.

Words: 1 Cycles: 1 Example:

DECF CNT,

Before Instruction

CNT = 0x01 Z = 0

After Instruction

CNT = 0x00 Z = 1

DECFSZ Decrement f, Skip if 0

label

Syntax: [

] DECFSZ f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (f) – 1 → d; skip if result = 0 Status Affected: None Encoding: Description:

0010 11df ffff

The contents of register 'f' are decre-

mented. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

If the result is 0, the next instruction,

which is already fetched, is discarded

and an NOP is executed instead mak-

ing it a two cycle instruction.

Words: 1 Cycles: 1(2) Example:

HERE DECFSZ CNT, 1

GOTO LOOP

CONTINUE •

•

Before Instruction

PC = address (HERE)

After Instruction

CNT = CNT - 1; if CNT = 0, PC = address (CONTINUE); if CNT ≠ 0, PC = address (HERE+1)

GOTO Unconditional Branch

label

Syntax: [

] GOTO k

Operands: 0 ≤ k ≤ 511

Operation: k → PC<8:0>;

STATUS<6:5> → PC<10:9> Status Affected: None Encoding: Description:

101k kkkk kkkk

GOTO is an unconditional branch. The

9-bit immediate value is loaded into PC

bits <8:0>. The upper bits of PC are

loaded from STATUS<6:5>. GOTO is a

two cycle instruction.

Words: 1 Cycles: 2 Example:

GOTO THERE

After Instruction

PC = address (THERE)

DS40192A-page 44 Preliminary  1998 Microchip Technology Inc.

PIC16C505

INCF Increment f

label

Syntax: [

] INCF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (f) + 1 → (dest) Status Affected: Z Encoding: Description:

0010 10df ffff

The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Words: 1 Cycles: 1 Example:

INCF CNT,

Before Instruction

CNT = 0xFF Z = 0

After Instruction

CNT = 0x00 Z = 1

INCFSZ Increment f, Skip if 0

label

Syntax: [

] INCFSZ f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (f) + 1 → (dest), skip if result = 0 Status Affected: None Encoding: Description:

0011 11df ffff

The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

If the result is 0, then the next instruc-

tion, which is already fetched, is dis-

carded and an NOP is executed

instead making it a two cycle instruc-

tion.

Words: 1 Cycles: 1(2) Example:

HERE INCFSZ CNT, 1

GOTO LOOP

CONTINUE •

•

Before Instruction

PC = address (HERE)

After Instruction

CNT = CNT + 1; if CNT = 0, PC = address (CONTINUE); if CNT ≠ 0, PC = address (HERE +1)

IORLW Inclusive OR literal with W

label

Syntax: [

] IORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. (k) → (W) Status Affected: Z Encoding: Description:

1101 kkkk kkkk

The contents of the W register are OR’ed with the eight bit literal 'k'. The result is placed in the W register.

Words: 1 Cycles: 1 Example:

IORLW 0x35

Before Instruction

W = 0x9A

After Instruction

W = 0xBF Z = 0

IORWF Inclusive OR W with f

label

Syntax: [

] IORWF f,d Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (W).OR. (f) → (dest) Status Affected: Z Encoding: Description:

0001 00df ffff

Inclusive OR the W register with regis-

ter 'f'. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Words: 1 Cycles: 1 Example:

IORWF RESULT, 0

Before Instruction

RESULT = 0x13 W = 0x91

After Instruction

RESULT = 0x13 W = 0x93 Z = 0

 1998 Microchip Technology Inc. Preliminary DS40192A-page 45

PIC16C505

MOVF Move f

label

Syntax: [

] MOVF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (f) → (dest) Status Affected: Z Encoding: Description:

0010 00df ffff

The contents of register 'f' is moved to

destination 'd'. If 'd' is 0, destination is

the W register . If 'd' is 1, the destination

is ﬁle register 'f'. 'd' is 1 is useful to test

a ﬁle register since status ﬂag Z is

affected.

Words: 1 Cycles: 1 Example:

MOVF FSR, 0

After Instruction

W = value in FSR register

MOVLW Move Literal to W

label

Syntax: [

] MOVLW k Operands: 0 ≤ k ≤ 255 Operation: k → (W) Status Affected: None Encoding: Description:

1100 kkkk kkkk

The eight bit literal 'k' is loaded into the W register. The don’t cares will assemble as 0s.

Words: 1 Cycles: 1 Example:

MOVLW 0x5A

After Instruction

W = 0x5A

MOVWF Move W to f

label

Syntax: [

] MOVWF f Operands: 0 ≤ f ≤ 31 Operation: (W) → (f) Status Affected: None Encoding: Description:

0000 001f ffff

Move data from the W register to register 'f'

. Words: 1 Cycles: 1 Example:

MOVWF TEMP_REG

Before Instruction

TEMP_REG = 0xFF W = 0x4F

After Instruction

TEMP_REG = 0x4F W = 0x4F

NOP No Operation

label

Syntax: [

] NOP Operands: None Operation: No operation Status Affected: None Encoding:

0000 0000 0000

Description: No operation. Words: 1 Cycles: 1 Example:

NOP

DS40192A-page 46 Preliminary  1998 Microchip Technology Inc.

PIC16C505

OPTION Load OPTION Register

label

Syntax: [

] OPTION Operands: None Operation: (W) → OPTION Status Affected: None Encoding: Description:

0000 0000 0010

The content of the W register is loaded into the OPTION register.

Words: 1 Cycles: 1 Example

OPTION

Before Instruction

W = 0x07

After Instruction

OPTION = 0x07

RETLW Return with Literal in W

label

Syntax: [

] RETLW k Operands: 0 ≤ k ≤ 255 Operation: k → (W);

TOS → PC Status Affected: None Encoding: Description:

1000 kkkk kkkk

The W register is loaded with the eight

bit literal 'k'. The program counter is

loaded from the top of the stack (the

return address). This is a two cycle

instruction.

Words: 1 Cycles: 2 Example:

TABLE

CALL TABLE ;W contains

;table offset

;value.

• ;W now has table

• ;value.

•

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2 ;

•

RETLW kn ; End of table

Before Instruction

W = 0x07

After Instruction

W = value of k8

RLF Rotate Left f through Carry

label

Syntax: [

] RLF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: See description below Status Affected: C Encoding: Description:

0011 01df ffff

The contents of register 'f' are rotated

one bit to the left through the Carry

Flag. If 'd' is 0 the result is placed in the

W register. If 'd' is 1 the result is stored

back in register 'f'.

Words: 1 Cycles: 1 Example:

RLF REG1,0

Before Instruction

REG1 = 1110 0110 C = 0

After Instruction

REG1 = 1110 0110 W = 1100 1100 C = 1

RRF Rotate Right f through Carry

label

Syntax: [

] RRF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: See description below Status Affected: C Encoding: Description:

0011 00df ffff

The contents of register 'f' are rotated

one bit to the right through the Carry

Flag. If 'd' is 0 the result is placed in the

W register. If 'd' is 1 the result is placed

back in register 'f'.

Words: 1 Cycles: 1 Example:

RRF REG1,0

Before Instruction

REG1 = 1110 0110 C = 0

After Instruction

REG1 = 1110 0110 W = 0111 0011 C = 0

 1998 Microchip Technology Inc. Preliminary DS40192A-page 47

PIC16C505

SLEEP Enter SLEEP Mode

Syntax:

label

[

]

SLEEP Operands: None Operation: 00h → WDT;

0 → WDT prescaler;

1 → T

0 → PD Status Affected: TO, PD, RBWUF Encoding: Description:

0000 0000 0011

Time-out status bit (TO) is set. The

power down status bit (PD) is cleared.

RBWUF is unaffected.

The WDT and its prescaler are

cleared.

The processor is put into SLEEP mode

with the oscillator stopped. See sec-

tion on SLEEP for more details.

Words: 1 Cycles: 1 Example: SLEEP

SUBWF Subtract W from f

Syntax:

label

] SUBWF f,d

[

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (f) – (W) → (dest) Status Affected: C, DC, Z Encoding: Description:

0000 10df ffff

Subtract (2’s complement method) the

W register from register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd' is

1 the result is stored back in register 'f'.

Words: 1 Cycles: 1

SUBWF REG1, 1

Example 1

Before Instruction

REG1 = 3 W = 2 C = ?

After Instruction

REG1 = 1 W = 2 C = 1 ; result is positive

Example 2:

Before Instruction

REG1 = 2 W = 2 C = ?

After Instruction

REG1 = 0 W = 2 C = 1 ; result is zero

Example 3:

Before Instruction

REG1 = 1 W = 2 C = ?

After Instruction

REG1 = FF W = 2 C = 0 ; result is negative

DS40192A-page 48 Preliminary  1998 Microchip Technology Inc.

PIC16C505

SWAPF Swap Nibbles in f

label

Syntax: [

] SWAPF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f<3:0>) → (dest<7:4>);

(f<7:4>) → (dest<3:0>) Status Affected: None Encoding: Description:

0011 10df ffff

The upper and lower nibbles of register

'f' are exchanged. If 'd' is 0 the result is

placed in W register. If 'd' is 1 the result

is placed in register 'f'.

Words: 1 Cycles: 1

SWAPF

Example

REG1, 0

Before Instruction

REG1 = 0xA5

After Instruction

REG1 = 0xA5 W = 0X5A

TRIS Load TRIS Register

label

Syntax: [ Operands: f =

] TRIS f

Operation: (W) → TRIS register f Status Affected: None Encoding: Description:

0000 0000 0fff

TRIS register 'f' (f = 6 or 7) is loaded

with the contents of the W register

Words: 1 Cycles: 1 Example

TRIS PORTB

Before Instruction

W = 0XA5

After Instruction

TRIS = 0XA5

XORLW Exclusive OR literal with W

Syntax:

label

] XORLW k

[ Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Encoding: Description:

1111 kkkk kkkk

The contents of the W register are

XOR’ed with the eight bit literal 'k'. The

result is placed in the W register.

Words: 1 Cycles: 1 Example: XORLW 0xAF

Before Instruction

W = 0xB5

After Instruction

W = 0x1A

XORWF Exclusive OR W with f

label

Syntax: [

] XORWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (W) .XOR. (f) → (dest) Status Affected: Z Encoding: Description:

0001 10df ffff

Exclusive OR the contents of the W

result is stored in the W register. If 'd' is

1 the result is stored back in register 'f'.

Words: 1 Cycles: 1 Example XORWF

REG,1

Before Instruction

REG = 0xAF W = 0xB5

After Instruction

REG = 0x1A W = 0xB5

 1998 Microchip Technology Inc. Preliminary DS40192A-page 49

PIC16C505

NOTES:

DS40192A-page 50 Preliminary  1998 Microchip Technology Inc.

PIC16C505

9.0 DEVELOPMENT SUPPORT

9.1 Development Tools

The PICmicrο microcontrollers are supported with a full range of hardware and software dev elopment tools:

• PICMASTER In-Circuit Emulator

• ICEPIC Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator

• PRO MATE

• PICSTART Programmer

• PICDEM-1 Low-Cost Demonstration Board

• PICDEM-2 Low-Cost Demonstration Board

• PICDEM-3 Low-Cost Demonstration Board

• MPASM Assembler

• MPLAB SIM Software Simulator

• MPLAB-C17 (C Compiler)

• Fuzzy Logic Development System (

fuzzy

9.2 PICMASTER: High Performance

The PICMASTER Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the PIC14C000, PIC12CXXX, PIC16C5X, PIC16CXXX and PIC17CXX families. PICMASTER is supplied with the MPLAB Integrated Development Environment (IDE), which allows editing, “make” and download, and source debugging from a single environment.

Interchangeable target probes allow the system to be easily reconﬁgured for emulation of different processors. The universal architecture of the PICMASTER allows expansion to support all new Microchip microcontrollers.

The PICMASTER Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows

3.x environment were chosen to best make these fea-

tures available to you, the end user. A CE compliant version of PICMASTER is availab le f or

European Union (EU) countries.



/PICMASTER CE Real-Time



II Universal Programmer



Plus Entry-Level Prototype

TECH−MP)

Universal In-Circuit Emulator with MPLAB IDE

9.3 ICEPIC: Low-Cost PICmicro™ In-Circuit Emulator

ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC12CXXX, PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers.

ICEPIC is designed to operate on PC-compatible machines ranging from 286-AT based machines under Windows 3.x environment. ICEPIC features real time, non-intrusive emulation.



through Pentium

9.4 PRO MATE II: Universal Programmer

The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. PRO MATE II is CE compliant.

The PRO MATE II has programmable V supplies which allows it to verify programmed memory at V

DD min and VDD max for maximum reliability. It has

an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices. It can also set conﬁguration and code-protect bits in this mode.

DD and VPP

9.5 PICSTART Plus Entry Level Development System

The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efﬁcient. PICSTART Plus is not recommended for production programming.

PICSTART Plus supports all PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923, PIC16C924 and PIC17C756 may be supported with an adapter socket. PICSTART Plus is CE compliant.



 1998 Microchip Technology Inc. Preliminary DS40192A-page 51

PIC16C505

9.6 PICDEM-1 Low-Cost PICmicro Demonstration Board

The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE II or PICSTART-Plus programmer, and easily test ﬁrmware. The user can also connect the PICDEM-1 board to the PICMASTER emulator and download the ﬁrmware to the emulator for testing. Additional prototype area is available f or the user to b uild some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB.

9.7 PICDEM-2 Low-Cost PIC16CXX Demonstration Board

The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART -Plus , and easily test ﬁrmware. The PICMASTER emulator may also be used with the PICDEM-2 board to test ﬁrmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the f eatures include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I tion to an LCD module and a keypad.

C bus and separate headers for connec-

9.8 PICDEM-3 Low-Cost PIC16CXXX Demonstration Board

The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and easily test ﬁrmware. The PICMASTER emulator may also be used with the PICDEM-3 board to test ﬁrmware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include

an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also pro vided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC . A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.

9.9 MPLAB™ Integrated Development Environment Software

The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains:

• A full featured editor

• Three operating modes

- editor

- emulator

- simulator

• A project manager

• Customizable tool bar and key mapping

• A status bar with project information

• Extensive on-line help

MPLAB allows you to:

• Edit your source ﬁles (either assembly or ‘C’)

• One touch assemble (or compile) and download

to PICmicro tools (automatically updates all project information)

• Debug using:

- source ﬁles

- absolute listing ﬁle

• Transfer data dynamically via DDE (soon to be

replaced by OLE)

• Run up to four emulators on the same PC

The ability to use MPLAB with Microchip’s simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools.

9.10 Assembler (MPASM)

The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It suppor ts all microcontroller series including the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX families.

MPASM offers full featured Macro capabilities, conditional assembly , and se veral source and listing f ormats. It generates various object code formats to support Microchip's development tools as well as third party programmers.

MPASM allows full symbolic debugging from PICMASTER, Microchip’s Universal Emulator System.

DS40192A-page 52 Preliminary  1998 Microchip Technology Inc.

PIC16C505

MPASM has the following features to assist in developing software for speciﬁc use applications.

• Provides translation of Assembler source code to object code for all Microchip microcontrollers.

• Macro assembly capability.

• Produces all the ﬁles (Object, Listing, Symbol, and special) required for symbolic debug with Microchip’s emulator systems.

• Supports Hex (default), Decimal and Octal source and listing formats.

MPASM provides a rich directive language to suppor t programming of the PICmicro. Directives are helpful in making the development of your assemb le source code shorter and more maintainable.

9.11 Software Simulator (MPLAB-SIM)

The MPLAB-SIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PICmicro series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/ output radix can be set by the user and the execution can be performed in; single step, e x ecute until break, or in a trace mode.

MPLAB-SIM fully supports symbolic debugging using MPLAB-C and MPASM. The Software Simulator offers the low cost ﬂexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.

9.12 C Compiler (MPLAB-C17)

The MPLAB-C Code Development System is a complete ‘C’ compiler and integrated development environment for Microchip’s PIC17CXXX family of microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with other compilers.

For easier source level debugging, the compiler provides symbol information that is compatible with the MPLAB IDE memory display.

9.13 Fuzzy Logic Development System

(

fuzzy

TECH-MP)

fuzzy

TECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, menting more complex systems.

Both versions include Microchip’s stration board for hands-on experience with fuzzy logic systems implementation.

fuzzy

TECH-MP, Edition for imple-

fuzzy

LAB demon-

9.14 MP-DriveWay – Application Code

Generator

MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can visually conﬁgure all the peripherals in a PICmicro device and, with a click of the mouse, generate all the initialization and many functional code modules in C language. The output is fully compatible with Microchip’s MPLAB-C C compiler. The code produced is highly modular and allows easy integration of your own code. MP-DriveWay is intelligent enough to maintain your code through subsequent code generation.

9.15 SEEVAL Evaluation and Programming System

The SEEVAL SEEPROM Designer’s Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart Serials and secure serials. The Total Endurance Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can signiﬁcantly reduce time-to-market and result in an optimized system.

9.16 KEELOQ Evaluation and Programming Tools

KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters.

 1998 Microchip Technology Inc. Preliminary DS40192A-page 53

DS40192A-page 54 Preliminary  1998 Microchip Technology Inc.

EMULATOR PRODUCTS

PICMASTER/ PICMASTER-CE In-Circuit Emulator

ICEPIC Low-Cost In-Circuit Emulator

SOFTWARE PRODUCTS

MPLAB Integrated Development Environment

MPLAB C17 Compiler

fuzzy

TECH-MP Explorer/Edition Fuzzy Logic Dev. Tool

MP-DriveWay Applications Code Generator

Total Endurance Software Model

PROGRAMMERS

PICSTARTPlus Low-Cost Universal Dev. Kit

PRO MATE II Universal Programmer

KEELOQ Programmer

DEMO BOARDS

SEEVAL Designers Kit PICDEM-1 PICDEM-2 PICDEM-3 KEELOQ Evaluation Kit

PIC12C5XX

PIC16C505

PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C75X

24CXX 25CXX 93CXX

ü ü ü ü ü ü ü ü ü ü

ü ü ü ü ü ü ü

ü ü ü ü ü ü ü ü ü ü

ü ü

ü ü ü ü ü ü ü ü ü

ü ü ü ü ü ü ü

ü ü ü ü ü ü ü ü ü ü

ü ü ü ü ü ü ü ü ü ü ü ü

ü ü ü ü

ü ü

HCS200 HCS300 HCS301

TABLE 9-1: DEVELOPMENT TOOLS FROM MICROCHIP

PIC16C505

10.0 ELECTRICAL CHARACTERISTICS - PIC16C505

Absolute Maximum Ratings†

Ambient Temperature under bias........................................................................................................... –40˚C to +125˚C

Storage Temperature.............................................................................................................................. –65˚C to +150˚C

Voltage on V

Voltage on MCLR

Voltage on all other pins with respect to V

Total Power Dissipation

Max. Current out of V

Max. Current into V

Input Clamp Current, I

Output Clamp Current, I

Max. Output Current sunk by any I/O pin................................................................................................................25 mA

Max. Output Current sourced by any I/O pin...........................................................................................................25 mA

Max. Output Current sourced by I/O port .............................................................................................................100 mA

Max. Output Current sunk by I/O port ..................................................................................................................100 mA

Note 1: Power Dissipation is calculated as follows: P

†

NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

DD with respect to VSS .................................................................................................................0 to +7.5 V

with respect to VSS...............................................................................................................0 to +14 V

(1)

....................................................................................................................................700 mW

SS pin...................................................................................................................................200 mA

DD pin......................................................................................................................................150 mA

IK (VI < 0 or VI > VDD) ....................................................................................................................±20 mA

OK (VO < 0 or VO > VDD) ............................................................................................................±20 mA

SS ................................................................................–0.6 V to (VDD + 0.6 V)

DIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)

 1998 Microchip Technology Inc. Preliminary DS40192A-page 55

PIC16C505

10.1 DC CHARACTERISTICS: PIC16C505-04 (Commercial, Industrial, Extended) PIC16C505-20(Commercial, Industrial, Extended)

DC Characteristics Power Supply Pins

Characteristic Sym Min

Supply Voltage V

RAM Data Retention

(2)

Voltage

DD Start Voltage to ensure

V Power-on Reset

DD Rise Rate to ensure

V Power-on Reset

Supply Current

Power-Down Current

(3)

(5)

WDT Enabled

WDT Disabled

* These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-

ance only and is not tested. 2: This is the limit to which V 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on

the current consumption.

a) The test conditions for all I

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to V

ss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as speciﬁed.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: I

R = VDD/2Rext (mA) with Rext in kOhm.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is mea-

sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to V

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

DD 3.0

–40°C ≤ T –40°C ≤ T

(1)

Max Units Conditions

Typ

5.5

VVXT, EXTRC, INTRC and LP OSC conﬁgura-

A ≤ +85°C (industrial) A ≤ +125°C (extended)

tion

4.5

5.5

HS OSC conﬁguration

VDR 1.5* V Device in SLEEP mode

VPOR VSS V See section on Power-on Reset for details

SVDD 0.05* V/ms See section on Power-on Reset for details

XT and EXTRC options (Note 4)

2.4

IDD —

DD can be lowered in SLEEP mode without losing RAM data.

DD measurements in active operation mode are:

1.8 F

OSC = 4 MHz, VDD = 5.5V

2.4

1.8

—

— — —

— — — — — —

4.5

4 4 5

0.25

0.25 2

35 16

12 14 22

4 5

INTRC Option F

OSC = 4 MHz, VDD = 5.5V

µA

LP O

PTION, Commercial Temperature

OSC = 32 kHz, VDD = 3.0V, WDT disabled

µA

LP O

PTION, Industrial Temperature

OSC = 32 kHz, VDD = 3.0V, WDT disabled

µA

LP O

PTION, Extended Temperature

OSC = 32 kHz, VDD = 3.0V, WDT disabled

HS O

PTION, Industrial Temperature

OSC = 20 MHz, VDD = 5.5V

µA

DD = 3.0V, Commercial

µA

DD = 3.0V, Industrial

µA

DD = 3.0V, Extended

µA

DD = 3.0V, Commercial

µA

DD = 3.0V, Industrial

µA

DD = 3.0V, Extended

DD or VSS.

DS40192A-page 56 Preliminary  1998 Microchip Technology Inc.

PIC16C505

10.2 DC CHARACTERISTICS: PIC16LC505-04 (Commercial, Industrial, Extended)

DC Characteristics Power Supply Pins

Characteristic Sym Min

Supply Voltage V

RAM Data Retention

(2)

Voltage

DD Start Voltage to ensure

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

DD 3.0

2.5

–40°C ≤ T –40°C ≤ T

(1)

Max Units Conditions

Typ

5.5

VVXT, EXTRC, INTRC OSC conﬁguration

5.5

A ≤ +85°C (industrial) A ≤ +125°C (extended)

LP OSC conﬁguration

VDR 1.5* V Device in SLEEP mode

VPOR VSS V See section on Power-on Reset for details

Power-on Reset

Standard Operating Conditions (unless otherwise speciﬁed)

DD Rise Rate to ensure

SVDD 0.05* V/ms See section on Power-on Reset for details

Power-on Reset Supply Current

(3)

Power-Down Current WDT Enabled

WDT Disabled

2.4

IDD —

(5)

1.8

2.4

1.8

—

— — —

0.25

—

0.25

— —

4.5

35 16

4 5

XT and EXTRC options (Note 4)

OSC = 4 MHz, VDD = 5.5V

INTRC Option F

OSC = 4 MHz, VDD = 5.5V

µA

LP O

PTION, Commercial Temperature

OSC = 32 kHz, VDD = 3.0V, WDT disabled

µA

LP O

PTION, Industrial Temperature

OSC = 32 kHz, VDD = 3.0V, WDT disabled

µA

LP O

PTION, Extended Temperature

OSC = 32 kHz, VDD = 3.0V, WDT disabled

HS O

PTION, Industrial Temperature

OSC = 20 MHz, VDD = 5.5V

µA

DD = 3.0V, Commercial

µA

DD = 3.0V, Industrial

µA

DD = 3.0V, Extended

µA

DD = 3.0V, Commercial

µA

DD = 3.0V, Industrial

µA

DD = 3.0V, Extended

* These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-

ance only and is not tested.

2: This is the limit to which V

DD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption.

a) The test conditions for all I

DD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to V

ss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as speciﬁed.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: I

R = VDD/2Rext (mA) with Rext in kOhm.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is mea-

sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to V

DD or VSS.

 1998 Microchip Technology Inc. Preliminary DS40192A-page 57

PIC16C505

10.3 DC CHARACTERISTICS: PIC16C505-04 (Commercial, Industrial, Extended) PIC16C505-20(Commercial, Industrial, Extended) PIC16LC505-04 (Commercial, Industrial, Extended)

Standard Operating Conditions (unless otherwise speciﬁed)

DC Characteristics

All Pins Except

Power Supply Pins

Characteristic Sym Min Typ

Input Low Voltage

I/O ports

MCLR and RC5 (Schmitt Trigger) OSC1 OSC1 OSC1

Input High Voltage

I/O ports

and RC5 (Schmitt Trigger)

MCLR OSC1 (Schmitt Trigger)

IPUR

Input Leakage Current

(2,3)

I/O ports MCLR OSC1

Output Low Voltage

I/O ports

(3,4)

Output High Voltage

I/O ports

* These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-

ance only and is not tested.

2: The leakage current on the MCLR

iﬁed levels represent normal operating conditions. Higher leakage current may be measured at different

input voltage. 3: Negative current is deﬁned as coming out of the pin. 4: For PIC16C505 devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the

PIC16C505 be driven with external clock in RC mode. 5: The user may use the better of the two speciﬁcations.

Operating Temperature 0°C ≤ T

Operating Voltage V

DD range is described in Section 10.1.

(1)

VSS VSS VSS

0.6 VDD -1.0

0.25VDD+0.8V

2.0

0.2V

DD+1V

0.8 V

0.9 VDD

0.7 VDD

–1

0.5

–40°C ≤ T

Max Units Conditions

0.8

0.15 V

0.20 VDD

0.3 VDD

VDD VDD VDD VDD VDD VDD

A ≤ +70°C (commercial)

A ≤ +85°C (industrial)

A ≤ +125°C (extended)

V V

V V V V

V V V V V V

µA

Pin at hi-impedance

4.5V < V

DD ≤ 5.5V

Pin at hi-impedance

3.0V < V

DD ≤ 4.5V

EXTRC option only XT and HS options LP option

2.5V < V

DD ≤ 4.5V

4.5V < V

DD ≤ 5.5V

Full VDD range Full VDD range EXTRC option only HS, XT and LP options

For V

DD ≤ 5.5V

SS ≤ VPIN ≤ VDD,

Pin at hi-impedance

20 –3

130

0.5

250

+5 +3

µA

PIN = VSS + 0.25V

µA

VPIN = VDD

µA

VSS ≤ VPIN ≤ VDD, XT and LP options

Vol

0.6 V I

OL = 8.7 mA, VDD = 4.5V

VoH

DD –0.7 V IOH = –5.4 mA, VDD = 4.5V

/VPP/RB3 pin is strongly dependent on the applied voltage level. The spec-

(4)

(5)

(4)

(2)

DS40192A-page 58 Preliminary  1998 Microchip Technology Inc.

10.4 Timing Parameter Symbology and Load Conditions - PIC16C505

The timing parameter symbols have been created following one of the following formats:

1. TppS2ppS

2. TppS

F Frequency T Time Lowercase subscripts (pp) and their meanings:

2 to mc MCLR ck CLKOUT osc oscillator cy cycle time os OSC1 drt device reset timer t0 T0CKI io I/O port wdt watchdog timer Uppercase letters and their meanings:

F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance

FIGURE 10-1: LOAD CONDITIONS - PIC16C505

PIC16C505

VSS

 1998 Microchip Technology Inc. Preliminary DS40192A-page 59

L = 50 pF for all pins except OSC2

15 pF for OSC2 in XT, HS or LP

modes when external clock is used to drive OSC1

PIC16C505

10.5 Timing Diagrams and Speciﬁcations FIGURE 10-2: EXTERNAL CLOCK TIMING - PIC16C505

OSC1

Q1 Q2

1 3 3

Q3 Q4 Q1

4 4

TABLE 10-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C505

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Parameter

No.

1 T

2 Tcy

* These parameters are characterized but not tested.

Sym Characteristic Min

FOSC

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested. 2: All speciﬁed values are based on characterization data for that particular oscillator type under standard oper-

ating conditions with the device executing code. Exceeding these speciﬁed limits may result in an unstable

oscillator operation and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 3: Instruction cycle period (T

Operating Temperature 0°C ≤ T

Operating Voltage V

External CLKIN Frequency

Oscillator Frequency

OSC

External CLKIN Period

Oscillator Period

Instruction Cycle Time

(2)

CY) equals four times the input oscillator time base period.

–40°C ≤ T –40°C ≤ T

DD range is described in Section 10.1

(2)

(3)

A ≤ +70°C (commercial),

A ≤ +85°C (industrial), A ≤ +125°C (extended)

(1)

Max Units Conditions

Typ

DC — 4 MHz XT osc mode DC — 4 MHz HS osc mode

DC — 200 kHz LP osc mode DC — 4 MHz EXTRC osc mode

0.1 — 4 MHz XT osc mode 4 — 4 MHz HS osc mode

4 — 20 MHz HS osc mode

DC — 200 kHz LP osc mode

250 — — ns XT osc mode

5 — — µs LP osc mode

250 — — ns EXTRC osc mode 250 — 10,000 ns XT osc mode 250 — 250 ns HS ocs mode

50 — 250 ns HS ocs mode

5 — — µs LP osc mode

— 4/FOSC DC ns

200 — ns TC4 = 4/FOSC

(PIC16C505-04)

(PIC16C505-20)

(PIC16C505-04)

(PIC16C505-20)

DS40192A-page 60 Preliminary  1998 Microchip Technology Inc.

PIC16C505

TABLE 10-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C505 (CONTINUED)

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature 0°C ≤ T

–40°C ≤ T –40°C ≤ T

Operating Voltage V

Parameter

No.

3 TosL, TosH Clock in (OSC1) Low or High Time 50* — — ns XT oscillator

4 TosR, TosF Clock in (OSC1) Rise or Fall Time — — 25* ns XT oscillator

* These parameters are characterized but not tested.

Sym Characteristic Min

DD range is described in Section 10.1

A ≤ +70°C (commercial),

A ≤ +85°C (industrial), A ≤ +125°C (extended)

(1)

Typ

2* — — µs LP oscillator 10 ns HS oscillator

— — 50* ns LP oscillator — — 15 ns HS oscillator

Max Units Conditions

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

2: All speciﬁed values are based on characterization data for that particular oscillator type under standard oper-

ating conditions with the device executing code. Exceeding these speciﬁed limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

3: Instruction cycle period (T

CY) equals four times the input oscillator time base period.

 1998 Microchip Technology Inc. Preliminary DS40192A-page 61

PIC16C505

FIGURE 10-3: I/O TIMING - PIC16C505

Q2 Q3

OSC1

I/O Pin

(input)

I/O Pin

(output)

Note: All tests must be done with speciﬁed capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.

Old Value

20, 21

New Value

TABLE 10-2: TIMING REQUIREMENTS - PIC16C505

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Parameter

No. Sym Characteristic Min Typ

17 18

20 21

TosH2ioV TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid

TioV2osH Port input valid to OSC1↑

TioR TioF

* These parameters are characterized but not tested. ** These parameters are design targets and are not tested. No characterization data available at this time.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25˚C unless otherwise stated. These parameters are for design

guidance only and are not tested. 2: Measurements are taken in EXTRC mode. 3: See Figure 10-1 for loading conditions.

Operating Temperature 0°C ≤ T

–40°C ≤ T –40°C ≤ T

Operating Voltage V

OSC1↑ (Q1 cycle) to Port out valid

DD range is described in Section 10.1

(3)

(I/O in hold time)

(I/O in setup time) Port output rise time Port output fall time

(3)

A ≤ +70°C (commercial)

A ≤ +85°C (industrial) A ≤ +125°C (extended)

— — 100* ns

TBD — — ns

— 10 25** ns — 10 25** ns

(1)

Max Units

DS40192A-page 62 Preliminary  1998 Microchip Technology Inc.

PIC16C505

FIGURE 10-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C505

VDD

MCLR

Internal

POR

DRT

Timeout (Note 2)

Internal RESET

Watchdog

Timer

RESET

I/O pin (Note 1)

Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software. 2: Runs in MCLR or WDT reset only in XT, LP and HS modes.

TABLE 10-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C505

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Parameter

No. Sym Characteristic Min Typ

30 31

32 34

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

Operating Temperature 0°C ≤ T

–40°C ≤ T –40°C ≤ T

Operating Voltage V

DD range is described in Section 10.1

A ≤ +70°C (commercial) A ≤ +85°C (industrial) A ≤ +125°C (extended)

(1)

Max Units Conditions

TmcL MCLR Pulse Width (low) 2000* — — ns VDD = 5 V

Twdt Watchdog Timer Time-out Period

9* 18* 30* ms VDD = 5 V (Commercial)

(No Prescaler)

TDRT Device Reset Timer Period

(2)

9* 18* 30* ms VDD = 5 V (Commercial)

TioZ I/O Hi-impedance from MCLR Low — — 2000* ns

TABLE 10-4: DRT (DEVICE RESET TIMER PERIOD - PIC16C505

Oscillator Conﬁguration POR Reset Subsequent Resets

IntRC & ExtRC 18 ms (typical) 300 µs (typical) XT, HS & LP 18 ms (typical) 18 ms (typical)

 1998 Microchip Technology Inc. Preliminary DS40192A-page 63

PIC16C505

FIGURE 10-5: TIMER0 CLOCK TIMINGS - PIC16C505

T0CKI

40 41

TABLE 10-5: TIMER0 CLOCK REQUIREMENTS - PIC16C505

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature 0°C ≤ T

–40°C ≤ T –40°C ≤ T

Operating Voltage V

Parameter

No.

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only

Sym Characteristic Min Typ

40 Tt0H T0CKI High Pulse Width - No Prescaler 0.5 TCY + 20* — — ns

- With Prescaler 10* — — ns

41 Tt0L T0CKI Low Pulse Width - No Prescaler 0.5 TCY + 20* — — ns

- With Prescaler 10* — — ns

42 Tt0P T0CKI Period 20 or TCY + 40*

and are not tested.

DD range is described in Section 10.1.

A ≤ +70°C (commercial)

A ≤ +85°C (industrial) A ≤ +125°C (extended)

(1)

Max Units Conditions

— — ns Whichever is greater.

N = Prescale Value

(1, 2, 4,..., 256)

TABLE 10-6: PULL-UP RESISTOR RANGES - PIC16C505

VDD (Volts) Temperature (°C) Min Typ Max Units

RB0/RB1/RB4

3.0 -40 27K 32K 35K Ω 25 33K 38K 43K Ω 85 33K 39K 43K Ω

125 37K 42K 60K Ω

5.5 -40 15K 17K 20K Ω 25 18K 20K 23K Ω 85 19K 22K 25K Ω

125 22K 24K 28K Ω

RB3

3.0 -40 271K 326K 395K Ω 25 327K 390K 492K Ω 85 348K 427K 500K Ω

125 400K 472K 567K Ω

5.5 -40 247K 292K 360K Ω 25 288K 341K 437K Ω 85 306K 371K 448K Ω

125 351K 407K 500K Ω

* These parameters are characterized but not tested.

DS40192A-page 64 Preliminary  1998 Microchip Technology Inc.

PIC16C505

11.0 DC AND AC CHARACTERISTICS - PIC16C505

The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside speciﬁed operating range (e.g., outside speciﬁed V for information only and devices will operate properly only within the speciﬁed range.

The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean – 3σ) respectively, where σ is standard deviation.

FIGURE 11-1: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. TEMPERATURE (VDD = 5.0V)

(INTERNAL RC IS CALIBRATED TO 25°C, 5.0V)

Not available at this time.

DD range). This is

FIGURE 11-2: CALIBRATED INTERNAL RC FREQUENCY RANGE VS. TEMPERATURE (V

(INTERNAL RC IS CALIBRATED TO 25°C, 5.0V)

DD = 3.0V)

Not available at this time.

 1998 Microchip Technology Inc. Preliminary DS40192A-page 65

PIC16C505

FIGURE 11-3: INTERNAL RC FREQUENCY VS. CALIBRATION VALUE (VDD = 5.5V)

Not available at this time.

FIGURE 11-4: INTERNAL RC FREQUENCY VS. CALIBRATION VALUE (V

Not available at this time.

TABLE 11-1: DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25°C

Oscillator Frequency

External RC 4 MHz Internal RC 4 MHz 420 µA 1.1 mA XT 4 MHz 251 µA 775 µA LP 32 KHz 7 µA 37 µA HS 20 MHz N/A 4.5 mA

Note 1: LP oscilator based on V Note 2: Does not include current through external R&C.

DD = 2.5V

DD = 3.0V

250 µA

(1)

(2)

VDD = 5.5V

(2)

620 µA

DD = 3.5V)

DS40192A-page 66 Preliminary  1998 Microchip Technology Inc.

PIC16C505

FIGURE 11-5: WDT TIMER TIME-OUT

PERIOD vs. VDD

WDT period (µs)

2 3 4 5 6 7

DD (Volts)

Max +125°C

Max +85°C

Typ +25°C

MIn –40°C

FIGURE 11-6: SHORT DRT PERIOD VS. VDD

1000

900

800

700

600

500

WDT period (µs)

400

300

200

100

2 3 4 5 6 7

DD (Volts)

Max +125°C

Max +85°C

Typ +25°C

MIn –40°C

 1998 Microchip Technology Inc. Preliminary DS40192A-page 67

PIC16C505

FIGURE 11-7: IOH vs. VOH, VDD = 2.5 V

-1

-2

-3

IOH (mA)

-4

Min +125°C

-5

Min +85°C

-6

Typ +25°C

Max –40°C

-7

500m 1.0 1.5

2.0 2.5

VOH (Volts)

FIGURE 11-8: IOH vs. VOH, VDD = 5.5 V

FIGURE 11-9: IOL vs. VOL, VDD = 2.5 V

Max –40°C

Typ +25°C

IOL (mA)

Min +85°C

Min +125°C

250.0m 500.0m 1.0

OL (Volts)

FIGURE 11-10: IOL vs. VOL, VDD = 5.5 V

-5

Max –40°C

-10

-15

Typ +25°C

IOH (mA)

-20

Min +125°C

Min +85°C

-25

Typ +25°C

Max –40°C

-30

3.5 4.0 4.5

5.0 5.5

VOH (Volts)

DS40192A-page 68 Preliminary  1998 Microchip Technology Inc.

IOL (mA)

250.0m

500.0m 750.0m 1.0

OL (Volts)

Min +85°C

Min +125°C

12.0 PACKAGING INFORMATION

12.1 Package Marking Information

PIC16C505

14-Lead PDIP (300 mil)

MMMMMMMMMMMMMM XXXXXXXXXXXXXX

AABBCDE

14-Lead SOIC (150 mil)

MMMMMMMMMM

AABBCDE

14-Lead Windowed Ceramic Side Brazed (300 mil)

MMMMMMM

Legend: MM...M Microchip part number information

XX...X Customer speciﬁc information* AA Year code (last 2 digits of calendar year) BB Week code (week of January 1 is week ‘01’) C Facility code of the plant at which wafer is manufactured

O = Outside Vendor C = 5” Line S = 6” Line

H = 8” Line D Mask revision number E Assembly code of the plant or country of origin in which

part was assembled

Example

16C505-04I/P BUILT 4 SPEED

9804SAZ

Example

16C505-04I

9804SAZ

Example

16C505

Note: In the event the full Microchip part number cannot be marked on one line,

it will be carried over to the next line thus limiting the number of available characters for customer speciﬁc information.

* Standard OTP marking consists of Microchip part number, year code, week

code, facility code, mask re v#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Ofﬁce. For QTP devices, any special marking adders are included in QTP price.

 1998 Microchip Technology Inc. Preliminary DS40192A-page 69

PIC16C505

Package Type: K04-005 14-Lead Plastic Dual In-line (P) – 300 mil

Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX PCB Row Spacing 0.300 7.62 Number of Pins n 14 14 Pitch p 0.100 2.54 Lower Lead Width B 0.013 0.018 0.023 0.33 0.46 0.58 Upper Lead Width Shoulder Radius R 0.000 0.005 0.010 0.00 0.13 0.25 Lead Thickness c 0.006 0.010 0.012 0.20 0.25 0.30 Top to Seating Plane A 0.120 0.145 0.170 3.05 3.68 4.32 Top of Lead to Seating Plane A1 0.065 0.085 0.105 1.65 2.16 2.67 Base to Seating Plane A2 0.000 0.015 0.035 0.00 0.38 0.89 Tip to Seating Plane L 0.125 0.130 0.135 3.18 3.30 3.43 Package Length Molded Package Width Radius to Radius Width E1 0.260 0.280 0.300 6.60 7.11 7.62 Overall Row Spacing eB 0.310 0.368 0.425 7.87 9.33 10.80 Mold Draft Angle Top Mold Draft Angle Bottom

Controlling Parameter.

†

Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”

‡

Dimensions “D” and “E” do not include mold ﬂash or protrusions. Mold ﬂash or protrusions shall not exceed 0.010”(0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”

D E

α β

†

0.055 0.060 0.065 1.40 1.52 1.65

‡

0.740 0.750 0.760 18.80 19.05 19.30

‡

0.240 0.245 0.250 6.10 6.22 6.35

5 10 15 5 10 15 5 10 15 5 10 15

DS40192A-page 70 Preliminary  1998 Microchip Technology Inc.

PIC16C505

Package Type: K04-065 14-Lead Plastic Small Outline (SL) – Narrow, 150 mil

E1 E

n 1

45°

Units

Pitch Number of Pins Overall Pack. Height Shoulder Height Standoff Molded Package Length Molded Package Width Outside Dimension Chamfer Distance Shoulder Radius Gull Wing Radius Foot Length Foot Angle Radius Centerline Lead Thickness Lower Lead Width Mold Draft Angle Top Mold Draft Angle Bottom

Controlling Parameter.

†

Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”

‡

Dimensions “D” and “E” do not include mold ﬂash or protrusions. Mold ﬂash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”

p n A A1 A2 D E E1 X R1 R2 L

L1 c B

α β

MINDimension Limits

‡

†

INCHES* MILLIMETERS

0.050 14

0.058

0.027

0.004

0.338

0.150

0.230

0.010

0.005

0.011

0.000

0.008

0.014

0.063

0.036

0.006

0.341

0.153

0.236

0.014

0.005

0.016

0.005

0.009

0.017

0 0

0.068

0.044

0.008

0.344

0.156

0.242

0.018

0.010

0.021

4 8

0.010

0.019 12 12

15 15

1.47

0.69

0.10

8.59

3.81

5.84

0.25

0.13

0.28 0

0.00

0.19

0.36 0 0

1.27

1.60

0.90

0.15

8.66

5.99

0.36

0.13

0.41

0.13

0.22

0.42

MAXNOMMINMAXNOM

1.73

1.12

0.20

8.74

3.963.89

6.15

0.46

0.25

0.53

12 12

0.25

0.48 15 15

 1998 Microchip Technology Inc. Preliminary DS40192A-page 71

PIC16C505

Package Type: 14-Lead Ceramic Side Brazed Dual In-line with Window (JW) – 300 mil

Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Lead Thickness Top to Seating Plane Top of Body to Seating Plane Base to Seating Plane Tip to Seating Plane Package Length Package Width Overall Row Spacing Window Diameter Lid Length Lid Width

* Controlling Parameter.

n p B B1 c A A1 A2 L D E eB W T U

MIN

0.098

0.016

0.050

0.008

0.145

0.103

0.025

0.130

0.680

0.280

0.310

0.161

0.440

0.260

INCHES*

NOM

0.300

0.100

0.018

0.055

0.010

0.165

0.123

0.035

0.140

0.700

0.290

0.338

0.166

0.450

0.270

MILLIMETERS

0.102

0.020

0.060

0.012

0.185

0.143

0.045

0.150

0.720

0.300

0.365

0.171

0.460

0.280

MIN

2.49

0.41

1.27

0.20

3.68

2.62

0.64

3.30

17.27

7.11

7.87

4.09

11.18

6.60

MAX

NOM

17.78

11.43

7.62

2.54

0.46

1.40

0.25

4.19

3.12

0.89

3.56

7.37

8.57

4.22

6.86

MAX

2.59

0.51

1.52

0.30

4.70

3.63

1.14

3.81

18.29

7.62

9.27

4.34

11.68

7.11

DS40192A-page 72 Preliminary  1998 Microchip Technology Inc.

PIC16C505

INDEX A

ALU....................................................................................... 7

Applications........................................................................... 3

Architectural Overview.......................................................... 7

Assembler

MPASM Assembler..................................................... 52

Block Diagram

On-Chip Reset Circuit.................................................33

Timer0......................................................................... 23

TMR0/WDT Prescaler................................................. 26

Watchdog Timer..........................................................35

Brown-Out Protection Circuit ..............................................36

CAL0 bit..............................................................................16

CAL1 bit..............................................................................16

CAL2 bit..............................................................................16

CAL3 bit..............................................................................16

CALFST bit .........................................................................16

CALSLW bit ........................................................................16

Carry.....................................................................................7

Clocking Scheme................................................................ 10

Code Protection............................................................27, 37

Configuration Bits................................................................ 27

Configuration Word............................................................. 27

DC and AC Characteristics................................................. 65

Development Support.........................................................51

Development Tools............................................................. 51

Device Varieties.................................................................... 5

Digit Carry............................................................................. 7

Family of Devices

PIC16C505 ...................................................................4

FSR..................................................................................... 18

Fuzzy Logic Dev. System (

fuzzy

TECH-MP) ....................53

I/O Interfacing .....................................................................19

I/O Ports.............................................................................. 19

I/O Programming Considerations........................................ 20

ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator............51

ID Locations.................................................................. 27, 37

INDF.................................................................................... 18

Indirect Data Addressing..................................................... 18

Instruction Cycle .................................................................10

Instruction Flow/Pipelining..................................................10

Instruction Set Summary..................................................... 40

KeeLoq Evaluation and Programming Tools....................53

Loading of PC.....................................................................17

Memory Organization.......................................................... 11

Data Memory ..............................................................12

Program Memory........................................................ 11

MP-DriveWay™ - Application Code Generator................... 53

MPLAB C............................................................................53

MPLAB Integrated Development Environment Software.... 52

OPTION Register ............................................................... 15

OSC selection..................................................................... 27

OSCCAL Register .............................................................. 16

Oscillator Configurations .................................................... 28

Oscillator Types

HS............................................................................... 28

LP............................................................................... 28

RC .............................................................................. 28

XT............................................................................... 28

Package Marking Information............................................. 69

Packaging Information........................................................ 69

PICDEM-1 Low-Cost PICmicro Demo Board ..................... 52

PICDEM-2 Low-Cost PIC16CXX Demo Board................... 52

PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 52

PICMASTER In-Circuit Emulator..................................... 51

PICSTART Plus Entry Level Development System......... 51

POR

Device Reset Timer (DRT)................................... 27, 34

PD............................................................................... 36

Power-On Reset (POR).............................................. 27

TO............................................................................... 36

PORTB ............................................................................... 19

Power-Down Mode............................................................. 37

Prescaler ............................................................................ 26

PRO MATE II Universal Programmer.............................. 51

Program Counter................................................................ 17

Q cycles.............................................................................. 10

RC Oscillator ...................................................................... 29

Read Modify Write.............................................................. 20

Registers

Special Function......................................................... 13

Reset .................................................................................. 27

Reset on Brown-Out........................................................... 36

SEEVAL Evaluation and Programming System .............. 53

SLEEP.......................................................................... 27, 37

Software Simulator (MPLAB-SIM)...................................... 53

Special Features of the CPU.............................................. 27

Special Function Registers................................................. 13

Stack................................................................................... 17

STATUS ................................................................................7

STATUS Register............................................................... 14

Timer0

Switching Prescaler Assignment................................ 26

Timer0 ........................................................................ 23

Timer0 (TMR0) Module .............................................. 23

TMR0 with External Clock.......................................... 25

Timing Diagrams and Specifications .................................. 60

Timing Parameter Symbology and Load Conditions.......... 59

TRIS Registers ................................................................... 19

Wake-up from SLEEP ........................................................ 37

Watchdog Timer (WDT)................................................ 27, 34

Period......................................................................... 35

Programming Considerations..................................... 35

Zero bit ..................................................................................7

 1998 Microchip Technology Inc. Preliminary DS40192A-page 73

PIC16C505

NOTES:

DS40192A-page 74 Preliminary  1998 Microchip Technology Inc.

PIC16C505

ON-LINE SUPPORT

Microchip provides on-line support on the Microchip World Wide Web (WWW) site.

The web site is used by Microchip as a means to make ﬁles and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site.

Connecting to the Microchip Internet Web Site

The Microchip web site is available by using your favorite Internet browser to attach to:

www.microchip.com

The ﬁle transfer site is available by using an FTP service to connect to:

ftp://ftp.futureone.com/pub/microchip

The web site and ﬁle transfer site provide a variety of services. Users may download ﬁles for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip speciﬁc business information is also available, including listings of Microchip sales ofﬁces, distributors and factory representatives. Other data available for consideration is:

• Latest Microchip Press Releases

• Technical Support Section with Frequently Asked Questions

• Design Tips

• Device Errata

• Job Postings

• Microchip Consultant Program Member Listing

• Links to other useful web sites related to Microchip Products

• Conferences for products, De v elopment Systems, technical information and more

• Listing of seminars and events

Systems Information and Upgrade Hot Line

The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are:

1-800-755-2345 for U.S. and most of Canada, and 1-602-786-7302 for the rest of the world.

980106

Trademarks: The Microchip name, logo , PIC, PICSTART, PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. PICmicro, LAB are trademarks and SQTP is a service mark of Microchip in the U.S.A.

All other trademarks mentioned herein are the property of their respective companies.

Flex

ROM, MPLAB and

fuzzy-

 1998 Microchip Technology Inc. Preliminary DS40192A-page 75

PIC16C505

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to pro vide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.

Please list the following information, and use this outline to provide us with your comments about this Data Sheet.

To:

Technical Publications Manager

RE: Reader Response From:

Name Company

Address City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional): Would you like a reply? Y N

Device:

PIC16C505

Questions:

1. What are the best features of this document?

Literature Number:

DS40192A

Total Pages Sent

FAX: (______) _________ - _________

2. How does this document meet your hardware and software development needs?

3. Do you ﬁnd the organization of this data sheet easy to follow? If not, why?

4. What additions to the data sheet do you think would enhance the structure and subject?

5. What deletions from the data sheet could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

8. How would you improve our software, systems, and silicon products?

DS40192A-page 76 Preliminary  1998 Microchip Technology Inc.

PIC16C505

PIC16C505 Product Identiﬁcation System

PART NO. -XX X /XX XXX

Pattern: Special Requirements

Package: SL = 150 mil SOIC

Temperature Range:

Frequency Range:

Device PIC16C505

P = 300 mil PDIP JW = 300 mil Windowed Ceramic Side Brazed

- = 0°C to +70°C I = -40°C to +85°C E = -40°C to +125°C

04 = 4 MHz (XT, INTRC, EXTRC OSC) 04 = 200 KHz (LP OSC) 20 = 20 MHz (HS OSC)

PIC16LC505 PIC16C505T (Tape & reel for SOIC only) PIC16LC505T (Tape & reel for SOIC only)

Please contact your local sales ofﬁce for exact ordering procedures.

Sales and Support

Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

Your local Microchip sales ofﬁce (see below)

1. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.

Examples

a) PIC16C505-04/P

Commercial Temp., PDIP Package, 4 MHz, normal V

b) PIC16C505-04I/SL

Industrial Temp., SOIC package, 4 MHz, normal

DD limits

c) PIC16C505-04I/P

Industrial Temp., PDIP package, 4 MHz, normal V

DD limits

 1998 Microchip Technology Inc. Preliminary DS40192A-page 77

PIC16C505

NOTES:

DS40192A-page 78 Preliminary  1998 Microchip Technology Inc.

NOTES:

PIC16C505

 1998 Microchip Technology Inc. Preliminary DS40192A-page 79

WORLDWIDE SALES AND SERVICE

AMERICAS

Corporate Ofﬁce

Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277

Technical Support: Web:

http://www.microchip.com

Atlanta

Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307

Boston

Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575

Chicago

Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075

Dallas

Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 972-991-7177 Fax: 972-991-8588

Dayton

Microchip Technology Inc. Two Prestige Place, Suite 150 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175

Los Angeles

Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 714-263-1888 Fax: 714-263-1338

New York

Microchip Technology Inc. 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 516-273-5305 Fax: 516-273-5335

San Jose

Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955

Toronto

Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253

602 786-7627

ASIA/PACIFIC

Hong Kong

Microchip Asia Paciﬁc RM 3801B, Tower Two Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431

India

Microchip Technology Inc. India Liaison Ofﬁce No. 6, Legacy, Convent Road Bangalore 560 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062

Japan

Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa 222-0033 Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122

Korea

Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934

Shanghai

Microchip Technology RM 406 Shanghai Golden Bridge Bldg. 2077 Yan’an Road West, Hong Qiao District Shanghai, PRC 200335 Tel: 86-21-6275-5700 Fax: 86 21-6275-5060

Singapore

Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850

ASIA/PACIFIC (continued)

Taiwan, R.O.C

Microchip Technology Taiwan 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886-2-2717-7175 Fax: 886-2-2545-0139

EUROPE

United Kingdom

Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-1189-21-5858 Fax: 44-1189-21-5835

France

Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Germany

Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Müchen, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44

Italy

Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-39-6899939 Fax: 39-39-6899883

4/3/98

Microchip received ISO 9001 Quality System certiﬁcation for its worldwide headquarters, design, and wafer fabrication facilities in January , 1997. Our ﬁeld-programmable PICmicro™ 8-bit MCUs, Serial EEPROMs, related specialty memory products and development systems conform to the stringent quality standards of the International Standard Organization (ISO).

Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

DS40192A-page 80  1998 Microchip Technology Inc.

Microchip Technology Inc PIC16C505T-20I-SL, PIC16C505-20E-SL, PIC16C505-20I-JW, PIC16C505-20I-P, PIC16C505-20I-SL Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1.0 GENERAL DESCRIPTION

1.1 Applications

2.0 PIC16C505 DEVICE VARIETIES

3.0 ARCHITECTURAL OVERVIEW

4.0 MEMORY ORGANIZATION

4.2.1 GENERAL PURPOSE REGISTER FILE The general purpose register ﬁle is accessed either

4.2.2 SPECIAL FUNCTION REGISTERS

4.4 OPTION Register

4.5 OSCCAL Register

4.6 Program Counter

4.6.1 EFFECTS OF RESET The Program Counter is set upon a RESET, which

4.7 Stack

5.0 I/O PORT

5.1 PORTB

5.2 PORTC

5.3 TRIS Registers

5.4 I/O Interfacing

5.5 I/O Programming Considerations

5.5.1 BI-DIRECTIONAL I/O PORTS Some instructions operate internally as read followed

6.0 TIMER0 MODULE AND TMR0 REGISTER

6.1 Using Timer0 with an External Clock

6.1.1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used, the external clock input is

6.1.2 TIMER0 INCREMENT DELAY Since the prescaler output is synchronized with the

6.2 Prescaler

6.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control

7.0 SPECIAL FEATURES OF THE CPU

7.2.1 OSCILLATOR TYPES The PIC16C505 can be operated in four different

7.2.4 EXTERNAL RC OSCILLATOR For timing insensitive applications, the RC device

7.2.5 INTERNAL 4 MHz RC OSCILLATOR The internal RC oscillator provides a ﬁxed 4 MHz (nom-

7.3 RESET

7.3.1 MCLR ENABLE This conﬁguration bit when unprogrammed (left in the

7.5 Device Reset Timer (DRT)

7.6 Watchdog Timer (WDT)

7.6.1 WDT PERIOD The WDT has a nominal time-out period of 18 ms,

7.6.2 WDT PROGRAMMING CONSIDERATIONS The CLRWDT instruction clears the WDT and the

7.8 Reset on Brown-Out

7.9 Power-Down Mode (SLEEP)

SLEEP instruction. If enabled, the Watchdog Timer will be cleared but

7.9.2 WAKE-UP FROM SLEEP The device can wake-up from SLEEP through one of

7.11 ID Locations

7.12 In-Circuit Serial Programming

8.0 INSTRUCTION SET SUMMARY

9.0 DEVELOPMENT SUPPORT

9.1 Development Tools

9.4 PRO MATE II: Universal Programmer

9.10 Assembler (MPASM)

9.11 Software Simulator (MPLAB-SIM)

9.12 C Compiler (MPLAB-C17)

10.0 ELECTRICAL CHARACTERISTICS - PIC16C505

11.0 DC AND AC CHARACTERISTICS - PIC16C505

12.0 PACKAGING INFORMATION

12.1 Package Marking Information

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